A solar cell and a manufacturing method thereof, a photovoltaic module

Abstract

This application discloses a solar cell and its manufacturing method, as well as a photovoltaic module, relating to the field of photovoltaic technology. The solar cell includes: a semiconductor substrate, the first surface of which includes a first region and a second region; the second region includes an edge region and a middle region, both of which include stepped structures recessed into the second surface, the step depth of the step structure in the edge region of the second region being greater than the step depth of the step structure in the middle region of the second region; a first doped layer disposed on the first region, and the height of the bottom wall of the stepped structure in the middle region of the second region being lower than the height of the first doped layer; and a first passivation layer disposed on the side of the first doped layer away from the semiconductor substrate and on the second region. In this embodiment, the thickness along the cleaving direction is reduced, thereby reducing the difficulty of cleaving, reducing carrier recombination, and improving the passivation effect.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510792152.8, filed on June 12, 2025, entitled “A Solar Cell and a Method for Manufacturing the Same Thereof, and a Photovoltaic Module”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of photovoltaic technology, and in particular to a solar cell and its manufacturing method, and a photovoltaic module. Background Technology

[0004] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight shines on the semiconductor pn junction of the solar cell, forming new electron-hole pairs. Under the influence of the built-in electric field of the pn junction, photogenerated holes flow to the p-region, and photogenerated electrons flow to the n-region. When the circuit is connected, an electric current is generated.

[0005] Half-cell solar cells offer better power output and efficiency compared to full-cell solar cells. Therefore, they are commonly used in the fabrication of photovoltaic modules. However, the process of cutting full-cell solar cells into half-cells can create defects such as dangling bonds near the cut side, increasing carrier recombination and reducing photoelectric conversion efficiency. Summary of the Invention

[0006] The purpose of this application is to provide a solar cell and its manufacturing method, as well as a photovoltaic module, to improve the passivation effect near the cut side, reduce carrier recombination, and improve photoelectric conversion efficiency.

[0007] To achieve the above objectives, this application provides the following technical solution:

[0008] In a first aspect, a solar cell is provided, comprising:

[0009] A semiconductor substrate includes a first surface and a second surface opposite to each other, a first cut side surface connecting the first surface and the second surface, the first surface including a first region and a second region adjacent to the first cut side surface; along the extension direction of the second region, the second region includes an edge region and a middle region, both the edge region and the middle region including a stepped structure recessed into the second surface, the step depth of the stepped structure of the edge region of the second region being greater than the step depth of the stepped structure of the middle region of the second region;

[0010] A first doped layer is disposed on the first region; along the thickness direction of the semiconductor substrate, the height of the bottom wall of the stepped structure in the middle region of the second region is lower than the height of the first doped layer;

[0011] A first passivation layer is disposed on the side of the first doped layer away from the semiconductor substrate and on the second region.

[0012] In the solar cell provided in this application, the step depth of the stepped structure in the edge region of the second region is greater than that in the middle region, which facilitates dicing the cell from the edge region. The bottom wall height of the stepped structure in the middle region is lower than the height of the first doped layer, effectively thinning the cell along the dicing direction and further reducing the difficulty of dicing. Furthermore, the bottom walls of the stepped structures in both the middle and edge regions are lower than the height of the first doped layer, allowing the laser cutting position to be farther from the first doped layer during the dicing process. Considering the formation of numerous dangling bonds during dicing, the lower bottom wall of the stepped structure also prevents charge carriers from approaching the dangling bonds in the dicing area, reducing recombination between charge carriers and dangling bonds and improving photoelectric conversion efficiency. Additionally, the fact that the stepped structures in both the middle and edge regions are lower than the height of the first doped layer means that the first doped layer is etched away at the stepped structures in both regions, making passivation of the first passivation layer easier and improving the passivation effect near the dicing area.

[0013] In one implementation, the step structure in the middle region is a first step structure, and the step structure in the edge region is a second step structure, wherein the step depth of the second step structure is greater than the step depth of the first step structure.

[0014] In this embodiment, the shallow grooves in the entire solar cell do not extend through the entire cell; they are only formed in the middle region, while deep grooves are formed in the edge regions. In other words, the thickness of the solar cell along the cutting direction is reduced, decreasing the difficulty of cleaving the cell from the deep grooves in the edge regions.

[0015] In one implementation, the step structure in the middle region and the step structure in the edge region are connected to form a first step structure, and the bottom wall of the step structure in the edge region is provided with a second step structure.

[0016] When the entire solar cell is cut along the cutting line, a shallower groove is created in the middle area, and a deeper groove is then created in the edge area. This thins the cell as a whole along the cutting direction, further reducing the difficulty of dicing. Furthermore, through-grooves, compared to non-through-grooves, reduce the requirements for laser alignment, thus lowering the complexity of the process. In addition, the depth of laser penetration within the shallow through-grooves is less than the depth of laser penetration directly in the edge area, reducing the laser intensity requirements and lowering the cost of the laser, thereby reducing the overall process cost. Moreover, in schemes applied to negative spacing between adjacent solar cells (i.e., overlapping edges of adjacent solar cells), the first step structure can also be used for negative spacing overlap, improving the flatness of the entire surface of adjacent solar cells.

[0017] In one implementation, the first region is provided with a first type of pyramid structure, the bottom wall of the first step structure of the second region is provided with a first texture structure, and the second surface is provided with a second texture structure, wherein the one-dimensional dimension of the first texture structure is larger than the one-dimensional dimension of the second texture structure.

[0018] In one implementation, the solar cell further includes a second doped layer disposed on the second surface, the second doped layer having a conductivity type opposite to the first doped layer, and the entire second surface being provided with the second texture structure; or

[0019] The solar cell further includes a second doped layer disposed at intervals on the second surface, the second doped layer having the opposite conductivity type to the first doped layer, and the second texture structure being disposed in the interval region between two adjacent second doped layers on the second surface.

[0020] In one implementation, a first region is provided with a first type of pyramid structure, and the bottom wall of the first step structure in the second region is provided with a second type of pyramid structure, wherein the one-dimensional dimension of the first type of pyramid structure is larger than the one-dimensional dimension of the second type of pyramid structure.

[0021] In one implementation, the solar cell further includes a second doped layer disposed at intervals on the second surface, the second doped layer having an opposite conductivity type to the first doped layer, and a third type of pyramid structure disposed in the interval region between two adjacent second doped layers on the second surface, the one-dimensional dimension of the third type of pyramid structure being smaller than the one-dimensional dimension of the second type of pyramid structure.

[0022] In one implementation, the depth range of the spacing region between two adjacent second doped layers on the second surface is the same as the step depth range of the first step structure.

[0023] In one implementation, the first step sidewall is wavy or bent along its extending direction; and / or,

[0024] Along the extending direction of the sidewall of the first step, the first step structure extends continuously or intermittently; and / or,

[0025] Along the direction perpendicular to the first cut side, the width of the first step structure is 20μm~500μm.

[0026] In one implementation, the first step sidewall is parallel to the thickness direction of the semiconductor substrate; or,

[0027] The first step sidewall has an angle with the thickness direction of the semiconductor substrate.

[0028] In one implementation, the first passivation layer is disposed on the step sidewall and the step bottomwall of the first step structure;

[0029] In one implementation, a second passivation layer is provided in the first region near the edge of the second region, the second region, and the first cut side. In the first region near the edge of the second region and the first step structure, the second passivation layer is located on the side of the first passivation layer away from the semiconductor substrate.

[0030] In one implementation, the width of the first step structure is greater than the width of the second step structure.

[0031] In one implementation, the second surface is provided with a third passivation layer, the first cut side is provided with a second passivation layer, and the second passivation layer extends to the edge region of the second surface and is located on the side of the third passivation layer opposite to the semiconductor substrate.

[0032] In one implementation, along the thickness direction of the semiconductor substrate, the depth of the middle region of the first step structure is 2µm to 10µm; the depth of the edge region of the first step structure is 30%H to 100%H, where H is the thickness of the solar cell.

[0033] In one implementation, the one-dimensional size of the first texture structure is 15um to 50um; the one-dimensional size of the second texture structure is 2um to 20um.

[0034] In one implementation, the semiconductor substrate further includes a second diced side surface, which is disposed opposite to the first diced side surface. The first surface also includes a third region adjacent to the second diced side surface, and the first region is located on the side of the third region away from the second diced side surface. Along the extension direction of the third region, the third region includes an edge region and a middle region. Both the edge region and the middle region include a stepped structure. The step depth of the stepped structure in the edge region of the third region is greater than the step depth of the stepped structure in the middle region of the third region. The height of the bottom wall of the stepped structure in the middle region of the third region is lower than the height of the first doped layer.

[0035] In one implementation, the step depth of the stepped structure in the middle region of the second region is the same as the step depth of the stepped structure in the middle region of the third region; and / or

[0036] The step depth of the step structure at the edge of the second region is the same as the step depth of the step structure at the edge of the third region; and / or,

[0037] The step width of the stepped structure in the middle area of ​​the second region is the same as the step width of the stepped structure in the middle area of ​​the third region; and / or

[0038] The step width of the step structure in the edge region of the second region is the same as the step width of the step structure in the edge region of the third region.

[0039] In a second aspect, a solar cell is provided, the solar cell including a groove, wherein the solar cell is segmented at the groove to obtain a solar cell as described above.

[0040] In one implementation, the groove is located in the middle region of the second region along the extension direction of the second region.

[0041] In one implementation, the edge region of the second region is provided with a groove structure; the groove structure is a Y-shaped groove.

[0042] In one implementation, the depth of the trench structure is greater than the depth of the groove.

[0043] Thirdly, a method for manufacturing a solar cell is provided, comprising:

[0044] A semiconductor substrate is provided, the semiconductor substrate including opposing first and second surfaces, the first surface including a first region and a second region;

[0045] A first doped layer and a first doped silicon glass layer are formed on the first surface;

[0046] Laser irradiation is used to reduce the density of the first doped silicon glass layer in the second region.

[0047] The second surface is polished in a groove and a portion of the first doped silicon glass layer in the second region is removed, and a groove is formed in the second region that is recessed into the second surface;

[0048] A second doped layer is formed on the second surface, the second doped layer having an opposite conductivity type to the first doped layer;

[0049] Remove the second doped silicon glass layer from the second surface, and along the thickness direction of the semiconductor substrate, the height of the bottom wall of the groove is lower than the height of the first doped layer;

[0050] A first electrode is formed on the first doped layer, and a second electrode is formed on the second doped layer;

[0051] A groove is formed at the edge of the second region, the depth of the groove being greater than the depth of the recess.

[0052] The semiconductor substrate is sliced ​​along the trench to obtain multiple solar cells.

[0053] The cut grooves form stepped structures on the two solar cells. Along the thickness direction of the semiconductor substrate, the height of the bottom wall of the stepped structure is lower than the height of the first doped layer, facilitating dicing of the cell from the edge region. The bottom wall of the stepped structure in the middle region is also lower than the height of the first doped layer, effectively thinning part or all of the cell thickness along the dicing direction, further reducing the difficulty of dicing. Furthermore, the bottom wall of the stepped structure in the middle region near the cutting surface is lower than the height of the first doped layer 12, meaning the dicing point is farther from the first doped layer 12 during the cutting process. Since more dangling bonds are formed during the cutting process, being farther from the first doped layer 12 prevents charge carriers from approaching the cutting area, reducing carrier recombination and improving photoelectric conversion efficiency. In addition, in this embodiment, the process of reusing the polishing back side is combined with the first cleaning of the first doped silicon glass layer in the groove, saving process steps and reducing process costs.

[0054] In one implementation, forming a trench in the edge region of the second region using a laser includes:

[0055] The groove is formed in the edge region within the recess.

[0056] Fourthly, a method for manufacturing a solar cell is provided, comprising:

[0057] A semiconductor substrate is provided, the semiconductor substrate including opposing first and second surfaces, the first surface including a first region and a second region;

[0058] A first doped layer and a first doped silicon glass layer are formed on the first surface;

[0059] A second doped layer and a second doped silicon glass layer are formed on the second surface, wherein the second doped layer has the opposite conductivity type to the first doped layer.

[0060] Using a laser, the density of the first doped silicon glass layer and the spacer in the second region is reduced;

[0061] Remove the first doped silicon glass layer and the second doped silicon glass layer, and form a groove in the second region that is recessed toward the second surface, wherein the height of the bottom wall of the groove is lower than the height of the first doped layer along the thickness direction of the semiconductor substrate;

[0062] A first electrode is formed on the first doped layer, and a second electrode is formed on the second doped layer;

[0063] A groove is formed at the edge of the second region, the depth of the groove being greater than the depth of the recess.

[0064] The semiconductor substrate is sliced ​​along the trench to obtain multiple solar cells.

[0065] In the same step, the laser irradiates the first doped silicon glass layer in the second region and the second doped silicon glass layer in the spacer region between the adjacent second doped layers. This facilitates the removal of the doped silicon glass layers in the second region and the spacer region in the subsequent process, thereby avoiding the need to add a separate laser step. In other words, the laser step that would have been used to create the spacer region on the back side is reused.

[0066] In one implementation, forming a trench in the edge region of the second region using a laser includes:

[0067] The groove is formed in the edge region within the recess.

[0068] Fifthly, a photovoltaic module is provided, comprising: a plurality of battery strings connected in series and / or in parallel, each battery string comprising: an electrical connector and a first solar cell and a second solar cell, wherein the first solar cell and the second solar cell are both solar cells as described in the first aspect, or solar cells obtained by the manufacturing method as described in the second aspect, the first solar cell and the second solar cell are connected by the electrical connector, the distance between the starting end of the electrical connector and the edge of the first region is greater than the width of the stepped structure of the intermediate region, and the conductive element passes through a first surface and a second side surface of the first solar cell, and through a second surface of the second solar cell, wherein the second side surface is the side surface opposite to the first cut surface of the first solar cell, and the edge of the first region is the boundary edge between the first region and the second region.

[0069] In some possible implementations, the distance between the starting end of the electrical connector and the edge of the first region is greater than or equal to 1 mm.

[0070] In some possible implementations, the second side is a non-cut side. Attached Figure Description

[0071] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0072] Figure 1 A schematic diagram of a photovoltaic module provided in an embodiment of this application;

[0073] Figure 2 A microscopic schematic diagram of a solar cell provided in an embodiment of this application;

[0074] Figure 3 A top view of the first surface of the entire battery cell before cutting, provided in an embodiment of this application;

[0075] Figure 4 A top view of the first surface of a whole battery cell before cutting, provided for another embodiment of this application;

[0076] Figure 5 A partial cross-sectional view of the entire battery cell before cutting, provided for an embodiment of this application;

[0077] Figure 6 A partial cross-sectional view of a solar cell provided in an embodiment of this application;

[0078] Figure 7 A partial cross-sectional view of a solar cell provided in another embodiment of this application;

[0079] Figure 8 A partial cross-sectional view of a solar cell provided in another embodiment of this application;

[0080] Figure 9 A partial cross-sectional view of a solar cell provided in another embodiment of this application;

[0081] Figure 10 A partial cross-sectional view of a solar cell provided in another embodiment of this application;

[0082] Figure 11 A partial cross-sectional view of a solar cell provided in another embodiment of this application;

[0083] Figure 12 A cross-sectional view of the components provided in the application embodiment.

[0084] Figure label:

[0085] 1-First region, 2-Second region, 3-First step sidewall, 4-Groove, 5-Trench structure, 10-Semiconductor substrate, 11-First interface layer, 12-First doped layer, 13-First passivation layer, 14-First electrode, 15-Second interface layer, 16-Second doped layer, 17-Third passivation layer, 18-Second electrode, 19-Second passivation layer, 30-Groove structure, 31-Groove, 32-Trench, 21-Intermediate region, 22-Edge region;

[0086] A - Solar cell, a - Cell segment, C - Cutting line. Detailed Implementation

[0087] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0088] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0089] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.

[0090] In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0091] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0092] It should be noted that the various embodiments of this application can be individual embodiments, or they can be combined separately without logical conflict, and this application does not limit them in this regard.

[0093] This application provides a photovoltaic module comprising multiple parallel and / or series-connected cell strings. Each cell string includes an electrical connector and multiple solar cells connected in series. The electrical connector electrically connects at least two of the solar cells. Exemplarily, Figure 1 A schematic diagram showing multiple solar cells electrically connected together is provided. (For example...) Figure 1 As shown, multiple solar cells are arranged sequentially along direction A to form a cell string, and the solar cells in the cell string are connected in series. Two or more cell strings are arranged sequentially along direction A to form a group of cell strings, and multiple groups of cell strings are arranged sequentially along direction B.

[0094] Half-cell solar cells offer better power output and efficiency compared to full-cell solar cells. Therefore, they are commonly used in photovoltaic module fabrication. However, during the process of cutting full-cell solar cells into half-cells, laser losses can create defects such as dangling bonds near the cut side, increasing carrier recombination and reducing photoelectric conversion efficiency.

[0095] In view of the above, in order to improve the passivation effect near the cut side, reduce carrier recombination, and improve photoelectric conversion efficiency, this application also provides a solar cell and a method for fabricating the same, which can be applied to the aforementioned photovoltaic modules.

[0096] The semiconductor substrate 10 includes a first surface and a second surface, which are opposite each other along the thickness direction of the semiconductor substrate 10. The first surface may correspond to the light-facing side of the solar cell, and the second surface may correspond to the back-lighting side of the solar cell; or, the first surface may correspond to the back-lighting side of the solar cell, and the second surface may correspond to the light-facing side of the solar cell. In this application, the first surface is described as corresponding to the light-facing side of the solar cell, and the second surface is described as corresponding to the back-lighting side of the solar cell.

[0097] The semiconductor substrate 10 includes a first diced side surface, meaning the solar cell is a diced cell, and at least one side of the semiconductor substrate 10 is a diced surface after dicing; the first diced side surface is the diced surface after dicing. The following embodiments will first be described using a diced cell as an example. Figure 2 As shown, the first surface includes a first region 1 and a second region 2. The second region 2 is adjacent to the first cutting side, and the first region 1 is located on the side of the second region 2 that faces away from the first cutting side. That is, the second region 2 is adjacent to the first cutting side compared to the first region 1, and the second region 2 is located between the first region 1 and the first cutting side. Figure 2 As shown, the second region 2 includes a stepped structure recessed into the second surface. The second region 2 can be entirely recessed to form the stepped structure, or a partial recess in the second region 2 can form the stepped structure. A first stepped sidewall 3 is formed between the stepped structure and the first region 1. The stepped structure includes the first stepped sidewall 3 and a stepped bottom wall. Wherein, as... Figure 3 or Figure 4 The second region 2 includes an intermediate region 21 and an edge region 22. The intermediate region 21 and the edge region 22 can each form a stepped structure, and the step depth of the stepped structure of the edge region 22 is greater than the step depth of the stepped structure of the intermediate region 21. This facilitates framing from the stepped structure of the edge region.

[0098] In addition, such as Figure 6As shown, the first doped layer 12 is disposed in the first region 1. Specifically, the first doped layer 12 can cover all or part of the first region 1. The first doped layer 12 can be additionally formed on the semiconductor substrate 10 by deposition technology, or it can be formed within the semiconductor substrate 10 by diffusion, ion implantation, or other methods. Along the thickness direction of the semiconductor substrate 10, the height of the bottom wall of the stepped structure in the middle region is lower than the height of the first doped layer 12. That is, when the first surface is facing upward, the bottom wall of the stepped structure in the middle region is set lower than the bottom side of the first doped layer 12, or in other words, there is a height difference between the bottom wall of the stepped structure in the middle region and the first doped layer 12. It can be understood that if the step depth of the edge region is greater than the step depth of the middle region, then the bottom wall of the edge region is also lower than the first doped layer 12. In this way, both the middle region and the edge region keep the first doped layer away from the first cutting surface, avoiding recombination of dangling bonds formed during the cutting process.

[0099] Reference Figure 6 The first passivation layer 13 is disposed on the side of the first doped layer 12 facing away from the semiconductor substrate 10, and also on all or part of the second region. For example, the first passivation layer 13 can be disposed on all of the second region, i.e., the bottom and side walls of the stepped structure in the middle region, and the bottom and side walls of the stepped structure in the edge region. Alternatively, the first passivation layer 13 can be disposed on part of the second region, i.e., the first passivation layer is only disposed on the bottom and side walls of the stepped structure in the middle region, and the bottom and side walls of the stepped structure in the edge region are not disposed on the first passivation layer. Alternatively, the first passivation layer can be disposed on some other areas of the second region, which is not limited in this application. The first passivation layer 13 can protect the surface of the solar cell, preventing moisture or oxygen from penetrating into the interior of the solar cell, thereby avoiding performance degradation caused by oxidation or hydrolysis of the solar cell; and the first passivation layer 13 can reduce the surface recombination rate of the solar cell and reduce the light reflectivity, thereby improving the photoelectric conversion efficiency of the solar cell.

[0100] It is understood that the first passivation layer 13 can be a single-layer structure; or, the first passivation layer 13 can be a multi-layer structure. Specifically, the first passivation layer 13 is at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and an aluminum oxide layer, or a composite film formed by stacking these. For example, the first passivation layer 13 can be a two-layer structure, which includes an aluminum oxide layer and a silicon nitride layer, and the aluminum oxide layer is located on the side of the silicon nitride layer closest to the semiconductor substrate 10.

[0101] Therefore, in the solar cell provided in this application, the step depth of the step structure in the edge region of the second region is greater than that in the middle region, which facilitates dicing the cell from the edge region. The bottom wall height of the step structure in the middle region is lower than the height of the first doped layer, effectively thinning the cell along the dicing direction, further reducing the difficulty of dicing. Furthermore, the bottom walls of the step structures in both the middle and edge regions are lower than the height of the first doped layer, allowing the laser cutting position to be further away from the first doped layer during the cutting process. Considering the formation of numerous dangling bonds during the cutting process, the lower bottom wall of the step structure compared to the first doped layer also prevents charge carriers from approaching the dangling bonds in the cutting area, reducing recombination between charge carriers and dangling bonds and improving photoelectric conversion efficiency. Additionally, the fact that the step structures in both the middle and edge regions are lower than the height of the first doped layer means that the first doped layer is etched away at the step structures in both regions, making passivation of the first passivation layer easier and improving the passivation effect near the cutting area.

[0102] It is understood that the first doped layer 12 can be a P-type doped layer or an N-type doped layer. The P-type doped layer can contain one or more elements from Group IIIA (e.g., boron). The N-type doped layer can contain one or more elements from Group VA (e.g., phosphorus). The materials of the N-type and P-type doped layers can include any semiconductor material such as silicon, germanium-silicon, germanium, or gallium arsenide. In terms of the arrangement of matter, the crystal phase of the doped layer can be amorphous, microcrystalline, nanocrystalline, single-crystal, or polycrystalline. The materials of the N-type and P-type doped layers can be the same or different. For example, both the N-type and P-type doped layers can be doped polycrystalline silicon. Another example: the material of the P-type doped layer can include doped polycrystalline silicon, and the material of the N-type doped layer can include at least one of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The P-type doped layer can be obtained by in-situ doping on the surface of a silicon substrate or by deposition on the surface of a silicon substrate. Similarly, the N-type doped layer can be obtained by in-situ doping on the surface of a silicon substrate or by deposition on the surface of a silicon substrate. The silicon substrate can be either N-type or P-type monocrystalline silicon, which can provide long-lived charge carriers.

[0103] In some possible embodiments, when a PN junction is formed between the semiconductor substrate and the first doped layer 12, for example, if the semiconductor substrate 10 is an N-type substrate and the first doped layer 12 is a P-type doped layer, then the semiconductor substrate 10 and the first doped layer 12 form a PN junction. The height of the bottom wall of the stepped structure is lower than the height of the first doped layer 12. This can be understood as removing the PN junction in the edge region of the solar cell near the cutting surface, i.e., removing the P-type doped layer (i.e., removing highly doped B atoms). This can effectively suppress the probability of carrier recombination in the second region, reduce the impact on the passivation effect of the passivation layer field on the subsequent cutting surface, and make the subsequent passivation effect better, thereby helping to reduce power loss caused by laser cutting.

[0104] In some possible embodiments, refer to Figure 3 , Figure 3 A top view of the first surface of a whole solar cell before cutting is shown. The middle region 21 is recessed towards the second surface to form a first stepped structure, and the edge region 22 is recessed towards the second surface to form a second stepped structure. The step depth of the second stepped structure is greater than the step depth of the first stepped structure. That is, the shallow groove (groove 31) of the whole solar cell does not extend through the entire cell; it is only formed in the middle region 21, while the edge region 22 has a deep groove (groove 32). In other words, the thickness of the solar cell along the cutting direction is reduced, decreasing the difficulty of cleaving from the deep groove in the edge region.

[0105] It should be noted that in this application, the widths of the deep groove and the shallow groove can be the same, or the width of the deep groove can be smaller than the width of the shallow groove. For ease of description, the following embodiments are illustrated using the example of a deep groove width being smaller than a shallow groove width, but this application is not limited thereto.

[0106] It is understandable that the edge region of the solar cell can be either end along the cutting direction (i.e., Figure 3 The upper and lower edge areas 22) can also be one end along the cutting direction (i.e. Figure 3 The application does not limit the scope of the upper or lower edge region 22.

[0107] It is also understood that in this embodiment, the second step structure and the first step structure may or may not be connected, that is, the deep groove and shallow groove of the entire battery cell may or may not be connected, and this application does not limit this.

[0108] It is also understood that, in this embodiment, the intermediate region 21 can be obtained by a combination of laser and wet processing, as described in the preparation method below. The edge region 22 can be obtained by laser processing, or obtained simultaneously with the intermediate region 21 using the same steps; this application does not limit this.

[0109] In other possible embodiments, such as Figure 4 As shown ( Figure 4 (A top view of the first surface of a whole solar cell before cutting is shown). Extending along the second region, the second region includes an edge region 22 and a middle region 21. The middle region and the edge region include a communicating first step structure recessed into the second surface, and the bottom wall of the first step structure in the edge region is provided with a second step structure. That is, for the whole solar cell, the shallow groove is a through groove along the cutting direction, and the deep groove is disposed in the shallow groove. Further reference... Figure 5 , Figure 5 A partial cross-sectional view of a whole solar cell before cutting is shown. The step depth H2 of the edge region 22 of the second region is greater than the step depth H1 of the middle region 21 of the second region. Thus, when the whole solar cell is cut along the cutting line C, a deeper groove 32 is created in the edge region 22 on top of the shallower groove 31 in the middle region 21, making the solar cell thinner overall along the cutting direction, thereby further reducing the difficulty of dicing. Furthermore, through-grooves, compared to non-through-grooves, can reduce the requirements for laser alignment, thus reducing the complexity of the process. In addition, the depth of laser influence within the shallow through-grooves is less than the depth of laser influence directly in the edge region, reducing the requirements for laser intensity and allowing the laser to act directly on the surface of silicon substrates with low or no doping concentration, making more efficient use of the laser, improving the accuracy of dicing, and reducing the cost of the laser, i.e., reducing the overall process cost and reducing the impact of the laser on the action area. Moreover, in the scheme applied to the setting of negative spacing between adjacent solar cells (i.e., overlapping edge regions of adjacent solar cells), the first step structure can also be used for negative spacing overlap, improving the flatness of the surfaces of adjacent solar cells in the entire module.

[0110] For example, a single solar cell can be cut into multiple solar cells, such as 2, 3, 4, 6... solar cells. On the first surface of the solar cell, grooves 31 (shallow grooves) and trenches 32 (shallow slots) can be arranged along the extension direction of the cutting line C. Subsequent cutting based on the groove structure 30 makes the cutting operation easier, improves cutting efficiency and the quality of the finished product. Specifically, the grooves 31 can reduce the overall structural thickness of the solar cell in the cutting extension direction, thereby further reducing the difficulty of dicing. Figure 3 , 4 As shown in the example in Figure 5, after the entire solar cell is cut, two solar cells (i.e., half solar cells) can be obtained. Specifically, along the cutting line C, two edge regions 22 and a middle region 21 can be divided in the first surface of the entire solar cell. The groove structure 30 can include a shallow groove 31 located mostly in the middle region 21 and a deep trench 32 located in the edge region 22.

[0111] In some possible embodiments, refer to Figure 3 and Figure 5 The step width W2 of the edge region 22 is smaller than the step width W1 of the middle region 21. The step structure of the edge region is used for cleaving and is deeper. Therefore, the step width of the edge region is smaller than that of the middle region, which can avoid causing more damage to the solar cell.

[0112] In some possible embodiments, the first region 1 is provided with a first type of pyramid structure, and the second region 2 is provided with a first texture structure or a second type of pyramid structure. For example Figure 6 In the middle, the second region 2 is equipped with a second type of pyramid structure; or, for example, Figure 7 In the first region 1, a first textured structure is provided. The first type of pyramid structure and / or the second type of pyramid structure can include a pyramid with sharp apex, a pyramid-like structure with rounded chamfers, or a pyramid-like structure with flattened apex. Using this technical solution, the first type of pyramid structure in the first region 1 and the first textured structure or second type of pyramid structure in the second region 2 improve the light-trapping effect of the light-facing surface, reduce light reflectivity, and allow more light to be reflected into and utilized by the semiconductor substrate 10, thus improving light absorption and utilization efficiency. The first textured structure or second type of pyramid structure in the second region 2 can increase the specific surface area and roughness of the second region 2, playing a certain anchoring role, which helps to improve the adhesion of the second region 2 after lamination, preventing partial delamination or peeling of the second region 2 of the solar cell, and extending the lifespan of the solar cell.

[0113] It should be noted that the texture structure of this application can be the surface morphology of a polished surface or a base structure (e.g., a raised structure or a pitted structure, etc.), and this application does not limit it in this regard. For example, the first texture structure mentioned above, and the second and third texture structures described below, but each texture structure can be the same or different, and this application does not limit it in this regard.

[0114] In some possible embodiments, the bottom wall of the first step structure is provided with a first texture structure. Since the undulation of the first texture structure is small (which can be understood as having no spire), in conjunction with the aforementioned embodiments, the bottom wall of the first step structure is provided with a second step structure. When the laser forms the second step structure on the bottom wall of the first step structure, the concentration of laser at the tip position is reduced, making the laser action more uniform and causing less damage to the solar cell.

[0115] In some possible embodiments, the one-dimensional dimensions of the first type of pyramid structure and the second type of pyramid structure are different, or their size ranges are different. The second type of pyramid structure in the second region is smaller than the one-dimensional dimension of the first type of pyramid structure in the first region. This results in a smaller pyramid structure height in the second region, a smaller increase in specific surface area, which is more conducive to the coverage of the passivation layer and thus further improves the passivation effect in the second region.

[0116] It is understood that the pyramid-like structure involved in the embodiments of this application can be a pyramid structure with a apex or a pyramid structure without a apex, and this application does not limit it in this way.

[0117] In some possible embodiments, the second region is provided with multiple second texture structures, with the second texture structures closer to the sidewalls being denser and the second texture structures farther from the sidewalls being sparser. For example, the number of tower base structures closer to the sidewalls is greater than the number of second texture structures farther from the sidewalls.

[0118] In some embodiments, the depth of the first step structure is set along the thickness direction of the semiconductor substrate 10. If the depth of the first step structure is too large, it will reduce the mechanical strength of the semiconductor substrate 10; if the depth of the first step structure is too small, it will have a greater impact on the first doped layer 12 during laser cutting, affecting the passivation effect of the first doped layer 12. In this technical solution, to balance the above two aspects, the depth of the middle region of the first step structure is 2µm to 10µm along the thickness direction of the semiconductor substrate, so as to ensure the mechanical strength of the semiconductor substrate 10 while reducing the impact of cutting on the passivation effect. The depth of the edge region of the first step structure is 30%H to 100%H, where H is the thickness of the solar cell. This depth range ensures that the formed cutting guide region effectively divides the entire solar cell into two segmented solar cells. Furthermore, when the ratio is less than 100%, the damage to the solar cell caused by destructive laser light can be reduced.

[0119] It should be noted that for a scheme with a through shallow trench, where the deep trench is inside the shallow trench, the depth of the deep trench can be understood as being measured from the first surface of the solar cell.

[0120] For example, the depth of the first step structure is 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um or 10um.

[0121] The embodiments of this application can be applied to bifacial batteries (e.g., TOPCon (passivated contact) batteries) and also to back contact batteries (e.g., BC batteries).

[0122] In some embodiments, the solar cell further includes a second doping layer provided on the second surface, the second doping layer having a conductivity type opposite to that of the first doping layer, and the second surface is entirely provided with the second texture structure. That is to say, the embodiments of the present application can be applied to the scheme where the second doping layer is provided on the entire back surface.

[0123] It can be understood that the entire back surface does not necessarily mean that the second doping layer is provided on the entire back surface, but is only used to distinguish from products with doping layers provided at intervals on the back surface.

[0124] In some embodiments, the solar cell further includes second doping layers provided at intervals on the second surface, the second doping layers having a conductivity type opposite to that of the first doping layer, and the second texture structure is provided in the interval region between two adjacent second doping layers on the second surface.

[0125] The solar cell further includes a second doping layer 16 provided on the second surface. The second doping layer 16 can be provided on the second surface as a whole layer or partially. The second doping layer 16 can be additionally formed on the semiconductor substrate 10 through a deposition technique, or can be formed in the semiconductor substrate 10 by diffusion, ion implantation, etc. The conductivity type of the second doping layer 16 is opposite to that of the first doping layer 12 to respectively collect and export electrons and holes, which is beneficial to the formation of photocurrent.

[0126] When the second doping layer 16 is partially provided on the second surface, the second doping layer 16 can be distributed at intervals along the first direction on the second surface; the second doping layer 16 extends along the second direction, and the second doping layer 16 can be distributed in a strip shape, a shape similar to a rich font, etc. The first direction and the second direction intersect, and the included angle between the first direction and the second direction can be an acute angle or a right angle. The first direction can be the length direction of the semiconductor substrate 10 or the width direction of the semiconductor substrate 10. When the first direction is the length direction of the semiconductor substrate 10, the second direction is the width direction of the semiconductor substrate 10; when the first direction is the width direction of the semiconductor substrate 10, the second direction is the length direction of the semiconductor substrate 10.

[0127] As Figure 7 shown, the second doping layer 16 is distributed at intervals along the first direction on the second surface. When the first texture structure is provided in the second region 2, the second texture structure is provided in the interval region between two adjacent second doping layers 16 on the second surface. The shape of the second texture structure can be the same as or different from that of the first texture structure. Adopting this technical solution, the second texture structure is beneficial to improving the light trapping effect on the light incident surface, reducing the light reflectance, and making more light be reflected into the semiconductor substrate 10 and utilized by the semiconductor substrate 10, improving the light absorption and utilization rate; and the second texture structure can further reduce the lateral recombination of carriers.

[0128] In some embodiments, the first region 1 is provided with a first type of pyramid structure, the second region 2 is provided with a first texture structure, and the second surface is provided with a second texture structure, wherein the one-dimensional dimension of the first texture structure is larger than the one-dimensional dimension of the second texture structure.

[0129] The first texture structure has a one-dimensional dimension larger than the second texture structure. Light is then directed onto the second region 2. This one-dimensional dimension can be a parameter such as the height, width, or spacing of the first or second texture structure; for example, the height of the first texture structure is greater than the height of the second texture structure, or the width of the first texture structure is greater than the width of the second texture structure, etc. The fact that the first texture structure has a larger one-dimensional dimension than the second texture structure indicates that the first texture structure has less undulation, which helps to cover the passivation layer in the cutting area, thereby further improving the passivation effect near the cutting area.

[0130] In some embodiments, the one-dimensional size of the first texture structure is set within a reasonable range of 15µm to 50µm to improve the light-trapping effect and light absorption utilization rate of the second region 2, while avoiding the situation where the one-dimensional size of the first texture structure is too large, affecting the formation quality of the passivation layer in the second region 2, and avoiding the situation where the reduced formation quality of the passivation layer leads to a poor passivation effect. For example, the one-dimensional size of the first texture structure is 15µm, 18µm, 20µm, 22µm, 25µm, 26µm, 27µm, 28µm, 29µm, 30µm, 31µm, 32µm, 33µm, 34µm, 35µm, 38µm, 40µm, 42µm, 45µm, 48µm, or 50µm, etc.

[0131] In some embodiments, the one-dimensional size of the second texture structure is set within a reasonable range of 2µm to 20µm to prevent the size of the second texture structure in the gap region between two adjacent second doped layers 16 on the second surface from being too large. This would result in severe etching in the gap region between the two adjacent second doped layers 16, forming too many dangling bonds, leading to severe carrier recombination, which is detrimental to improving power generation efficiency and affecting the mechanical properties of the silicon wafer. For example, the one-dimensional size of the second texture structure is 2µm, 3µm, 4µm, 5µm, 6µm, 7µm, 8µm, 9µm, 10µm, 11µm, 12µm, 13µm, 14µm, 15µm, 18µm, or 20µm, etc.

[0132] In other embodiments, when the second region 2 has a first textured structure, the second surface has a second textured structure. That is, in this technical solution, the entire surface of the second surface has a second textured structure. The first textured structure and the second textured structure can be the same or different. The first textured structure may include a base structure, which facilitates the formation of a higher-quality passivation layer in the second region 2, improves the passivation effect of the second region 2, further reduces carrier recombination on the surface of the solar cell, and improves photoelectric conversion efficiency. Using this technical solution, the second textured structure further improves the light-trapping effect of the solar cell, reduces light reflectivity, and allows more light to be reflected into and utilized by the semiconductor substrate 10, thus improving light absorption and utilization efficiency. In addition, the second surface is provided with a second texture structure, which can be applied to a battery structure in which the entire back surface is covered with a tunneling oxide layer and a doped polycrystalline silicon layer (i.e., a second doped layer). That is, a tunneling oxide layer and a doped polycrystalline silicon layer are deposited on a semiconductor substrate with a second texture structure. Since the tunneling oxide layer is difficult to grow, a smaller second texture structure is required. However, the bottom wall of the step in the second area on the front side is only used to deposit a passivation layer (e.g., aluminum oxide) and is not affected by the tunneling oxide layer. Therefore, a larger tower base structure can be set here, which helps to deposit the passivation layer better.

[0133] Optionally, the first step sidewall 3 is provided with a prismatic structure. In addition to forming a complete textured structure, the first step sidewall 3 may also form other structures, such as raised strip structures, or include prismatic structures extending from the bottom to the top of the first step structure. This prismatic structure can increase the surface area of ​​the first step sidewall 3, thereby increasing the adhesive force of the first step sidewall 3 after lamination and preventing the edge of the battery cell from delaminating.

[0134] like Figure 6 As shown, in some embodiments, the second doped layers 16 are spaced apart along the first direction on the second surface. When the second region 2 has a second type of pyramid structure, a third type of pyramid structure is provided in the spacer region between two adjacent second doped layers 16 on the second surface. Optionally, the third type of pyramid structure is smaller than the second type of pyramid structure. The base portion of the second type of pyramid has a larger volume and surface area, resulting in better light reflection and scattering effects at the top of the pyramid-like structure.

[0135] In some possible embodiments, the depth range of the spacer region between adjacent second doped layers is the same as the step depth range of the first step structure. The depth of the spacer region can be greater than or equal to the thickness of the tunneling oxide layer and the second doped layer, plus the thickness of the inner extension layer, so that the recess depth of the front and back sides can be substantially consistent, thereby enabling the front and back sides to withstand relatively consistent pressure and ensuring the mechanical properties of the solar cell.

[0136] In some embodiments, a fourth type of pyramid structure is provided on the first step sidewall 3. The size range of the fourth type of pyramid structure may be the same as or different from that of the third type of pyramid structure. This technical solution facilitates the first step sidewall 3 to have good light-trapping properties, further improving the light utilization efficiency of the solar cell. It is understood that in addition to forming complete pyramid-like structures and incomplete pyramid-like structures, other structures may also be formed on the first step sidewall 3, such as protruding strip structures or prismatic structures extending from the bottom to the top of the first step structure.

[0137] The shapes of the third and fourth types of pyramid structures mentioned above can be referenced from the shape of the first type of pyramid structure, and will not be described in detail here.

[0138] Alternatively, the size range of the fourth type of pyramid structure can be the same as that of the first type of pyramid structure.

[0139] In some embodiments, along the sidewall 3 of the first step (e.g., as Figure 2 As shown in the diagram, the first step sidewall 3 extends in a wavy or bent shape. The extension direction of the first step sidewall 3 can be the same as the extension direction of the second region, i.e., the first step sidewall 3 extends along the second direction. This technical solution increases the overall extension length of the first step sidewall 3, which is beneficial for improving the adhesion of the first step sidewall 3 after lamination, thereby improving the stability of solar energy. Of course, the first step sidewall 3 can also extend in a straight line along its extension direction; this is not limited here.

[0140] In some embodiments, the first step structure can extend continuously; specifically, the first step structure can extend continuously along a first direction. By employing this technical solution, the first doped layer 12 at any location in the first region 1 is far from the cutting position, ensuring that the passivation effect of the first doped layer 12 near the edge of the second region 2 is reduced, further reducing carrier recombination.

[0141] In other embodiments, the first step structure extends discontinuously. Specifically, the first step structure may extend discontinuously along a first direction, that is, the first step structure is intermittently set.

[0142] In some embodiments, considering that an excessively wide first step structure would reduce the area of ​​the first doped layer 12, affecting its current collection efficiency, and an excessively narrow first step structure would fail to effectively interrupt the transmission performance of the doped layer during laser cutting, and would significantly affect the passivation effect, resulting in a marked reduction in passivation efficiency, this technical solution balances these two aspects. Along the direction perpendicular to the first cutting side, the width of the first step structure is 20μm to 500μm. Alternatively, along the second direction, the width of the first step structure is 20μm to 500μm. This technical solution sets the width of the first step structure within the reasonable range of 20μm to 500μm to prevent a reduction in the area of ​​the first doped layer 12, ensuring its current collection efficiency, while simultaneously avoiding a significant reduction in the passivation effect of the first doped layer 12 during laser cutting, thus guaranteeing high power generation efficiency.

[0143] For example, the width of the first step structure is 20μm, 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 550μm, 400μm, 450μm or 500μm, etc.

[0144] It is understandable that the width of the first step structure is 20μm~500μm, and correspondingly, the overall width of the second region is 40μm~1000μm.

[0145] In some embodiments, the first step sidewall 3 is parallel to the thickness direction of the semiconductor substrate 10. Specifically, the first step sidewall 3 can be disposed perpendicular to the first surface of the semiconductor substrate 10. Such a disposal is beneficial for simplifying the processing technology and improving processing efficiency.

[0146] In other embodiments, reference is made to Figure 10 The first step sidewall 3 has an angle with the thickness direction of the semiconductor substrate 10. Specifically, the first step sidewall 3 gradually slopes towards the first region 1 from bottom to top, forming a ramp. This design ensures a smooth transition from the first step structure to the upper surface of the first doped layer 12, avoiding stress concentration near the first step sidewall 3 during lamination. This prevents microcracks in the solar cell caused by stress concentration and improves product yield. The angle between the first step sidewall 3 and the thickness direction of the semiconductor substrate 10 can be 15°, 30°, 45°, 60°, etc.

[0147] In some embodiments, multiple surfaces of the semiconductor substrate 10 are cut-side surfaces. For example, after a whole battery cell is quartered, the two middle battery slices have two cut-side surfaces. For example, as... Figure 10As shown, in this technical solution, the semiconductor substrate 10 further includes a second diced side surface, which is the side surface opposite to the first diced side surface. The first surface also includes a third region adjacent to the second diced side surface, and the first region 1 is located on the side of the third region away from the second diced side surface; that is, the third region is adjacent to the first diced side surface compared to the first region 1, and the third region is located between the first region 1 and the second diced side surface. Along the extension direction of the third region, the third region includes an edge region and a middle region. Both the edge region and the middle region of the third region include a stepped structure. The step depth of the stepped structure in the edge region of the third region is greater than the step depth of the stepped structure in the middle region of the third region, and the height of the bottom wall of the stepped structure in the middle region of the third region is lower than the height of the first doped layer. During the process of cutting to form the second diced surface, the laser cutting position is farther away from the first doped layer 12, thereby reducing the loss effect of the laser on the first doped layer 12, avoiding the formation of more dangling bonds and carrier recombination, and reducing the impact of the passivation layer on the passivation effect of the cutting region after the first doped layer is etched away by the stepped structure. In other words, the embodiments of this application can improve the passivation effect of half-cell batteries with diced surfaces on both sides.

[0148] It should be noted that the third region may have the same implementation methods as the aforementioned second region, which will not be elaborated here for ease of description.

[0149] In some embodiments, the step depth of the step structure in the middle region of the second region is the same as the step depth of the step structure in the middle region of the third region.

[0150] In other embodiments, the step depth of the step structure at the edge of the second region is the same as the step depth of the step structure at the edge of the third region. This makes the structures on both sides of the battery cell more consistent, and the mechanical properties on both sides of the battery cell are also balanced.

[0151] In some embodiments, the step width of the stepped structure in the middle region of the second region is the same as the step width of the stepped structure in the middle region of the third region. The width of the stepped structure in the second region refers to the dimension of the stepped structure along the direction perpendicular to the first cut side; the width of the stepped structure in the third region refers to the dimension of the stepped structure along the direction perpendicular to the second cut side. This configuration allows the width of the stepped structure to be set according to the laser energy forming the first cut side and the laser energy forming the second cut side, respectively, which helps to make the passivation effect of the cut regions on both sides more consistent. Furthermore, if the first or second stepped structure is too wide, it will lead to a reduction in the area of ​​the first doped layer 12, a decrease in carrier collection efficiency, and a reduction in the mechanical properties of the solar cell.

[0152] In other embodiments, the step width of the step structure in the edge region of the second region is the same as the step width of the step structure in the edge region of the third region.

[0153] It should be noted that the same width or depth of the step structure in the aforementioned embodiments can be understood as being the same within the error range.

[0154] In some embodiments, the extended shape of the first step sidewall 3 in the second region is the same as the extended shape of the step sidewall in the third region. The step structures on both sides can be completed in the same process flow, improving processing efficiency.

[0155] In some embodiments, the edge region has a first chamfer structure, and the sidewall edge of the first region and the second side has a second chamfer structure. The second side is a plane parallel to the first cut side. The size of the first chamfer structure is less than or equal to the size of the second chamfer structure. This configuration can prevent the battery cell from cracking at the corners when cutting the edge region, thus improving product yield. Furthermore, using chamfers of different sizes can be used to identify the cut edges.

[0156] In practical applications, the semiconductor substrate 10 can be made of materials such as silicon (Si), germanium (Ge), or gallium arsenide (GaAs). Obviously, in terms of conductivity type, the semiconductor substrate 10 can be an intrinsically conductive substrate, an n-type conductive substrate, or a p-type conductive substrate. Optionally, the semiconductor substrate 10 can be a p-type conductive substrate or an n-type conductive substrate. Compared to an intrinsically conductive substrate, a p-type conductive substrate or an n-type conductive substrate has better conductivity, resulting in a lower bulk resistivity in the final solar cell, thereby improving the efficiency of the solar cell.

[0157] For example, the semiconductor substrate 10 can be a p-type substrate or an n-type substrate. The n-type substrate has advantages such as high minority carrier lifetime, no light decay, and good performance in weak light.

[0158] The first doped layer 12 may include doped polycrystalline silicon. Doped polycrystalline silicon layers have higher carrier transport characteristics; therefore, when the first doped layer 12 is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which is beneficial for improving the photoelectric conversion efficiency of the solar cell. Of course, the first doped layer 12 may also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0159] The second doped layer 16 may include doped polycrystalline silicon, or the second doped layer 16 may be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0160] In some embodiments, a first interface layer 11 is disposed between the first doped layer 12 and the semiconductor substrate 10, and a second interface layer 15 is disposed between the second doped layer 16 and the semiconductor substrate 10. The passivated contact structure composed of the interface layer and the doped layer has excellent interface passivation effect and can achieve selective collection of charge carriers, reducing the carrier recombination rate in the region where the doped layer is formed on the surface of the semiconductor substrate 10, thereby further improving the photoelectric conversion efficiency of the solar cell. The material and thickness of the first interface layer 11 can be set according to the material of the first doped layer 12 and actual requirements, and the material and thickness of the second interface layer 15 can be set according to the material of the second doped layer 16 and actual requirements; no specific limitations are made here.

[0161] It should be noted that, referring to Figure 6 In this embodiment of the application, the solar cell may also omit the first interface layer.

[0162] For example, the first doped layer 12 can be a doped polysilicon layer, and the first interface layer 11 can be a tunneling oxide layer. The second doped layer 16 can be a doped polysilicon layer, and the second interface layer 15 can be a tunneling oxide layer.

[0163] The materials of the first doped layer 12 and the second doped layer 16 can be silicon (Si), germanium (Ge), silicon carbide (SiCx), or gallium arsenide (GaAs), etc. In terms of conductivity type, the first doped layer 12 can be an n-type doped layer and the second doped layer 16 can be a p-type doped layer; or, the first doped layer 12 can be a p-type doped layer and the second doped layer 16 can be an n-type doped layer.

[0164] In some possible embodiments, refer to Figures 3-10 The first passivation layer is disposed on the side wall and bottom wall of the first step structure.

[0165] For example, in the case where groove 31 is a non-through groove, the corresponding Figure 3 In the non-through shallow trench scheme shown, the first passivation layer 13 is disposed on the step sidewall and step bottom wall of the first step structure in the middle region 21 of the second region.

[0166] For example, refer to Figure 4 and Figure 9 ,correspond Figure 4 In the illustrated shallow trench design, the first passivation layer 13 is disposed on the sidewall and bottom wall of the first step structure. This first passivation layer on the bottom wall of the first step structure protects the edge portion of the bottom wall near the second step structure. Especially when the second step structure is manufactured using a destructive laser, the passivation effect of the first passivation layer on the bottom wall of the first step is significant.

[0167] In some embodiments, refer to Figures 3-10 The solar cell also includes a second passivation layer 19, which is disposed on the edge of the first region 1 near the second region 2, the second region 2, and the first cut side surface. The second passivation layer 19 is located on the side of the first passivation layer 13 facing away from the semiconductor substrate 10. The second passivation layer 19 can protect the second region 2 and the first cut side surface of the solar cell, especially by bypassing the edge from the first cut side surface to the second region 2 and the sidewall edge from the second region 2 to the first region, thus providing sufficient passivation, reducing recombination sites, and improving the photoelectric conversion efficiency of the solar cell. The technical characteristics such as the number of layers and material of the second passivation layer 19 can be referred to the description of the first passivation layer 13. For example, the second passivation layer 19 can be a single-layer structure, and the single-layer structure is an aluminum oxide layer.

[0168] For example, in conjunction with the above Figure 3 In the embodiment shown, the second passivation layer 19 can protect the second region 2 and the first cut side of the battery cell, especially the bottom wall of the stepped structure that extends from the first cut side to the middle region of the second region, the side wall of the stepped structure that extends from the middle region of the second region to the edge of the first region, the bottom wall of the stepped structure that extends from the first cut side to the edge region of the second region, and the side wall of the stepped structure that extends from the edge region of the second region to the edge of the first region.

[0169] For example, in conjunction with the above Figure 4 and Figure 9 In the embodiment shown, the second passivation layer 19 can protect the second region 2 and the first cut side of the solar cell. In particular, it can bypass the edge of the first cut side to the bottom wall of the second step structure, the edge of the second step structure sidewall to the bottom wall of the first step structure, and the edge of the first step structure sidewall to the first region, thus providing sufficient passivation, reducing recombination sites, and improving the photoelectric conversion efficiency of the solar cell.

[0170] In other embodiments, such as Figures 6-8As shown, a third passivation layer 17 is disposed on the second surface, and a second passivation layer 19 is disposed on the first cut side. The second passivation layer 19 extends to the vicinity of the edge of the second surface and is located on the side of the third passivation layer 17 facing away from the semiconductor substrate 10. The third passivation layer 17 not only protects the second surface of the solar cell, preventing moisture or oxygen from penetrating into the cell and extending the lifespan of the solar cell, but also reduces reflection, improving the light absorption and utilization rate. The number of layers and material of the third passivation layer 17 can be referenced from the description of the first passivation layer 13. For example, the third passivation layer 17 can be a single-layer structure, and the single-layer structure is a silicon nitride layer. The second passivation layer can passivate the first cut side and the back side in the same step, thereby further improving the passivation effect and saving process steps. Alternatively, the second passivation layer can wrap around the edge of the first region of the first surface and the edge of the second surface in the same step, thereby further improving the passivation effect and saving process steps.

[0171] It should be noted that the second passivation layer on the first cut side can be the same passivation layer as in the aforementioned embodiment, that is, the second passivation layer on the first cut side can passivate both the front and back sides simultaneously.

[0172] This application also provides another type of solar cell, such as... Figure 11 As shown, in some embodiments, such as Figure 11 As shown, the shallow grooves at the edge of the second region can also be configured as Y-shaped grooves. This configuration avoids issues such as chipping at the corners of the solar cells when cutting the edge areas, thus improving product yield. It is understood that cutting along the Y-shaped groove results in a chamfered edge on the solar cell.

[0173] In some embodiments, the edge region has a first chamfer structure, and the sidewall edge of the first region and the second side has a second chamfer structure. The second side is a plane parallel to the first cut side. The size of the first chamfer structure is less than or equal to the size of the second chamfer structure. This configuration can prevent the battery cell from cracking at the corners when cutting the edge region, thus improving product yield. Furthermore, using chamfers of different sizes can be used to identify the cut edges.

[0174] Figure 12 A schematic diagram of a component according to an embodiment of this application is shown. For example... Figure 12 As shown, an electrical connector is provided between adjacent first solar cells 121 and second solar cells 122. The first solar cell 121 is the solar cell involved in the aforementioned embodiments. The connection method of the electrical connector is as follows: Figure 12As shown, from the first surface and second side surface of the first solar cell 121, and then through the second surface of the second solar cell, the second side surface is the side surface opposite to the first cut surface. The starting end of the electrical connector can be at a distance (e.g., the distance between the edge of the first region and the boundary between the first and second regions) from the edge of the first region. Figure 12 d) is greater than the width of the stepped structure in the middle area. Considering that there may be burrs or other protrusions at the starting end of the electrical connector, the starting end of the electrical connector is set at a certain distance from the edge. This will not damage the passivation layer in the cutting area and will ensure the passivation effect in the cutting area.

[0175] Alternatively, the second solar cell 122 may also be the solar cell involved in the foregoing embodiments.

[0176] Optionally, the second side is a non-cut side. That is, as shown below. Figure 12 As shown, one side of the first solar cell 121 is a cut surface, and the opposite side is a non-cut surface. In this way, the starting end of the electrical connector starts from the front side near the cut surface and extends around to the non-cut surface, causing compression on the non-cut side. Compared with the electrical connector wrapping around the cut side with a stepped structure to compress the cut side, the embodiments of this application can avoid affecting the mechanical properties of the solar cell.

[0177] It is understandable that the second side surface can also be a cut surface, for example, it can be the aforementioned second cut side surface.

[0178] It is also understandable that electrical connectors can be solder strips.

[0179] In some possible embodiments, the distance between the starting end of the electrical connector and the edge of the first region (i.e., the boundary between the first and second regions) is greater than or equal to 1 mm.

[0180] This invention also provides a first method for manufacturing a solar cell, which can prepare the solar cell described in any of the above embodiments. The method for manufacturing the solar cell includes the following steps:

[0181] S1: Provide a semiconductor substrate 10, the semiconductor substrate 10 including a first surface and a second surface opposite to each other, the first surface including a first region 1 and a second region 2.

[0182] Among them, the first region 1 is used to form the first type of pyramid structure.

[0183] Prior to this step, in some embodiments, the semiconductor substrate 10 may be immersed in a polishing and cleaning machine to remove the cutting damage layer of the semiconductor substrate 10 using a polishing slurry. Furthermore, in this step, the morphology of the first and second surfaces of the semiconductor substrate 10 after polishing and cleaning can be adjusted by regulating parameters such as temperature, time, type of cleaning slurry, and concentration of the cleaning slurry. It should be noted that in some examples, the polishing and cleaning step may be omitted.

[0184] S2: A first type of pyramid structure is formed on the first surface;

[0185] In this step, a first-type pyramid structure can be formed on the first surface by texturing.

[0186] S3: A first doped layer 12 and a first doped silicon glass layer are formed on the first surface having the first type of pyramid structure.

[0187] The first doped layer 12 can be additionally formed on the first surface of the semiconductor substrate 10 by deposition technology, or it can be formed within the semiconductor substrate 10 by diffusion, ion implantation, or other methods. During the formation of the first doped layer 12, a first doped silicon glass layer is formed simultaneously.

[0188] It should be noted that, in the case where the solar cell also includes a first interface layer 11, the first interface layer 11 can be formed by deposition and etching processes before forming the first doped layer.

[0189] S4: The density of the first doped silicon glass layer in the second region 2 is reduced by laser irradiation.

[0190] In this step, the first doped silicon glass layer in the second region 2 is irradiated with a laser to reduce the density of the first doped silicon glass layer in the second region 2, which makes it easier to remove the first doped silicon glass layer in the second region 2 in the subsequent process.

[0191] S5: The second surface is polished in a groove and a portion of the first doped silicon glass layer in the second region 2 is removed, and a groove is formed in the second region 2 that is recessed into the second surface.

[0192] In this step, the first doped silicon glass layer in the second region 2 can be removed by etching with an etchant. With the first doped silicon glass layer formed on both the second surface and side surfaces, it is first removed from both surfaces using a chain conveyor. Then, the cell is polished using a trough-type machine to polish the second surface and remove the first doped silicon glass layer in the second region 2, thus forming a groove in the second region 2. In this way, polishing and groove formation are achieved in a single process step, reusing the polishing step during groove formation, saving process steps.

[0193] S6: A second doped layer 16 is formed on the second surface, the second doped layer 16 having the opposite conductivity type to the first doped layer 12.

[0194] The second doped layer 16 can be additionally formed on the second surface of the semiconductor substrate 10 by deposition technology, or it can be formed within the semiconductor substrate 10 by diffusion, ion implantation, or other methods. The second doped layer 16 can be disposed entirely or partially on the second surface. When the second doped layer 16 is partially disposed on the second surface, the second doped layer 16 can be spaced apart along the first direction on the second surface; when the second doped layer 16 extends along the second direction, the second doped layer 16 can be distributed in the shape of strips, a shaped pattern, or the like.

[0195] It should be noted that, in the case where the solar cell also includes a second interface layer 15, the second interface layer 15 can be formed by deposition and etching processes before forming the second doped layer.

[0196] When the second doped layer 16 is a doped polycrystalline silicon layer and the second interface layer 15 is a tunneling oxide layer, a tunneling oxide layer and an intrinsic polycrystalline silicon layer can be formed sequentially on the second surface first, and then the intrinsic polycrystalline silicon layer can be diffused to obtain a doped polycrystalline silicon layer. During the formation of the doped polycrystalline silicon layer, a second doped glass silicon layer can be formed simultaneously.

[0197] S7: Remove the second doped silicon glass layer on the second surface and form a first textured structure or a second type of pyramid structure within the groove, wherein the height of the bottom wall of the groove is lower than the height of the first doped layer along the thickness direction of the semiconductor substrate. This step allows for the simultaneous removal of the remaining first doped silicon glass layer and all of the second doped silicon glass layer on the first surface.

[0198] Step S7 first removes part of the first doped silicon glass layer on the front side using a chain-type process, and then uses a tank-type etching device to completely remove the first doped silicon glass layer and the first doped layer in the groove. In other words, multiple cleaning processes are required to remove the relatively thick first doped silicon glass layer in the groove.

[0199] S8: A first electrode 14 is formed on the first doped layer 12, and a second electrode 18 is formed on the second doped layer 16.

[0200] The first electrode 14 and / or the second electrode 18 can be formed using processes such as screen printing, electroplating, sputtering, or vapor deposition. The first electrode 14 is electrically connected to the first doped layer 12 to conduct the current collected in the first doped layer 12, and the second electrode 18 is electrically connected to the second doped layer 16 to conduct the current collected in the second doped layer 16. The first electrode 14 and the second electrode 18 can be made of silver, copper, aluminum, or their alloys. The first electrode 14 and the second electrode 18 can be the same or different.

[0201] S9: A groove is formed in the edge region of the second region, the groove having a greater depth than the groove having a greater depth.

[0202] The second region includes a middle region and an edge region extending along the second region. In this step, before cutting the battery cell, a groove can be formed in the edge region of the second region of the entire battery cell. The depth of the groove is greater than the depth of the recess. This reduces the thickness of the battery structure to a certain extent along the cutting direction. Subsequently, the cutting line can be automatically disconnected by non-destructive laser and water spraying to complete the cutting. This cutting method has high cutting efficiency and accuracy, which can ensure the quality of the finished product after cutting.

[0203] Understandably, in S9, grooves can be formed in the edge region using a laser.

[0204] In some embodiments, forming a groove in the edge region of the second region using a laser includes: forming the groove in the edge region within the groove.

[0205] In this case, the groove can be a through groove. When creating a through groove, the requirements for laser alignment can be reduced, thereby reducing the complexity of the process.

[0206] S10: Cut the semiconductor substrate 10 along the groove to obtain multiple solar cells.

[0207] Specifically, a laser can be used to cut the semiconductor substrate 10 along the groove to form multiple solar cells. The cut grooves form stepped structures on two solar cells respectively. Along the thickness direction of the semiconductor substrate, the height of the bottom wall of the stepped structure is lower than the height of the first doped layer, which facilitates the dicing of the cell from the edge region. The bottom wall height of the stepped structure in the middle region is lower than the height of the first doped layer, which is equivalent to the cell thickness along the dicing direction being partially or completely reduced, thereby further reducing the difficulty of dicing. In addition, the bottom wall of the stepped structure in the middle region near the cutting surface is lower than the height of the first doped layer 12, so the dicing position is farther from the first doped layer 12 during the cutting process. Since more dangling bonds are formed during the cutting process, being farther away from the first doped layer 12 can prevent charge carriers from approaching the cutting area, reduce charge carrier recombination, and improve photoelectric conversion efficiency. In addition, in this embodiment, the process of reusing the polishing back side is combined with the first cleaning of the first doped silicon glass layer in the groove, saving process steps and reducing process costs.

[0208] In some embodiments, S6 forming the second doped layer 16 on the second surface includes: S61 forming the second doped layer 16 and the second doped glass silicon layer on the second surface; S62 using laser irradiation to reduce the density of the second doped glass silicon layer in the gap region between two adjacent second doped layers 16; S63 removing all the second doped glass silicon layers and forming a second texture structure in the gap region between two adjacent second doped layers 16. Specifically, in this technical solution, the second doped glass silicon layer is formed simultaneously with the formation of the second doped layer 16. The second doped glass silicon layer is irradiated at intervals using laser irradiation to reduce the density and spacing of the second doped glass silicon layer, which facilitates subsequent removal. The second doped glass silicon layer is removed by etching with an etchant, and a second texture structure is formed in the gap region between two adjacent second doped layers 16, and the first texture structure is formed in the groove. Simultaneously with the removal of the second doped glass silicon layer, the remaining first doped glass silicon layer on the first surface can be removed together, specifically using chain cleaning and tank cleaning methods. This technical solution forms a second textured structure within the spaced region of the second surface, which improves the light-trapping effect of the light-facing surface, reduces light reflectivity, and also reduces lateral recombination of charge carriers. The second textured structure can be a tower-based structure, and the size of the tower-based structure formed within the spaced region can differ from the size of the tower-based structures formed on the second surface, side surfaces, and grooves of the semiconductor substrate 10.

[0209] In some embodiments, S6 forming a second doped layer 16 on the second surface includes: S61 forming a second doped layer 16 and a second doped glass silicon layer on the second surface; S62 using laser irradiation to reduce the density of the second doped glass silicon layer in the spacer region between two adjacent second doped layers 16; S63 removing the second doped glass silicon layer and forming a pyramid-like structure in the spacer region between two adjacent second doped layers 16 and in the groove.

[0210] This application also provides a second method for manufacturing a solar cell, which can prepare the solar cell described in any of the above embodiments. The method for manufacturing the solar cell includes the following steps:

[0211] S1': Provide a semiconductor substrate 10, the semiconductor substrate 10 including a first surface and a second surface opposite to each other, the first surface including a first region 1 and a second region 2.

[0212] This step S1' can be referred to the description of step S1 above, and will not be repeated here.

[0213] S2': A first type of pyramid structure is formed on the first surface.

[0214] Step S2' can be referred to the description of step S2 above, and will not be repeated here.

[0215] S3': A first doped layer 12 and a first doped silicon glass layer are formed on the first surface having the first type of pyramid structure.

[0216] This step S3' can be referred to the description of step S3 above, and will not be repeated here.

[0217] S4': A second doped layer 16 and a second doped silicon glass layer are formed on the second surface. The second doped layer 16 has the opposite conductivity type to the first doped layer 12.

[0218] The second doped layer 16 can be additionally formed on the second surface of the semiconductor substrate 10 by deposition technology, or it can be formed within the semiconductor substrate 10 by diffusion, ion implantation, or other methods. A second doped silicon glass layer is formed simultaneously with the formation of the second doped layer 16. The second doped layer 16 can be locally disposed on the second surface, or it can be spaced apart along a first direction on the second surface; the second doped layer 16 can extend along a second direction, or it can be distributed in strip, U-shape, or similar shapes.

[0219] It should be noted that, in the case where the solar cell also includes a second interface layer 15, the second interface layer 15 can be formed by deposition and etching processes before forming the second doped layer.

[0220] When the second doped layer 16 is a doped polycrystalline silicon layer and the second interface layer 15 is a tunneling oxide layer, a tunneling oxide layer and an intrinsic polycrystalline silicon layer can be formed sequentially on the second surface first, and then the intrinsic polycrystalline silicon layer can be diffused to obtain a doped polycrystalline silicon layer. During the formation of the doped polycrystalline silicon layer, a second doped glass silicon layer can be formed simultaneously.

[0221] S5': Using a laser, the density of the first doped silicon glass layer and the spacer of the second doped silicon glass layer in the second region 2 is reduced.

[0222] In the same step, laser irradiation reduces the density of the second doped silicon glass layer in the spacer region between the first doped silicon glass layer and the adjacent second doped layer 16 in the second region 2. Specifically, the first doped silicon glass layer in the second region 2 can be lasered first, and then the solar cell can be flipped over to laser the second doped silicon glass layer in the spacer region. Alternatively, the second doped silicon glass layer in the spacer region can be lasered first, and then the solar cell can be flipped over to laser the first doped silicon glass layer in the second region 2.

[0223] S6': Remove the first doped silicon glass layer and the second doped silicon glass layer, and form a groove that is recessed toward the second surface in the second region 2, and form a first texture structure or a second type of pyramid structure in the groove, and the height of the bottom wall of the groove is lower than the height of the first doped layer along the thickness direction of the semiconductor substrate.

[0224] In this step, the first and second doped silicon glass layers can be removed by etching with an etchant, and a groove is formed in the second region 2, recessing into the second surface. A first textured structure or a second type of pyramid structure is also formed in the second region 2. Furthermore, the removal of the doped silicon glass layers and the formation of the groove are achieved in a single process step, reusing the removal operation during groove formation, thus saving process steps.

[0225] S7': A first electrode is formed on the first doped layer, and a second electrode is formed on the second doped layer;

[0226] S8': A groove is formed in the edge region of the second region, the groove having a greater depth than the groove having a greater depth; the second region includes a middle region and the edge region extending along the direction of extension of the second region.

[0227] Understandably, in S8, grooves can be formed in the edge region using a laser.

[0228] S9': Cut the semiconductor substrate 10 along the trench to obtain multiple solar cells. A first step structure is formed in the second region 2 of the solar cell. Along the thickness direction of the semiconductor substrate 10, the height of the bottom wall of the first step structure is lower than the height of the first doped layer.

[0229] This step S9' can be referred to the description of step S10 above, and will not be repeated here.

[0230] The main difference between the second method of manufacturing solar cells and the first method of manufacturing solar cells is that, in the same step, laser irradiates the first doped silicon glass layer in the second region 2 and the second doped silicon glass layer in the spacer region between adjacent second doped layers 16. This facilitates the subsequent removal of the doped silicon glass layers in the second region 2 and the spacer region, thereby avoiding the need to add a separate laser step. In other words, the laser step that would normally be used to create the spacer region on the back side is reused.

[0231] It should be noted that in the embodiments of this application, the spacing area in step S5' can also be made on the front side, or on both the front and back sides. This application does not limit this.

[0232] In some embodiments, during the removal of the second doped glass silicon layer, a second texture structure is formed in the spacer region between two adjacent second doped layers 16. Specifically, the second doped glass silicon layer can be removed by wet etching, and a portion of the semiconductor substrate 10 is etched to form the second texture structure in the spacer region, which helps to improve the light-trapping effect of the light-facing surface and reduce the light reflectivity.

[0233] In some embodiments, during the removal of the second doped glass silicon layer, a third type of pyramid structure is formed in the spacer region between two adjacent second doped layers 16. Specifically, the second doped glass silicon layer can be removed by wet etching, and a portion of the semiconductor substrate 10 is etched to form a third type of pyramid structure in the spacer region, which helps to improve the light-trapping effect of the light-facing surface and reduce the light reflectivity. The base portion of the pyramid-like structure has a large volume and a large surface area, which helps to ensure the passivation effect of the passivation layer covering the base of the pyramid-like structure, while the top of the pyramid-like structure has a better effect on light reflection and scattering. In this technical solution, steps S61'-S62' are the same as S61-S62 in the above technical solution, and the specific details can be found in the previous description of S61 and S62. In step S63', a chain cleaning method can be used to remove part of the second doped glass silicon layer, and then texturing is performed to form a pyramid-like structure in the spacer region and the trench 4. The base of the pyramid-like structure has a large volume and surface area, which helps to ensure the passivation effect of the passivation layer covering the base of the pyramid-like structure, while the top of the pyramid-like structure has a better effect on the reflection and scattering of light.

[0234] In the two methods for manufacturing the aforementioned solar cells, prior to step S8 or S7', the method may further include: forming a first passivation layer 13 on a first surface, the first passivation layer 13 being located on the side of the first doped layer 12 facing away from the semiconductor substrate 10; and forming a third passivation layer 17 on a second surface, the third passivation layer 17 being located on the side of the second doped layer 16 facing away from the semiconductor substrate 10. In this technical solution, the first electrode 14 passes through the first passivation layer 13 and is electrically connected to the first doped layer 12, and the second electrode 18 passes through the third passivation layer 17 and is electrically connected to the second doped layer 16.

[0235] After step S10 or S9', the method for manufacturing a solar cell further includes forming a second passivation layer 19 at the edge of the first region 1 near the second region 2, the second region 2 and the first cut side, and the second passivation layer 19 is located on the side of the first passivation layer 13 away from the semiconductor substrate 10.

[0236] The structure, material, and function of the first passivation layer 13, the second passivation layer 19, and the third passivation layer 17 can be referred to in the previous text and will not be repeated here.

[0237] In some embodiments, the laser may be a green laser, and the laser spot diameter or spot width is 105μm~410μm. For example, the laser spot diameter or spot width is 105μm, 120μm, 150μm, 200μm, 220μm, 250μm, 280μm, 300μm, 320μm, 350μm, 380μm, 400μm or 410μm, etc.

[0238] The laser frequency is 200KHz~800KHz. For example, the laser frequency is 200KHz, 250KHz, 300KHz, 350KHz, 400KHz, 450KHz, 500KHz, 550KHz, 600KHz, 650KHz, 700KHz or 8000KHz, etc.

[0239] The power of the laser can range from 50W to 150W. For example, the power of the laser can be 50W, 55W, 60W, 65W, 70W, 75W, 80W, 85W, 90W, 95W, 100W, 105W, 110W, 115W, 120W, 125W, 130W, 140W, or 1500W.

[0240] The power density of the laser ranges from 100 m / cm² to 800 m / cm². For example, the power density of the laser is 100 m / cm², 200 m / cm², 300 m / cm², 400 m / cm², 500 m / cm², 600 m / cm², 700 m / cm², or 800 m / cm².

[0241] During laser irradiation, the overlap rate of adjacent laser spots is 30% to 50%. For example, the overlap rate of adjacent laser spots is 30%, 35%, 40%, 45%, or 50%.

[0242] Laser engraving speeds range from 20,000 mm / s to 40,000 mm / s. For example, laser engraving speeds are 20,000 mm / s, 22,000 mm / s, 25,000 mm / s, 27,000 mm / s, 29,000 mm / s, 30,000 mm / s, 32,000 mm / s, 35,000 mm / s, 38,000 mm / s, or 40,000 mm / s.

[0243] Of course, the laser used in the first method of manufacturing solar cells can be different or the same as the laser used in the second method of manufacturing solar cells, and this is not limited here.

[0244] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0245] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A solar cell, characterized in that, include: A semiconductor substrate includes a first surface and a second surface opposite to each other, a first cut side surface connecting the first surface and the second surface, the first surface including a first region and a second region adjacent to the first cut side surface; along the extension direction of the second region, the second region includes an edge region and a middle region, both the edge region and the middle region including a stepped structure recessed into the second surface, the step depth of the stepped structure of the edge region of the second region being greater than the step depth of the stepped structure of the middle region of the second region; A first doped layer is disposed on the first region; along the thickness direction of the semiconductor substrate, the height of the bottom wall of the stepped structure in the middle region of the second region is lower than the height of the first doped layer; A first passivation layer is disposed on the side of the first doped layer away from the semiconductor substrate, and on the second region; The first doped layer forms a PN junction with the semiconductor substrate.

2. The solar cell according to claim 1, characterized in that, The stepped structure in the middle region and the stepped structure in the edge region are connected to form a first stepped structure, and the bottom wall of the stepped structure in the edge region is provided with a second stepped structure.

3. The solar cell according to claim 1, characterized in that, The stepped structure in the middle area is a first stepped structure, and the stepped structure in the edge area is a second stepped structure. The step depth of the second stepped structure is greater than that of the first stepped structure.

4. The solar cell according to claim 2 or 3, characterized in that, The first region is provided with a first type of pyramid structure, the bottom wall of the first step structure of the second region is provided with a first texture structure, and the second surface is provided with a second texture structure. The one-dimensional dimension of the first texture structure is larger than the one-dimensional dimension of the second texture structure.

5. The solar cell according to claim 4, characterized in that, The solar cell further includes a second doped layer disposed on the second surface, the second doped layer having an opposite conductivity type to the first doped layer, and the entire second surface being provided with the second texture structure; or The solar cell further includes a second doped layer disposed at intervals on the second surface, the second doped layer having the opposite conductivity type to the first doped layer, and the second texture structure being disposed in the interval region between two adjacent second doped layers on the second surface.

6. The solar cell according to claim 2 or 3, characterized in that, The solar cell further includes a second doped layer disposed at intervals on the second surface. The second doped layer has the opposite conductivity type to the first doped layer. The first region is provided with a first type of pyramid structure, and the bottom wall of the first step structure in the second region is provided with a second type of pyramid structure.

7. The solar cell according to claim 6, characterized in that, The one-dimensional dimension of the first type of pyramid structure is larger than the one-dimensional dimension of the second type of pyramid structure; and / or A third type of pyramid structure is disposed in the spacer region between two adjacent second doped layers on the second surface, and the one-dimensional dimension of the third type of pyramid structure is smaller than the one-dimensional dimension of the second type of pyramid structure; and / or The depth range of the spacing region between two adjacent second doped layers on the second surface is the same as the step depth range of the first stepped structure.

8. The solar cell according to claim 2 or 3, characterized in that, Along the extending direction of the sidewall of the first step, the sidewall of the first step is wavy or bent; and / or, Along the extending direction of the sidewall of the first step, the first step structure extends continuously or intermittently; and / or, Along the direction perpendicular to the first cut side, the width of the first step structure is 20μm~500μm.

9. The solar cell according to claim 2 or 3, characterized in that, The first step sidewall is parallel to the thickness direction of the semiconductor substrate; or, The first step sidewall has an angle with the thickness direction of the semiconductor substrate, the angle being 15° to 60°.

10. The solar cell according to claim 2 or 3, characterized in that, The first passivation layer is disposed on the step sidewall and the step bottomwall of the first step structure.

11. The solar cell according to claim 10, characterized in that, A second passivation layer is provided on the edge of the first region near the second region, the second region and the first cut side, and the second passivation layer is located on the side of the first passivation layer away from the semiconductor substrate.

12. The solar cell according to claim 4, characterized in that, The first texture structure has a one-dimensional size of 15um to 50um, and the second texture structure has a one-dimensional size of 2um to 20um.

13. The solar cell according to claim 2 or 3, characterized in that, The width of the first step structure is greater than the width of the second step structure.

14. The solar cell according to claim 2 or 3, characterized in that, Along the thickness direction of the semiconductor substrate, the step depth of the intermediate region of the first stepped structure is 2µm to 10µm; and / or The step depth of the edge region of the second step structure is 30%H~100%H, where H is the thickness of the solar cell.

15. The solar cell according to claim 1, characterized in that, The second surface is provided with a third passivation layer, the first cut side is provided with a second passivation layer, and the second passivation layer extends to the edge region of the second surface and is located on the side of the third passivation layer away from the semiconductor substrate.

16. The solar cell according to claim 1, characterized in that, The semiconductor substrate further includes a second diced side surface, which is disposed opposite to the first diced side surface. The first surface also includes a third region adjacent to the second diced side surface, and the first region is located on the side of the third region away from the second diced side surface. Along the extension direction of the third region, the third region includes an edge region and a middle region. Both the edge region and the middle region include a stepped structure. The step depth of the stepped structure in the edge region of the third region is greater than the step depth of the stepped structure in the middle region of the third region. The height of the bottom wall of the stepped structure in the middle region of the third region is lower than the height of the first doped layer.

17. The solar cell according to claim 16, characterized in that, The step depth of the stepped structure in the middle region of the second region is the same as the step depth of the stepped structure in the middle region of the third region; and / or The step depth of the step structure at the edge of the second region is the same as the step depth of the step structure at the edge of the third region; and / or, The step width of the stepped structure in the middle area of ​​the second region is the same as the step width of the stepped structure in the middle area of ​​the third region; and / or The step width of the step structure in the edge region of the second region is the same as the step width of the step structure in the edge region of the third region.

18. A method for manufacturing a solar cell, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including opposing first and second surfaces, the first surface including a first region and a second region; A first doped layer and a first doped silicon glass layer are formed on the first surface; Laser irradiation is used to reduce the density of the first doped silicon glass layer in the second region. The second surface is polished in a groove and a portion of the first doped silicon glass layer in the second region is removed, and a groove is formed in the second region that is recessed into the second surface; A second doped layer is formed on the second surface, the second doped layer having an opposite conductivity type to the first doped layer; Remove the second doped silicon glass layer from the second surface, and along the thickness direction of the semiconductor substrate, the height of the bottom wall of the groove is lower than the height of the first doped layer; A first electrode is formed on the first doped layer, and a second electrode is formed on the second doped layer; A groove is formed at the edge of the second region, the depth of the groove being greater than the depth of the recess. Along the trench, the semiconductor substrate is sliced ​​to obtain multiple solar cells; The first doped layer forms a PN junction with the semiconductor substrate.

19. A method for manufacturing a solar cell, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including opposing first and second surfaces, the first surface including a first region and a second region; A first doped layer and a first doped silicon glass layer are formed on the first surface; A second doped layer and a second doped silicon glass layer are formed on the second surface, wherein the second doped layer has the opposite conductivity type to the first doped layer. Using a laser, the density of the first doped silicon glass layer and the spacer in the second region is reduced; Remove the first doped silicon glass layer and the second doped silicon glass layer, and form a groove in the second region that is recessed toward the second surface, wherein the height of the bottom wall of the groove is lower than the height of the first doped layer along the thickness direction of the semiconductor substrate; A first electrode is formed on the first doped layer, and a second electrode is formed on the second doped layer; A groove is formed at the edge of the second region, the depth of the groove being greater than the depth of the recess. The semiconductor substrate is sliced ​​along the trench to obtain multiple solar cells; The first doped layer forms a PN junction with the semiconductor substrate.

20. A photovoltaic module, characterized in that, include: Multiple battery strings connected in series and / or in parallel, each battery string comprising: an electrical connector and a first solar cell and a second solar cell, wherein the first solar cell is a solar cell according to any one of claims 1 to 17, or a solar cell obtained by the manufacturing method according to claim 18 or 19, the first solar cell and the second solar cell are connected by the electrical connector, the distance between the starting end of the electrical connector and the edge of the first region of the first solar cell is greater than the width of the stepped structure of the middle region of the second region, and the conductive element passes through the first surface and the second side surface of the first solar cell, and through the second surface of the second solar cell, wherein the second side surface is the side surface opposite to the first cut surface in the first solar cell, and the edge of the first region is the boundary edge between the first region and the second region.

21. The photovoltaic module according to claim 20, characterized in that, The distance between the starting end of the electrical connector and the edge of the first region is greater than or equal to 1 mm.

22. The photovoltaic module according to claim 20, characterized in that, The second side is a non-cut surface.

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