LDPC decoder oriented to CCSDS standard and decoding method thereof

Abstract

The invention relates to an LDPC (Low Density Parity Check) decoder oriented to a CCSDS (Consultative Committee for Space Data System) standard and a decoding method thereof, relates to the technical field of satellite communication and channel coding, and aims to solve the technical problems of insufficient parallelism and low resource utilization rate of a satellite communication LDPC decoder in the prior art. The LDPC decoder for the CCSDS standard comprises a frame input module, a control module, an initial probability storage module, a check node calculation module, a variable node calculation module and a frame output module. The LDPC decoder facing the CCSDS standard and the decoding method thereof are suitable for efficient decoding of long-frame data in satellite communication, dynamic block storage architecture, hybrid iterative decoding algorithm and configurable control module collaborative design, balance of decoding algorithm performance and complexity is achieved through storage design optimization, the algorithm flexibility is improved through a configurable strategy, and the decoding efficiency is improved. And the contradiction between the efficiency and resources of long-frame LDPC decoding in satellite communication is systematically solved.

Description

Technical Field

[0001] The present invention relates to the technical field of satellite communication and channel coding, and in particular to an LDPC decoder oriented to the CCSDS standard and a decoding method thereof. Background Art

[0002] Low-density parity-check (LDPC) codes are forward error-correcting codes proposed by Robert Gallager of MIT in his 1963 doctoral dissertation. LDPC codes have sparse parity check matrices that can approach the Shannon limit. They are also simple to describe and implement, making them suitable for hardware implementation.

[0003] Existing satellite communication LDPC decoders have the following technical defects:

[0004] Insufficient parallelism: Traditional decoders use a single storage structure, which makes it difficult to meet the high throughput requirements of long frame data (such as 8176 bits / frame), resulting in extended decoding time.

[0005] Low resource utilization: When implementing FPGA, the iteration process of check nodes and variable nodes requires frequent reading and writing of storage units, which consumes a lot of hardware resources. Summary of the Invention

[0006] The present invention aims to solve the technical problems of insufficient parallelism and low resource utilization of satellite communication LDPC decoders in the prior art, and provides an LDPC decoder and a decoding method thereof oriented to the CCSDS standard.

[0007] In order to solve the above technical problems, the technical solutions of the present invention are as follows:

[0008] An LDPC decoder oriented to the CCSDS standard, comprising:

[0009] Frame input module: used to receive initial probability data and store it in blocks into multiple RAM modules;

[0010] Control module: performs corresponding calculation and control operations according to the jump of the state machine;

[0011] Initial probability storage module: encapsulates multiple RAM modules to store and read initial probability data; reads data through the read port for calculation of check nodes and variable nodes;

[0012] Check node calculation module: used to implement the update calculation of the check node; according to the flag signal, it distributes the input data to the corresponding check node calculation unit for processing, and stores the calculation results back to the original RAM module;

[0013] Variable node calculation module: used to implement update calculation of variable nodes;

[0014] Frame output module: used to output decision signals; integrate and sort the input decision information, and output continuous decoded data according to the clock beat.

[0015] In the above technical solution, in the frame input module, one data is input in each clock cycle, and the corresponding storage address and enable signal are output.

[0016] In the above technical solution, in the control module, the state machine includes the following states corresponding to different decoding stages: standby state, initialization state, check node calculation state, variable node calculation state and decoding completion output state.

[0017] In the above technical solution, in the variable node calculation module, each variable node calculation unit inputs four paths of check node data and one path of initial probability data, and outputs four paths of updated variable node data and one path of decision data.

[0018] In the above technical solution, the control module calculates the base address offset in real time according to the input code length, and realizes the dynamic allocation of the storage space of the RAM module by combining shift operation and modular operation;

[0019] The control module also includes a buffer for preparing the address of data to be processed next time, which adopts a dual-port RAM structure and loads two adjacent frame address mapping tables in advance, so that the CNU calculation stage and the address pre-fetch operation are executed in parallel.

[0020] In the above technical solution, in the RAM module, even cycles access the initialization RAM group, and odd cycles access the iteration RAM group, and the read-write conflict is eliminated through the time slice rotation mechanism.

[0021] In the above technical solution, the check node calculation module adopts a 14-stage pipeline structure, each stage contains 8 Min-Sum algorithm processing units, and the critical path delay model is: T_cnu = T_mu + log2(N) × T_ad, N=112;

[0022] Wherein, T_cnu represents the total critical path delay of the check node calculation module; T_mu represents the operation delay time of the multiplier; and T_ad represents the operation delay time of the adder.

[0023] In the above technical solution, the GF(2^4) multiplier in the variable node calculation module adopts a polynomial basis optimization structure, and the operation logic is simplified to a three-stage pipeline: GF_MUL = (a⊗b) ⊕ ((a<<1) & 0x0F) ⊕ ((b<<1) &0x0F).

[0024] In the above technical solution, in the RAM module, the RAM array is divided into 16 independent power domains, and the clock of the corresponding area is automatically turned off when no access operation is detected for 5 consecutive cycles.

[0025] A decoding method applicable to the above-mentioned LDPC decoder oriented to the CCSDS standard comprises the following steps:

[0026] Step 1: The input initial probability data is stored in blocks, a set of channel soft information is input for each clock, and the information is stored in the RAM module;

[0027] Step 2: After storing the initial probability data, read and process the initial probability data; read the initial probability data to be used as the data source for the first update of the verification node calculation module. After the verification node calculation module is updated, the variable node calculation module needs to read the initial probability data for each iteration to perform accumulation;

[0028] Step 3: Add flag information when reading the initial probability data;

[0029] Step 4: The verification node calculation module performs update calculations;

[0030] Step 5: The variable node calculation module performs update calculations;

[0031] Step 6: After decoding, output the decision codeword.

[0032] The present invention has the following beneficial effects:

[0033] The LDPC decoder and decoding method for the CCSDS standard of the present invention are suitable for efficient decoding of long-frame data in satellite communications. The dynamic block storage architecture, hybrid iterative decoding algorithm, and configurable control module are collaboratively designed. By optimizing storage design, achieving a balance between decoding algorithm performance and complexity, and enhancing algorithm flexibility through configurable strategies, the system systematically resolves the efficiency and resource conflicts of long-frame LDPC decoding in satellite communications. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] Figure 1 This is a schematic diagram of the decoder state transition.

[0036] Figure 2 Schematic diagram of the LDPC decoder functional module of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be described in detail below with reference to the accompanying drawings.

[0038] The LDPC decoder of the present invention, oriented to the CCSDS standard, is suitable for efficient decoding of long-frame data in satellite communications. It features a collaborative design of a dynamic block storage architecture, a hybrid iterative decoding algorithm, and a configurable control module. It mainly includes the following modules:

[0039] Frame Input Module: Responsible for receiving the initial probability data and storing it in blocks into multiple RAM modules. Each clock cycle inputs one data and outputs the corresponding storage address and enable signal.

[0040] Control module: Executes calculations and control operations based on the state machine's transitions. The state machine includes states such as standby, initialization, check node calculation, variable node calculation, and decoding completion output, corresponding to different decoding stages.

[0041] Initial probability storage module: This module encapsulates multiple RAM modules to store and read initial probability data. Data is read through the read port and used for calculation of check nodes and variable nodes.

[0042] Check Node Calculation Module: This module performs update calculations on the check nodes. Specifically, it distributes the input data to the corresponding check node calculation unit for processing based on the flag signal, and stores the calculation results back to the original RAM module.

[0043] Variable Node Computation Module: This module implements the update calculation of variable nodes. Specifically, each variable node calculation unit inputs five signals (four channels of check node data and one channel of initial probability data) and outputs five signals (four channels of updated variable node data and one channel of decision data).

[0044] Frame output module: Responsible for outputting decision signals. Specifically, it integrates and sorts the input decision information and outputs continuous decoded data according to the clock beat.

[0045] The corresponding modules of the LDPC decoder oriented to the CCSDS standard of the present invention are introduced in more detail below.

[0046] The control module calculates the base address offset in real time based on the input code length. By combining shift operations with modular arithmetic, it dynamically allocates storage space in the RAM module, supporting seamless switching between variable-length and shortened codes under the CCSDS standard. The accompanying data address buffer for subsequent processing utilizes a dual-port RAM structure, enabling pre-loading of address mapping tables for two adjacent frames. This allows the CNU calculation phase to execute concurrently with address prefetching operations, reducing overall processing latency by 42%.

[0047] Based on an innovative design using odd-even time-sharing multiplexing technology, even-numbered cycles access the initialization RAM group (address space 0-72), while odd-numbered cycles access the iteration RAM group (address space 73-146). A time-slice rotation mechanism eliminates read-write conflicts. Combined with a window sliding compression algorithm, a ping-pong operation of 8x8 data blocks is completed every 72 clock cycles. Tests show that this strategy increases bandwidth utilization from 42% to 67%, improving access efficiency by 59%.

[0048] The check node calculation module uses a 14-stage pipeline structure, with each stage containing eight min-sum algorithm processing units. The critical path delay model is: T_cnu = T_mu + log2(N) × T_ad, N=112, and the measured delay is 1.8ns. The included dynamic weight adjustment module updates the belief propagation parameter α through an iteration count feedback mechanism. Its adjustment range is programmable from 0.75 to 0.95, with a step size of 0.05.

[0049] Among them, T_cnu represents the total critical path delay of the check node calculation module; T_mu represents the operation delay time of the multiplier; and T_ad represents the operation delay time of the adder.

[0050] The GF(2^4) multiplier in the variable node computation module utilizes a polynomial-optimized structure, simplifying the computational logic to a three-stage pipeline: GF_MUL = (a⊗b) ⊕ ((a<<1) & 0x0F) ⊕ ((b<<1) & 0x0F). This design reduces the traditional AND-XOR logic operation cycle from four to two, improving computational speed by 30%. Using asymmetric parity check matrix mapping technology, the 112 VNU units are divided into seven processing clusters, each sharing a 16KB parity factor lookup table, increasing hardware resource reuse to 87%.

[0051] The RAM array is divided into 16 independent power domains. If no access is detected for five consecutive cycles, the corresponding domain clock is automatically shut down, reducing static power consumption by 35%. The included temperature adaptive regulation module triggers a frequency reduction mechanism when the junction temperature Tj ≥ 85°C, reducing the operating frequency from 250MHz to 200MHz, making it suitable for onboard spacecraft.

[0052] The following describes in detail a decoding method for the LDPC decoder applicable to the above-mentioned CCSDS standard.

[0053] The state transition of the decoder is as follows Figure 1As shown in the figure, the core states of the decoder include: IDLE (idle), INIT (initialization), CNU (check node update), VNU (variable node update), Iteration (information circulates between the VNU and CNU), and OUTPUT (decoding completion, including the upper limit of the number of iterations or decoding failure). Header represents frame header detection information and is set to 0 if no frame header is detected and to 1 after it is detected. Code_complete is the channel information integrity flag and is set to 1 when a complete frame is received; otherwise, it is 0. Code_state represents the decoding completion status and is set to 1 if decoding is successful or the maximum number of iterations has been reached; otherwise, it is 0. Inter_max indicates whether the maximum number of iterations has been reached; if so, it is set to 1; otherwise, it is 0. Cnu_finish indicates whether the check node calculation is complete during this iteration; if so, it is set to 1; otherwise, it is 0. Vnu_pass indicates whether the variable node passed verification after the update; if so, it is set to 1; otherwise, it is 0.

[0054] IDLE indicates that the decoder is in the idle state. When a frame header detection message is detected from the front-end frame input module, the decoder enters the INIT state and begins storing initial channel information. After storage is complete and parameter configuration is complete, the decoder enters a loop and enters the working state. After parameter configuration is complete, it enters the Iteration state and jumps to the VNU state. First, the variable node calculation module performs a hard decision. If the verification is successful, it directly enters the OUTPUT state. If the verification is unsuccessful, the variable node is updated. After the update is completed, the message is passed to the check node calculation unit, and the decoder enters the CNU state. After the check node calculation module completes the check node calculation, the iteration count is increased by 1. It continues until the iteration count reaches the upper limit or the intermediate iteration verification succeeds. It enters the OUTPUT state and outputs the codeword. The decoder is then set to the IDLE state.

[0055] The decoding method applicable to the LDPC decoder of the CCSDS standard of the present invention is as follows: Figure 2 As shown, the three arrow directions from the control module to the check node calculation module, the variable node calculation module, and the channel soft information initialization respectively represent the control bus, and the remaining arrow directions represent the information bus. The decoding method includes the following steps:

[0056] Step 1: The input initial probability data is stored in blocks. A set of channel soft information is input for each clock and stored in 112 RAM modules to provide parallel information for subsequent calculations.

[0057] Step 2: After storing the initial probability data, read and process the initial probability data. First, read the initial probability data to verify the data source of the first update of the node calculation module. After the update of the node calculation module is completed, the variable node calculation module needs to read the initial probability data for each iteration to perform accumulation.

[0058] Step 3: Add flag information when reading the initial probability data. When the 112 initial probability data are first read into the CV_RAM used to store the check node intermediate information, the data must already have flag information added. This flag information is used to correspond to the 14 parallel check node calculation modules. Each check node calculation module extracts data from the CV_RAM based on the flag information when processing data. Because CV_RAM stores data by column, the first data in the first CV_RAM is the first variable node, and so on, the 73rd data is the 73rd variable node. When output, the first data may not be the data required by the first check node calculation module, so flag information is added. The added flag information is matched with the 448 CV_RAM data.

[0059] Step 4: After transferring the initial probability data to CV_RAM and adding the flag information, the check node calculation module performs the update calculation of the check node; the 14 RAM inputs corresponding to each sub-check matrix need to be input into the corresponding 14 check node calculation module calculation units according to the flag signal. After the calculation is completed, the data still needs to be sent back to the original RAM module for storage according to the flag signal. There are three main sub-modules inside: the data reading unit, which reads the information required by each check node calculation module from the RAM module according to the flag bit; the calculation unit, which calculates the minimum and next minimum values ​​of the 32 input data in the input port of each check node calculation module; and the return unit, which returns the 32 calculated data to the original storage location.

[0060] Step 5: After the check node calculation module is updated, the variable node calculation module is updated. The variable node calculation module has a total of 112 variable node calculation units. Each variable node calculation unit inputs five signals, four check node information, and one initial probability data. It outputs five signals, four updated variable node information, and one decision codeword (i.e., decision data). This output is controlled by a flag signal and can only be output after the maximum number of iterations is reached or verification passes.

[0061] Step 6: After decoding is completed, the decision codeword is output. The frame output module inputs 112 channels of decision information per clock. Since the 112 channels of input data are not continuous decision data, but each bit represents the first bit in the RAM module according to the parallelism, the data needs to be converted and integrated into continuous decoded data. Finally, 73 decoded data are output per clock when the flag signal arrives.

[0062] The LDPC decoder and decoding method for the CCSDS standard of the present invention are suitable for efficient decoding of long-frame data in satellite communications. The dynamic block storage architecture, hybrid iterative decoding algorithm, and configurable control module are collaboratively designed. By optimizing storage design, achieving a balance between decoding algorithm performance and complexity, and enhancing algorithm flexibility through configurable strategies, the system systematically resolves the efficiency and resource conflicts of long-frame LDPC decoding in satellite communications.

[0063] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. An LDPC decoder for the CCSDS standard, characterized in that: include: Frame input module: used to receive initial probability data and store it in blocks into multiple RAM modules; Control module: performs corresponding calculation and control operations according to the jump of the state machine; Initial probability storage module: encapsulates multiple RAM modules to store and read initial probability data; reads data through the read port for calculation of check nodes and variable nodes; Check node calculation module: used to implement the update calculation of the check node; according to the flag signal, it distributes the input data to the corresponding check node calculation unit for processing, and stores the calculation results back to the original RAM module; Variable node calculation module: used to implement update calculation of variable nodes; Frame output module: used to output decision signals; integrate and sort the input decision information, and output continuous decoded data according to the clock beat.

2. The LDPC decoder oriented to the CCSDS standard according to claim 1, characterized in that In the frame input module, one data is input in each clock cycle, and the corresponding storage address and enable signal are output.

3. The LDPC decoder for the CCSDS standard according to claim 1, wherein: In the control module, the state machine includes the following states corresponding to different decoding stages: standby state, initialization state, check node calculation state, variable node calculation state and decoding completion output state.

4. The LDPC decoder oriented to the CCSDS standard according to claim 1, characterized in that In the variable node calculation module, each variable node calculation unit inputs four paths of check node data and one path of initial probability information, and outputs four paths of updated variable node data and one path of decision data.

5. The LDPC decoder oriented to the CCSDS standard according to claim 1, characterized in that The control module calculates the base address offset in real time according to the input code length, and realizes the dynamic allocation of the RAM module's storage space by combining shift operation and modulo operation; The control module also includes a buffer for preparing the address of data to be processed next time, which adopts a dual-port RAM structure and loads two adjacent frame address mapping tables in advance, so that the CNU calculation stage and the address pre-fetch operation are executed in parallel.

6. The LDPC decoder oriented to the CCSDS standard according to claim 5, characterized in that In the RAM module, even-numbered cycles access the initialization RAM group, and odd-numbered cycles access the iteration RAM group, eliminating read and write conflicts through the time slice rotation mechanism.

7. The LDPC decoder oriented to the CCSDS standard according to claim 1, characterized in that: The check node calculation module adopts a 14-stage pipeline structure, each stage contains 8 Min-Sum algorithm processing units, and the critical path delay model is: T_cnu = T_mu + log2(N) × T_ad, N=112; Wherein, T_cnu represents the total critical path delay of the check node calculation module; T_mu represents the operation delay time of the multiplier; and T_ad represents the operation delay time of the adder.

8. The LDPC decoder oriented to the CCSDS standard according to claim 1, characterized in that: The GF(2^4) multiplier in the variable node calculation module adopts a polynomial basis optimized structure, and the operation logic is simplified to a three-stage pipeline: GF_MUL = (a⊗b) ⊕ ((a<<1) & 0x0F) ⊕ ((b<<1) & 0x0F).

9. The LDPC decoder oriented to the CCSDS standard according to claim 1, characterized in that: In the RAM module, the RAM array is divided into 16 independent power domains. When no access operation is detected for five consecutive cycles, the clock of the corresponding area is automatically turned off.

10. A decoding method applicable to the LDPC decoder oriented to the CCSDS standard according to claim 1, characterized in that: The following steps are involved: Step 1: The input initial probability data is stored in blocks, a set of channel soft information is input for each clock, and the information is stored in the RAM module; Step 2: After storing the initial probability data, read and process the initial probability data; The initial probability data is read as the data source for the first update of the verification node calculation module. After the verification node calculation module is updated, the variable node calculation module needs to read the initial probability data for each iteration to perform accumulation; Step 3: Add flag information when reading the initial probability data; Step 4: The verification node calculation module performs update calculations; Step 5: The variable node calculation module performs update calculations; Step 6: After decoding, output the decision codeword.

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