Efficient memory allocation for sequentially written memory devices

Abstract

The invention relates to efficient memory allocation for sequentially written memory devices. Input / output (I / O) write requests directed to a plurality of memory devices having memory cells are received by a processing device. The write request includes a data set. The processing device attaches the data set to a composite data object. The composite data object comprises one or more sequentially written data objects. The processing device associates the composite data object with one or more groups of memory cells of the plurality of memory devices. The processing device causes the composite data object to be written to the one or more groups of memory cells of the plurality of memory devices.

Description

[0001] Divisional application

[0002] This application is a divisional application of the invention patent application with the application date of February 24, 2022, application number 202210172301.7, and invention name “Effective storage allocation of sequentially written memory devices”. Technical Field

[0003] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to efficient storage allocation for sequential write memory devices. Background Art

[0004] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0005] One aspect of the present application relates to a system comprising a plurality of memory devices and a processing device coupled to the plurality of memory devices, the processing device performing operations comprising: receiving an input / output (I / O) write request directed to the plurality of memory devices, wherein the I / O write request comprises a data set; appending the data set to a composite data object, wherein the composite data object comprises one or more sequentially written data objects; associating the composite data object with one or more memory cell groups of the plurality of memory devices; and causing the composite data object to be written to the one or more memory cell groups of the plurality of memory devices.

[0006] Another aspect of the present application relates to a method comprising: receiving, by a processing device executing a file system of an operating system, an input / output (I / O) write request directed to a memory subsystem including a memory device, wherein the memory device includes a plurality of zones, and wherein the I / O write request includes at least a portion of a file; appending the at least portion of the file to a compound file, wherein the compound file includes one or more sequentially written files; allocating the compound file to one or more of the plurality of zones; and causing the compound file to be written to the one or more of the plurality of zones.

[0007] Yet another aspect of the present application relates to a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving an input / output (I / O) write request directed to a plurality of memory devices, wherein the I / O write request comprises a data set; appending the data set to a composite data object, wherein the composite data object comprises one or more sequentially written data objects; associating the composite data object with one or more groups of memory cells of the plurality of memory devices; and causing the composite data object to be written to the one or more groups of memory cells of the plurality of memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0009] Figure 1A An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0010] Figure 1B According to some embodiments Figure 1A Detailed block diagram of the computing system.

[0011] Figure 2 is a block diagram illustrating an example of a region mapping data structure according to some embodiments.

[0012] Figure 3 FIG. 1 is a diagram illustrating a data object attached to a composite data object according to some embodiments.

[0013] Figure 4 FIG. 1 is a diagram illustrating data objects allocated to memory cell groups according to some embodiments.

[0014] Figure 5 A flowchart of an example method for efficiently allocating data objects to groups of memory cells of a memory device according to some embodiments of the present disclosure is provided.

[0015] Figure 6 is a flow chart of an example method for implementing a zone reset according to some embodiments of the present disclosure.

[0016] Figure 7 A flowchart of an example method for efficiently allocating sequentially written files to regions of a memory device according to some embodiments of the present disclosure.

[0017] Figure 8 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0018] Various aspects of the present disclosure relate to efficient storage allocation for sequential writes to a memory device. A memory subsystem may be a memory device, a memory module, or a combination of a memory device and a memory module. Figure 1A Examples of storage devices and memory modules are described. Typically, a host system may utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0019] The memory subsystem may include high-density non-volatile memory devices where it is desirable to retain data when no power is supplied to the memory devices. One example of a non-volatile memory device is a NAND memory device. Figure 1A Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more die. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and have various logical states related to the number of bits stored. The logical states can be represented as binary values, such as "0" and "1," or combinations of such values.

[0020] A memory subsystem may include multiple components, such as memory devices that can store data from a host system in a storage medium (e.g., an integrated circuit (IC) die having individually addressable memory cells that store data). Processing in some current memory subsystems is often performed through random allocations to the IC die and in small data increments (e.g., four kilobytes (KB)). These random allocations of pages or blocks of data include non-sequential and / or random writes to the IC die. This practice results in high costs in terms of memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), or persistent memory, for storing mapping data structures that track the logical-to-physical (L2P) address mapping between the logical block address (LBA) space and the physical address space of the IC die. For example, mapping overhead is approximately gigabytes (GB) per terabyte (TB) of host-addressable media, and thus, a 16TB solid-state drive (SSD) requires a substantial 16GB of memory mapping overhead. Furthermore, periodic snapshots and logging are performed to preserve the mapping data structures during power-off and unexpected power failure scenarios. This adds additional write overhead to the IC die and performance loss.

[0021] A storage stack that can map physical block devices onto higher-level virtual block devices can exploit sequential input / output (I / O) memory device efficiencies. The storage stack can be used to direct I / O from user-space applications to physical memory devices. For example, the storage stack contains file system group data by locality (e.g., by thread, process, age, or application) and writes data sequentially to the storage device. The file system can then write data of different localities to the storage device as parallel sequential streams, each with its own locality. References to locality can refer to temporal locality or spatial locality. Data with temporal locality is data that the processor tends to access repeatedly at the same memory location within a short period of time, for example, data that is written, overwritten, and fine-tuned at approximately the same time. Data with spatial locality exhibits the following tendency: when a memory device references a particular memory location at a particular time, it is likely that the memory device has recently referenced nearby memory locations. In this case, the processor can attempt to determine the size and shape of an area surrounding the current reference that is worth accessing more quickly for subsequent accesses. References to sequential locality are a special case of spatial locality that occurs when data elements are arranged and accessed linearly (e.g., when iterating over the elements in a one-dimensional array).

[0022] When writing localized data sequentially, the data is written to groups of memory cells, also referred to as zones, where each zone can store multiple physical blocks of data. Therefore, mappings can be recorded at a higher granularity (megabytes rather than kilobytes) to map a specific data group to a zone in the LBA space, significantly reducing the amount of recorded metadata. The mapping space associated with the LBA space at this granularity can be referred to as a zone name space (ZNS), and a memory device written in this manner is referred to as a ZNS memory device. In one example, a data group consists of multiple localized data blocks, each corresponding to a physical block (e.g., an erase unit) of the IC die. In one embodiment, the size of a physical block (or erase unit) of a memory device is approximately 16 megabytes (MB). A memory cell group (or zone) can be at least two to four times (or more) the size of a physical block. Thus, a zone can store at least 64MB of data (e.g., 64MB, 128MB, 256MB, 512MB, or more), each of which is significantly larger than four kilobytes (KB).

[0023] In some host operating systems, a file system manages files from the operating system, files from applications running on the operating system, and metadata generated by the file system to organize files and allocate space in the IC die necessary to write the files and metadata when they are generated. The file systems of some host operating systems (e.g., Linux, Unix, etc.) allocate block groups (e.g., contiguous portions of a file, such as a range of LBAs) to a range of physical addresses in the IC die where the block groups are stored. Files can include, for example, data files, metadata containing inodes, directory structures, free space managers, and other data structures (or objects) capable of encapsulating data / metadata and writing to the IC. These file systems typically allocate certain types of block groups to specific ranges of physical addresses in the memory device based on whether the block group contains data or metadata, and attempt to prevent data and metadata from being intermixed within these specific ranges of physical addresses. In some host operating systems, a device mapper operating at the kernel level manages data objects from the operating system to organize data objects and allocate space in the memory device. For example, the host system may include a software framework designed to receive (or intercept) write requests directed to the memory device. A write request may include a payload, which contains the data to be written. The payload may have certain characteristics, such as, for example, whether the data to be written represents metadata or data in a file system, or a key or value in a key-value store.

[0024] In some host operating systems, the file system driver and / or storage driver can be configured to allocate groups of memory cells (or extents) to specific data sets. For example, the host operating system (e.g., the host operating system's file system) can allocate one or more groups of memory cells (or extents) to each stream. A stream can contain data sets (e.g., files, groups of files, data objects, groups of data objects, or another similar construct) that share one or more characteristics (e.g., creation or deletion time, access frequency, etc.).

[0025] Each memory cell group may have a specific size. In some host systems, each data set is assigned to one or more memory cell groups so that a memory cell group is not shared between two or more data sets (streams). However, the size of a data set may not match the size of a memory cell group. When this happens, the data set does not completely fill the memory cell group, resulting in empty and unusable memory cells. For example, a data set that is one-quarter the size of a memory cell group will be stored in one memory cell group, leaving the other three-quarters of the memory cell group empty. As another example, a data set that is 3.5 times the size of a memory cell group will be stored in four memory cell groups, leaving half of the memory cell group empty. This empty space can lead to inefficient utilization of the memory device.

[0026] Aspects of the present disclosure address the above-identified deficiencies and others by enhancing the ability of a host system (e.g., a file system of a host operating system and / or a device mapper associated with the host system) to allocate one or more data sets to each memory cell group (e.g., to each zone in a ZNS). In some embodiments, the aspects of the present disclosure may be implemented by a memory subsystem controller. Rather than allocating each data set to one or more memory cell groups, a host system operating in accordance with aspects of the present disclosure may append one or more data sets to a composite data object, such as a temporary file residing on volatile memory. The composite data object contains two or more data sets (data objects) that are written sequentially. The host system associates the composite data object with one or more memory cell groups of a memory device and causes the composite data object to be written to the one or more memory cell groups. As a result, each memory cell group (e.g., each zone in a ZNS) can be shared among one or more data sets, and each memory cell group can be fully utilized.

[0027] Advantages of the present disclosure include, but are not limited to, improving the utilization efficiency of each zone by utilizing ZNS. Some storage allocation systems for sequentially writing to memory devices (e.g., using ZNS) (where zones are not shared among data sets) may result in partially filled zones that are equivalent to wasted storage capacity. In contrast, aspects of the present disclosure achieve full filling of zones by enabling zones to be shared among multiple data sets, thereby avoiding wasted storage capacity. In addition, aspects of the present disclosure reduce write amplification. Zone reset involves erasing the entire zone. During a zone reset in some systems where zones are partially filled, erasing the entire zone will result in unnecessary erasure of empty blocks, thereby resulting in increased write amplification, which adversely affects the wear of the memory device. Therefore, advantages of the present disclosure include reduced write amplification, which will result in longer life for the memory device. Those skilled in the art of memory allocation and mapping to memory devices will be aware of other advantages discussed below.

[0028] Figure 1A An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0029] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0030] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0031] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1A An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., with no intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0032] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110 to, for example, write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0033] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket supporting Double Data Rate (DDR)), and the like. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface can provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1A Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0034] Memory devices 130 and 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0035] Some examples of nonvolatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of nonvolatile memory cells. The cross-point array of nonvolatile memory cells can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, compared to many flash-based memories, cross-point nonvolatile memory can perform write-in-place operations, in which nonvolatile memory cells can be programmed without first erasing the nonvolatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0036] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion of memory cells as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory devices 130 may be grouped into pages, which may refer to a logical unit of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0037] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), selectable memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-OR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0038] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0039] The memory subsystem controller 115 may include a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines to control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0040] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1A The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0041] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and convert them into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may also include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0042] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0043] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is a raw memory device 130 with on-die control logic (e.g., local media controller 135) and a controller for media management (e.g., memory subsystem controller 115) within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0044] The computing system 100 includes a storage driver 133 in the host system 120, which is configured with the storage allocation and device mapping functionality discussed throughout the various figures herein. In some embodiments, the storage allocation and device mapping functionality may be implemented by a user space driver. In some embodiments, the host system 120 includes at least a portion of the storage allocation and device mapping functionality. In other embodiments, the memory subsystem controller 115 includes at least a portion of the storage allocation and device mapping functionality. For example, the memory subsystem controller 115 and the processing device (processor) of the host system 120 may be configured to execute instructions stored in memory for performing the operations of the mapping and storage allocation functionality described herein.

[0045] Figure 1B According to some embodiments Figure 1ADetailed block diagram of computing system 100. In various embodiments, host system 120 includes a processing device 122, a cache 123, a file system driver 124, one or more applications 126A-126B, and a storage driver 133. In embodiments, processing device 122 may execute instructions to execute storage driver 133 and / or file system driver 124, for example, by executing the kernel of an operating system of host system 120. Host system 120 may execute one or more applications 126A-126B. In the illustrative example, application 126A may communicate with file system driver 124. File system driver 124 may run in kernel space of host system 120 and may be used to process I / O requests (e.g., read, write, and erase operations) initiated by one or more applications 126 (including application 126A) running in user space of host system 120. In embodiments, file system driver 124 may translate read, write, erase, and other requests issued by application 126A to storage driver 133. The storage driver 133 may be communicated to the memory subsystem controller 115. The storage driver 133 may run in kernel space of the host system 120 and may process requests received from the file system driver 124 and / or from the application 126B. The storage driver 133 may process the requests into commands to be processed by the memory subsystem controller 115. In some embodiments, the fully described storage allocation and device mapping functions may be implemented by a user space driver. That is, the functions described with respect to the storage driver 133 may be implemented by a user space driver (not illustrated).

[0046] In various embodiments, computing system 100 includes a memory device 130 associated with a sequential namespace (e.g., ZNS). In one embodiment, memory device 130 is implemented by NVM Express. TM (NVMe TM ) organization defines a Zone Name Space (ZNS) solid-state device. A zone in a ZNS may be a group of blocks of sequentially numbered LBAs that map to sequentially ordered physical addresses within a physical address space. The memory device 130 may be the previously mentioned storage device comprising a plurality of IC dies. Sequential writes to zones, also referred to as groups of memory cells (e.g., Zone 0, Zone 1, ... Zone N-1) are generally performed sequentially from the top (or smallest address) of the IC die to the bottom (or largest address) of the IC die, as illustrated by the patterned blocks of data written to the illustrated zones. The memory device 130 may also include a composite data object 160 and a zone mapping data structure 158. In conjunction Figure 2An example zone mapping data structure is described. In embodiments, the zone mapping data structure 158 and / or the composite data object 160 may be stored in a volatile memory device. In embodiments, the zone mapping data structure 158 may be a data structure used to provide memory device layout information for each zone in a namespace. In embodiments, the zone mapping data structure 158 may include a logical-to-physical (L2P) mapping data structure to map logical block numbers (or addresses) of the LBA space to memory blocks assigned to zones or memory groups. In these embodiments, the storage driver 133 may track the logical block numbers (or addresses) of the LBA space to the ZNS of the memory device 130 by a sequential relationship, such as by sequential physical addresses of zones (or groups of memory cells) within multiple IC dies programmed to access the memory device 130. Write pointers (WPs) to the zones of the memory device 130 may be stored in the cache 123.

[0047] In an embodiment, the storage driver 133 of the host system 120 may receive a write request from the application 126A and / or from the file system driver 124. The write request may be directed to multiple IC dies of the memory device 130. The write request may include at least a portion of a stream to be stored at the memory device 130. The stream may contain data sets (e.g., files, file groups, data objects, data object groups, or other similar structures) that share one or more characteristics (e.g., creation or deletion time, access frequency, etc.). The storage driver 133 may identify the data set from the write request and append the data set to the composite data object 160. The composite data object 160 contains data objects that are written sequentially. The composite data object 160 may be stored as a temporary file residing on a volatile memory device of the memory subsystem. Additionally or alternatively, the composite data object 160 may be stored in the non-volatile memory device 130. Examples of data sets appended to the composite data object 160 are described below. Figure 3 . The storage driver 133 may associate and write the composite data object to a group of memory cells of the memory device 130 by updating the zone mapping data structure 158. For example, the storage driver 133 may associate each data set in the composite data object 160 with one or more zones. The storage driver 133 may update the zone mapping data structure 158 to include which data set(s) are assigned to each zone and increment a data set counter. Figure 2 The region map data structure 158 is further described.

[0048] In an embodiment, the storage driver 133 may maintain a data set counter for each memory cell group (the memory cell group is in Figure 1B1 . In one embodiment, the counters may be stored in cache 123 and / or in zone mapping data structure 158. Each data set counter represents the number of streams (or data sets) allocated to the zone. When storage driver 133 associates composite data object 160 with zones in memory device 130, storage driver 133 may increment the counter associated with each zone based on the number of data sets associated with each respective zone. For example, zone 0 may be shared among three data sets, and thus storage driver 133 may increment (e.g., by one) the counter associated with zone 0 three times. As another example, zone 1 may be shared among two data sets, and thus storage driver 133 may increment the counter associated with zone 1 twice.

[0049] In an embodiment, the storage driver 133 of the host system 120 may receive an erase or delete request directed to multiple IC dies of the memory device 130. The erase request may specify which stream (or data set) is to be deleted. Using the zone mapping data structure 158, the storage driver 133 may identify the group of memory cells (e.g., a zone) storing the data set. In an embodiment, the erase request may include the LBA where the data set to be erased is located. The storage driver 133 may use the zone mapping data structure 158 to translate the LBA into the physical address of the block of the memory device 130 storing the data set to be erased. The storage driver 133 may mark the block storing the data set to be erased for erasure. In addition, the storage driver 133 may decrement a counter associated with the group of memory cells storing the data set marked for erasure. For example, if the storage driver 133 receives an erase request for a data set associated with zone 0, the storage driver 133 may mark the block storing the data set for erasure and may decrement (e.g., by 1) the counter associated with zone 0. As another example, if storage driver 133 receives an erase request for a data set associated with both zone 0 and zone 1, storage driver 133 may mark the block storing the data set for erasure and may decrement the counters associated with zone 0 and zone 1. In an embodiment, marking the data set for erasure may include updating the L2P map data structure to indicate that the block storing the data set contains invalid data.

[0050] To perform a zone reset, the storage driver 133 may use a dataset counter to identify an empty zone. In an embodiment, the zone mapping data structure 158 may maintain a pool of free zones that the storage driver 133 may use to allocate newly written datasets. Once a zone is empty (e.g., a dataset stored in the zone has been marked for erasure), the zone may be reset and returned to the free zone pool. The storage driver 133 may identify zones that meet the zone reset condition by identifying zones with counters that meet a threshold condition. In an embodiment, the threshold condition may be a threshold value, such as a value of zero. Thus, the storage driver 133 may identify zones that meet the zone reset condition and have a counter value of zero. The storage driver 133 may perform a zone reset for zones with dataset counter values ​​that meet the threshold condition. This may involve marking multiple memory devices associated with the zone for erasure and returning the zone to the free pool. In an embodiment, memory cells associated with the zone are not erased until immediately prior to being overwritten to avoid threshold voltage shifts.

[0051] Figure 2 FIG. 1 is a block diagram illustrating an example of a region mapping data structure 158 according to various embodiments. The controller 115 may store the region mapping data structure 158 in a Figure 1B Alternatively or in addition, the controller 115 may store the region mapping data structure 158 in a volatile memory device (e.g., Figure 1A Alternatively or in addition, the host system 120 may store at least a portion of the region map data structure 158 in local memory. The controller 115 may use the region map data structure 158 by itself or in combination with other data structures not depicted to configure or implement a media layout (e.g., a layout of where data groups for a region are to be located within a physical address space).

[0052] exist Figure 2 In the embodiment of the present invention, the zone map data structure 158 is configured to provide storage device layout information for zones in a name space (e.g., an LBA space used for ZNS operations). The zone map data structure 158 may have multiple entries. Each zone map entry in the zone map data structure 158 identifies information about a zone, such as a starting LBA 260 for the zone, a block set identifier 262 for the zone, a zone cursor value 264, a status 266 for the zone, a data set identifier 268, a counter 270 for the zone, and the like.

[0053] Host system 120 may associate compound data object 160 with one or more extents starting at the starting LBA 260 of the first free extent. Host system 120 may sequentially write compound data object 160 to the extents in the LBA space. After a certain amount of data has been written to an extent, the current starting LBA address for writing subsequent data is identified by extent cursor value 264. Status 266 may have values ​​indicating whether the extent is empty, full, implicitly open, explicitly open, closed, etc., to track the progress of writing to the extent.

[0054] Composite data object 160 includes one or more data sets. In an embodiment, zone mapping data structure 158 may include data set identifier 268. Data set identifier 268 may store a reference to a data set stored in the zone. For example, data set identifier 268 may include a specific data set ID for each data set stored in the zone. Furthermore, for each data set stored in the zone, counter 270 may be incremented by a predetermined value (e.g., by one). For each data set marked for erasure in the zone, counter 270 may be decremented by a predetermined value (e.g., by one). Thus, counter 270 represents the number of data sets associated with each zone. Therefore, counter 270 can be used to identify empty zones. For example, if counter 270 starts at a value of zero, host system 120 and / or controller 115 may determine that a zone with a counter 270 value of zero is empty. An empty zone is a zone in which all data stored in the zone has been marked for erasure. Controller 115 may assign an empty zone to a free zone pool.

[0055] Figure 3 1 illustrates data objects attached to a composite data object 300 according to some embodiments of the present disclosure. In some embodiments, the composite data object 300 may be associated with Figure 1B This example illustrates attaching a data set to a composite data object. However, as described throughout this disclosure, embodiments of the present disclosure may be applied to data objects, groups of data objects, files, groups of files, or other similar constructs. In an embodiment, the composite data object 300 may be stored in Figure 1B The region mapping data structure 158 may be stored locally in Figure 1B On the host system 120.

[0056] In an embodiment, processing logic of a host system (e.g., device mapping logic of a kernel) receives write requests directed to a plurality of memory devices. Figure 3In the example illustrated in FIG, a write request includes data sets (DS) AD 310A through 310D. For example, the first write request includes data set A 310A, the second write request includes DS B 310B, the third write request includes DS C 310C, and the fourth write request includes DS D 310D. In a conventional host operating system, the host system's processing logic would associate each data set with an integer number of groups of memory cells (e.g., banks). For example, if data set A 310A is 3.5 times the bank size, the conventional host operating system would allocate four banks to data set A 310A, leaving half the banks empty. As another example, if DS C 310C is one-tenth the bank size, the conventional host operating system would allocate one bank to DS C 310C, leaving nine-tenths of the bank empty.

[0057] like Figure 3 As illustrated in FIG, data sets AD 310A-310D are sequentially appended to a composite data object 300. In an embodiment, the kernel may store entries in a logical-to-physical (L2P) mapping data structure that map the data sets to the composite data object 300. In addition, the kernel may store additional entries that map the composite data object to a specific group of memory cells, as described below. Figure 4 As described in .

[0058] Figure 4 Description from Figure 3 The data sets are allocated to groups of memory cells (illustrated as zones) in the memory device 130. Figure 4 As illustrated in FIG, dataset A 310A completely fills zones 0, 1, 2, and 3, and fills a portion of zone 4. Zone 4 is shared between dataset A 310A and dataset B 310B. Dataset B 310B further completely fills zones 5 through 7, and fills a portion of zone 8. Dataset C 310C is assigned to a portion of zone 8. The remainder of zone 8 is assigned to dataset D 310D. Dataset D 310D further fills zones 9 through 12, and a portion of zone 13. Figure 4 As explained in , each region can be assigned to more than one dataset.

[0059] In response to allocating an extent (or portion of an extent) to a data set, the storage driver increments a counter associated with the extent (e.g., by 1). For example, each data set counter may start at 0 and may be incremented by 1 each time a data set is written to the extent. Thus, in Figure 4, the counter associated with zone 0 will be 1 because only data set A 310A is associated with zone 0. The counter associated with zone 4 will be incremented twice because zone 4 is associated with data set A 310A and data set B 310B. The counter associated with zone 8 will be incremented three times because zone 8 is associated with data set B 310B, data set C 310C, and data set D 310D.

[0060] According to this illustrative example, the DS identifier 268 entry for zone 0 in the zone mapping data structure 158 references data set A, and the counter 270 entry for zone 0 in the zone mapping data structure 158 is incremented by a predetermined value (e.g., by 1). The DS identifier 268 entry for zone 4 in the zone mapping data structure 158 references data sets A and B, and the counter 270 entry for zone 4 in the zone mapping data structure 158 is incremented by the predetermined value twice. The DS identifier 268 entry for zone 8 in the zone mapping data structure 158 references data sets A, B, and C, and the counter 270 entry for zone 8 in the zone mapping data structure 158 is incremented by the predetermined value three times. Finally, the DS identifier 268 entries for zone 13 in the zone mapping data structure 158 all reference data set D, the counter 270 entries for zone 13 in the zone mapping data structure 158 are incremented by a predetermined value, and the status 266 entries for zone 13 in the zone mapping data structure 158 may indicate that the zone is not full and that the next composite data object written by the host system will start from that zone.

[0061] In an embodiment, the kernel receives a delete or erase request. The storage driver identifies which data set is included in the delete request and marks the data set for erasure. Specifically, the storage driver may identify the zone to which the data set in the delete request is allocated and may mark blocks associated with the data set for erasure. The storage driver also decrements counters associated with the zone to which the data set is associated. As an illustrative example, if the kernel receives a delete request for data set C 310C, the storage driver may identify blocks in zone 8 to which data set C 310C is allocated and mark those blocks for erasure. In addition, the storage driver may decrement a counter associated with zone 8 (e.g., by one). The storage driver may use counters associated with each zone to identify empty zones. If the data set counter associated with a particular zone meets a threshold, the storage driver may determine that the particular zone is empty and may perform a zone reset, as described below with respect to Figure 6 Further description.

[0062] Figure 5is a flow chart of an example method 500 for efficiently allocating data objects from write requests to groups of memory cells of a memory device according to some embodiments of the present disclosure. The method 500 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1A and 1B The processes are executed by the host system 120 (e.g., via the storage driver 133 executed by the processing device 122). Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in a different order, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0063] At operation 510, processing logic receives a pointer to, for example, Figure 1A The system may include an input / output (I / O) write request for a plurality of memory devices of the memory device 130. The write request may be a request to write a data set to the memory device 130. The data set may include one or more data objects that share one or more characteristics (e.g., creation or deletion time, access frequency, etc.). In an embodiment, the write request is received from a file system executing on a host system.

[0064] At operation 520, processing logic appends the data set to a composite data object. The composite data object may be a data object that contains one or more sequentially written data objects. Thus, at operation 520, processing logic sequentially appends the one or more data objects contained in the data set to the end of the composite data object. In one embodiment, processing logic stores an entry in a region mapping data structure that maps the data set to the composite data object.

[0065] At operation 530, processing logic associates a composite data object with one or more memory cell groups of a plurality of memory devices. In one embodiment, processing logic may allocate one or more sequentially written data objects from the composite data object to one or more memory cell groups of the plurality of memory devices. The memory cell groups may be sequentially numbered LBAs that map to sequentially ordered physical addresses within the physical address space of the die. Processing logic may increment a data set counter associated with each of the one or more memory cell groups of the plurality of memory devices. The data set counter indicates the number of data sets allocated to each memory cell group, and thus processing logic increments each data set counter according to the number of data sets allocated to the corresponding memory cell group.

[0066] At operation 540, processing logic causes the composite data object to be written to one or more memory cell groups of the plurality of memory devices. For example, processing logic sends a write command to the memory device. The write command may include the composite data object and may be directed to the one or more memory cell groups. In one embodiment, a storage driver may access physical addresses of the memory cell groups of the plurality of memory devices. Furthermore, the storage driver performs sequential write operations on the physical addresses.

[0067] At operation 550, processing logic stores one or more entries to a logical-to-physical (L2P) mapping data structure that maps one or more data objects from logical block addresses (LBAs) to memory blocks in nonvolatile memory allocated to one or more memory cell groups.

[0068] Figure 6 is a flow chart of an example method 600 for implementing a region reset according to some embodiments of the present disclosure. The method 600 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by Figure 1A and 1B The processes are executed by the host system 120 (e.g., via the storage driver 133 executed by the processing device 122). Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in a different order, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0069] Processing logic receives an input / output (I / O) erase request directed to a plurality of memory devices at operation 610. The I / O erase request includes a data set to be erased.

[0070] At operation 620, processing logic identifies memory cell groups of a plurality of memory devices associated with a data set. A logical-to-physical (L2P) mapping data structure includes entries that map the data set from logical block addresses (LBAs) to memory blocks in nonvolatile memory allocated to one or more memory cell groups. Processing logic may use the L2P mapping data structure to identify the memory cell group associated with the data set in the erase request.

[0071] At operation 630, processing logic marks the data set for erasure. Processing logic may use the L2P map data structure to identify the physical block storing the data set and mark the physical block for erasure. In an embodiment, marking the physical block for erasure may include marking the block as invalid in the L2P map data structure.

[0072] At operation 640, processing logic decrements a counter associated with the memory cell groups of the plurality of memory devices. The counter represents the number of data sets associated with each memory cell group.

[0073] At operation 650, processing logic identifies an empty memory cell group, wherein a data set counter associated with the empty memory cell group satisfies a threshold condition. The threshold condition may be a threshold value, such as a value of zero. Thus, processing logic identifies the memory cell group having a data set counter of zero as empty.

[0074] At operation 660, processing logic marks empty memory cell groups for erasure. Processing logic may reset the memory cell groups marked for erasure and return them to the free pool. Memory cell groups allocated to the free pool may be erased and allocated to newly received write requests.

[0075] Figure 7 is a flow chart of an example method 700 for efficiently allocating sequentially written files to regions of a memory device according to some embodiments of the present disclosure. The method 700 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 700 is performed by Figure 1A and 1BThe processes are executed by the host system 120 (e.g., via the execution of the file system driver 124 and / or the storage driver 133 by the processing device 122). Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in a different order, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0076] At operation 710, processing logic receives an input / output (I / O) write request directed to a memory subsystem comprising a memory device, wherein the memory device comprises a plurality of zones, and wherein the I / O write request comprises at least a portion of a file. In an embodiment, the memory subsystem comprises a solid-state drive (SSD), and the plurality of zones comprise a partition namespace.

[0077] At operation 720, processing logic appends at least a portion of the file to a compound file, wherein the compound file comprises one or more sequentially written files.In an embodiment, the compound file may be a temporary file residing on a volatile memory device.

[0078] At operation 730, processing logic allocates the compound file to one or more of the plurality of zones. Processing logic stores entries in a logical-to-physical (L2P) mapping data structure that map sequentially written files from logical block addresses to memory blocks in the non-volatile memory allocated to the zone.

[0079] At operation 740, processing logic causes the composite file to be sequentially written to one or more of the plurality of zones. Processing logic may increment a file counter associated with each of the one or more zones. Each file counter may represent the number of files associated with the respective zone.

[0080] In an embodiment, processing logic may receive an erase request directed to a memory subsystem. The erase request may specify a file to be erased. The processing logic may use an L2P mapping data structure to identify the zone to which the file to be erased is allocated and decrement a file counter associated with the identified zone. Using the file counter, the processing logic may identify an empty zone that meets a zone reset condition. A zone reset may include erasing data stored at the zone and assigning the zone to a free zone pool. The processing logic may identify an empty zone that meets a zone reset condition by identifying a zone with a file counter that meets a threshold condition. In an embodiment, the threshold condition may be, for example, a threshold of zero. Thus, the processing logic identifies a zone with a file counter equal to zero as a zone that meets the zone reset condition. The processing logic may mark the identified empty zone for erasure, for example, by updating the LPT mapping data structure to mark the data stored in the empty zone as invalid. The processing logic may further associate the identified empty zone with a free zone pool.

[0081] Figure 8 An example machine illustrating a computer system 800 in which a set of instructions may be executed for causing the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 800 may correspond to a host system (e.g., Figure 1A and 1B host system 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0082] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" should also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0083] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0084] The processing device 802 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 802 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. The computer system 800 may also include a network interface device 808 for communicating over a network 820.

[0085] The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 826 or software embodying any one or more of the methodologies or functions described herein. The instructions 826 may also reside, completely or at least partially, within the main memory 804 and / or within the processing device 802 during execution thereof by the computer system 800, with the main memory 804 and the processing device 802 also constituting machine-readable storage media. The machine-readable storage medium 824, the data storage system 818, and / or the main memory 804 may correspond to Figure 1A Memory subsystem 110.

[0086] In one embodiment, instructions 826 include implementing instructions corresponding to Figure 1A and 1B The storage drive 133 may be operable to store instructions for the functions of the storage drive 133. Although the machine-readable storage medium 824 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods disclosed herein. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0087] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to others skilled in the art. An algorithm is considered here, and generally, to be a self-consistent sequence of operations that produces a desired result. The operations are those that require physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, it has proven convenient, primarily for general reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0088] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0089] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any other type of medium suitable for storing electronic instructions, each medium coupled to a computer system bus.

[0090] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure described herein may be implemented using a variety of programming languages.

[0091] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0092] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It should be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: a plurality of memory devices; as well as a processing device coupled to the plurality of memory devices, the processing device performing operations comprising: receiving an input / output (I / O) write request directed to the plurality of memory devices, wherein the I / O write request includes a data object, wherein the plurality of memory devices include a plurality of memory cell groups corresponding to sequential logical addresses, and wherein each memory cell group of the plurality of memory cell groups is associated with an available capacity status, the available capacity status indicating at least one of: a full status or a not full status; appending the data object to a composite data object, wherein the composite data object comprises one or more sequentially written data objects; associating the composite data object with the plurality of memory cell groups of the plurality of memory devices, wherein a first memory cell group of the plurality of memory cell groups is in the not full state, and wherein one or more subsequent memory cell groups are identified as free memory cell groups in an order corresponding to the sequential logical addresses; as well as The composite data object is caused to be written to the plurality of memory cell groups, resulting in the full state of the first memory cell group and the not full state of at least one of the one or more subsequent memory cell groups.

2. The system of claim 1 , wherein associating the composite data object with the plurality of memory cell groups comprises: allocating the one or more sequentially written data objects to the first memory cell group and the one or more subsequent memory cell groups; as well as A data set counter associated with the first memory cell group and each of the one or more subsequent memory cell groups is incremented, wherein the data set counter represents a number of data sets associated with the first memory cell group and each of the one or more subsequent memory cell groups.

3. The system of claim 1, wherein the operations performed are performed by a storage driver of an operating system on which a host file system is executing. 4 . The system of claim 3 , wherein the storage driver accesses physical addresses of cell groups of the plurality of memory devices, and wherein the storage driver performs sequential write operations with respect to the physical addresses.

5. The system of claim 1 , wherein the operations further comprise: receiving an input / output (I / O) erase request directed to the plurality of memory devices, wherein the I / O erase request includes a second data set; identifying a second group of memory cells in the plurality of memory devices associated with the second data set; marking the second data set for erasure; as well as A data set counter associated with the second memory cell group of the plurality of memory devices is decremented, wherein the data set counter represents a number of data sets associated with each of the second memory cell group.

6. The system of claim 1 , wherein the operations further comprise: identifying an empty memory cell group, wherein a data set counter associated with the empty memory cell group satisfies a threshold condition; as well as The empty groups of memory cells are marked for erasure.

7. The system of claim 1 , wherein the operations further comprise: One or more entries are stored in a logical-to-physical L2P mapping data structure, wherein the one or more entries map the one or more sequentially written data objects from a logical block address LBA to a memory block in a non-volatile memory allocated to the first memory cell group and the one or more subsequent memory cell groups.

8. A method comprising: receiving, by a processing device, an input / output (I / O) write request directed to a plurality of memory devices, wherein the I / O request includes a data object, wherein the plurality of memory devices include a plurality of memory cell groups corresponding to sequential logical addresses, and wherein each memory cell group of the plurality of memory cell groups is associated with an available capacity status, the available capacity status indicating at least one of: a full status or a not full status; appending the data object to a composite data object associated with one of the plurality of memory devices, wherein the composite data object comprises one or more sequentially written data objects; associating the composite data object with the plurality of memory cell groups of the plurality of memory devices, wherein a first memory cell group of the plurality of memory cell groups is in the not full state, and wherein one or more subsequent memory cell groups are identified as free memory cell groups in an order corresponding to the sequential logical addresses; as well as The composite data object is caused to be written to the plurality of memory cell groups, resulting in the full state of the first memory cell group and the not full state of at least one of the one or more subsequent memory cell groups.

9. The method of claim 8, wherein associating the composite data object with the plurality of memory cell groups comprises: allocating the one or more sequentially written data objects to the first memory cell group and the one or more subsequent memory cell groups; as well as A data set counter associated with the first memory cell group and each of the one or more subsequent memory cell groups is incremented, wherein the data set counter represents a number of data sets associated with the first memory cell group and each of the one or more subsequent memory cell groups.

10. The method of claim 8, wherein the method is performed by a storage driver on which an operating system of a host file system is executing.

11. The method of claim 10, wherein the storage driver accesses physical addresses of cell groups of the plurality of memory devices, and wherein the storage driver performs sequential write operations with respect to the physical addresses.

12. The method according to claim 8, further comprising: receiving an input / output (I / O) erase request directed to the plurality of memory devices, wherein the I / O erase request includes a second data set; identifying a second group of memory cells in the plurality of memory devices associated with the second data set; marking the second data set for erasure; as well as A data set counter associated with the second memory cell group of the plurality of memory devices is decremented, wherein the data set counter represents a number of data sets associated with each of the second memory cell group.

13. The method of claim 8, further comprising: identifying an empty memory cell group, wherein a data set counter associated with the empty memory cell group satisfies a threshold condition; as well as The empty groups of memory cells are marked for erasure.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving an input / output (I / O) write request directed to a plurality of memory devices, wherein the I / O write request includes a data object, wherein the plurality of memory devices include a plurality of memory cell groups corresponding to sequential logical addresses, and wherein each memory cell group of the plurality of memory cell groups is associated with an available capacity status, the available capacity status indicating at least one of: a full status or a not full status; appending the data object to a composite data object, wherein the composite data object comprises one or more sequentially written data objects; associating the composite data object with the plurality of memory cell groups of the plurality of memory devices, wherein a first memory cell group of the plurality of memory cell groups is in the not full state, and wherein one or more subsequent memory cell groups are identified as free memory cell groups in an order corresponding to the sequential logical addresses; and The composite data object is caused to be written to the plurality of memory cell groups, resulting in the full state of the first memory cell group and the not full state of at least one of the one or more subsequent memory cell groups.

15. The non-transitory computer-readable storage medium of claim 14, wherein associating the composite data object with the plurality of memory cell groups comprises: allocating the one or more sequentially written data objects to the first memory cell group and the one or more subsequent memory cell groups; as well as A data set counter associated with the first memory cell group and each of the one or more subsequent memory cell groups is incremented, wherein the data set counter represents a number of data sets associated with the first memory cell group and each of the one or more subsequent memory cell groups.

16. The non-transitory computer-readable storage medium of claim 14, wherein the operations performed are performed by a storage driver of an operating system on which a host file system is executing. 17 . The non-transitory computer-readable storage medium of claim 16 , wherein the storage drive accesses physical addresses of cell groups of the plurality of memory devices, wherein the storage drive performs sequential write operations with respect to the physical addresses.

18. The non-transitory computer-readable storage medium of claim 14, wherein the processing device is configured to perform operations further comprising: receiving an input / output (I / O) erase request directed to the plurality of memory devices, wherein the I / O erase request includes a second data set; identifying a second group of memory cells in the plurality of memory devices associated with the second data set; marking the second data set for erasure; as well as A data set counter associated with the second memory cell group of the plurality of memory devices is decremented, wherein the data set counter represents a number of data sets associated with the second memory cell group.

19. The non-transitory computer-readable storage medium of claim 14, wherein the processing device is configured to perform operations further comprising: identifying an empty group of memory cells, wherein a data set counter associated with the empty group of memory cells satisfies a threshold condition; and The empty groups of memory cells are marked for erasure.

20. The non-transitory computer-readable storage medium of claim 14, wherein the processing device is configured to perform operations further comprising: One or more entries are stored in a logical-to-physical L2P mapping data structure, wherein the one or more entries map the one or more sequentially written data objects from a logical block address LBA to a memory block in a non-volatile memory allocated to the first memory cell group and the one or more subsequent memory cell groups.

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