Data accumulation method, accumulator, chip and electronic equipment

Abstract

The invention provides a data accumulation method, an accumulator, a chip and electronic equipment. The method comprises the following steps: acquiring an instruction; the instruction comprises an identifier of processed data and a type of the processed data; the type is a floating-point number type or a fixed-point number type; sequentially reading a group of data based on the identifier; wherein each group comprises # imgabs 0 # processing data, mC is the single minimum processing capacity, nB is the bit number of any processing data, and # imgabs 1 # is an integer down function; and for each group, carrying out compression based on a Wallace tree based on types, and carrying out leading zero detection on a compression result to obtain an accumulation result of data of the group. The method provided by the invention comprises the following steps: reading a group of data in sequence based on an identifier in an instruction; wherein each group comprises a preset number of processing data; and for each group, compression based on the Wallace tree is carried out based on the type, and leading zero detection is carried out on the compression result to obtain an accumulation result of the group of data, so that the data processing speed is accelerated, and the processing efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data accumulation method, an accumulator, a chip, and an electronic device. Background Art

[0002] With the development of artificial intelligence, the demand for multiplication and addition computing has increased dramatically. Take deep learning technology as an example. It is the core technology of artificial intelligence and has played a significant role in promoting many applications.

[0003] Deep learning algorithms are typically computationally intensive. Matrix multiplication, the core of these algorithms, is a computationally and data-intensive operation. Deep learning algorithms require a large number of matrix multiplications.

[0004] In the existing technology, when accumulating data, it is necessary to accumulate the data in each row one by one and then output the horizontal accumulation result. However, each instruction can only operate on one data in the matrix, so the matrix operation needs to be broken down into operations on multiple data. Due to the large amount of data in the matrix operation, the efficiency in the data accumulation calculation process is extremely low and the power consumption is high. Summary of the Invention

[0005] In order to solve one of the above technical defects, the present application provides a data accumulation method, an accumulator, a chip, and an electronic device.

[0006] In a first aspect, the present application provides a data accumulation method, characterized in that the method includes:

[0007] Get an instruction; the instruction includes an identifier of processing data and a type of processing data; the type is a floating point number type or a fixed point number type;

[0008] Based on the identifier, read a group of data in sequence; each group includes processing data, mC is the minimum processing amount for a single time, nB is the number of bits of any processing data, is the floor function;

[0009] For each group, Wallace tree-based compression is performed based on the type, and leading zero detection is performed on the compressed result to obtain the accumulated result of the group of data.

[0010] Optionally, for any group, perform Wallace tree-based compression based on type, including:

[0011] Determine first data tD1 according to the type and the processed data of any group;

[0012] Compress tD1 based on the Wallace tree to obtain 2 second data and

[0013] Will and Add them together to get the compressed result.

[0014] Optionally, determining the first data tD1 according to the type and the processed data of any group includes:

[0015] If the type is a fixed-point number type, then tD1 is determined to be the processing data of any group;

[0016] If the type is a floating-point number type, then the order of the processed data of any group is shifted according to the type to obtain tD1.

[0017] Optionally, according to the type, the processed data of any group is shifted to obtain tD1, including:

[0018] Extract the exponent and mantissa of each processed data in any group according to the type;

[0019] Determine the two's complement of each mantissa;

[0020] Perform order shift according to the complements of each exponent and each mantissa to obtain the third data tD3;

[0021] After performing floating point special value detection on tD3, tD1 is obtained.

[0022] Optionally, a rank shift is performed according to the complements of each exponent and each mantissa to obtain third data tD3, including:

[0023] Determine the maximum value E among each index max ;

[0024] For any processed data, perform docking shift through the following steps to obtain the corresponding tD3:

[0025] Set the bit count value nC i =0;

[0026] Calculate E from low to high max With E i The difference between the Every time you get a difference of nC i At the same time, every time nC i When a non-zero segment value is reached, the difference between the current segment value -1 and the previous segment value is used to form the shift bit. according to Shift the shift result of the previous segment to obtain tD3 corresponding to any processed data;

[0027] Among them, i is the processing data identifier, E i is the index of processing data i, j is the bit identifier, For E max With E i The first segment value is 0. If the current segment value is the first non-zero value, the target segment value is 0. If the current segment value is not the first non-zero value, the target segment value is the previous segment value of the current segment value + 1. v is the segment identifier. The initial value of v is 1. If v = 1, the shift result src of the previous segment i It consists of a sign bit and the complement of the mantissa of the processed data i.

[0028] Optionally, the segment values ​​are 0, 3, 6, 11;

[0029] Whenever nC i When a non-zero segment value is reached, the difference between the current segment value and the target segment value is used to form the shift bit. according to Shift the shift result of the previous segment to obtain tD3 corresponding to any processed data, including:

[0030] When nC i =3, the difference between 2 and 0 is used to form the shift number src i Shift right bits, get the shift result of the first segment

[0031] When nC i =6, the difference between 5 and 3 is used to form the shift number Will Shift right bits, and get the shift result of the second segment

[0032] When nC i =11, the difference between 10 and 6 is used to form the shift number like Then determine the corresponding processing data i Otherwise, it is determined that tD3 corresponding to the processed data i is equal to 0.

[0033] Optionally, a leading zero detection is performed on the compression result to obtain an accumulation result of the group of data, including:

[0034] Determine the number of bits nd as the total number of bits of the compression result;

[0035] Determine the compression result as fourth data tD4;

[0036] Determine whether the high nd bits of tD4 are all 0;

[0037] If all 0s, then when nd is the total number of bits of the compression result, the fifth data tD5=0 is obtained; when nd is the total number of bits of the non-compression result, tD4=tD4<<nd is determined. If nd=1, tD5=tD4 is obtained. If nd≠1, then Repeat the step of determining whether the high nd bits of tD4 are all 0 and the subsequent steps;

[0038] If it is not all 0, then when nd=1, tD5=tD4, and when nd≠1, Repeat the step of determining whether the high nd bits of tD4 are all 0 and the subsequent steps; wherein, is the ceiling function;

[0039] Expand tD5 to obtain sixth data tD6;

[0040] After performing floating point special value detection on tD6, the accumulated result of this group of data is obtained.

[0041] In a second aspect of the present application, an accumulator is provided, the accumulator comprising:

[0042] An acquisition module is used to acquire an instruction; the instruction includes an identifier of the processing data and a type of the processing data; the type is a floating point number type or a fixed point number type;

[0043] The reading module is used to read a group of data in sequence based on the identifier; each group includes processing data, mC is the minimum processing amount for a single time, nB is the number of bits of any processing data, is the floor function;

[0044] The accumulation module is used to perform Wallace tree compression based on the type of each group read by the reading module, perform leading zero detection on the compression result, and obtain the accumulation result of the group of data.

[0045] A third aspect of the present application provides a chip, comprising: the accumulator described in the second aspect;

[0046] The accumulator is used to implement the data accumulation method described in the first aspect above.

[0047] According to a fourth aspect of the present application, an electronic device is provided, comprising: the chip described in the third aspect.

[0048] The present application provides a data accumulation method, an accumulator, a chip, and an electronic device, the method comprising: obtaining an instruction; the instruction comprising an identifier of processing data and a type of processing data; the type being a floating point number type or a fixed point number type; reading a group of data in sequence based on the identifier; wherein each group comprises processing data, mC is the minimum processing amount for a single time, nB is the number of bits of any processing data, The method provided in this application sequentially reads a set of data based on an identifier in an instruction, wherein each set includes a preset number of processed data items. For each set, a Wallace tree-based compression is performed based on the type of the data item, and a leading zero check is performed on the compressed result to obtain the accumulated result of the data item. This method accelerates data processing and improves processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0050] Figure 1 A flow chart of a data accumulation method provided in an embodiment of the present application;

[0051] Figure 2 A schematic diagram of the fp64 data format provided in an embodiment of the present application;

[0052] Figure 3 A schematic diagram of the fp32 data format provided in an embodiment of the present application;

[0053] Figure 4 A schematic diagram of a Wallace tree provided in an embodiment of the present application;

[0054] Figure 5 A schematic diagram of the structure of an accumulator provided in an embodiment of the present application;

[0055] Figure 6 A schematic diagram of the structure of a vector processor provided in an embodiment of the present application;

[0056] Figure 7 A schematic diagram of the structure of a high-performance processor provided in an embodiment of the present application;

[0057] Figure 8 A schematic diagram of the structure of a scalar processor provided in an embodiment of the present application;

[0058] Figure 9 A schematic structural diagram of a synchronization unit of a scalar processor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to make the technical solutions and advantages of the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

[0060] In the process of implementing this application, the inventors found that the deep learning algorithm is a typical computationally intensive algorithm. The matrix multiplication, which is the core part of the algorithm, is a computationally and data intensive operation. The deep learning algorithm requires a large number of matrix multiplications. In the prior art, when accumulating data, it is necessary to accumulate each row of data one by one and then output the horizontal accumulation result. However, each instruction can only operate on one data in the matrix, so the matrix operation needs to be decomposed into operations on multiple data. Due to the large amount of matrix operation data, the efficiency is extremely low and the power consumption is high during the data accumulation calculation process.

[0061] In response to the above problems, the present invention provides a data accumulation method, an accumulator, a chip, and an electronic device. The method includes: obtaining an instruction; the instruction includes an identifier of the processing data and the type of the processing data; the type is a floating point number type or a fixed point number type; based on the identifier, a group of data is read in sequence; wherein each group includes processing data, mC is the minimum processing amount for a single time, nB is the number of bits of any processing data, The method provided in this application sequentially reads a set of data based on an identifier in an instruction, wherein each set includes a preset number of processed data items. For each set, a Wallace tree-based compression is performed based on the type of the data item, and a leading zero check is performed on the compressed result to obtain the accumulated result of the data item. This method accelerates data processing and improves processing efficiency.

[0062] See also Figure 1 This embodiment provides a data accumulation method, and the implementation process of the method is as follows:

[0063] 101, get instructions.

[0064] The instruction includes an identifier of the processed data and a type of the processed data, which may be a floating-point number type or a fixed-point number type.

[0065] Before executing the method provided in this embodiment, the corresponding data will be stored based on the calculation requirements. For example, if the calculation requirement is to calculate the multiplication of two matrices, the data of the two matrices will be stored. Then, the identification of the data (such as the location of the data storage location, etc., the identification can uniquely point to the data, that is, the data can be accurately read according to the identification) and the type of the data are written into the instruction.

[0066] The type can be a fixed-point number (such as int32) or a floating-point number (such as fp32 or fp64). For example, the instruction is a 40-bit instruction, which includes the identifier of the processed data and the 2-bit type of the processed data. If the 2-bit value is 01, it means that the processed data type is fp64 (double-precision floating point number), 10 means that the processed data type is fp32 (single-precision floating point number), and 11 means that the processed data type is int32 (32-bit signed integer).

[0067] The identification of the processing data mentioned above is only an example, and in actual application, it can be determined based on pre-configured information.

[0068] The method of this embodiment does not limit the type of processed data, that is, the method of this embodiment can process any type of data.

[0069] In step 101, the instruction is obtained, and the identifier of the processed data and the type of the processed data are obtained from the instruction.

[0070] 102. Based on the identifier, read a group of data in sequence.

[0071] Each group includes processing data, mC is the minimum processing amount for a single time, nB is the number of bits of any processing data, is the floor function.

[0072] For example, if the minimum processing capacity of a single transaction is 512 bits and the type of the processed data is fp64, then the number of bits of the processed data is 64 bits. A set of data includes Then 8 processing data will be read each time to form a group, that is, each group of data will include 8 processing data.

[0073] For example, if the minimum processing capacity of a single transaction is 512 bits and the type of the processed data is fp32, then the number of bits of the processed data is 32 bits. A set of data includes Then 16 processing data will be read each time to form a group, that is, each group of data will include 16 processing data.

[0074] For example, if the minimum processing capacity of a single transaction is 512 bits and the type of the processed data is int32, then the number of bits of the processed data is 32 bits. A set of data includes Then 16 processing data will be read each time to form a group, that is, each group of data will include 16 processing data.

[0075] In addition, the read data is closely arranged into a group. For example, a group of data includes: processed data 0, processed data 1, processed data 2, processed data 3, processed data 4, processed data 5, processed data 6, and processed data 7. Then the group of data is shown in Table 1.

[0076] Table 1

[0077]

[0078] For the convenience of description, unless otherwise specified, the method provided in this embodiment is described below by taking the case where the minimum single processing amount is 512 bits, the type of the processing data is fp64, and 8 processing data are obtained each time as an example. For other types of processing data, refer to fp64 and no further explanation is given.

[0079] 103. For each group, perform compression based on the Wallace tree based on the type, perform leading zero detection on the compression result, and obtain the accumulated result of the group data.

[0080] In a specific implementation, step 102 is executed once to read a set of data. Step 103 is then executed again to perform Wallace tree compression based on the data type. The compressed result is checked for leading zeros to obtain the accumulated result of the set of data. Step 102 is then executed again to read the next set of data. Step 103 is then executed again to perform Wallace tree compression based on the data type. The compressed result is checked for leading zeros to obtain the accumulated result of the data set. Step 102 and step 103 are then executed again, and this cycle continues until all processed data have been processed once, and steps 102 and 103 have been executed once to obtain the accumulated result.

[0081] For any group of data read in step 102 (for example, the group of data includes processed data 0, processed data 1, processed data 2, processed data 3, processed data 4, processed data 5, processed data 6, and processed data 7), in step 103, the group of data will be compressed based on the Wallace tree based on the type, and the leading zero detection will be performed on the compression result to obtain the cumulative result of the group of data.

[0082] The implementation details are as follows:

[0083] 1. Wallace tree-based compression based on type.

[0084] 1) Determine first data tD1 according to the type and processing data of any group.

[0085] If the type is a fixed-point number (such as int32), then tD1 is determined to be the processing data of any group. Then tD1 also includes 7 data, namely, processing data 0, processing data 1, processing data 2, processing data 3, processing data 4, processing data 5, processing data 6, and processing data 7.

[0086] If the type is a floating point number (such as fp32 or fp64), then according to the type, the order of the processed data of any group is shifted to obtain tD1. The specific implementation process is as follows:

[0087] (1) Extract the exponent and mantissa of each processed data in any group according to the type.

[0088] Different types of data have their own data formats. For example, fp64 is represented as 64-bit binary, with 1 bit sign, 11 bits exponent, and 52 bits fraction. Figure 2 shown.

[0089] For another example, fp32 is represented by 32-bit binary, including 1-bit sign, 8-bit exponent, and 23-bit fraction. Figure 3 shown.

[0090] Here, the corresponding data can be read from the corresponding exponent bit and bit according to the data type.

[0091] For example, if the data set includes processed data 0, processed data 1, processed data 2, processed data 3, processed data 4, processed data 5, processed data 6, and processed data 7, and the processed data type is fp64, then the contents of [51:0] in processed data 0 are used as the mantissa F0 of data 0, and the contents of [62:52] in processed data 0 are used as the exponent E0 of data 0. The contents of [51:0] in processed data 1 are used as the mantissa F1 of data 1, and the contents of [62:52] in processed data 1 are used as the exponent E1 of data 1. The contents of [51:0] in processed data 2 are used as the mantissa F2 of data 2, and the contents of [62:52] in processed data 2 are used as the exponent E2 of data 2. … The contents of [51:0] in processed data 7 are used as the mantissa F7 of data 7, and the contents of [62:52] in processed data 7 are used as the exponent E7 of data 7.

[0092] In this way, 8 exponents (such as E0, E1, E2, E3, E4, E5, E6, E7) and 8 mantissas (such as F0, F1, F2, F3, F4, F5, F6, F7) of 8 processing data are extracted in this step.

[0093] It should be noted that, when expressing the number of bits in this embodiment and subsequent embodiments, [51:0] represents the 51st to 0th bits, and [62:52] represents the 62nd to 52nd bits. If there are similar expressions, please refer to this and no specific explanation will be given.

[0094] At the same time, the symbols of each processed data in any group are also extracted here.

[0095] (2) Determine the complement of each mantissa.

[0096] In this step, an existing solution can be used to determine the complement of each mantissa, such as determining the complements F'0, F'1, F'2, F'3, F'4, F'5, F'6, and F'7 of F0, F1, F2, F3, F4, F5, F6, and F7.

[0097] (3) Perform order shift according to the complements of the exponents and mantissas to obtain the third data tD3.

[0098] The docking shift process is: determine the maximum value E in each index max For any processed data, the docking shift is performed through the following steps to obtain the corresponding tD3:

[0099] Set the bit count value nC i =0.

[0100] Calculate E from low to high max With E i The difference between the Every time you get a difference of nC i At the same time, every time nC i When a non-zero segment value is reached, the difference between the current segment value -1 and the previous segment value is used to form the shift bit. according to Shift the shift result of the previous segment to obtain tD3 corresponding to any processed data.

[0101] Among them, i is the processing data identifier, E i is the index of processing data i, j is the bit identifier, For E max With E iThe first segment value is 0. If the current segment value is the first non-zero value, the target segment value is 0. If the current segment value is not the first non-zero value, the target segment value is the previous segment value of the current segment value + 1. v is the segment identifier. The initial value of v is 1. If v = 1, the shift result src of the previous segment i It is composed of the sign bit and the complement of the mantissa of the processed data i, such as src i It is the overflow bit + the complement of the mantissa of the processed data i + the precision bit.

[0102] In specific implementation, such as fp64, src i It is 65 bits, of which [64:60] are overflow bits, which can be obtained by expanding the sign or copying the sign to 5 bits. [59:8] are the mantissa bits, which are the complement of the mantissa. [7:0] are the precision bits, which are all 0. The precision bits are used for the subsequent Wallace number compression processing. For example, fp32, src i The value is 37 bits, of which [36:32] are overflow bits, which can be obtained by expanding the sign or copying the sign to 5 bits. [31:8] are the mantissa bits, which are the complement of the mantissa with a hidden bit. [7:0] are the precision bits, which are all 0. The precision bits are used for subsequent Wallace number compression.

[0103] Among them, the segment values ​​are 0, 3, 6, and 11.

[0104] Whenever nC i When a non-zero segment value is reached, the difference between the current segment value and the target segment value is used to form the shift bit. according to The implementation details of shifting the shift result of the previous segment to obtain tD3 corresponding to any processed data are as follows:

[0105] When nC i =3, the difference between 2 and 0 is used to form the shift number src i Shift right bits, get the shift result of the first segment

[0106] Specific The implementation process is shown in Table 2:

[0107] Table 2

[0108]

[0109]

[0110] When nC i =6, the difference between 5 and 3 is used to form the shift number Will Shift right bits, and get the shift result of the second segment

[0111] Specific The implementation process is shown in Table 3:

[0112] Table 3

[0113]

[0114] When nC i =11, the difference between 10 and 6 is used to form the shift number like Then determine the corresponding processing data i Otherwise, it is determined that tD3 corresponding to the processed data i is equal to 0.

[0115] The specific tD3 implementation process is shown in Table 4:

[0116] Table 4

[0117]

[0118] Still taking the example that the group includes 8 data, namely processed data 0, processed data 1, processed data 2, processed data 3, processed data 4, processed data 5, processed data 6, and processed data 7, the 8 exponents of the 8 processed data are E0, E1, E2, E3, E4, E5, E6, and E7, the complements of the 8 mantissas are F'0, F'1, F'2, F'3, F'4, F'5, F'6, and F'7, and the segment values ​​are 0, 3, 6, and 11, the above-mentioned docking and shifting process is exemplified.

[0119] Determine the maximum value E among E0, E1, E2, E3, E4, E5, E6, and E7 max .

[0120] For processing data 0: set the bit count value nC0 = 0.

[0121] Calculate E max The difference between the 0th bit of E0 and the 0th bit of E0 nC0=nC0+1=1;calculate E max The difference between the first digit of and the first digit of E0 nC0=nC0+1=2;calculate E max The difference between the second digit of and the second digit of E0 nC0=nC0+1=3; at this time, nC0 reaches the first non-zero segment value (ie 3), then the difference between 2, 1, and 0 bits forms the shift number (Right now for );Get the shift result of the first segment Where src0 is the sign bit of the processing data 0 + the complement of the mantissa of the processing data 0 + the precision bit.

[0122] Calculate E max The difference between the third digit of and the third digit of E0 nC0=nC0+1=4;calculate E max The difference between the 4th digit of and the 4th digit of E0 nC0=nC0+1=5;calculate E max The difference between the 5th digit of and the 5th digit of E0 nC0=nC0+1=6; at this time, nC0 reaches the second non-zero segment value (i.e. 6), then the difference between bits 5, 4, and 3 forms the shift bit (Right now for );Get the shift result of the second segment

[0123] Calculate E max The difference between the 6th digit of and the 6th digit of E0 nC0=nC0+1=7;calculate E max The difference between the 7th digit of and the 7th digit of E0 nC0=nC0+1=8;calculate E max The difference between the 8th digit of and the 8th digit of E0 nC0=nC0+1=9;calculate E max The difference between the 9th digit of and the 9th digit of E0 nC0=nC0+1=10;calculate E max The difference between the 10th digit of and the 10th digit of E0 nC0=nC0+1=11; at this time, nC0 reaches the third non-zero segment value (ie 11), which is also the last segment value, and the difference between 10, 9, 8, 7, and 6 bits forms the shift number (Right now for );like Then we get the corresponding value of processed data 0 Otherwise, tD3 corresponding to the processed data 0 is obtained as tD3=0.

[0124] For processing data 1: set the bit count value nC1 = 0.

[0125] Calculate E max The difference between the 0th bit of E1 and the 0th bit of E1 nC1=nC1+1=1; calculate E max The difference between the first digit of and the first digit of E1 nC1=nC1+1=2;calculate Emax The difference between the second digit of and the second digit of E1 nC1=nC1+1=3; at this time, nC1 reaches the first non-zero segment value (ie 3), then the difference between 2, 1, and 0 is formed into the shift number (Right now for );Get the shift result of the first segment Where src1 is the sign bit of processing data 1 + the complement of the mantissa of processing data 1 + the precision bit.

[0126] Calculate E max The difference between the third digit of and the third digit of E1 nC1=nC1+1=4;calculate E max The difference between the 4th digit of and the 4th digit of E1 nC1=nC1+1=5;calculate E max The difference between the 5th digit of and the 5th digit of E1 nC1=nC1+1=6; at this time, nC1 reaches the second non-zero segment value (i.e. 6), then the difference between bits 5, 4, and 3 forms the shift bit (Right now for );Get the shift result of the second segment

[0127] Calculate E max The difference between the 6th digit of and the 6th digit of E1 nC1=nC1+1=7;calculate E max The difference between the 7th digit of and the 7th digit of E1 nC1=nC1+1=8;calculate E max The difference between the 8th digit of and the 8th digit of E1 nC1=nC1+1=9; calculate E max The difference between the 9th digit of and the 9th digit of E1 nC1=nC1+1=10;calculate E max The difference between the 10th digit of and the 10th digit of E1 nC1=nC1+1=11; at this time, nC1 reaches the third non-zero segment value (i.e. 11), which is also the last segment value, and the difference between 10, 9, 8, 7, and 6 bits forms the shift number (Right now for );like Then we get the corresponding value of processed data 1 Otherwise, tD3 corresponding to the processed data 1 is obtained as 0.

[0128] …

[0129] Until processing data 7, tD3 corresponding to 8 processing data 8 is obtained, that is, there are 8 tD3, each corresponding to one processing data.

[0130] It should be noted that no matter how many digits the mantissa has, the final tD3 can be obtained by taking the difference of the first 11 digits, thus completing the docking shift process.

[0131] In the shifting process (3) above, the 11 bits are not all shifted after the difference calculation. Instead, the shifting is performed whenever a segmented difference is obtained. This method divides an overall shift into multiple shifts according to the minimum shift width, which can improve the shifting speed.

[0132] (4) After performing floating point special value detection on tD3, tD1 is obtained.

[0133] During this process, the existing floating-point special value detection method is used to detect 8 tD3s, and tD1 is obtained after the detection.

[0134] After the floating point special value detection, special values ​​such as 0, infinity and non-number (NaN) are detected.

[0135] Among them, NaN is used to represent undefined or unrepresentable values, such as 0 / 0, ∞-∞, etc.

[0136] For example, for each processing data (fp64 or pf32), when the value of the exponent part is the maximum value and the mantissa part is 0, infinity is detected; when the value of the exponent part is the maximum value and the mantissa part is not 0, non-number is detected; when the value of the exponent part is 0 and the value of the fraction part is also 0, zero is detected.

[0137] The results of multiplication and addition of special values ​​are deterministic. For example, the result of multiplying any number by zero is zero; the result of multiplying infinity by zero is NaN; the result of adding zero to any number is the number itself; when a non-zero number is multiplied by infinity, the result is positive infinity or negative infinity, depending on the sign of the multiplier; adding positive infinity or negative infinity to any positive or negative number results in positive infinity or negative infinity, respectively; the result of adding positive infinity to negative infinity is NaN; the result of multiplying or adding any number to NaN is NaN.

[0138] Taking fp64 as an example, at this point, eight 65-bit tD1s are obtained, i.e., tD1 is 65 bits. Taking fp32 as an example, at this point, eight 37-bit tD1s are obtained, i.e., tD1 is 37 bits.

[0139] 2) Compress tD1 based on the Wallace tree to obtain two second data and

[0140] Since the Wallace tree adder only supports two's complement operations, and the mantissa bits in tD1 are the two's complement of the mantissa of the processed data, tD1 can be compressed based on the Wallace tree to obtain two second data and

[0141] where the Wallace tree is as shown in Figure 4 where the adjacent two levels of the Wallace tree differ by 1 bit

[0142] 3) Add and to obtain the compression result

[0143] For example, if the processed data is fp64, the compression result is 65 bits; if the processed data is fp32, the compression result is 37 bits; if the processed data is int32, the compression result is 13 bits (where 5 bits are overflow bits)

[0144] 2. Perform leading zero detection on the compression result to obtain the accumulated result of this group of data

[0145] 1) Determine that the number of bits to judge nd is the total number of bits of the compression result

[0146] 2) Determine the compression result as the fourth data tD4

[0147] 3) Judge whether the high nd bits of tD4 are all 0

[0148] 4) If all 0, when nd is the total number of bits of the compression result, obtain the fifth data tD5 = 0. When nd is not the total number of bits of the compression result, determine tD4 = tD4 << nd. If nd = 1, obtain tD5 = tD4. If nd ≠ 1, Repeat the steps of judging whether the high nd bits of tD4 are all 0 and the subsequent steps

[0149] If not all 0, when nd = 1, obtain tD5 = tD4. When nd ≠ 1, Repeat the steps of judging whether the high nd bits of tD4 are all 0 and the subsequent steps. Where is the ceiling function <()

[0150] 5) Expand tD5 to obtain the sixth data tD6

[0151] For example, fill 0s at the low positions of tD5 until the requirements are met to obtain tD6

[0152] 6) After performing floating-point special value detection on tD6, obtain the accumulated result of this group of data

[0153] The floating-point special value detection here is similar to the process of "obtaining tD1 after performing a floating-point special value detection on tD3" and is not repeated here. For details, see the implementation process of obtaining tD1 after performing a floating-point special value detection on tD3.

[0154] Taking the compression result as result 1, in which all 65 bits are 0, as an example, determine nd=65, tD4=result 1.

[0155] The upper 65 bits of result 1 are all 0, so nd = 65, that is, nd is the total number of bits of the compressed result. Therefore, the fifth data tD5 = 0. tD5 is expanded to obtain the sixth data tD6. After performing a floating-point special value test on tD6, the accumulated result of this group of data is obtained.

[0156] Taking the compression result as result 2 and 65 bits in result 1 not all being 0 as an example, determine nd=65, tD4=result 2.

[0157] The upper 65 bits of tD4 are not all 0, and nd=65≠1, then Determine whether the upper 33 bits of tD4 are all 0s.

[0158] If the upper 33 bits of tD4 are all 0, then nd=33, the total number of bits of the uncompressed result, therefore, tD4=tD4<<33 is determined. Determine whether the upper 17 bits of tD4 are all 0. If the upper 33 bits of tD4 are not all 0, then Determine whether the upper 17 bits of tD4 are all 0s.

[0159] If the upper 17 bits of tD4 are all 0, then nd=17, the total number of bits of the uncompressed result, therefore, tD4=tD4<<17 is determined. Determine whether the upper 9 bits of tD4 are all 0. If the upper 17 bits of tD4 are not all 0, then Determine whether the upper 9 bits of tD4 are all 0s.

[0160] If the upper 9 bits of tD4 are all 0, then nd=9, the total number of bits of the uncompressed result, therefore, tD4=tD4<<9 is determined. Determine whether the upper 5 bits of tD4 are all 0. If the upper 9 bits of tD4 are not all 0, then Determine whether the upper 5 bits of tD4 are all 0s.

[0161] If the high 5 bits of tD4 are all 0, then nd=5, the total number of bits of the uncompressed result, therefore, tD4=tD4<<5 is determined. Determine whether the upper 3 bits of tD4 are all 0. If the upper 5 bits of tD4 are not all 0, then Determine whether the upper 3 bits of tD4 are all 0s.

[0162] If the upper 3 bits of tD4 are all 0, then nd=3, the total number of bits of the uncompressed result, therefore, tD4=tD4<<3 is determined. Determine whether the upper 2 bits of tD4 are all 0. If the upper 3 bits of tD4 are not all 0, then Determine whether the upper 2 bits of tD4 are all 0s.

[0163] If the upper two bits of tD4 are all 0, then nd=2, the total number of bits of the uncompressed result, therefore, tD4=tD4<<2 is determined. At this point, tD4 must be non-zero (because if it were 0, it would only mean that result 2 was all zeros, and tD5 = 0 would have already been obtained in the first judgment, so no subsequent judgment would be performed). The high-order bit of tD4 is 0 (i.e., not all zeros), and nd = 1, so tD5 = tD4. tD5 is expanded to obtain the sixth data tD6. After performing a floating-point special value check on tD6, the accumulated result of this group of data is obtained.

[0164] The above leading zero detection process can quickly and accurately determine tD6, and then obtain the accumulated result of the group of data.

[0165] In a specific implementation, step 103 is completed within three cycles, wherein the first cycle completes determining the first data tD1 based on the type and the processed data of any group. The second cycle completes compressing tD1 based on the Wallace tree to obtain two second data and Will and The compression result is obtained by adding them together. The third cycle completes the leading zero detection of the compression result to obtain the cumulative result of the group of data. This allows continuous data processing, for example:

[0166] The first cycle is to get the instruction and parse it.

[0167] In the second cycle, the first set of data is obtained.

[0168] In the third cycle, the first data tD1 of the first group of data is determined, and at the same time, the second group of data is obtained.

[0169] In the fourth cycle, the compression result of the first group of data is determined, and at the same time, the first data tD1 of the second group of data is determined, and at the same time, the third group of data is obtained.

[0170] In the fifth cycle, the accumulation result of the first group of data is determined, and at the same time, the compression result of the second group of data is determined. At the same time, the first data tD1 of the third group of data is determined, and at the same time, the fourth group of data is obtained.

[0171] In the sixth cycle, the accumulation result of the second group of data is determined, and at the same time, the compression result of the third group of data is determined. At the same time, the first data tD1 of the fourth group of data is determined, and at the same time, the fifth group of data is obtained.

[0172] Execute in sequence until all processed data are accumulated.

[0173] The solution of this embodiment can efficiently complete data accumulation through the above-mentioned continuous processing process.

[0174] This embodiment provides a data accumulation method, which obtains an instruction; the instruction includes an identifier of the processed data and the type of the processed data; the type is a floating point number type or a fixed point number type; based on the identifier, a group of data is read in sequence; wherein each group includes processing data, mC is the minimum processing amount for a single time, nB is the number of bits of any processing data, is a floor function; for each group, Wallace tree compression is performed based on the type, and a leading zero check is performed on the compressed result to obtain the accumulated result of the group of data. The method provided in this embodiment sequentially reads a group of data based on an identifier in an instruction; each group includes a preset number of processed data; for each group, Wallace tree compression is performed based on the type, and a leading zero check is performed on the compressed result to obtain the accumulated result of the group of data, thereby accelerating the data processing rate and improving processing efficiency.

[0175] Based on the same inventive concept of the data accumulation method, this embodiment provides an accumulator, see Figure 5 , the accumulator includes:

[0176] The acquisition module 501 is used to acquire an instruction. The instruction includes an identifier of the processing data and a type of the processing data. The type is a floating point number type or a fixed point number type.

[0177] The reading module 502 is used to read a group of data in sequence based on the identifier. Each group includes processing data, mC is the minimum processing amount for a single time, nB is the number of bits of any processing data, is the floor function.

[0178] The accumulation module 503 is configured to perform Wallace tree-based compression on each group read by the reading module 502 based on the type, perform leading zero detection on the compression result, and obtain an accumulation result of the group of data.

[0179] The accumulation module 503 is configured to determine the first data tD1 according to the type and the processed data of any group.

[0180] Compress tD1 based on the Wallace tree to obtain 2 second data and

[0181] Will and Add them together to get the compressed result.

[0182] Wherein, determining the first data tD1 according to the type and the processed data of any group includes:

[0183] If the type is a fixed-point number type, tD1 is determined to be the processing data of any group.

[0184] If the type is a floating-point number type, then the order of the processed data of any group is shifted according to the type to obtain tD1.

[0185] According to the type, the processed data of any group is shifted to obtain tD1, including:

[0186] Extract the exponent and mantissa of each processed data in any group according to the type.

[0187] Determine the two's complement of each mantissa.

[0188] According to the complements of the exponents and the mantissas, the order is shifted to obtain the third data tD3.

[0189] After performing floating point special value detection on tD3, tD1 is obtained.

[0190] According to the complements of the exponents and the mantissas, the order shift is performed to obtain the third data tD3, including:

[0191] Determine the maximum value E among each index max .

[0192] For any processed data, perform docking shift through the following steps to obtain the corresponding tD3:

[0193] Set the bit count value nC i =0.

[0194] Calculate E from low to high max With E i The difference between the Every time you get a difference of nC i At the same time, every time nC i When a non-zero segment value is reached, the difference between the current segment value -1 and the previous segment value is used to form the shift bit. according to Shift the shift result of the previous segment to obtain tD3 corresponding to any processed data.

[0195] Among them, i is the processing data identifier, E i is the index of processing data i, j is the bit identifier, For E max With E i The first segment value is 0. If the current segment value is the first non-zero value, the target segment value is 0. If the current segment value is not the first non-zero value, the target segment value is the previous segment value of the current segment value + 1. v is the segment identifier. The initial value of v is 1. If v = 1, the shift result src of the previous segment i It consists of a sign bit and the complement of the mantissa of the processed data i.

[0196] Among them, the segment values ​​are 0, 3, 6, and 11.

[0197] Whenever nC i When a non-zero segment value is reached, the difference between the current segment value and the target segment value is used to form the shift bit. according to Shift the shift result of the previous segment to obtain tD3 corresponding to any processed data, including:

[0198] When nC i =3, the difference between 2 and 0 is used to form the shift number src i Shift right bits, get the shift result of the first segment

[0199] When nC i =6, the difference between 5 and 3 is used to form the shift number Will Shift right bits, and get the shift result of the second segment

[0200] When nC i =11, the difference between 10 and 6 is used to form the shift number like Then determine the corresponding processing data i Otherwise, it is determined that tD3 corresponding to the processed data i is equal to 0.

[0201] The leading zero detection is performed on the compression result to obtain the cumulative result of the group of data, including:

[0202] The number of determination bits nd is determined to be the total number of bits of the compression result.

[0203] The compression result is determined as fourth data tD4.

[0204] Determine whether the high nd bits of tD4 are all 0.

[0205] If all 0s, then when nd is the total number of bits of the compression result, the fifth data tD5=0 is obtained. When nd is the total number of bits of the non-compression result, determine tD4=tD4<<nd. If nd=1, then tD5=tD4 is obtained. If nd≠1, then Repeat the step of determining whether the upper nd bits of tD4 are all 0s and subsequent steps.

[0206] If it is not all 0, then when nd=1, tD5=tD4, and when nd≠1, Repeat the steps of determining whether the high nd bits of tD4 are all 0 and the subsequent steps. is the ceiling function.

[0207] tD5 is expanded to obtain sixth data tD6.

[0208] After performing floating point special value detection on tD6, the accumulated result of this group of data is obtained.

[0209] This embodiment provides an accumulator that reads a group of data in sequence based on an identifier in an instruction; each group includes a preset number of processed data; for each group, Wallace tree-based compression is performed based on the type, and leading zero detection is performed on the compression result to obtain the accumulation result of the group of data, thereby accelerating the data processing rate and improving processing efficiency.

[0210] Based on the same inventive concept of the data accumulation method, this embodiment provides a chip comprising Figure 5 The accumulator shown.

[0211] The accumulator is used to implement the data accumulation method shown in 1.

[0212] Specifically, in the data accumulation method, an instruction is obtained. The instruction includes an identifier of the processed data and a type of the processed data. The type is a floating point number type or a fixed point number type.

[0213] Based on the identifier, read a group of data in sequence. Each group includes processing data, mC is the minimum processing amount for a single time, nB is the number of bits of any processing data, is the floor function.

[0214] For each group, Wallace tree-based compression is performed based on the type, and leading zero detection is performed on the compressed result to obtain the accumulated result of the group of data.

[0215] Optionally, for any group, perform Wallace tree-based compression based on type, including:

[0216] According to the type and the processed data of any group, the first data tD1 is determined.

[0217] Compress tD1 based on the Wallace tree to obtain 2 second data and

[0218] Will and Add them together to get the compressed result.

[0219] Optionally, determining the first data tD1 according to the type and the processed data of any group includes:

[0220] If the type is a fixed-point number type, tD1 is determined to be the processing data of any group.

[0221] If the type is a floating-point number type, then the order of the processed data of any group is shifted according to the type to obtain tD1.

[0222] Optionally, according to the type, the processed data of any group is shifted to obtain tD1, including:

[0223] Extract the exponent and mantissa of each processed data in any group according to the type.

[0224] Determine the two's complement of each mantissa.

[0225] According to the complements of the exponents and the mantissas, the order is shifted to obtain the third data tD3.

[0226] After performing floating point special value detection on tD3, tD1 is obtained.

[0227] Optionally, a rank shift is performed according to the complements of each exponent and each mantissa to obtain third data tD3, including:

[0228] Determine the maximum value E among each index max .

[0229] For any processed data, perform docking shift through the following steps to obtain the corresponding tD3:

[0230] Set the bit count value nC i =0.

[0231] Calculate E from low to high max With E i The difference between the Every time you get a difference of nC i At the same time, every time nC iWhen a non-zero segment value is reached, the difference between the current segment value -1 and the previous segment value is used to form the shift bit. according to Shift the shift result of the previous segment to obtain tD3 corresponding to any processed data.

[0232] Among them, i is the processing data identifier, E i is the index of processing data i, j is the bit identifier, For E max With E i The first segment value is 0. If the current segment value is the first non-zero value, the target segment value is 0. If the current segment value is not the first non-zero value, the target segment value is the previous segment value of the current segment value + 1. v is the segment identifier. The initial value of v is 1. If v = 1, the shift result src of the previous segment i It consists of a sign bit and the complement of the mantissa of the processed data i.

[0233] Optionally, the segment value is 0, 3, 6, or 11.

[0234] Whenever nC i When a non-zero segment value is reached, the difference between the current segment value and the target segment value is used to form the shift bit. according to Shift the shift result of the previous segment to obtain tD3 corresponding to any processed data, including:

[0235] When nC i =3, the difference between 2 and 0 is used to form the shift number src i Shift right bits, get the shift result of the first segment

[0236] When nC i =6, the difference between 5 and 3 is used to form the shift number Will Shift right bits, and get the shift result of the second segment

[0237] When nC i =11, the difference between 10 and 6 is used to form the shift number like Then determine the corresponding processing data i Otherwise, it is determined that tD3 corresponding to the processed data i is equal to 0.

[0238] Optionally, a leading zero detection is performed on the compression result to obtain an accumulation result of the group of data, including:

[0239] The number of determination bits nd is determined to be the total number of bits of the compression result.

[0240] The compression result is determined as fourth data tD4.

[0241] Determine whether the high nd bits of tD4 are all 0.

[0242] If all 0s, then when nd is the total number of bits of the compression result, the fifth data tD5=0 is obtained. When nd is the total number of bits of the non-compression result, determine tD4=tD4<<nd. If nd=1, then tD5=tD4 is obtained. If nd≠1, then Repeat the step of determining whether the upper nd bits of tD4 are all 0s and subsequent steps.

[0243] If it is not all 0, then when nd=1, tD5=tD4, and when nd≠1, Repeat the steps of determining whether the high nd bits of tD4 are all 0 and the subsequent steps. is the ceiling function.

[0244] tD5 is expanded to obtain sixth data tD6.

[0245] After performing floating point special value detection on tD6, the accumulated result of this group of data is obtained.

[0246] In a specific implementation, the chip may be a vector processor, and the accumulator serves as a functional unit in the vector processor.

[0247] In addition to the accumulator, the vector processor may also include a vector program control unit, other functional units, a register file, and a scalar register register, such as Figure 6 shown.

[0248] In addition, the vector processor also includes: a private vector register of a vector interleaving unit and a private vector register of a vector access unit.

[0249] 1. Vector program control unit

[0250] Vector program control unit, used for instruction fetching and instruction issuance.

[0251] That is, the vector program control unit is used to fetch instructions, determine whether to execute them, and send the instructions to the functional units based on the determination result.

[0252] The vector program control unit is also used to control instruction jumps.

[0253] The vector program control unit has scalar computing capabilities.

[0254] The vector program control unit interacts with the scalar registers.

[0255] In specific implementation, the vector program control unit is an instruction fetch and instruction issuance unit. It takes instructions from the cache according to the PC value, and after determining whether to execute them, it issues the instructions to each functional unit according to the wait value (configured by the wait instruction). At the same time, it controls the jump of instructions and has some scalar computing capabilities.

[0256] In addition, the vector program control unit is further configured to receive a start command from other operation processors to start the vector processor and return an indication signal to the other operation processors indicating whether the vector processor has finished operation.

[0257] Taking the scalar processor as an example, the vector program control unit receives the start command issued by the synchronization unit of the scalar processor, starts the vector processor execution, and also returns an indication signal indicating whether the synchronization unit vector processor execution is completed.

[0258] 2. Functional Unit

[0259] Functional unit, used to perform functional processing according to instructions.

[0260] For example, the functional unit receives an instruction from the vector program control unit, processes data accordingly according to the instruction, and outputs the processing result according to the address specified in the instruction.

[0261] The functional units include: one or more vector operation units, one or more vector interleaving units, and one or more vector access units.

[0262] 1) Vector operation unit

[0263] Any vector arithmetic unit, used to perform vector operations according to instructions.

[0264] For example, the vector operation unit is Figure 5 The accumulator shown.

[0265] 2) Vector interleaving unit

[0266] Any vector interleaving unit is used to perform data interleaving and logic processing according to instructions.

[0267] The vector interleaver unit is the control and data processing unit within the vector processor. It is responsible for interleaving data and supports logical and some fixed-point and floating-point calculations. It also supports a wide range of customized instructions, including table lookup, lateral calculations, sparse matrix calculations, precision conversion, and FIFO (First Input First Output). It also executes instructions such as data broadcasting, extraction, and internal interleaving.

[0268] Each vector interleaving unit has a set of private vector registers, so the private vector registers of the vector interleaving units correspond one to one with the vector interleaving units.

[0269] 3) Vector access unit

[0270] Any vector access unit, used to perform multi-mode memory access, address calculation and scalar calculation according to the instruction.

[0271] The vector access unit is a memory access unit within a vector processor, primarily responsible for reading / writing instructions and various scalar calculations.

[0272] The read instruction / write instruction supports multiple memory access modes, such as row mode, column mode / discrete mode / extended mode / accumulated mode.

[0273] It also supports multiple parameter configurations, with a maximum read / write instruction data width of 1024 bits. It can also perform address calculation, load / store and other instructions.

[0274] All vector access units share a set of private vector registers, so the private vector registers of a vector access unit are shared by multiple vector access units.

[0275] 3. Register file stack

[0276] The register file receives read and write requests and returns data. It rearranges the data before returning it. It interacts with the functional units for read and write operations. The vector program control unit's configuration registers are configured using data in the register file.

[0277] The register file is a general-purpose vector register stack and is the main storage unit within the vector processor. It is responsible for receiving read and write requests and returning data. In some functions, it can rearrange the data before returning it to the request module.

[0278] The register file stack performs read and write interactions with the functional units in the vector processor (such as the floating-point multiplication-addition operator unit, the floating-point arithmetic operator unit, the floating-point multiplication-accumulation operator unit, and the tensor multiplication subunit), and supports the use of data in the register file stack to configure the instruction fetch unit configuration register.

[0279] The register file stack is also used to write data to other processors and receive status information from other processors to check whether the data has been written.

[0280] Taking a scalar processor as an example, the synchronization unit of the scalar processor can write data into the register file stack, and the register file stack can also receive status information from the synchronization unit of the scalar processor to inquire whether the data has been written.

[0281] The depth of the register file is configurable.

[0282] In addition, a read FIFO unit and a write FIFO unit are provided between the vector processor and other operation processors.

[0283] The vector program control unit and other operation processors both perform a read operation on the read FIFO unit and a write operation on the write FIFO unit.

[0284] Other arithmetic processors perform read operations or write operations on the vector registers.

[0285] Taking a scalar processor as an example, a read FIFO and a write FIFO unit for transmitting data are provided between the scalar processor and the vector processor. The scalar processor and the vector program control unit can perform read operations or write operations on the read and write FIFO.

[0286] At the same time, the synchronization unit of the scalar processor can read or write the scalar register of the vector processor.

[0287] In addition, in specific implementation, the chip can also be a high-performance processor.

[0288] The high-performance processor includes a scalar processor and a vector processor.

[0289] The connection relationship between the scalar processor and the vector processor can be shown as follows Figure 7 shown.

[0290] The scalar processor and the vector processor share memory. The vector processor can only access memory and can only be called and executed by the scalar processor.

[0291] A connection is established between the scalar processor and the vector processor. For example, the scalar processor and the vector processor are connected via a dedicated instruction channel.

[0292] In addition, the high-performance processor may also include two registers, one register corresponding to the scalar processor and the other register corresponding to the vector processor. The vector processor can read and write its corresponding register, and the scalar processor can read and write its corresponding register as well as the vector processor's corresponding register.

[0293] The scalar processor can read and write the registers of the vector processor.

[0294] Scalar processors establish connections to global memory.

[0295] (1) Scalar processor

[0296] See also Figure 8The scalar processor may include: an instruction fetch unit, a register renaming unit, an operation reservation stack unit, a storage reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit.

[0297] In addition, the scalar processor may also include one or more other units, such as one or more other functional modules, one or more instruction caches, one or more data storages, one or more special vector registers, one or more status flag registers, etc.

[0298] 1. Instruction fetch unit

[0299] The instruction fetch unit is used to fetch and dispatch instructions.

[0300] Specifically, the instruction fetch unit generates an instruction fetch request address, outputs the fetch request address to the instruction cache for instruction fetching, receives instructions from the instruction cache, and stores them in the data store. Each cycle, it sequentially reads qualified instructions from the data store, decodes and performs relevant checks on the read instructions, and then dispatches the checked instructions sequentially.

[0301] For example, the instruction fetch unit generates an instruction fetch request address and outputs it to the instruction cache for instruction fetch, and receives instructions from the instruction cache and stores them in the data storage. In each cycle, it sequentially selects one or more instructions from the qualified instructions for decoding and related checks, and dispatches the qualified instructions sequentially, dispatching at most one program control unit instruction and one synchronization unit instruction at a time. In addition, one or more scalar operation unit instructions and one or more memory access unit instructions can also be dispatched each time.

[0302] 2. Register renaming unit

[0303] The register renaming unit is used to receive instructions dispatched by the instruction fetch unit and rename registers.

[0304] Specifically, the register renaming unit receives and stores instructions dispatched by the instruction fetch unit, renames special vector registers, conditionally decodes instructions, and generates pipeline stall signals. It also receives and writes data from one or more of the scalar arithmetic unit, memory access unit, program control unit, synchronization unit, special vector registers, condition registers, and flag registers. It also sends instructions to one or more of the arithmetic hold stack unit, memory hold stack unit, program control unit, and synchronization unit.

[0305] For example, the register renaming unit is used in a scalar processor to receive instructions dispatched by the instruction fetch unit and perform register and special vector register renaming, instruction conditional decoding, and generate pipeline congestion signals. At the same time, it receives data from the execution unit (such as the scalar operation unit, memory access unit, program control unit, synchronization unit) to write back registers, special vector registers, condition registers, and status flag registers and writes them back to the corresponding registers.

[0306] The scalar processor write-back supports out-of-order write-back, has high execution efficiency, and distributes instructions to the operation retention stack unit, the storage retention stack unit, the program control unit, or the synchronization unit.

[0307] The register renaming unit bandwidth may be 6 bits, wherein multiple (eg, 4) input instructions may be valid at the same time.

[0308] There can be multiple condition registers, which are located in the register renaming unit.

[0309] The instructions of the scalar operation unit and memory access unit support the operations of reading and writing condition registers.

[0310] The synchronous unit's instructions support the operation of reading the condition register.

[0311] The jump and function call instructions of the program control unit support the operation of reading the condition register.

[0312] When an instruction enters the condition register, if there is an unexecuted instruction in the condition register, the pipeline will be blocked.

[0313] That is, the condition register is not renamed, and when a read-write dependency occurs, a dispatch block is triggered to wait. The read and write rules for the condition register are as follows:

[0314] ●Read the rules:

[0315] (1) All instructions of the scalar arithmetic unit, memory access unit, and synchronization unit support conditional execution and require reading the value of the condition register.

[0316] (2) The scalar arithmetic unit also supports read conditional register instruction operations.

[0317] (3) The jump and function call instructions of the program control unit support read condition register operations.

[0318] ●Write rules:

[0319] (1) The scalar arithmetic unit supports write conditional register instructions.

[0320] (2) Scalar operation unit logic instructions and comparison instructions support the option of writing condition registers.

[0321] When the previously issued instruction to write the condition register has not yet been completed, and an instruction to read or write the same condition register enters, the pipeline is blocked and a conditional execution blocking signal is generated, waiting for the previous condition register to be written.

[0322] In addition, the register renaming unit includes: one or more physical registers and one or more logical registers.

[0323] Wherein, any physical register is one of the following: a vector physical register, a condition register, and a flag register.

[0324] Any logic register is one of the following: read-only register, vector logic register.

[0325] For example, the register renaming unit includes one or more physical registers, such as a plurality of 512-bit wide special vector registers, a plurality of condition registers, and a status flag register.

[0326] Among them, special vector registers are renamed, while condition registers and status flag registers are not renamed.

[0327] There are multiple logical registers, such as multiple read-only logical registers and multiple vector logical registers.

[0328] In addition, the mapping relationship between logical registers and physical registers is maintained by the register mapping table. The mapping relationship between vector logical registers and vector physical registers is maintained by the special vector register mapping table.

[0329] 1) Register Mapping Table

[0330] Initially, the physical registers mapped to the entries corresponding to all logical register indices in the register mapping table are all 0. When an instruction is executed or an interrupt occurs, the logical registers allocated to the relevant physical registers are determined, and the mappings of the entries corresponding to the allocated logical register indices in the register mapping table are updated to the identifiers of the relevant physical registers.

[0331] For example, a register map table with a depth of 32 bits and a width of 6 bits stores the mapping between all logical registers and all physical registers. Initially, the mapping in the register map table is invalid, and all entries for the mapped physical registers are set to zero. When a physical register is assigned to a logical register, the entry corresponding to the logical register index in the register map table is changed to the ID of the physical register.

[0332] It should be noted that the register mapping table is updated only when the instruction is actually executed. If the conditional execution instruction is not executed, the register mapping table will not be updated. In addition, the register mapping table will not be updated when a jump occurs. However, when an interrupt occurs, the interrupt return address must update the register mapping table to ensure that the interrupt can return normally.

[0333] 2) Special vector register mapping table

[0334] Initially, the mapping vector physical registers of all entries corresponding to the vector logical register indexes in the special vector register mapping table are all 0. When an instruction is executed, the vector logical register allocated to the relevant vector physical register is determined, and the mapping of the entry corresponding to the allocated vector logical register index in the special vector register mapping table is updated to the identifier of the relevant vector physical register.

[0335] For example, the special vector register mapping table has a depth of 4 and a width of 3 bits, storing the mapping relationship between all vector logical registers and all vector physical registers. Initially, the special vector register mapping table is invalid, and all entries for the mapped vector physical registers are all zeros. When a vector physical register is assigned to a vector logical register, the entry corresponding to the vector logical register index in the special vector register mapping table is changed to the ID of the vector physical register.

[0336] It should be noted that the special vector register mapping table is updated only when the instruction is actually executed. If the conditional execution instruction is not executed, the special vector register mapping table will not be updated. In addition, the special vector register mapping table will not be updated when a jump occurs.

[0337] 3. Operation reservation stack unit

[0338] The operation reserve stack unit is the emission queue of the scalar operation unit.

[0339] The operation reserve stack unit receives instructions, dispatch and renaming information from the register renaming unit and pushes them into the queue. It then pops ready instructions to the scalar operation unit for execution.

[0340] The operation reserve stack unit is also used to decode input instructions and store instruction type information.

[0341] In other words, the Arithmetic Hold Stack unit acts as the issue queue for the scalar arithmetic unit. It receives instructions and associated dispatch and renaming information from the register renaming unit, pushes them into the queue, and then pops ready instructions onto the scalar arithmetic unit for execution. The Arithmetic Hold Stack unit decodes the incoming instructions and stores the instruction type information.

[0342] In specific implementation, the depth of the operation reserve stack unit can be flexibly adjusted, for example, the depth of the operation reserve stack unit is 8. Multiple scalar operation units share one operation reserve stack unit.

[0343] The rules for issuing and receiving instructions for the operation reserve stack unit are as follows:

[0344] (1) The output of the register renaming unit enters the operation preservation stack unit.

[0345] (2) When there is any idle scalar operation unit, it will fetch instructions and operands from the operation reservation stack unit for execution.

[0346] (3) The principle of executing instructions from the operation reservation stack unit is to execute the executable instructions that can be sent from the operation reservation stack unit in a forward-to-back order.

[0347] (4) Whether the transmission can be made is determined by whether the values ​​of all source registers or special vector registers or condition registers and status flag registers are ready.

[0348] (5) If there are multiple instructions that can be sent, the oldest instruction will be sent first according to the instruction order.

[0349] (6) If any scalar operation unit is blocked, it can no longer receive new instructions.

[0350] (7) If the instruction previously sent to any scalar operation unit is a division instruction, a new division instruction can only be sent to it after the division result calculation is completed and the calculation completion En signal is returned.

[0351] 4. Storage Retention Stack Unit

[0352] The storage reservation stack unit is the transmit queue of the memory access unit.

[0353] The storage reservation stack unit is used to receive instructions and register renaming information from the register renaming unit and push them into the queue.

[0354] The storage reservation stack unit is also used to send a read request to the register renaming unit when the instruction address register is ready, and save the read address operand.

[0355] The register renaming unit is also used to calculate the address, decode the address, and save the decoding information after the instruction obtains the address.

[0356] The register renaming unit is also used to detect when the source register of any instruction is ready and the address decoding is completed, and then send it to the memory access unit for execution.

[0357] In specific implementation, the depth of the storage reservation stack unit can be flexibly adjusted, such as the depth of the storage reservation stack unit is 16. Multiple memory access units share one storage reservation stack unit. The storage reservation stack unit is the transmission queue of the memory access unit. The storage reservation stack unit receives instructions and register renaming information from the register renaming unit and pushes them into the queue. When the instruction address register in the storage reservation stack unit is ready, a read request is sent to the register renaming unit and the read address operand is saved in the queue. After the instruction in the storage reservation stack unit obtains the address, the address can be calculated and decoded, and the generated decoding information is saved in the queue. When the source register of an instruction (such as a write instruction) in the storage reservation stack unit is ready and the address decoding is completed, it can be transmitted to the memory access unit for execution. Before transmission, it must undergo a series of checks, such as address type check, address comparison check, and address forward check.

[0358] The rules for sending and receiving instructions to the storage reserve stack unit are as follows:

[0359] (1) The output of the register renaming unit enters the storage reservation stack unit.

[0360] (2) When the source operand for calculating the address is ready, the memory access address is calculated and saved in the storage reservation stack unit.

[0361] (3) Instructions with unrelated addresses: They can be sent out of order. The out-of-order rules are: read instructions after read instructions, write instructions after read instructions, and read instructions after write instructions. They can all be sent out of order. Write instructions after write instructions need to maintain order (they cannot be sent to different memory access units at the same time). Even if the addresses are unrelated, write instructions after write instructions still need to maintain order.

[0362] (4) Address-related instructions: read instructions followed by write instructions, write instructions followed by read instructions, write instructions followed by write instructions, and read instructions followed by read instructions all need to be performed in order.

[0363] (5) When the addresses are unrelated but all instructions that have not been sent successfully (i.e., instructions on the way that have not been sent to the destination, including those at the memory access unit level and the memory access unit output level) are located in the same storage space, they can be sent out of order to the same memory access unit, but they cannot be sent to two or more memory access units.

[0364] (6) Only one memory access instruction located in the same storage space but with unrelated addresses can be sent at the same time, and two or more memory access units cannot be sent at the same time.

[0365] (7) Address correlation judgment principle: Whether the addresses are related is irrelevant if they are located in different storage spaces. If they are located in the same storage space, whether the addresses are related is determined based on the data granularity.

[0366] 5. Scalar arithmetic unit

[0367] In a specific implementation, there may be one or more scalar operation units.

[0368] For example, the scalar processor includes two scalar arithmetic units, namely scalar arithmetic unit 0 and scalar arithmetic unit 1.

[0369] The scalar operation unit is used to receive instructions and data sent by the operation reservation stack unit, perform operations on the data based on the instructions, and write the operation results back to the register renaming unit.

[0370] The scalar arithmetic unit is the computing unit of the scalar processor, which can perform various types of fixed-point and floating-point operations, such as addition, subtraction, multiplication, division, logical operations, comparison operations, shifts, etc. It receives instructions and data sent by the operation reserve stack unit, performs operations, and writes the results back to the register file unit of the register renaming unit or the special vector register file unit.

[0371] Several instruction examples are provided below as examples. In specific implementation, they are not limited to the following instructions, nor are they limited to including all instructions.

[0372] Instructions with execution level one include: fixed-point addition and subtraction, logical instructions, shift instructions, fixed-point and floating-point comparison instructions, read and write Flag instructions, fixed-point maximum and minimum instructions, ABS instructions, bit reversal instructions, selection instructions, special vector register distribution instructions, read special vector register instructions, Byte reversal instructions, Merge instructions, immediate value assignment instructions, FirstOne instructions, CRC instructions, floating-point classification instructions, floating-point partial domain extraction, and Rounding instructions.

[0373] Instructions with execution level three include: fixed-point multiplication instructions, fixed-floating-point conversion instructions, bit filtering instructions, Count instructions, and floating-point addition and subtraction instructions.

[0374] Instructions that support Bypass include: selection instructions, fixed-point addition and subtraction instructions, shift instructions, immediate value assignment instructions, ABS instructions, logical instructions, comparison instructions, and maximum and minimum instructions.

[0375] The execution cycle of the division instruction is uncertain and is related to the data of the divisor and the dividend. When the instruction is executed, a DivEn instruction will be generated to indicate that the instruction is executed and the result is output to the register stack. No new division instructions can be input during the execution of the division instruction, but other scalar calculation unit instructions can be input. After the division is executed, the output result is reused with the output port of the first-stage pipeline. When the output port of the first-stage pipeline is not used by other scalar calculation unit instructions, the division outputs its result and outputs the DivEn identifier at the same time. The DivEn identifier is output to the operation retention stack unit, indicating that the Div instruction can continue to be output to the current scalar calculation unit.

[0376] 6. Memory access unit

[0377] In a specific implementation, there may be one or more memory access units.

[0378] For example, a scalar processor includes two memory access units, namely memory access unit 0 and memory access unit 1.

[0379] The memory access unit is used to receive instructions, data and register information sent by the storage reservation stack unit, and read and write the data based on the instructions and register information.

[0380] The memory access unit is a functional module that executes memory access-related instructions for scalar processors. The memory access unit receives instructions and data, as well as register-related information, from the storage retention stack unit. It executes instructions accordingly and interacts with other units to read and write data. Read instructions and atomic write instructions require writing data back to the register renaming unit. These instructions include register-level read and write instructions, including 8-bit, 16-bit, 32-bit, 64-bit, or other bit granularities, as well as vector read and write instructions, including 128-bit, 256-bit, 512-bit, or other bit granularities. Different instructions have different processing cycles.

[0381] In addition, the memory access unit is responsible for providing the relevant instruction quantity information required by FENCE. The memory access unit interacts with the storage reservation stack unit to complete the data storage configuration.

[0382] 7. Program control unit

[0383] In a specific implementation, there is only one program control unit.

[0384] The program control unit is configured to receive instructions and data from the register renaming unit, process the data based on the instructions, and output a processing result.

[0385] The program control unit (PCU) executes instructions related to the scalar processor's program execution sequence. The PCU receives instructions and data from the register renaming unit (RRU), processes the data accordingly, and outputs the results to other modules in the scalar processor. Different instructions are processed in different time periods.

[0386] The program control unit is responsible for controlling the direction of program execution (such as stop, interrupt, jump, function call), involving the execution of related instructions and the reading and writing control of configuration information; the program control unit is responsible for the configuration and prefetch operations of the instruction cache, as well as FENCE operations; the program control unit is responsible for the reading, writing and control of the counter, as well as the reading and writing of some other control information.

[0387] 8. Synchronization unit

[0388] In a specific implementation, there is only one synchronization unit.

[0389] Synchronization unit, used to synchronize the scalar processor and the vector processor.

[0390] like Figure 9 As shown, a communication connection is established between the synchronization unit and the pipeline control unit, the register renaming unit, the program control unit, and the vector processor.

[0391] The instructions of the synchronization unit come from the register renaming unit, and the reading and writing of the data of the synchronization unit interact with the register renaming unit.

[0392] The synchronization unit is used to receive the pause signal sent by the pipeline control unit and send the execution level pause signal generated when communicating with the vector processor to the pipeline control unit so as to generate the execution pause signal of the scalar processor.

[0393] The synchronization unit is used to generate instructions and transmit them to the program control unit.

[0394] That is to say, the synchronization unit is a unit that synchronizes the scalar processor and the vector processor. It receives instructions and data sent by the register renaming unit, reads data from the vector processor and writes it back to the register stack, reads data from the register stack unit or the special vector register stack unit and sends it to the functional module of the vector processor. It is responsible for the startup and status query of the vector processor, such as querying the reading and writing of the read and write FIFO (FirstInput FirstOutput) in the vector program control unit of the vector processor, the configuration of the register file stack, the reading or writing of the scalar register, the register file stack status query, the reading FIFO depth, the reading of the startup vector processor instruction counter, etc., and providing the program control unit with the synchronization unit instruction information.

[0395] The synchronization unit interacts with the pipeline control unit, register renaming unit, and program control unit within the scalar processor, as well as with the external vector processor, scalar processor, and vector processor transfer queue module. Synchronization unit instructions originate from the register renaming unit, and data reading and writing must interact with the register renaming unit. The synchronization unit receives a stall signal from the pipeline control unit and, when communicating with the vector processor, generates its own execute-level stall signal, which is sent to the pipeline control unit to generate the ExeStall signal for the entire scalar processor. The synchronization unit generates the instruction to be executed in the next cycle and transmits it to the program control unit for use by the program control unit's counter instruction. Interactions with the vector processor include, but are not limited to, configuring the register file with special vector registers or registers, reading and writing scalar registers, and querying the write status of the register file. Interactions with the scalar processor and vector processor transfer queue module include, but are not limited to, starting the vector processor, querying vector processor status, reading and writing data in the vector processor's instruction fetch unit FIFO, reading the FIFO depth, and reading the start vector processor instruction counter.

[0396] Therefore, in a specific implementation, the synchronization unit may have the following functions (it should be noted that the following functions are only examples, and other functions may be provided. This embodiment and subsequent embodiments do not limit the specific functions of the synchronization unit):

[0397] The start vector processor function is used to start the vector processor, including immediate start and register start, such as the pipeline waits until the start is successful, or writes the result of the start success or failure back to the destination register.

[0398] Query the vector processor execution status function, support option B.

[0399] Read and write FIFO function, the FIFO is located in the instruction fetch unit of the vector processor, such as the FIFO bit width 32 bits, the read and write FIFO such as the read and write FIFO waits until success, or the read and write FIFO success or failure result is written back to the register.

[0400] Write register file stack functions, including special vector register writes or register writes.

[0401] Read and write scalar register functions, including immediate index or register index read and write.

[0402] Query the register file stack write back status function, such as waiting until all writes to the register file stack are completed, or returning the result of whether the write to the register file stack is completed to the register.

[0403] When the related operations are not completed, the synchronization unit will generate its own blocking signal, blocking and waiting, and the signal will be sent to the pipeline control unit to generate a pipeline blocking signal.

[0404] A FIFO (such as a 32-bit deep FIFO) can also be added between the scalar processor and the vector processor to store the request to start the vector processor, and move the read and write FIFO previously located in the vector processor to the scalar processor and vector processor transmission queue module. The scalar processor and vector processor transmission queue module unit implements the startup of the vector processor, queries the execution status of the vector processor, reads and writes FIFO functions, reads FIFO depth functions, and reads the startup vector processor instruction counter function. The condition for the successful startup of the vector processor is that the startup vector processor FIFO is not full, and the query of the vector processor execution status is passed. The condition for the vector processor status to be stopped is that the vector processor execution is completed and the startup vector processor FIFO is empty.

[0405] 9. Assembly line control unit

[0406] The pipeline control unit is used to generate a pipeline pause signal and / or generate a start and stop signal for the scalar processor.

[0407] The pipeline control unit is the pipeline control unit of the scalar processor, which is connected to each unit inside the scalar processor and is responsible for generating pipeline blocking signals, such as blocking in normal working mode and blocking in debug mode.

[0408] The pipeline control unit also communicates with the communication and synchronization unit to generate signals for starting and stopping the scalar processor.

[0409] Furthermore, in practical applications, scalar processors can also perform conditional execution decoding. For example, when performing conditional execution decoding, a scalar processor determines the execution condition of the instruction's preset bits. If the condition is met, a valid instruction is output; otherwise, a null instruction is output. A null instruction refers to an empty or invalid instruction.

[0410] If there are read or write operations on the condition register, the pipeline is blocked and the read operation can only be performed after the write operation is completed. There is no bypass when reading or writing the condition register.

[0411] Taking two condition registers, namely condition register 0 and condition register 1, and the preset bits being [29:28] as an example, when the scalar processor performs conditional execution decoding, the scalar processor judges the execution condition of the input instruction based on the [29:28] bits of the instruction set encoding. If the condition is met, a valid instruction is output, otherwise an empty instruction is output.

[0412] Among them, [29:28] bits are 00, indicating that condition register 0 is 1 and execution is executed, [29:28] bits are 01, indicating that condition register 1 is 1 and execution is executed, [29:28] bits are 10, indicating that condition register 0 is executed, and [29:28] bits are 11, indicating unconditional execution. If the condition is not met, the instruction is invalid and a null instruction is output.

[0413] If the condition register is read or written, the pipeline is blocked and the read operation is performed after the condition register is written. There is no bypass when reading or writing the condition register.

[0414] (2) Vector Processor

[0415] The accumulator acts as a functional unit in a vector processor.

[0416] In a specific implementation, the chip can be a vector processor, and the accumulator is a functional unit in the vector processor. In addition to the accumulator, the vector processor can also include a vector program control unit, other functional units, a register file and a scalar register register, such as Figure 6 shown.

[0417] In addition, the vector processor also includes: a private vector register of a vector interleaving unit and a private vector register of a vector access unit.

[0418] This embodiment provides a chip, in which an accumulator reads a group of data in sequence based on an identifier in an instruction; each group includes a preset number of processed data; for each group, Wallace tree-based compression is performed based on the type, and leading zero detection is performed on the compressed result to obtain the accumulated result of the group of data, thereby accelerating the data processing rate and improving processing efficiency.

[0419] Based on the same inventive concept of the data accumulation method, this embodiment provides an electronic device, which includes a chip.

[0420] The chip includes Figure 5 The accumulator shown.

[0421] The accumulator is used to implement the data accumulation method shown in 1.

[0422] Specifically, in the data accumulation method, an instruction is obtained. The instruction includes an identifier of the processed data and a type of the processed data. The type is a floating point number type or a fixed point number type.

[0423] Based on the identifier, read a group of data in sequence. Each group includes processing data, mC is the minimum processing amount for a single time, nB is the number of bits of any processing data, is the floor function.

[0424] For each group, Wallace tree-based compression is performed based on the type, and leading zero detection is performed on the compressed result to obtain the accumulated result of the group of data.

[0425] Optionally, for any group, perform Wallace tree-based compression based on type, including:

[0426] According to the type and the processed data of any group, the first data tD1 is determined.

[0427] Compress tD1 based on the Wallace tree to obtain 2 second data and

[0428] Will and Add them together to get the compressed result.

[0429] Optionally, determining the first data tD1 according to the type and the processed data of any group includes:

[0430] If the type is a fixed-point number type, tD1 is determined to be the processing data of any group.

[0431] If the type is a floating-point number type, then the order of the processed data of any group is shifted according to the type to obtain tD1.

[0432] Optionally, according to the type, the processed data of any group is shifted to obtain tD1, including:

[0433] Extract the exponent and mantissa of each processed data in any group according to the type.

[0434] Determine the two's complement of each mantissa.

[0435] According to the complements of the exponents and the mantissas, the order is shifted to obtain the third data tD3.

[0436] After performing floating point special value detection on tD3, tD1 is obtained.

[0437] Optionally, a rank shift is performed according to the complements of each exponent and each mantissa to obtain third data tD3, including:

[0438] Determine the maximum value E among each index max .

[0439] For any processed data, perform docking shift through the following steps to obtain the corresponding tD3:

[0440] Set the bit count value nC i =0.

[0441] Calculate E from low to high max With E iThe difference between the Every time you get a difference of nC i At the same time, every time nC i When a non-zero segment value is reached, the difference between the current segment value -1 and the previous segment value is used to form the shift bit. according to Shift the shift result of the previous segment to obtain tD3 corresponding to any processed data.

[0442] Among them, i is the processing data identifier, E i is the index of processing data i, j is the bit identifier, For E max With E i The first segment value is 0. If the current segment value is the first non-zero value, the target segment value is 0. If the current segment value is not the first non-zero value, the target segment value is the previous segment value of the current segment value + 1. v is the segment identifier. The initial value of v is 1. If v = 1, the shift result src of the previous segment i It consists of a sign bit and the complement of the mantissa of the processed data i.

[0443] Optionally, the segment value is 0, 3, 6, or 11.

[0444] Whenever nC i When a non-zero segment value is reached, the difference between the current segment value and the target segment value is used to form the shift bit. according to Shift the shift result of the previous segment to obtain tD3 corresponding to any processed data, including:

[0445] When nC i =3, the difference between 2 and 0 is used to form the shift number src i Shift right bits, get the shift result of the first segment

[0446] When nC i =6, the difference between 5 and 3 is used to form the shift number Will Shift right bits, and get the shift result of the second segment

[0447] When nC i =11, the difference between 10 and 6 is used to form the shift number like Then determine the corresponding processing data i Otherwise, it is determined that tD3 corresponding to the processed data i is equal to 0.

[0448] Optionally, perform leading zero detection on the compression result to obtain the accumulated result of this set of data, including:

[0449] Determine that the number of bits for judgment nd is the total number of bits of the compression result.

[0450] Determine the compression result as the fourth data tD4.

[0451] Judge whether the high nd bits of tD4 are all 0.

[0452] If they are all 0, when nd is the total number of bits of the compression result, obtain the fifth data tD5 = 0. When nd is not the total number of bits of the compression result, determine tD4 = tD4 << nd. If nd = 1, then obtain tD5 = tD4. If nd ≠ 1, then Repeat the steps of judging whether the high nd bits of tD4 are all 0 and subsequent steps.

[0453] If they are not all 0, when nd = 1, obtain tD5 = tD4. When nd ≠ 1, Repeat the steps of judging whether the high nd bits of tD4 are all 0 and subsequent steps. Among them, <000!2;53>is the ceiling function. <U

[0454] : Expand tD5 to obtain the sixth data tD6.

[0455] After performing floating-point special value detection on tD6, obtain the accumulated result of this set of data.

[0456] This embodiment provides an electronic device. The accumulator in this electronic device sequentially reads a set of data based on the identifier in the instruction; where each set includes a preset number of processed data; for each set, perform compression based on Wallace tree according to the type, perform leading zero detection on the compression result, and obtain the accumulated result of this set of data, which speeds up the data processing rate and improves the processing efficiency.

[0457] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present application can be implemented in various computer languages, for example, object-oriented programming languages such as Java and interpreted scripting languages such as JavaScript.

[0458] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0459] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0460] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0461] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0462] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A data accumulation method, characterized in that: The method comprises: Get an instruction; the instruction includes an identifier of the processing data and a type of the processing data; the type is a floating point number type or a fixed point number type; Based on the identification, a group of data is read in sequence; wherein each group includes processing data, mC is the minimum processing amount for a single time, nB is the number of bits of any processing data, is the floor function; For each group, compression based on the Wallace tree is performed based on the type, and a leading zero detection is performed on the compression result to obtain an accumulated result of the group of data.

2. The method according to claim 1, characterized in that For any group, the Wallace tree-based compression is performed based on the type, including: determining first data tD1 according to the type and the processed data of any one group; Compress tD1 based on the Wallace tree to obtain 2 second data and Will and Add them together to get the compressed result.

3. The method according to claim 2, characterized in that The determining of first data tD1 according to the type and the processed data of any one group includes: If the type is a fixed-point number type, then tD1 is determined to be the processing data of any group; If the type is a floating point number type, then according to the type, the order shift is performed on the processed data of any group to obtain tD1.

4. The method according to claim 3, characterized in that The step-shifting of the processed data of any group according to the type to obtain tD1 includes: extracting the exponent and mantissa of each processed data in any one of the groups according to the type; Determine the two's complement of each mantissa; Perform order shift according to the complements of each exponent and each mantissa to obtain the third data tD3; After performing floating point special value detection on tD3, tD1 is obtained.

5. The method according to claim 4, characterized in that The step shift is performed according to the complements of the exponents and the mantissas to obtain the third data tD3, including: Determine the maximum value E among each index max ; For any processed data, perform docking shift through the following steps to obtain the corresponding tD3: Set the bit count value nC i =0; Calculate E from low to high max With E i The difference between the Every time you get a difference of nC i At the same time, every time nC i When a non-zero segment value is reached, the difference between the current segment value -1 and the previous segment value is used to form the shift bit. according to Shift the shift result of the previous segment to obtain tD3 corresponding to any processed data; Among them, i is the processing data identifier, E i is the index of processing data i, j is the bit identifier, For E max With E i The first segment value is 0. If the current segment value is the first non-zero value, the target segment value is 0. If the current segment value is not the first non-zero value, the target segment value is the previous segment value of the current segment value + 1. v is the segment identifier. The initial value of v is 1. If v = 1, the shift result src of the previous segment i It consists of a sign bit and the complement of the mantissa of the processed data i.

6. The method according to claim 5, characterized in that The segment values ​​are 0, 3, 6, 11; Whenever nC i When a non-zero segment value is reached, the difference between the current segment value and the target segment value is used to form the shift bit. according to Shift the shift result of the previous segment to obtain tD3 corresponding to any processed data, including: When nC i =3, the difference between 2 and 0 is used to form the shift number src i Shift right bits, get the shift result of the first segment When nC i =6, the difference between 5 and 3 is used to form the shift number Will Shift right bits, and get the shift result of the second segment When nC i =11, the difference between 10 and 6 is used to form the shift number like Then determine tD3 corresponding to the processed data i = Otherwise, it is determined that tD3 corresponding to the processed data i is equal to 0.

7. The method according to claim 1, characterized in that The step of performing leading zero detection on the compression result to obtain the accumulated result of the group of data includes: Determine the number of bits nd as the total number of bits of the compression result; Determine the compression result as fourth data tD4; Determine whether the high nd bits of tD4 are all 0; If it is all 0, when nd is the total number of bits of the compression result, the fifth data tD5 = 0 is obtained; when nd is not the total number of bits of the compression result, it is determined that tD4 = tD4 << nd. If nd = 1, then tD5 = tD4 is obtained. If nd ≠ 1, then Repeat the steps of determining whether the high nd bits of tD4 are all 0 and the subsequent steps; If it is not all 0, then when nd=1, tD5=tD4, and when nd≠1, Repeat the step of determining whether the high nd bits of tD4 are all 0 and the subsequent steps; wherein, is the ceiling function; Expand tD5 to obtain sixth data tD6; After performing floating point special value detection on tD6, the accumulated result of this group of data is obtained.

8. An accumulator, characterized in that: The accumulator comprises: An acquisition module is used to acquire an instruction; the instruction includes an identifier of processing data and a type of processing data; the type is a floating point number type or a fixed point number type; A reading module is used to read a group of data in sequence based on the identification; wherein each group includes processing data, mC is the minimum processing amount for a single time, nB is the number of bits of any processing data, is the floor function; The accumulation module is used to perform Wallace tree-based compression on each group read by the reading module based on the type, perform leading zero detection on the compression result, and obtain an accumulation result of the group of data.

9. A chip, characterized in that: include: The accumulator according to claim 8; The accumulator is used to implement the data accumulation method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: The chip according to claim 9.

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