Time sequence analysis method based on integrated circuit post-simulation, electronic equipment and storage medium

Abstract

The invention provides a time sequence analysis method based on integrated circuit post-simulation, electronic equipment and a storage medium, and relates to the technical field of chip design. The method comprises the following steps: constructing an equivalent STA environment according to a post-simulation verification environment corresponding to a to-be-post-simulated module in a target integrated circuit; based on the STA environment, checking whether the interface signal delay of the to-be-simulated module conforms to a preset interface time sequence constraint or not; if not, performing time sequence repair on the interface through a virtual time sequence engineering change list so as to converge the interface time sequence; the method comprises the following steps: configuring a module to be subjected to post-simulation as an STA environment of top design, and outputting a target standard delay format file SDF when determining that an internal path of the module to be subjected to post-simulation meets a preset time sequence requirement, so that the STA environment equivalent to a post-simulation verification environment is constructed; according to the method, the interface time sequence violation of the module to be subjected to post-simulation in the post-simulation environment can be reproduced and repaired, the target SDF is generated for post-simulation, the post-simulation time is saved, and convergence of the verification time sequence of the post-simulation module is accelerated.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a timing analysis method, electronic device, and storage medium based on integrated circuit post-simulation. Background Art

[0002] Post-simulation of digital integrated circuits is a crucial tool for verifying circuit functionality. Post-simulation input files include the gate-level netlist (after logic design placement and routing) and the Standard Delay Format (SDF) file. Compared to register transfer level (RTL) simulation without delay information, gate-level netlist simulation with delay back-annotation takes longer to run. This time increases exponentially with increasing design size.

[0003] In the existing technology, when performing post-simulation, verification engineers are often required to locate whether the phase relationship between the relevant interface signal and the clock matches based on the timing violation point, adjust the arrival time of the signal in the verification environment, and iterate repeatedly until all timing violations are resolved.

[0004] It can be seen that the existing post-simulation process often requires repeated iterations. Therefore, the existing post-simulation method has the problem of low simulation speed. Summary of the Invention

[0005] The purpose of this application is to address the deficiencies in the above-mentioned prior art and provide a timing analysis method, electronic device and storage medium based on integrated circuit post-simulation, which can save post-simulation time and accelerate the convergence of post-simulation module verification timing.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0007] In a first aspect, the present invention provides a timing analysis method based on integrated circuit post-simulation, the method comprising:

[0008] Construct an equivalent static timing analysis (STA) environment based on the post-simulation verification environment corresponding to the module to be post-simulated in the target integrated circuit;

[0009] Based on the STA environment, check whether the interface signal delay of the input interface and / or output interface of the module to be simulated meets the preset interface timing constraint;

[0010] If not, repair the timing of the interface signals of the input interface and / or output interface of the module to be simulated through a virtual timing engineering change order to close the interface timing;

[0011] The module to be simulated is configured as the STA environment of the top-level design, and when it is determined that the internal path of the module to be simulated meets the preset timing requirement, a target standard delay format file SDF corresponding to the module to be simulated is output.

[0012] In an optional embodiment, the step of constructing an equivalent static timing analysis environment based on the post-simulation verification environment corresponding to the module to be post-simulated in the target integrated circuit includes:

[0013] According to the post-simulation verification environment corresponding to the module to be post-simulated in the target integrated circuit, the read-in register transfer level RTL file, gate level netlist and standard delay format file SDF are obtained;

[0014] Constructing a gate-level netlist input design file in the STA environment according to the RTL file, in which both the unit delay and the interconnection delay are zero;

[0015] Constructing a gate-level netlist input design file with cell delay and interconnection delay in the STA environment according to the SDF file;

[0016] Based on the STA environment, a timing constraint file corresponding to the target integrated circuit is read in.

[0017] In an optional embodiment, the gate-level netlist input design file in the STA environment in which both the unit delay and the interconnection line delay are zero delay is obtained by back-annotating the zero delay setting.

[0018] In an optional embodiment, the checking, based on the STA environment, whether the interface signal delay of the input interface and / or output interface of the module to be simulated complies with the preset interface timing constraint includes:

[0019] Based on the STA environment, check whether the interface signal delay of the input interface and / or output interface of the module to be simulated meets the initial setup timing check constraint and the initial hold timing check constraint respectively, wherein the interface signal delay includes: unit delay and interconnection line delay.

[0020] In an optional embodiment, if the timing is not met, repairing the timing of the interface signals of the input interface and / or output interface of the module to be simulated through a virtual timing engineering change order to converge the interface timing includes:

[0021] If not, adjusting the initial setup timing check constraint and the initial hold timing check constraint to obtain a target setup timing check constraint and a target hold timing check constraint;

[0022] Based on the target establishment timing check constraint and the target maintenance timing check constraint, the timing of the interface signals of the input interface and / or output interface of the module to be simulated is repaired through a virtual timing engineering change order to converge the interface timing.

[0023] In an optional embodiment, the initial setup time indicated by the initial setup timing check constraint is one clock cycle, and the initial hold time indicated by the initial hold timing check constraint is zero;

[0024] The target setup time indicated by the target setup timing check constraint is two clock cycles; the target hold time indicated by the target hold timing check constraint is one clock cycle.

[0025] In an optional embodiment, the establishing a timing check constraint and a target maintaining timing check constraint based on the target, and repairing the timing of interface signals of the input interface and / or output interface of the module to be simulated through a virtual timing engineering change order to close the interface timing, includes:

[0026] Obtaining a common path of the internal clock tree of the module to be simulated, and back-labeling all unit delays and interconnection delays on the common path with zero delay;

[0027] If there is a hold timing violation on the interface signal of the input interface and / or the output interface of the module to be subsequently simulated, then back-labeling a positive delay on the first target logic unit and / or the first target interconnection line in the module to be subsequently simulated so that the timing of the interface signal satisfies the target hold timing check constraint;

[0028] If there is a setup timing violation in the interface signal of the input interface and / or output interface of the module to be simulated, the second target logic unit and / or the second target interconnection line in the module to be simulated is reverse-labeled with zero delay or negative delay to make the timing of the interface signal meet the target setup timing check constraint.

[0029] In an optional embodiment, configuring the module to be simulated later as the STA environment of the top-level design and outputting the target standard delay format file SDF corresponding to the module to be simulated later when determining that the internal path of the module to be simulated later meets the preset timing requirements includes:

[0030] Configuring the module to be simulated later as the STA environment of the top-level design, reading the back-annotated delay command introduced in the repair process of the virtual timing engineering change order, and checking whether the internal path of the module to be simulated later has a maintain timing violation and / or a setup timing violation;

[0031] If so, the timing of the internal signal of the module to be simulated is repaired through a virtual timing engineering change order until the internal path of the module to be simulated meets the preset hold timing constraints and establish timing constraints, and the target standard delay format file SDF corresponding to the module to be simulated is output.

[0032] In an optional embodiment, the method further comprises:

[0033] Obtaining a netlist file corresponding to the module to be simulated;

[0034] Post-simulation processing is performed on the module to be post-simulated according to the netlist file and the target SDF.

[0035] In a second aspect, the present invention provides a timing analysis device based on integrated circuit post-simulation, comprising:

[0036] A construction module is used to construct an equivalent static timing analysis environment according to the post-simulation verification environment corresponding to the module to be post-simulated in the target integrated circuit;

[0037] A checking module, configured to check, based on the STA environment, whether an interface signal delay of an input interface and / or an output interface of a module to be simulated complies with a preset interface timing constraint;

[0038] A repair module is used to repair the timing of the interface signals of the input interface and / or output interface of the module to be simulated through a virtual timing engineering change order if there is any non-compliance so as to converge the interface timing;

[0039] The output module is used to configure the module to be simulated later as the STA environment of the top-level design, and output the target standard delay format file SDF corresponding to the module to be simulated later when it is determined that the internal path of the module to be simulated later meets the preset timing requirements.

[0040] In an optional embodiment, the construction module is specifically configured to obtain the read-in register transfer level RTL file, gate level netlist and standard delay format file SDF according to the post-simulation verification environment corresponding to the module to be post-simulated in the target integrated circuit;

[0041] Constructing a gate-level netlist input design file in the STA environment according to the RTL file, in which both the unit delay and the interconnection delay are zero;

[0042] Constructing a gate-level netlist input design file with cell delay and interconnection delay in the STA environment according to the SDF file;

[0043] Based on the STA environment, a timing constraint file corresponding to the target integrated circuit is read in.

[0044] In an optional embodiment, the gate-level netlist input design file in the STA environment in which both the unit delay and the interconnection line delay are zero delay is obtained by back-annotating the zero delay setting.

[0045] In an optional embodiment, the inspection module is specifically used to check whether the interface signal delay of the input interface and / or output interface of the module to be simulated meets the initial establishment timing check constraint and the initial maintenance timing check constraint respectively based on the STA environment, wherein the interface signal delay includes: unit delay and interconnection line delay.

[0046] In an optional embodiment, the repair module is specifically configured to adjust the initial setup timing check constraint and the initial hold timing check constraint respectively if they are not met, to obtain a target setup timing check constraint and a target hold timing check constraint;

[0047] Based on the target establishment timing check constraint and the target maintenance timing check constraint, the timing of the interface signals of the input interface and / or output interface of the module to be simulated is repaired through a virtual timing engineering change order to converge the interface timing.

[0048] In an optional embodiment, the initial setup time indicated by the initial setup timing check constraint is one clock cycle, and the initial hold time indicated by the initial hold timing check constraint is zero;

[0049] The target setup time indicated by the target setup timing check constraint is two clock cycles; the target hold time indicated by the target hold timing check constraint is one clock cycle.

[0050] In an optional embodiment, the repair module is specifically configured to obtain a common path of the internal clock tree of the module to be subsequently simulated, and reverse-label all unit delays and interconnect delays on the common path with zero delays;

[0051] If there is a hold timing violation on the interface signal of the input interface and / or the output interface of the module to be subsequently simulated, then back-labeling a positive delay on the first target logic unit and / or the first target interconnection line in the module to be subsequently simulated so that the timing of the interface signal satisfies the target hold timing check constraint;

[0052] If there is a setup timing violation in the interface signal of the input interface and / or output interface of the module to be simulated, the second target logic unit and / or the second target interconnection line in the module to be simulated is reverse-labeled with zero delay or negative delay to make the timing of the interface signal meet the target setup timing check constraint.

[0053] In an optional embodiment, the output module is specifically configured to configure the module to be simulated later as an STA environment of the top-level design, read the back-annotated delay command introduced by the virtual timing engineering change order during the repair process, and check whether the internal path of the module to be simulated later has a maintain timing violation and / or a setup timing violation;

[0054] If so, the timing of the internal signal of the module to be simulated is repaired through a virtual timing engineering change order until the internal path of the module to be simulated meets the preset hold timing constraints and establish timing constraints, and the target standard delay format file SDF corresponding to the module to be simulated is output.

[0055] In an optional embodiment, the apparatus further comprises: a post-simulation module, configured to obtain a netlist file corresponding to the module to be post-simulated;

[0056] Post-simulation processing is performed on the module to be post-simulated according to the netlist file and the target SDF.

[0057] In a second aspect, the present invention provides an electronic device comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of the timing analysis method based on integrated circuit post-simulation as described in any of the aforementioned embodiments.

[0058] In a third aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, executes the steps of the timing analysis method based on integrated circuit post-simulation as described in any of the aforementioned embodiments.

[0059] The beneficial effects of this application are:

[0060] In the timing analysis method based on integrated circuit post-simulation provided by the embodiment of the present application, an electronic device and a storage medium are provided. According to the post-simulation verification environment corresponding to the module to be post-simulated in the target integrated circuit, an equivalent static timing analysis environment is constructed; based on the STA environment, whether the interface signal delay of the input interface and / or output interface of the module to be post-simulated meets the preset interface timing constraints is checked; if not, the timing of the interface signal of the input interface and / or output interface of the module to be post-simulated is repaired through a virtual timing engineering change order to make the interface timing converge; the module to be post-simulated is configured as the STA environment of the top-level design, and the internal path of the module to be post-simulated is determined. When the path meets the preset timing requirements, the target standard delay format file SDF corresponding to the module to be post-simulated is output. By building a static timing analysis environment equivalent to the post-simulation verification environment corresponding to the module to be post-simulated, the timing of the post-simulation module seen by the chip back-end design and the front-end design is completely consistent. That is, the interface timing violation of the module to be post-simulated in the post-simulation environment can be reproduced, and the interface timing violation can be repaired to generate a target SDF that meets the post-simulation interface timing requirements for the front-end for post-simulation, avoiding the need for multiple iterations to meet the interface timing of the post-simulation module using the existing method, which can effectively save post-simulation time and accelerate the convergence of the verification timing of the post-simulation module. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0062] Figure 1 A flowchart of a timing analysis method based on integrated circuit post-simulation provided in an embodiment of the present application;

[0063] Figure 2 A flowchart of another timing analysis method based on integrated circuit post-simulation provided in an embodiment of the present application;

[0064] Figure 3 A flowchart of another timing analysis method based on integrated circuit post-simulation provided in an embodiment of the present application;

[0065] Figure 4 A flowchart of another timing analysis method based on integrated circuit post-simulation provided in an embodiment of the present application;

[0066] Figure 5 A flowchart of another timing analysis method based on integrated circuit post-simulation provided in an embodiment of the present application;

[0067] Figure 6 A flowchart of another timing analysis method based on integrated circuit post-simulation provided in an embodiment of the present application;

[0068] Figure 7 A schematic diagram of the functional modules of a timing analysis device based on integrated circuit post-simulation provided in an embodiment of the present application;

[0069] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0071] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0072] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0073] In existing technologies, post-simulation input files include a gate-level netlist after logic design layout and routing, and a standard delay format file (SDF). Compared to register transfer-level (RTL) simulation without delay information, gate-level netlist simulation with delay back-annotation takes longer to run, and the time required for post-simulation increases exponentially with increasing design scale. In practice, the most critical factor affecting the convergence of post-simulation functional points is the interface timing violation between the post-simulation module and the RTL design. Traditionally, verification engineers identify the phase relationship between the relevant interface signal and the clock based on the timing violation, adjust the signal arrival time within the verification environment, and iterate repeatedly until all timing violations are resolved. This results in extremely uncontrollable post-simulation verification progress for the entire chip, causing either delays in chip tape-out or tape-out with unknown risks—both of which project managers are reluctant to encounter.

[0074] As integrated circuit designs become larger and larger and their logic complexity increases, it is necessary to increase the verification speed of post-simulation within the limited chip design signoff time window.

[0075] In order to better understand the present application, we first briefly explain the application scenario of the present application. Post-simulation of digital integrated circuits is a supplement to static timing analysis. Functional problems of some circuits can only be exposed in post-simulation at the netlist level with delay. Post-simulation of chips needs to be carried out when the timing is close to convergence after the chip layout and routing is completed. From the perspective of the chip development cycle, this stage is almost approaching the chip tape-out time point.

[0076] In addition, according to the stages of the chip design process, chip design can be divided into front-end design and back-end design. Among them, front-end design (hereinafter referred to as front-end) is the "logical implementation" stage of the chip, focusing on functional correctness and RTL-level optimization; back-end design (hereinafter referred to as back-end) is the "physical implementation" stage of the chip, focusing on layout generation, timing convergence and manufacturability. The two are connected through gate-level netlists and constraint files, and need to work closely together to solve design iteration problems. The ultimate goal is to deliver high-performance, low-power, manufacturable chips.

[0077] In view of this, an embodiment of the present application provides a timing analysis method based on integrated circuit post-simulation. For a module to be post-simulated in a target integrated circuit, a static timing analysis environment equivalent to its post-simulation verification environment is constructed to analyze the interface timing violations of the module to be post-simulated, and a virtual timing engineering change order is made for the timing violation path. After the interface timing is fully converged, the target standard delay format file SDF of the module to be post-simulated is re-output, and the netlist and SDF are submitted to the front-end for post-simulation. This method achieves that by constructing a static timing analysis environment equivalent to the post-simulation verification environment corresponding to the module to be post-simulated, the timing of the post-simulation module seen by the chip back-end design and the front-end design are completely consistent. That is, the interface timing violations of the module to be post-simulated in the post-simulation environment can be reproduced, and the interface timing violations can be repaired, and a target SDF that meets the post-simulation interface timing requirements is generated for the front-end for post-simulation. This avoids the need for multiple iterations to meet the interface timing of the post-simulation module using existing methods, effectively saving post-simulation time and accelerating the convergence of the post-simulation module verification timing.

[0078] Figure 1 The present invention provides a flow chart of a timing analysis method based on integrated circuit post-simulation. The execution subject of this method can be a computer, server, processor or other electronic device that can perform timing analysis. Figure 1 As shown, the method includes:

[0079] Step 101: Construct an equivalent static timing analysis environment according to the post-simulation verification environment corresponding to the module to be post-simulated in the target integrated circuit.

[0080] Among them, for the target integrated circuit, the post-simulation verification environment corresponding to the target integrated circuit can be sorted out to sort out the simulation models of each module to be verified. For example, which simulation models of the modules to be verified read in the register transfer level (RTL) file, and which simulation models of the modules to be verified read in the gate-level netlist and standard delay format (SDF) file. Then, the interface modules (including input interface modules and output interface modules) related to each module to be post-simulated are sorted out, and the input interface signals and / or output interface signals related to the RTL interface modules are determined as target timing analysis objects. A static timing analysis (STA) environment equivalent to the post-simulation verification logic structure is built so that the post-simulation module timing seen by the chip back-end and front-end designers based on the static timing analysis environment is completely consistent. Then, the back-end can reproduce the interface timing violations of the module to be post-simulated in the post-simulation environment in the static timing analysis environment, repair the interface timing violations, and generate an SDF that meets the post-simulation interface timing requirements. The specific process can be found in the relevant content below.

[0081] It should be noted that the module to be simulated may include at least one of the following: a trigger, combinational logic, a clock tree, a memory, an I / O interface, a reset circuit, a power management module, a data path, a control logic, an analog module, an interconnection and a test circuit, etc., which are not limited here and may vary according to the actual application scenario.

[0082] Step 102: Based on the STA environment, check whether the interface signal delay of the input interface and / or output interface of the module to be simulated meets the preset interface timing constraint.

[0083] Among them, the interface signals of the input interface and / or output interface are signals for interaction between modules or between the chip and the external system, such as data signals, clock / reset signals, status signals, etc., which are not limited here and may vary according to the actual application scenario.

[0084] Based on the above description, for the module to be simulated, after constructing a static timing analysis environment equivalent to the post-simulation verification environment, the timing violations of the interface signals of the module to be simulated can be checked based on the static timing analysis environment, that is, whether the interface signal delays of the input interface and / or output interface of the module to be simulated meet the preset interface timing constraints.

[0085] Among them, the preset interface timing constraints may include: initial establishment timing check constraints and initial maintenance timing check constraints. Of course, this application does not limit the specific content of the initial establishment timing check constraints and the initial maintenance timing check constraints, which may vary according to the actual application scenario.

[0086] Step 103: If not, repair the timing of the interface signals of the input interface and / or output interface of the module to be simulated through a virtual timing engineering change order to close the interface timing.

[0087] If it is determined that the interface signal delay of the input interface and / or output interface of the module to be simulated meets the preset interface timing constraint, it means that there is no need to adjust the preset interface timing constraint; otherwise, the preset interface timing constraint needs to be adjusted.

[0088] Optionally, during the repair, the timing of the interface signals of the input interface and / or output interface of the module to be simulated can be repaired through a virtual timing engineering change order (Virtual Timing ECO) to close the interface timing.

[0089] It should be noted that, in specific implementation, the timing of the interface signals of the input interface and / or output interface of the module to be simulated can be repaired through the back-labeling delay command. Optionally, the back-labeling delay command can be a positive delay, a negative delay or a zero delay, which is not limited here and can be flexibly set according to the actual application scenario.

[0090] Step 104 : configure the module to be simulated later as the STA environment of the top-level design, and output the target standard delay format file SDF corresponding to the module to be simulated later when it is determined that the internal path of the module to be simulated later meets the preset timing requirement.

[0091] Optionally, the preset timing requirement may indicate establishing a timing constraint requirement and / or maintaining a timing constraint requirement.

[0092] Based on the above description, if the interface timing of the interface signals of the input interface and / or output interface of the module to be simulated converges, the module to be simulated can be configured as the STA environment of the top-level design, and the back-labeled delay command corresponding to the virtual timing engineering change order is read in to check whether the internal path of the module to be simulated meets the preset timing requirements. If not, the above step 103 is re-executed until the internal path of the module to be simulated meets the preset timing requirements; if it meets, the target standard delay format file SDF corresponding to the module to be simulated can be output, and the front-end verification engineer can carry out post-simulation based on the target SDF.

[0093] By applying the embodiments of the present application, it is possible to achieve complete consistency in the timing of the post-simulation module seen by the chip back-end design and the front-end design by constructing a static timing analysis environment that is equivalent to the post-simulation verification environment corresponding to the module to be post-simulated. That is, the interface timing violations of the module to be post-simulated in the post-simulation environment can be reproduced, and the interface timing violations can be repaired to generate a target SDF that meets the post-simulation interface timing requirements for the front-end for post-simulation. This avoids the situation where, when using the existing method for post-simulation, the back-end is unable to perceive the violations in the provided SDF interface timing, and can only rely on the front-end personnel to iterate multiple times and manually adjust the input and output delays of the post-simulation module boundary signals and the external clock input delay based on the timing violations to meet the interface timing of the post-simulation module. Therefore, and as verified by experiments, the application of the method of the present application can effectively save more than half the post-simulation time in the existing technology, greatly accelerating the convergence of the post-simulation module verification timing.

[0094] In summary, the present application provides a timing analysis method based on post-simulation of integrated circuits, the method comprising: constructing an equivalent static timing analysis STA environment according to the post-simulation verification environment corresponding to the module to be post-simulated in the target integrated circuit; checking whether the interface signal delay of the input interface and / or output interface of the module to be post-simulated meets the preset interface timing constraints based on the STA environment; if not, repairing the timing of the interface signal of the input interface and / or output interface of the module to be post-simulated through a virtual timing engineering change order to converge the interface timing; configuring the module to be post-simulated as the STA environment of the top-level design, and When the path meets the preset timing requirements, the target standard delay format file SDF corresponding to the module to be post-simulated is output. By building a static timing analysis environment equivalent to the post-simulation verification environment corresponding to the module to be post-simulated, the timing of the post-simulation module seen by the chip back-end design and the front-end design is completely consistent. That is, the interface timing violation of the module to be post-simulated in the post-simulation environment can be reproduced, and the interface timing violation can be repaired to generate a target SDF that meets the post-simulation interface timing requirements for the front-end for post-simulation, avoiding the need for multiple iterations to meet the interface timing of the post-simulation module using the existing method, which can effectively save post-simulation time and accelerate the convergence of the verification timing of the post-simulation module.

[0095] Figure 2 A flow chart of another method for timing analysis based on integrated circuit post-simulation provided by the present invention. In an optional embodiment, as Figure 2 As shown, the above-mentioned post-simulation verification environment corresponding to the module to be post-simulated in the target integrated circuit is used to construct an equivalent static timing analysis environment, including:

[0096] Step 201: According to the post-simulation verification environment corresponding to the module to be post-simulated in the target integrated circuit, the read-in register transfer level RTL file, gate level netlist and standard delay format file SDF are obtained.

[0097] Step 202: Construct a gate-level netlist input design file in a STA environment according to the RTL file, in which both the cell delay and the interconnection delay are zero.

[0098] Step 203: Construct a gate-level netlist input design file with cell delay and interconnection delay in the STA environment according to the SDF file.

[0099] Among them, referring to the above content, it should be noted that, for the module to be simulated later, if the simulation model of the module to be simulated later reads in the RTL file, it means that it is for verifying the correctness of the logical function, but has no timing information; based on this, when constructing an equivalent static timing analysis environment, a gate-level netlist input design file with zero delay in the unit delay and the interconnection line delay in the STA environment can be constructed according to the RTL file; and if the simulation model of the module to be simulated later reads in the gate-level netlist and the standard delay format file SDF, it means that it is for verifying the timing behavior after physical implementation and contains actual delay information, based on this, when constructing an equivalent static timing analysis environment, a gate-level netlist input design file with unit delay and interconnection line delay in the STA environment can be constructed according to the SDF file, so that the STA environment netlist and SDF input equivalent to the post-simulation verification environment can be configured in the static timing analysis environment.

[0100] Step 204: Based on the STA environment, read the timing constraint file corresponding to the target integrated circuit.

[0101] Based on the above description, in addition, the timing constraint file (Synopsys Design Constraints, SDC) corresponding to the target integrated circuit can also be read into STA, so that the timing violation of the module to be simulated can be obtained based on the STA environment later.

[0102] Optionally, the SDC file corresponding to the target integrated circuit can be written by the designer according to the timing requirements of the target integrated circuit, or can be generated by the designer with the assistance of a synthesis tool (such as Design Compiler) or a timing analysis tool (such as PrimeTime), which is not limited here.

[0103] In summary, by applying the embodiments of the present application, it is possible to build an STA environment that is consistent with the post-simulation verification environment, ensuring that the post-simulation module timing seen by the chip back-end and front-end designers is completely consistent, thereby allowing the back-end designers to reproduce the interface timing violations in the post-simulation environment in the static timing analysis environment, so that by subsequently repairing the interface timing violations, an SDF that meets the post-simulation interface timing requirements can be generated, thereby accelerating the convergence of the post-simulation module verification timing.

[0104] In an alternative embodiment, a gate-level netlist input design file with zero cell delay and interconnect delay in the STA environment is achieved by back-annotating the zero delay setting. In other words, a gate-level netlist with zero cell delay and zero interconnect delay in the STA environment is achieved by back-annotating all cells and lines in the gate-level netlist with zero delay in the STA tool.

[0105] In an optional embodiment, the above-mentioned checking whether the interface signal delay of the input interface and / or output interface of the module to be simulated meets the preset interface timing constraint based on the STA environment includes:

[0106] Based on the STA environment, check whether the interface signal delay of the input interface and / or output interface of the module to be simulated meets the initial setup timing check constraint and the initial hold timing check constraint respectively, wherein the interface signal delay includes: unit delay and interconnection line delay.

[0107] Before introducing the embodiments of the present application, a brief description of the relevant terms is given first:

[0108] Setup time: This refers to the minimum time that data must remain stable and unchanged before the arrival of the valid clock edge (usually the rising or falling edge). This is to ensure that the data can be correctly sampled when the clock edge arrives. If the setup time is insufficient, that is, the data changes too late, resulting in the data not being stable before the arrival of the clock edge, a setup time violation may occur, resulting in data loss or erroneous reading.

[0109] Hold time: refers to the minimum time that data must remain unchanged after the effective clock edge. This is to prevent data from changing prematurely and affecting data sampling in the current clock cycle. If the hold time is insufficient, that is, the data changes too quickly and changes immediately after the clock edge, a hold violation may occur, resulting in data loss or erroneous reading.

[0110] The preset interface timing constraints may include an initial setup timing check constraint and an initial hold timing check constraint. Optionally, the initial setup time indicated by the initial setup timing check constraint may be one clock cycle, and the initial hold time indicated by the initial hold timing check constraint may be zero (i.e., the transmit and capture clock edges are aligned). Of course, the initial setup time and initial hold time are not limited to these settings and can be flexibly set based on actual application scenarios.

[0111] Among them, based on the constructed STA environment, the timing violation of the interface signals of the input interface and / or output interface of the module to be simulated can be checked, that is, whether the interface signal delay of the input interface and / or output interface of the module to be simulated meets the initial establishment timing check constraint and the initial maintenance timing check constraint respectively.

[0112] For example, taking an output interface of a module to be simulated as an example, if the initial setup timing check constraint corresponds to one clock cycle, then if it is determined that the unit delay and interconnection line delay of the output interface exceed one clock cycle, it means that the interface signal delay of the output interface does not meet the initial setup timing check constraint and there is a setup timing violation. Then, the initial setup timing check constraint can be adjusted subsequently so that the interface signal delay of the output interface meets the adjusted target setup timing check constraint.

[0113] Figure 3 A flow chart of another method for timing analysis based on integrated circuit post-simulation provided by the present invention. In an optional embodiment, as Figure 3 If the above is not met, the timing of the interface signals of the input interface and / or output interface of the module to be simulated is repaired through a virtual timing engineering change order to converge the interface timing, including:

[0114] Step 301: If not, adjust the initial setup timing check constraint and the initial hold timing check constraint respectively to obtain the target setup timing check constraint and the target hold timing check constraint.

[0115] Among them, referring to the above description, after constructing a static timing analysis environment equivalent to the post-simulation verification environment, the timing violations of the interface signals of the module to be post-simulated can be checked based on the static timing analysis environment. If it is determined that there are timing violations, the preset interface timing constraints can be adjusted.

[0116] Optionally, when making specific adjustments, the target setup time indicated by the target setup timing check constraint can be greater than the initial setup time indicated by the initial setup timing check constraint, so that the interface signals of the input interface and / or output interface can be correctly sampled when the clock edge arrives; the target hold time indicated by the target hold timing check constraint can be greater than the initial hold time indicated by the initial hold timing check constraint, so as to avoid premature changes in data after the effective clock edge, so that the data can be accurately transmitted.

[0117] Step 302: Establish timing check constraints and target retention timing check constraints based on the target, and repair the timing of the interface signals of the input interface and / or output interface of the module to be simulated through a virtual timing engineering change order to close the interface timing.

[0118] Based on the above description, after obtaining the target setup timing check constraints and the target hold timing check constraints, a virtual timing engineering change order ECO can be performed on the timing violation path of the input interface and / or output interface of the module to be simulated, so that the interface signals of the input interface and / or output interface of the module to be simulated do not have setup timing violations or hold timing violations, that is, the interface timing convergence is achieved.

[0119] By applying the embodiments of the present application, when an interface timing violation occurs in a post-simulation environment, further timing repair can be performed to generate an SDF that meets the post-simulation interface timing requirements, thereby accelerating the convergence of the post-simulation module verification timing.

[0120] In an optional embodiment, the initial setup time indicated by the initial setup timing check constraint is one clock cycle, and the initial hold time indicated by the initial hold timing check constraint is zero; after adjustment, the target setup time indicated by the target setup timing check constraint is two clock cycles; the target hold time indicated by the target hold timing check constraint is one clock cycle.

[0121] In some embodiments, the initial setup time, initial hold time, target setup time and target hold time can be set with reference to the embodiments of the present application. By comparison, it can be seen that in the embodiments of the present application, the target setup time is larger than the initial setup time. Therefore, it can be ensured that the interface signal of the input interface and / or output interface can be correctly sampled when the clock edge arrives; and the target hold time is greater than the initial hold time, which can avoid premature changes in data after the effective clock edge so that the data can be accurately transmitted.

[0122] Of course, it should be noted that the values ​​of the initial setup time, the initial hold time, the target setup time and the target hold time are not limited to the above embodiments and can be flexibly set according to actual application scenarios.

[0123] Figure 4 A flow chart of another method for timing analysis based on integrated circuit post-simulation provided by the present invention. In an optional embodiment, as Figure 4 As shown, the target-based establishment of timing check constraints and target-maintained timing check constraints, and the repair of the timing of the interface signals of the input interface and / or output interface of the module to be simulated through a virtual timing engineering change order to achieve interface timing convergence, include:

[0124] Step 401: Obtain a common path of the internal clock tree of the module to be simulated, and reverse-label all unit delays and interconnection delays on the common path with zero delay.

[0125] Step 402: If there is a hold timing violation in the interface signal of the input interface and / or the output interface of the module to be simulated, the first target logic unit and / or the first target interconnection line in the module to be simulated are reverse-annotated with positive delay to make the timing of the interface signal meet the target hold timing check constraint.

[0126] Step 403: If there is a setup timing violation in the interface signal of the input interface and / or the output interface of the module to be simulated, the second target logic unit and / or the second target interconnection line in the module to be simulated is reverse-annotated with zero delay or negative delay to make the timing of the interface signal meet the target setup timing check constraint.

[0127] Before introducing the embodiments of the present application, the following terms are first explained:

[0128] Unit delay: refers to the propagation time from input to output of a logic gate (such as an AND gate or a flip-flop), which can be defined by a process library.

[0129] Interconnect delay: refers to the time it takes for a signal to travel along a conductor (metal trace), which is determined by the physical parameters of the layout and routing (such as length, resistance, and capacitance).

[0130] Back-annotation: Inject actual physical delay information (such as SDF / SPEF files) into virtual timing ECO designs for timing analysis or simulation.

[0131] Back-annotate zero delay: Forces the delay of all cells and interconnects to zero, ignoring the actual physical delay and verifying only the logical functionality.

[0132] Optionally, when performing ECO on the timing violation path of the input interface and / or output interface of the module to be simulated, the process may be divided into the following steps:

[0133] Step 1: Obtain the common path of the internal clock tree of the module to be simulated, and back-annotate all units and lines on this common path with zero delay. This means that the delays of all units and interconnects on this common path are forced to zero. In some embodiments, the common path of the internal clock tree of the module to be simulated is the common path from the clock input of the module to be simulated to the clock terminals of different flip-flops, i.e., the path that all flip-flops traverse.

[0134] Step 2: Analyze the timing violations of interface signals of the input interface and / or output interface. For interface signals with hold timing violations, back-annotate the positive delay of the first target logic unit and / or the first target interconnection line in the module to be simulated so that the hold timing is not violated, and the position of the back-annotated positive delay should not cause a timing violation inside the module to be simulated.

[0135] For example, when the post-simulation module includes a trigger, based on the definition of the trigger hold time, repairing the hold timing violation is to delay the time for the interface signal to reach the trigger data port, and it is necessary to reverse-label the positive delay on the original logic gate or interconnection line delay; and based on the definition of the trigger setup time, repairing the setup timing violation is to accelerate the time for the interface signal to reach the trigger data port, and it is necessary to reverse-label the negative delay on the original logic gate or interconnection line delay.

[0136] Step 3: For interface signals with setup timing violations, back-label the second target logic unit and / or second target interconnection line in the module to be simulated with zero delay or negative delay so that the setup timing is no longer violated. Of course, back-labeling the zero delay or negative delay should not cause timing violations within the module to be simulated.

[0137] It should be noted that for interface signals with establishment timing violations, the selection of the second target logic unit and / or second target interconnection line in the module to be subsequently simulated can refer to the selection of the first target logic unit and first target interconnection line mentioned above, which will not be repeated here.

[0138] Regarding back-annotating negative delays, it's important to note that these should not result in negative values ​​after adding the original delay to the back-annotated object (including cells and interconnects). In other words, when back-annotating with negative delays, it's crucial to ensure that the total delay remains non-negative after adding the negative delay. This is because in actual physical circuits, signal propagation cannot have negative times. Negative delays are merely a logical adjustment. If the total delay after back-annotation is negative, post-simulation verification results will be inaccurate and fail to accurately reflect the actual performance of the circuit.

[0139] Furthermore, it should be noted that, using the input interface of the module to be subsequently simulated as an example, the selection of the second target logic unit and the second target interconnection line can be made according to the following rules: For example, a combinational logic unit with a relatively high delay (e.g., an AND gate, an OR gate, an adder, etc.) on the path where the input interface is located can be selected as the second target logic unit, and a wire network with a relatively high delay on the path where the input interface is located can be selected as the second target interconnection line. Of course, the selection of the second target logic unit and the second target interconnection line is not limited to this. For the selection of the second target logic unit and the second target interconnection line corresponding to the output interface of the module to be subsequently simulated, please refer to the relevant selection rules for the input interface described above, and will not be elaborated here.

[0140] Optionally, after executing the above three steps, all back-annotated delay commands can be saved to a specified file. In some embodiments, the specified file can be a file containing a set_annotated_delay command, so that the module to be simulated can be used as the STA environment of the top-level design based on this.

[0141] It should be noted that when performing ECO on the timing violation paths of the input interface and / or output interface of the module to be simulated, the setup timing and hold timing check margins of all timing paths passing through the interface signals can be captured through a script. Then, referring to steps 402 and 403 above, virtual ECO can be performed step by step from the input signal backward or the output signal forward according to the above method until the timing of the target timing analysis object interface is converged.

[0142] Figure 5A flow chart of another method for timing analysis based on integrated circuit post-simulation provided by the present invention. In an optional embodiment, as Figure 5 As shown, the above configuration of the module to be simulated is used as the STA environment of the top-level design, and when it is determined that the internal path of the module to be simulated meets the preset timing requirements, the target standard delay format file SDF corresponding to the module to be simulated is output, including:

[0143] Step 501: Configure the module to be simulated as the STA environment of the top-level design, read the back-annotated delay command introduced in the repair process of the virtual timing engineering change order, and check whether there are maintain timing violations and / or establish timing violations in the internal paths of the module to be simulated.

[0144] Step 502: If yes, repair the timing of the internal signal of the module to be simulated through the virtual timing engineering change order until the internal path of the module to be simulated meets the preset maintain timing constraints and establish timing constraints, and output the target standard delay format file SDF corresponding to the module to be simulated.

[0145] By configuring the module to be simulated as the top-level design in the STA environment, the back-annotated delay commands introduced during the repair process of the virtual timing engineering change order can be obtained. Based on these commands, the internal paths of the module to be simulated can be checked for hold timing violations and / or establish timing violations. It should be noted that if the virtual timing engineering change order has saved all back-annotated delay commands to a designated file during the repair process, the back-annotated delay commands contained in the designated file can be read from the designated file.

[0146] Optionally, if it is determined that the internal path of the module to be simulated does not have any hold timing violation and / or build timing violation, then the target standard delay format file SDF corresponding to the module to be simulated can be output; otherwise, the timing of the internal signal of the module to be simulated can be re-repaired through a virtual timing engineering change order, that is, the above step 103 is repeated until the internal path of the module to be simulated meets the preset hold timing constraints and build timing constraints, and then the target standard delay format file SDF corresponding to the module to be simulated is output.

[0147] By applying the embodiments of the present application, a static timing analysis environment equivalent to a post-simulation verification environment is implemented, and interface timing violations in a post-simulation environment can be reproduced and repaired. In addition, during the repair process, timing violations of the internal paths of the modules to be post-simulated can also be repaired, thereby generating a target SDF that meets the post-simulation interface timing requirements.

[0148] Figure 6 A flow chart of another method for timing analysis based on integrated circuit post-simulation provided by the present invention. In an optional embodiment, as Figure 6 As shown, the above method also includes:

[0149] Step 601: Obtain the netlist file corresponding to the module to be post-simulated.

[0150] Step 602: Perform post-simulation processing on the module to be post-simulated according to the netlist file and the target SDF.

[0151] Based on the above description, after obtaining the target standard delay format file (SDF), post-simulation processing can be performed. Optionally, during post-simulation processing, the netlist file (gate-level netlist) corresponding to the module to be post-simulated can be obtained. Combining the netlist file and the target SDF, post-simulation processing can be performed on the module to be post-simulated to verify whether the design after physical implementation meets the functional, timing, and power requirements. This ensures that the design still meets all requirements after physical implementation, providing a guarantee for the final tape-out.

[0152] Based on the above description, it can be understood that, since the interface timing violation of the module to be post-simulated in the post-simulation environment can be reproduced with reference to the aforementioned embodiment, and the interface timing violation can be repaired, a target SDF that meets the post-simulation interface timing requirements is generated and given to the front end for post-simulation. Then, when post-simulation is performed again at this time, the workload of post-simulation can be effectively reduced, the post-simulation time can be saved, and the convergence of the verification timing of the post-simulation module can be accelerated.

[0153] Of course, it should be noted that in addition to the netlist file and target SDF, the post-simulation process can also include a parasitic parameter file (Standard Parasitic Exchange Format, SPEF) and a timing constraint file (Synopsys Design Constraints, SDC). Among them, SPEF can contain the parasitic parameters of the interconnect (such as resistance and capacitance) for accurate timing analysis, and SDC can define the timing requirements of the design to guide timing analysis.

[0154] Figure 7 This is a functional module diagram of a timing analysis device based on integrated circuit post-simulation provided by the present invention. The basic principle and technical effects of this device are the same as those of the corresponding method embodiment described above. For the sake of simplicity, the parts not mentioned in this embodiment can be referred to the corresponding contents in the method embodiment. Figure 7 As shown, the timing analysis device includes:

[0155] A construction module 110 is configured to construct an equivalent static timing analysis environment according to a post-simulation verification environment corresponding to a module to be post-simulated in a target integrated circuit;

[0156] A checking module 120 is configured to check, based on the STA environment, whether the interface signal delay of the input interface and / or output interface of the module to be simulated complies with a preset interface timing constraint;

[0157] A repair module 130 is configured to repair the timing of the interface signals of the input interface and / or output interface of the module to be simulated by using a virtual timing engineering change order if the timing does not meet the requirements so as to close the interface timing;

[0158] The output module 140 is used to configure the module to be simulated as the STA environment of the top-level design, and output the target standard delay format file SDF corresponding to the module to be simulated when it is determined that the internal path of the module to be simulated meets the preset timing requirements.

[0159] In an optional embodiment, the construction module 110 is specifically configured to obtain the read-in register transfer level RTL file, gate level netlist, and standard delay format file SDF according to the post-simulation verification environment corresponding to the module to be post-simulated in the target integrated circuit;

[0160] Constructing a gate-level netlist input design file in the STA environment according to the RTL file, in which both the unit delay and the interconnection delay are zero;

[0161] Constructing a gate-level netlist input design file with cell delay and interconnection delay in the STA environment according to the SDF file;

[0162] Based on the STA environment, a timing constraint file corresponding to the target integrated circuit is read in.

[0163] In an optional embodiment, the gate-level netlist input design file in the STA environment in which both the unit delay and the interconnection line delay are zero delay is obtained by back-annotating the zero delay setting.

[0164] In an optional embodiment, the checking module 120 is specifically used to check whether the interface signal delay of the input interface and / or output interface of the module to be simulated meets the initial establishment timing check constraint and the initial maintenance timing check constraint respectively based on the STA environment, wherein the interface signal delay includes: unit delay and interconnection line delay.

[0165] In an optional embodiment, the repair module 130 is specifically configured to adjust the initial setup timing check constraint and the initial hold timing check constraint respectively if they are not met, to obtain a target setup timing check constraint and a target hold timing check constraint;

[0166] Based on the target establishment timing check constraint and the target maintenance timing check constraint, the timing of the interface signals of the input interface and / or output interface of the module to be simulated is repaired through a virtual timing engineering change order to converge the interface timing.

[0167] In an optional embodiment, the initial setup time indicated by the initial setup timing check constraint is one clock cycle, and the initial hold time indicated by the initial hold timing check constraint is zero;

[0168] The target setup time indicated by the target setup timing check constraint is two clock cycles; the target hold time indicated by the target hold timing check constraint is one clock cycle.

[0169] In an optional embodiment, the repair module 130 is specifically configured to obtain a common path of the internal clock tree of the module to be subsequently simulated, and reverse-label all unit delays and interconnect delays on the common path with zero delays;

[0170] If there is a hold timing violation on the interface signal of the input interface and / or the output interface of the module to be subsequently simulated, then back-labeling a positive delay on the first target logic unit and / or the first target interconnection line in the module to be subsequently simulated so that the timing of the interface signal satisfies the target hold timing check constraint;

[0171] If there is a setup timing violation in the interface signal of the input interface and / or output interface of the module to be simulated, the second target logic unit and / or the second target interconnection line in the module to be simulated is reverse-labeled with zero delay or negative delay to make the timing of the interface signal meet the target setup timing check constraint.

[0172] In an optional embodiment, the output module 140 is specifically configured to configure the module to be simulated later as an STA environment of the top-level design, read the back-annotated delay command introduced by the virtual timing engineering change order during the repair process, and check whether the internal path of the module to be simulated later has a maintain timing violation and / or a establish timing violation;

[0173] If so, the timing of the internal signal of the module to be simulated is repaired through a virtual timing engineering change order until the internal path of the module to be simulated meets the preset hold timing constraints and establish timing constraints, and the target standard delay format file SDF corresponding to the module to be simulated is output.

[0174] In an optional embodiment, the apparatus further comprises: a post-simulation module, configured to obtain a netlist file corresponding to the module to be post-simulated;

[0175] Post-simulation processing is performed on the module to be post-simulated according to the netlist file and the target SDF.

[0176] The above-mentioned device is used to execute the method provided in the above-mentioned embodiment. Its implementation principle and technical effect are similar and will not be repeated here.

[0177] The above modules can be one or more integrated circuits configured to implement the above methods, such as one or more application-specific integrated circuits (ASICs), one or more microprocessors, or one or more field programmable gate arrays (FPGAs). For another example, when a module is implemented by scheduling program code through a processing element, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules can be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0178] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device can be integrated into the aforementioned timing analysis device. Figure 8 As shown, the electronic device may include: a processor 210, a storage medium 220, and a bus 230. The storage medium 220 stores machine-readable instructions executable by the processor 210. When the electronic device is running, the processor 210 and the storage medium 220 communicate via the bus 230, and the processor 210 executes the machine-readable instructions to perform the steps of the above-mentioned method embodiment. The specific implementation methods and technical effects are similar and will not be repeated here.

[0179] Optionally, the present application further provides a storage medium storing a computer program, which, when executed by a processor, executes the steps of the above method embodiment. The specific implementation and technical effects are similar and will not be described in detail here.

[0180] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0181] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0182] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0183] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) or a processor (English: processor) to perform some steps of the methods of each embodiment of the present application. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (English: Read-Only Memory, abbreviated: ROM), a random access memory (English: Random Access Memory, abbreviated: RAM), a magnetic disk or an optical disk, and other media that can store program code.

[0184] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0185] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application. It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A timing analysis method based on integrated circuit post-simulation, characterized in that: The method comprises: Construct an equivalent static timing analysis (STA) environment based on the post-simulation verification environment corresponding to the module to be post-simulated in the target integrated circuit; Based on the STA environment, check whether the interface signal delay of the input interface and / or output interface of the module to be simulated meets the preset interface timing constraint; If not, repair the timing of the interface signals of the input interface and / or output interface of the module to be simulated through a virtual timing engineering change order to close the interface timing; The module to be simulated is configured as the STA environment of the top-level design, and when it is determined that the internal path of the module to be simulated meets the preset timing requirement, a target standard delay format file SDF corresponding to the module to be simulated is output.

2. The method according to claim 1, characterized in that The method of constructing an equivalent static timing analysis environment according to the post-simulation verification environment corresponding to the module to be post-simulated in the target integrated circuit includes: According to the post-simulation verification environment corresponding to the module to be post-simulated in the target integrated circuit, the read-in register transfer level RTL file, gate level netlist and standard delay format file SDF are obtained; Constructing a gate-level netlist input design file in the STA environment according to the RTL file, in which both the unit delay and the interconnection delay are zero; Constructing a gate-level netlist input design file with cell delay and interconnection delay in the STA environment according to the SDF file; Based on the STA environment, a timing constraint file corresponding to the target integrated circuit is read in.

3. The method according to claim 2, characterized in that The gate-level netlist input design file in the STA environment in which both the unit delay and the interconnection line delay are zero delay is obtained by back-annotating the zero delay setting.

4. The method according to claim 1, wherein The step of checking, based on the STA environment, whether the interface signal delay of the input interface and / or the output interface of the module to be simulated complies with the preset interface timing constraint comprises: Based on the STA environment, check whether the interface signal delay of the input interface and / or output interface of the module to be simulated meets the initial setup timing check constraint and the initial hold timing check constraint respectively, wherein the interface signal delay includes: unit delay and interconnection line delay.

5. The method according to claim 4, characterized in that If the timing is not met, the timing of the interface signals of the input interface and / or output interface of the module to be simulated is repaired through a virtual timing engineering change order to converge the interface timing, including: If not, adjusting the initial setup timing check constraint and the initial hold timing check constraint to obtain a target setup timing check constraint and a target hold timing check constraint; Based on the target establishment timing check constraint and the target maintenance timing check constraint, the timing of the interface signals of the input interface and / or output interface of the module to be simulated is repaired through a virtual timing engineering change order to converge the interface timing.

6. The method according to claim 5, characterized in that The initial setup time indicated by the initial setup timing check constraint is one clock cycle, and the initial hold time indicated by the initial hold timing check constraint is zero; The target setup time indicated by the target setup timing check constraint is two clock cycles; the target hold time indicated by the target hold timing check constraint is one clock cycle.

7. The method according to claim 5, characterized in that The establishing of the target timing check constraint and the target maintaining timing check constraint based on the target, and repairing the timing of the interface signals of the input interface and / or the output interface of the module to be simulated through a virtual timing engineering change order to close the interface timing, includes: Obtaining a common path of the internal clock tree of the module to be simulated, and back-labeling all unit delays and interconnection delays on the common path with zero delay; If there is a hold timing violation on the interface signal of the input interface and / or the output interface of the module to be subsequently simulated, then back-labeling a positive delay on the first target logic unit and / or the first target interconnection line in the module to be subsequently simulated so that the timing of the interface signal satisfies the target hold timing check constraint; If there is a setup timing violation in the interface signal of the input interface and / or output interface of the module to be simulated, the second target logic unit and / or the second target interconnection line in the module to be simulated is reverse-labeled with zero delay or negative delay to make the timing of the interface signal meet the target setup timing check constraint.

8. The method according to claim 1, characterized in that The configuring the module to be simulated later as the STA environment of the top-level design and outputting the target standard delay format file SDF corresponding to the module to be simulated later when determining that the internal path of the module to be simulated later meets the preset timing requirements includes: Configuring the module to be simulated later as the STA environment of the top-level design, reading the back-annotated delay command introduced in the repair process of the virtual timing engineering change order, and checking whether the internal path of the module to be simulated later has a maintain timing violation and / or a setup timing violation; If so, the timing of the internal signal of the module to be simulated is repaired through a virtual timing engineering change order until the internal path of the module to be simulated meets the preset hold timing constraints and establish timing constraints, and the target standard delay format file SDF corresponding to the module to be simulated is output.

9. The method according to any one of claims 1 to 8, characterized in that The method further comprises: Obtaining a netlist file corresponding to the module to be simulated; Post-simulation processing is performed on the module to be post-simulated according to the netlist file and the target SDF.

10. An electronic device, characterized in that: include: A processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the storage medium communicate via the bus, and the processor executes the machine-readable instructions to perform the steps of the timing analysis method based on integrated circuit post-simulation as described in any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the timing analysis method based on integrated circuit post-simulation according to any one of claims 1 to 9 are executed.

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