Graphics processor, chip product, computer equipment and data processing method

Abstract

The invention discloses a graphics processor, a chip product, computer equipment and a data processing method, and relates to the technical field of chips. The GPU includes at least one GPU core. The GPU core comprises a control unit, a DMA unit, a cache unit and at least one computing unit. The DMA unit is coupled to the CPU and the memory, respectively. By moving the DMA unit from the outside of the GPU core to the inside of the GPU core, the technical effect that the DMA bandwidth is synchronously expanded along with the improvement of the computing power of the GPU is achieved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a graphics processor, a chip product, a computer device, and a data processing method. Background Art

[0002] In a GPU (Graphics Processing Unit) system, there is generally a DMA (Direct Memory Access) unit responsible for moving data from the host's CPU (Central Processing Unit) to the GPU's memory (i.e., the GPU's memory, such as video memory).

[0003] However, in existing GPU systems, DMA bandwidth cannot be expanded synchronously with GPU computing power. Summary of the Invention

[0004] The embodiments of the present application provide a graphics processor, a chip product, a computer device, and a data processing method. The technical solutions provided by the embodiments of the present application include the following aspects.

[0005] According to one aspect of an embodiment of the present application, a GPU is provided, wherein the GPU includes at least one GPU core;

[0006] The GPU core includes: a control unit, a DMA unit, a cache unit and at least one computing unit;

[0007] The DMA units are coupled to the CPU and the memory, respectively.

[0008] According to one aspect of an embodiment of the present application, a chip product is provided, comprising the GPU as described above.

[0009] According to one aspect of an embodiment of the present application, a computer device is provided, comprising the GPU as described above.

[0010] According to one aspect of an embodiment of the present application, a data processing method for a GPU is provided, wherein the GPU includes at least one GPU core; the GPU core includes: a control unit, a DMA unit, a cache unit, and at least one computing unit; the DMA unit is coupled to a CPU and a memory, respectively; the method includes:

[0011] The control unit sends the first control instruction to the DMA unit when receiving the first control instruction sent by the CPU, where the first control instruction is used to execute a data reading and writing task related to the memory;

[0012] The DMA unit executes the first control instruction.

[0013] The technical solutions provided in the embodiments of the present application can bring the following beneficial effects:

[0014] By moving the DMA unit from the outside of the GPU core to the inside of the GPU core, when the GPU computing power is expanded, the number of GPU cores can be increased, or the number of computing units within the GPU core can be increased. If the number of GPU cores increases, the number of DMA units also increases accordingly, so the DMA bandwidth is naturally expanded. If the number of computing units within the GPU core increases, in order to adapt to the increase in the number of computing units, the cache units and data paths in the GPU core will both increase adaptably, which corresponds to an increase in the GPU bandwidth. At this time, the DMA bandwidth naturally benefits from the increase in GPU bandwidth. Therefore, the technical solution of the present application achieves the technical effect of synchronous expansion of DMA bandwidth as the GPU computing power increases. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the system architecture of a processor provided by the related art;

[0016] Figure 2 This is a timing diagram of data movement and data rendering / calculation without a DMA unit;

[0017] Figure 3 This is a timing diagram of data movement and data rendering / calculation in the presence of a DMA unit;

[0018] Figure 4 is a block diagram of a GPU provided in one possible implementation of the present application;

[0019] Figure 5 It is a schematic diagram of a data processing flow provided in a possible implementation of the present application;

[0020] Figure 6 This is a flowchart of a data processing method applied to a GPU provided in one possible implementation of the present application. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0022] Before introducing the technical solution of this application, some technical concepts involved in this application are first explained.

[0023] 1. GPU: A processor specifically designed for processing graphics and image processing. Also known as a display core, visual processing unit, or display chip, a GPU is a microprocessor specifically designed to perform image and graphics-related operations on personal computers, workstations, game consoles, and some mobile devices (such as tablets and smartphones).

[0024] 2. DMA: A technology in computer systems that allows external devices (such as hard drives, graphics cards, network cards, and sound cards) to directly access main memory without requiring data to be transferred through the CPU. DMA significantly improves data transfer efficiency, especially in situations where large amounts of data must be moved, such as when processing audio or video streams or transferring data between hard drives and memory at high speeds. At the heart of DMA is a hardware module called a DMA controller, which manages data transfers between devices and memory.

[0025] The DMA workflow is generally as follows:

[0026] (1) Requesting DMA transfer: When an external device needs to transfer data, it sends a request to the DMA controller. The CPU will start the DMA controller based on the device's request and specify the source address, destination address, and data length of the transfer.

[0027] (2) Data Transfer: The DMA controller is responsible for reading data from an external device and writing it to the memory, or reading data from the memory and writing it to an external device. Throughout the entire process, data is transferred directly between the external device and the memory without the need for CPU intervention.

[0028] (3) Notify the CPU of the transfer completion: After the transfer is complete, the DMA controller sends an interrupt signal to the CPU to notify it that the transfer has been successfully completed. After the CPU responds to the DMA completion interrupt signal, it can check the transfer results and continue operations.

[0029] 3. Video memory: Memory specifically used to store graphics data, installed on the graphics card, provides a temporary storage space for the GPU. Video memory primarily stores the large amounts of data generated during graphics rendering, such as textures, colors, and lighting information. The difference between video memory and main memory is that video memory is dedicated to the graphics card and primarily stores graphics-related data, while main memory typically refers to a computer's main memory, used to store various programs and data. Video memory typically transfers data faster than main memory, significantly impacting graphics processing performance; main memory, on the other hand, transfers data at a relatively slow speed, significantly impacting the computer's overall operating efficiency.

[0030] 4. GPU computing power: This refers to the computing power of a GPU when performing graphics processing or general computing. GPU computing power is usually measured in teraflops (TFLOPS).

[0031] 5. DMA bandwidth: refers to the data transfer rate of the DMA unit during data transfer. DMA bandwidth can be calculated using the following formula: (1) Data transfer size / transfer time, where data transfer size refers to the amount of data to be transferred in one DMA transfer, usually in bytes, and transfer time refers to the time required to complete one DMA transfer, usually in milliseconds or seconds; (2) Data transfer amount / transfer cycle, where data transfer amount refers to the amount of data transferred per DMA transfer, usually in bytes, and transfer cycle refers to the time required to complete one DMA transfer, usually in milliseconds or seconds.

[0032] Related technologies provide the following two solutions for transferring data from the CPU to the GPU's video memory.

[0033] Solution 1: In the absence of a DMA unit, the GPU is responsible for reading data from the CPU and writing it to the GPU's video memory. The GPU can then read the data from the video memory for rendering or calculation.

[0034] Solution 2: When there is a DMA unit, the DMA unit is responsible for reading data from the CPU and writing it to the GPU's video memory. The GPU can read data from the video memory for rendering or calculation, such as Figure 1 shown.

[0035] For the above solution 1, in the absence of a DMA unit, since both the data movement step and the data rendering / calculation step are executed by the GPU, the above two steps cannot be executed in parallel and can only be executed serially. Figure 2 As shown in FIG, it shows the timing diagram of data movement and data rendering / calculation without a DMA unit. Figure 2 In the DMA architecture, a copy operation refers to the process of copying data from the CPU's memory to the GPU's video memory, a download operation refers to the process of copying data from the GPU's video memory to the CPU's memory, and a draw operation refers to the process of the GPU using data in the video memory to perform rendering or calculations. Without a dedicated DMA unit, both copy and download operations are performed by the GPU. Draw is the GPU's primary function, but its hardware resources overlap with copy and download operations. When copying and downloading are in progress, draw operations cannot be performed simultaneously, so the various steps are executed serially.

[0036] For the second solution, if there is a DMA unit, the data movement step is performed by the DMA unit, and the GPU does not need to be responsible for the data unit. The GPU only needs to be responsible for performing the data rendering / calculation step, so the above two steps can be performed in parallel. Figure 3 The following figure shows the timing diagram of data movement and data rendering / calculation when a DMA unit is available. If a DMA unit is available, the DMA unit can perform copy and download work simultaneously, and there is no overlapping hardware resources with the GPU draw step, so they can be executed in parallel.

[0037] The current processor system architecture is as follows Figure 1 As shown, the processor includes a CPU 10, a GPU 20, a memory 30, and a DMA unit 40. Memory 30 can be considered as the video memory of GPU 20. DMA unit 40 can perform data movement tasks, such as copying data from the memory of CPU 10 to the video memory of GPU 20, and / or copying data from the video memory of GPU 20 to the memory of CPU 10.

[0038] However, in Figure 1 In the architecture shown, DMA bandwidth cannot be scaled synchronously with GPU computing power. GPU computing power is related to the number of its cores. Figure 1 In the illustrated architecture, the DMA unit is an independent module. As the number of GPU cores increases, the DMA unit also needs to be modified to accommodate the increased bandwidth requirements. Previously, the DMA unit's bandwidth design matched the evolution of PCIE (Peripheral Component Interconnect Express) bandwidth, which was much smaller than the GPU's memory bandwidth. As large models require multi-GPU clusters, the DMA unit is increasingly used for inter-card data transfer, far exceeding the PCIE interface bandwidth, and bandwidth demand is growing rapidly. Furthermore, the expansion of DMA bandwidth requires increasingly larger buffer space, resulting in an increasing area requirement for a separate DMA unit.

[0039] Based on this, the embodiments of the present application provide a new processor system architecture that can solve the problem that DMA bandwidth cannot be expanded synchronously with the increase of GPU computing power without consuming additional on-chip area. The following will introduce and illustrate the technical solution of the present application through several embodiments.

[0040] Please refer to Figure 4 , which shows a block diagram of a GPU structure provided in a possible implementation of the present application. The GPU includes at least one GPU core 20.

[0041] The GPU core 20 includes a control unit 21, a DMA unit 22, a cache unit 23, and at least one computing unit 24. The DMA unit 22 is coupled to the CPU 10 and the memory 30 respectively.

[0042] Each GPU core 20 is a GPU core. The entire GPU processor can include only one GPU core 20, or it can include multiple GPU cores 20, thereby improving the performance of the entire GPU processor. The memory 30 can be regarded as the video memory of the GPU core 20.

[0043] The control unit 21 within the GPU core 20, also known as the GPU control core, is a core component of the GPU core 20 and is responsible for coordinating and managing various operations and task scheduling within the GPU core 20. The control unit 21 plays a crucial role within the GPU core 20, ensuring that the GPU core 20 can efficiently and accurately execute various data processing tasks.

[0044] The functions and roles of the control unit 21 include, but are not limited to, at least one of the following: task scheduling, resource management, and error handling. The control unit 21 is responsible for scheduling various computing tasks within the GPU core 20, ensuring that each computing unit 24 can efficiently execute its assigned tasks. The control unit 21 manages resource allocation within the GPU core 20, including memory access and data processing, ensuring coordinated operation of all components within the GPU core 20. During execution, the control unit 21 also handles potential errors and exceptions to ensure stable operation of the GPU core 20.

[0045] The primary function of the cache unit 23 in the GPU core 20 is to reduce the number of main memory accesses, lower latency, and improve rendering efficiency. The cache unit 23 (i.e., cache) in the GPU core 20 can include multiple levels, such as L1 and L2. It has extremely high access speeds and can store frequently accessed data and instructions by the GPU core 20, thereby reducing the number of main memory accesses and improving rendering efficiency.

[0046] Specifically, the cache unit 23 in the GPU core 20 plays a role in the following aspects: (1) reducing access latency: since the cache is stored in high-speed memory, the access speed is very fast, which can significantly reduce the number of accesses to the main memory, thereby reducing latency; (2) improving rendering efficiency: by caching commonly used data and instructions, the GPU core 20 can execute graphics rendering tasks faster and improve overall rendering efficiency; (3) optimizing performance: the cache can store data and instructions frequently accessed by the GPU core 20, reducing dependence on the main memory, thereby optimizing the performance of the GPU core 20.

[0047] The computing units 24 within the GPU core 20 are also referred to as compute cores. The GPU core 20 typically includes multiple compute units 24. The primary function of the compute units 24 within the GPU core 20 is to execute parallel computing tasks. The GPU core 20 is designed with a large number of compute units 24, which are capable of simultaneously processing multiple simple computing tasks, thereby greatly improving computing efficiency. Compared to a CPU, the GPU core 20 has a larger number of compute units 24, but the computing power of each is relatively weak. This design enables the GPU core 20 to excel in processing graphics rendering, large-scale data-parallel computing, and other aspects.

[0048] and Figure 1 The difference from the illustrated architecture is that, in the embodiment of the present application, the DMA unit 22 is moved from the outside of the GPU core 20 to the inside of the GPU core 20. The DMA unit 22 is coupled to the CPU 10 and the memory 30, respectively, to perform data movement tasks, such as copying data from the memory of the CPU 10 to the display memory (i.e., the memory 30) of the GPU core 20, and / or copying data from the display memory (i.e., the memory 30) of the GPU core 20 to the memory of the CPU 10.

[0049] By moving the DMA unit 22 from the outside of the GPU core 20 to the inside of the GPU core 20, when computing power expansion is needed, the number of GPU cores 20 can be increased, or the number of GPU cores 20 can be fixed and the number of computing units 24 within the GPU core 20 can be increased. If the number of GPU cores 20 increases, the number of DMA units 22 also increases accordingly, so the DMA bandwidth is naturally expanded. If the number of computing units 24 within the GPU core 20 increases, in order to adapt to the increase in the number of computing units 24, the cache units 23 and data paths in the GPU core 20 will be adaptively increased, which corresponds to the increase in the bandwidth of the GPU core 20. At this time, the DMA unit 22 naturally benefits from the increase in the bandwidth of the GPU core 20, so that the DMA bandwidth is expanded synchronously with the GPU core 20.

[0050] In some embodiments, at least one computing unit 24 within the GPU core 20 shares a cache unit 23 within the GPU core 20, and the cache unit 23 serves as a data buffer for the DMA unit 22. The data buffer is used to temporarily store data transferred by the DMA unit 22. Because multiple computing units 24 within the GPU core 20 share the cache unit 23, which is typically of a certain size, the DMA unit 22 can use the cache unit 23 as a data buffer. In this way, the DMA unit 22 actually only has control logic, while the data path and data buffer share the resources of the GPU core 20, thereby helping to reduce the area occupied by the DMA unit 22.

[0051] In some embodiments, the control unit 21 is configured to, upon receiving a first control instruction sent by the CPU 10, send the first control instruction to the DMA unit 22, where the first control instruction is used to execute a data read and write task associated with the memory 30. The DMA unit 22 is configured to execute the first control instruction.

[0052] In the embodiment of the present application, after the DMA unit 22 is moved from the outside of the GPU core 20 to the inside of the GPU core 20, a set of software and hardware interaction interfaces needs to be implemented so that the driver in the CPU 10 can interact with the DMA unit 22 through the interface, such as controlling the DMA unit 22 to start working. For example, when a data movement task needs to be executed, the driver in the CPU 10 can send a first control instruction to the control unit 21, and the control unit 21 sends the first control instruction to the DMA unit 22 for execution. In this way, the CPU 10 controls the DMA unit 22 inside the GPU core 20 to control it to execute the data movement task.

[0053] In some embodiments, the first control instruction is any one of the following instructions: a write instruction, a read instruction, a modify instruction, and an invalidate instruction. A write instruction is used to write data to the memory 30. A read instruction is used to read data from the memory 30. A modify instruction is used to modify data in the memory 30. An invalidate instruction is used to mark data in the memory 30 as invalid.

[0054] Optionally, when the first control instruction received by the DMA unit 22 is a write instruction, the DMA unit 22 writes data to the corresponding address in the memory 30 according to the address corresponding to the write instruction. When the first control instruction received by the DMA unit 22 is a read instruction, the DMA unit 22 reads data from the corresponding address in the memory 30 according to the address corresponding to the read instruction. When the first control instruction received by the DMA unit 22 is a modify instruction, the DMA unit 22 modifies the data at the corresponding address in the memory 30 according to the address corresponding to the modify instruction. When the first control instruction received by the DMA unit 22 is an invalid instruction, the DMA unit 22 marks the data at the corresponding address in the memory 30 as invalid according to the address corresponding to the invalid instruction.

[0055] Through the above-mentioned manner, it is realized that the DMA unit 22 inside the GPU core 20 can perform operations such as writing, reading, modifying, and invalidating data on the memory 30, so that the memory 30 has a complete data processing capability.

[0056] Optionally, after the DMA unit 22 receives the first control instruction, it parses the first control instruction and generates an instruction to control the cache unit 23. The instruction to control the cache unit 23 can perform operations including but not limited to (read, write), (read, modify, write), (read, modify, write, invalidate) on the same cache line.

[0057] In some embodiments, the DMA unit 22 is configured to execute a first control instruction, including: temporarily storing data from a data provider in the cache unit 23 according to the first control instruction; and transmitting the data in the cache unit 23 to a data receiver. The data provider is the CPU 10, and the data receiver is the memory 30; alternatively, the data provider is the memory 30, and the data receiver is the CPU 10.

[0058] For example, in a scenario where data is transferred from the CPU 10 to the memory 30, the first control instruction is used to transfer the data from the CPU 10 to the memory 30. The DMA unit 22 is used to temporarily store the data from the CPU 10 in the cache unit 23 according to the first control instruction; the DMA unit 22 is used to send the data in the cache unit 23 to the memory 30.

[0059] For example, in a scenario where data is transferred from memory 30 to CPU 10, the first control instruction is used to transfer data from memory 30 to CPU 10. DMA unit 22 is used to temporarily store the data from memory 30 in cache unit 23 according to the first control instruction; DMA unit 22 is used to send the data in cache unit 23 to CPU 10.

[0060] The cache unit 23 serves as a data buffer for the DMA unit 22. The data buffer is used to temporarily store data transferred by the DMA unit 22. The data buffer is a space for temporarily storing data. When data is moved from a data provider to a data receiver via the DMA unit 22, the data buffer is needed for temporary storage. The functions of the data buffer include the following aspects: 1. Solving the speed mismatch problem. There may be a difference in access speed between the CPU memory and the GPU video memory (such as higher video memory bandwidth). The buffer serves as a temporary storage area to absorb burst data traffic and avoid data loss or transmission blockage due to speed difference; 2. Optimizing efficiency of batch transmission. The buffer allows the DMA unit 22 to carry multiple data units (such as 32-bit or 128-bit data blocks) at one time, reducing the number of bus control switches and improving throughput. For example, the single transmission volume of a 128-bit buffer is 16 times that of an 8-bit buffer; 3. Decoupling device and memory interaction. The buffer makes the physical addresses of peripherals (such as GPUs) and memory transparent. For example, the GPU only needs to write data to the buffer, and the DMA unit 22 automatically handles address mapping and transmission logic to simplify the programming model; 4. Error detection and format conversion. The DMA unit 22 can integrate check bits (such as parity check) in the buffer to enhance data transmission reliability. In some scenarios, data format conversion can also be achieved (such as 16-bit peripheral data to 32-bit memory storage).

[0061] In some embodiments, the control unit 21 is further configured to, upon receiving a second control instruction sent by the CPU 10, send the second control instruction to the computing unit 24, where the second control instruction is configured to perform a rendering or computing task based on the data in the memory 30. The computing unit 24 is configured to execute the second control instruction.

[0062] For example, when a rendering or computing task needs to be executed, the driver in CPU 10 can send a second control instruction to control unit 21, which then sends the second control instruction to one or more computing units 24 for execution. Computing unit 24 interprets the second control instruction and performs the corresponding data rendering or computing task. In this manner, CPU 10 controls computing unit 24 within GPU core 20 to execute rendering or computing tasks.

[0063] In some embodiments, the computing unit 24 is further used to store the intermediate processing data generated in the cache unit 23 during the process of executing the rendering or computing task based on the second control instruction. In the case where there are multiple computing units 24, multiple computing units 24 share the cache unit 23 to store the intermediate processing data generated by the multiple computing units 24 respectively. The intermediate processing data can be understood as the data generated in the process of the computing unit 24 executing the rendering or computing task, and the intermediate processing data will be used in the subsequent processing flow of the rendering or computing task. Temporarily storing the intermediate processing data in the process of rendering or computing tasks in the cache unit 23 helps the computing unit 24 to store and read the intermediate processing data more efficiently and quickly, thereby saving the processing time of the rendering or computing task. In addition, multiple computing units 24 share the cache unit 23, which can make full use of the storage resources of the cache unit 23 and avoid waste of resources.

[0064] In some embodiments, the DMA unit 22 and the computing unit 24 can execute corresponding control instructions in parallel. That is, within the same GPU core 20, the DMA unit 22 executes a first control instruction, while the computing unit 24 executes a second control instruction, without interfering with each other and allowing execution to proceed in parallel. Due to the presence of the DMA unit 22, the DMA unit 22 is responsible for data transfer tasks, while the computing unit 24 is responsible for rendering or computing tasks. Because these two tasks are performed by two different entities, rather than a single entity, they can be executed in parallel, improving efficiency.

[0065] In some embodiments, for a data read scenario, both the DMA unit 22 and the computing unit 24 read data from the memory 30 ; and / or, for a data write scenario, both the DMA unit 22 and the computing unit 24 write data to the memory 30 .

[0066] When data is in the cache unit 23 of the GPU core 20, or when multiple instructions require write operations on data at the same address, it is necessary to ensure that the final data result is consistent. The simplest way is: since in the processor architecture provided by this application, the memory 30 is LLC (Last Level Cache), and LLC is the synchronization point for all data, as long as the data is refreshed to LLC each time, data consistency can be guaranteed. Therefore, the DMA unit 22 in each GPU core 20 and all computing units 24 read / write data from the memory 30, which can ensure that the data in the memory 30 seen by all GPU cores 20 at the same time is consistent.

[0067] Next, combine Figure 5 , based on Figure 4 The data processing flow implemented by the processor shown is introduced and explained.

[0068] S1 : The driver of the CPU 10 sends one or more control instructions to the control unit 21 in the GPU core 20 .

[0069] Optionally, if there are multiple control instructions, the driver of the CPU 10 needs to set the dependency and synchronization relationship between the control instructions, that is, which control instructions can be executed synchronously and which control instructions need to be executed in sequence.

[0070] S2, the control unit 21 in the GPU core 20 sends the first control instruction to the DMA unit 22 when receiving the first control instruction, and sends the second control instruction to the computing unit 24 when receiving the second control instruction; wherein the first control instruction is used to execute data reading and writing tasks related to the memory 30, and the second control instruction is used to execute rendering or computing tasks based on the data in the memory 30.

[0071] S3 , when receiving the first control instruction, the DMA unit 22 determines whether there is an instruction dependency, and if so, waits; otherwise, executes the first control instruction.

[0072] S4, when receiving the second control instruction, the computing unit 24 determines whether there is an instruction dependency, and if so, waits; otherwise, executes the second control instruction.

[0073] Among them, instruction dependency means that when executing instructions, the execution of certain instructions depends on the results of other instructions. In GPUs, instruction dependency is mainly reflected in the following aspects: data dependency, control dependency, and resource dependency. Data dependency means that certain instructions require the result of the previous instruction as input. For example, when performing floating-point operations, if the output of one instruction is the input of the next instruction, then there is a data dependency between the two instructions. Control dependency means that the execution order of certain instructions is determined by conditional branches. For example, in a conditional statement, certain instructions will only be executed when specific conditions are met. Resource dependency means that the execution of certain instructions requires the use of specific resources (such as registers or memory), and these resources are only available after the previous instruction is executed. By determining instruction dependencies, the accuracy of instruction execution can be ensured.

[0074] The technical solution provided by the embodiment of the present application moves the DMA unit from the outside of the GPU core to the inside of the GPU core. When the GPU computing power is expanded, the number of GPU cores can be increased, or the number of computing units within the GPU core can be increased. If the number of GPU cores increases, the number of DMA units also increases accordingly, so the DMA bandwidth is naturally expanded. If the number of computing units within the GPU core increases, in order to adapt to the increase in the number of computing units, the cache units and data paths in the GPU core will be adaptively increased, which corresponds to the increase in GPU bandwidth. At this time, the DMA bandwidth naturally benefits from the increase in GPU bandwidth. Therefore, the technical solution of the present application achieves the technical effect of synchronous expansion of DMA bandwidth as the GPU computing power increases.

[0075] Furthermore, because multiple computing units within the GPU core share a cache unit, which is typically of a certain size, the DMA unit can use the cache unit as a data buffer. This effectively reduces the DMA unit's footprint by only containing control logic, while the data path and data buffer share the GPU core's resources. This allows the DMA unit to scale synchronously with GPU computing power without consuming additional on-chip area.

[0076] The following are examples of the method of the present application. For details not disclosed in the examples of the method of the present application, please refer to the above examples.

[0077] Please refer to Figure 6 , which shows a flow chart of a data processing method applied to a GPU provided in a possible implementation of the present application. The components and structure of the GPU can be found in the description of the above embodiment. Figure 6 As shown, the method may include the following steps:

[0078] Step 610: upon receiving a first control instruction sent by the CPU, the control unit sends the first control instruction to the DMA unit, where the first control instruction is used to execute a data reading and writing task related to the memory.

[0079] In step 620 , the DMA unit executes the first control instruction.

[0080] In some embodiments, the at least one computing unit shares a cache unit, and the cache unit is used as a data buffer of the DMA unit, and the data buffer is used to temporarily store data transferred by the DMA.

[0081] In some embodiments, the DMA unit executes a first control instruction, including: the DMA unit temporarily storing data from a data provider in a cache unit according to the first control instruction; and the DMA unit sending the data in the cache unit to a data receiver. The data provider is a CPU, and the data receiver is a memory. Alternatively, the data provider is a memory, and the data receiver is a CPU.

[0082] In some embodiments, the first control instruction is a write instruction, which is used to write data to the memory; or, the first control instruction is a read instruction, which is used to read data from the memory; or, the first control instruction is a modify instruction, which is used to modify the data in the memory; or, the first control instruction is an invalid instruction, which is used to mark the data in the memory as invalid.

[0083] In some embodiments, the method further includes: upon receiving a second control instruction sent by the CPU, the control unit sends the second control instruction to the computing unit, wherein the second control instruction is used to perform a rendering or computing task based on data in the memory, and the computing unit executes the second control instruction.

[0084] In some embodiments, the method further includes: storing, by the computing unit, intermediate processing data generated during the rendering or computing task based on the second control instruction in a cache unit. If there are multiple computing units, the multiple computing units share the cache unit to store the intermediate processing data generated by the multiple computing units.

[0085] In some embodiments, the DMA unit and the computing unit are supported to execute corresponding control instructions in parallel.

[0086] In some embodiments, for a data reading scenario, the DMA unit and the computing unit both read data from the memory; and / or, for a data writing scenario, the DMA unit and the computing unit both write data to the memory.

[0087] An exemplary embodiment of the present application further provides a chip product, which includes the GPU described above. Optionally, the chip product may be a chip product that integrates a CPU and a GPU.

[0088] An exemplary embodiment of this application further provides a computer device comprising the GPU described above. Optionally, the computer device may be a personal computer, workstation, game console, or mobile device (such as a tablet computer or smartphone). It may also be an in-vehicle terminal device, smart home device, smart TV, or smart robot. It may also be a server, server cluster, artificial intelligence computing cluster, or cloud computing cluster. The artificial intelligence computing cluster may also be referred to as an intelligent computing cluster or smart computing cluster, which is not limited in this application.

[0089] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application do not limit this.

[0090] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A graphics processing unit (GPU), characterized in that: The GPU includes at least one GPU core; The GPU core includes: a control unit, a direct memory access (DMA) unit, a cache unit, and at least one computing unit; The DMA unit is coupled to the central processing unit CPU and the memory respectively.

2. The GPU according to claim 1, wherein The at least one computing unit shares the cache unit, and the cache unit is used as a data buffer of the DMA unit, and the data buffer is used to temporarily store data transferred by the DMA unit.

3. The GPU according to claim 1, wherein The control unit is configured to send a first control instruction sent by the CPU to the DMA unit upon receiving the first control instruction, wherein the first control instruction is used to execute a data reading and writing task related to the memory; The DMA unit is used to execute the first control instruction.

4. The GPU according to claim 3, wherein: The first control instruction is a write instruction, and the write instruction is used to write data into the memory; or, The first control instruction is a read instruction, and the read instruction is used to read data from the memory; or, The first control instruction is a modification instruction, and the modification instruction is used to modify the data in the memory; or, The first control instruction is an invalid instruction, and the invalid instruction is used to mark the data in the memory as invalid.

5. The GPU according to claim 3, wherein: The control unit is further configured to, upon receiving a second control instruction sent by the CPU, send the second control instruction to the computing unit, wherein the second control instruction is configured to execute a rendering or computing task based on the data in the memory; The computing unit is configured to execute the second control instruction.

6. The GPU according to claim 1, wherein: For a data reading scenario, both the DMA unit and the computing unit read data from the memory; and / or, In a data writing scenario, both the DMA unit and the computing unit write data into the memory.

7. A chip product, characterized in that: The chip product includes a graphics processing unit (GPU) as claimed in any one of claims 1 to 6.

8. A computer device, characterized in that: The computer device comprises a graphics processing unit (GPU) according to any one of claims 1 to 6.

9. A data processing method applied to a graphics processing unit (GPU), characterized in that: The GPU includes at least one GPU core; the GPU core includes: a control unit, a direct memory access (DMA) unit, a cache unit, and at least one computing unit; the DMA unit is coupled to a central processing unit (CPU) and a memory, respectively; the method includes: The control unit sends the first control instruction to the DMA unit when receiving the first control instruction sent by the CPU, where the first control instruction is used to execute a data reading and writing task related to the memory; The DMA unit executes the first control instruction.

10. The method according to claim 9, characterized in that The DMA unit executes the first control instruction, including: The DMA unit temporarily stores the data from the data provider into the cache unit according to the first control instruction; The DMA unit sends the data in the cache unit to a data receiver; The data provider is the CPU, and the data receiver is the memory; or the data provider is the memory, and the data receiver is the CPU.

11. The method according to claim 9, characterized in that The first control instruction is a write instruction, and the write instruction is used to write data into the memory; or, The first control instruction is a read instruction, and the read instruction is used to read data from the memory; or, The first control instruction is a modification instruction, and the modification instruction is used to modify the data in the memory; or, The first control instruction is an invalid instruction, and the invalid instruction is used to mark the data in the memory as invalid.

12. The method according to claim 9, characterized in that The method further comprises: The control unit sends the second control instruction to the computing unit when receiving the second control instruction sent by the CPU, where the second control instruction is used to perform a rendering or computing task based on the data in the memory; The computing unit executes the second control instruction.

13. The method according to claim 12, characterized in that The method further comprises: The computing unit stores the generated intermediate processing data in the cache unit during the process of executing the rendering or computing task based on the second control instruction; Wherein, in the case that there are multiple computing units, the multiple computing units share the cache unit to store the intermediate processing data respectively generated by the multiple computing units.

14. The method according to claim 9, characterized in that For a data reading scenario, both the DMA unit and the computing unit read data from the memory; and / or, In a data writing scenario, both the DMA unit and the computing unit write data into the memory.

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