Memory device with vertical transistor in OTP memory cell

Abstract

The present disclosure describes memory systems and devices having vertical transistors in one time programming (OTP) memory cells and methods of making the same. An example semiconductor device includes a first array of memory cells, the first array of memory cells including at least first memory cells. The first memory cell includes a first vertical transistor and a storage structure coupled to the first vertical transistor in a first direction. The first array of memory cells is in a first region of a first semiconductor structure of the semiconductor device. The semiconductor device further includes a second array of memory cells, the second array of memory cells including at least second memory cells. The second memory cell includes a second vertical transistor in a second region of the first semiconductor structure. The second region is adjacent to the first region in a second direction orthogonal to the first direction.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods of manufacturing the same. Background Art

[0002] The semiconductor industry is driven by the need to produce smaller and faster chips. Makers of memory devices and systems are also pushing for improved scaling technologies. Dynamic random access memory (DRAM) is a common type of memory device widely used in computer systems. The mainstream DRAM architecture has used 8F for many years. 2 Unit Design and 6F 2 Unit design, and is now in the process of moving to 4F 2 In the process of unit design transformation. Summary of the Invention

[0003] The present disclosure describes memory systems and devices having vertical transistors in one-time programming (OTP) memory cells and methods of fabricating the same.

[0004] One aspect of the present disclosure is characterized by a semiconductor device. The semiconductor device includes: a first array of memory cells, the first array of memory cells including at least a first memory cell. The first memory cell includes a first vertical transistor and a storage structure coupled to the first vertical transistor in a first direction. The first array of memory cells is in a first region of a first semiconductor structure of the semiconductor device. The semiconductor device also includes: a second array of memory cells, the second array of memory cells including at least a second memory cell. The second memory cell includes a second vertical transistor in a second region of the first semiconductor structure. The second region is adjacent to the first region in a second direction orthogonal to the first direction.

[0005] In some embodiments, the second memory cell is an OTP memory cell and further includes an access transistor coupled to the second vertical transistor, and the access transistor is in a second semiconductor structure of the semiconductor device.

[0006] In some embodiments, the second memory cell is an OTP memory cell, the second vertical transistor is an access transistor of the OTP memory cell, the OTP memory cell further includes an anti-fuse capacitor coupled to the second vertical transistor, and the anti-fuse capacitor is in the second semiconductor structure of the semiconductor device.

[0007] In some implementations, a source of the access transistor is coupled to a source of the second vertical transistor.

[0008] In some embodiments, the second array of memory cells includes a first group of vertical transistors, the first group of vertical transistors being coupled to a first programming line through a gate of each vertical transistor in the first group of vertical transistors; the first group of vertical transistors includes the second vertical transistor; and the first group of vertical transistors is included in a first array of vertical transistors in the second region of the first semiconductor structure.

[0009] In some embodiments, each vertical transistor in the first set of vertical transistors is coupled to a corresponding access transistor in the second semiconductor structure through a first terminal of the vertical transistor; and a second terminal of the vertical transistor is floating.

[0010] In some embodiments, the second array of memory cells further includes a second group of vertical transistors coupled to a second programming line via a gate of each vertical transistor in the second group of vertical transistors; and the second group of vertical transistors is included in a second array of vertical transistors in the second region of the first semiconductor structure.

[0011] In some embodiments, the first group of vertical transistors is included in the same row or the same column of the first array of vertical transistors; and the gate of each vertical transistor in the first group of vertical transistors is part of the same connection line of the first array of vertical transistors.

[0012] In some embodiments, a terminal of each vertical transistor in the first group of vertical transistors is directly connected to a contact structure extending along the first direction; and the contact structure is further connected to a conductive line comprising metal, and the conductive line extends in a direction orthogonal to the first direction.

[0013] In some embodiments, a terminal of each vertical transistor in the first set of vertical transistors is directly connected to a conductive line extending in a direction orthogonal to the first direction; and the conductive line comprises metal.

[0014] In some embodiments, each vertical transistor in the first group of vertical transistors is in a different row or a different column of the first array of vertical transistors; and each vertical transistor in the first group of vertical transistors is coupled to the first programming line through a corresponding connection line of the first array of vertical transistors.

[0015] In some embodiments, a hybrid bonding structure is located between the second vertical transistor and the access transistor, the second vertical transistor and the access transistor are located at different positions along the first direction, and the second vertical transistor and the access transistor are coupled by at least one contact structure extending along the first direction and at least one conductive line extending along the second direction.

[0016] In some embodiments, the first programming line is coupled to the second semiconductor structure via a hybrid bonding structure, each vertical transistor in the first group of vertical transistors includes a first terminal coupled to a corresponding access transistor in the second semiconductor structure and a second terminal coupled to a floating bit line, and the second terminal of the vertical transistor is a drain of the vertical transistor.

[0017] Another aspect of the present disclosure features a semiconductor device. The semiconductor device includes an array of OTP memory cells, the array of OTP memory cells including at least one OTP memory cell. The OTP memory cell includes a vertical transistor in a first semiconductor structure of the semiconductor device and an access transistor in a second semiconductor structure of the semiconductor device. The first semiconductor structure and the second semiconductor structure are bonded via a hybrid bonding structure. The access transistor is coupled to the vertical transistor.

[0018] In some embodiments, the semiconductor device further includes an array of dynamic random access memory (DRAM) cells, the array of dynamic random access memory cells including at least a DRAM cell. The DRAM cell includes a first vertical transistor and a storage structure coupled to the first vertical transistor in a first direction. The array of DRAM cells is located in a first region of a first semiconductor structure of the semiconductor device. The vertical transistor of the OTP memory cell is a second vertical transistor in a second region of the first semiconductor structure; and the second region is adjacent to the first region in a second direction orthogonal to the first direction.

[0019] In some implementations, a source of the access transistor is coupled to a source of the second vertical transistor.

[0020] In some embodiments, the array of OTP memory cells includes a first group of vertical transistors, the first group of vertical transistors coupled to a first programming line through a gate of each vertical transistor in the first group of vertical transistors; the first group of vertical transistors includes the second vertical transistor; and the first group of vertical transistors is included in a first array of vertical transistors in the second region of the first semiconductor structure.

[0021] In some embodiments, each vertical transistor in the first set of vertical transistors is coupled to a corresponding access transistor in the second semiconductor structure through a first terminal of the vertical transistor; and a second terminal of the vertical transistor is floating.

[0022] In some embodiments, the array of OTP memory cells further includes a second group of vertical transistors coupled to a second programming line via a gate of each vertical transistor in the second group of vertical transistors; and the second group of vertical transistors is included in a second array of vertical transistors in the second region of the first semiconductor structure.

[0023] In some embodiments, the first group of vertical transistors is included in the same row or the same column of the first array of vertical transistors; and the gate of each vertical transistor in the first group of vertical transistors is part of the same connection line of the first array of vertical transistors.

[0024] In some embodiments, a terminal of each vertical transistor in the first group of vertical transistors is directly connected to a contact structure.

[0025] In some embodiments, a terminal of each vertical transistor in the first group of vertical transistors is directly connected to a conductive line.

[0026] In some embodiments, each vertical transistor in the first group of vertical transistors is in a different row or a different column of the first array of vertical transistors, and each vertical transistor in the first group of vertical transistors is coupled to the first programming line through a corresponding connection line of the first array of vertical transistors.

[0027] In some embodiments, a hybrid bonding structure is located between the second vertical transistor and the access transistor, the second vertical transistor and the access transistor are located at different positions along the first direction, and the second vertical transistor and the access transistor are coupled by at least one contact structure extending along the first direction and at least one conductive line extending along the second direction.

[0028] In some embodiments, the first programming line is coupled to the second semiconductor structure via a hybrid bonding structure, each vertical transistor in the first group of vertical transistors includes a first terminal coupled to a corresponding access transistor in the second semiconductor structure and a second terminal coupled to a floating bit line, and the second terminal of the vertical transistor is a drain of the vertical transistor.

[0029] Another aspect of the present disclosure features a method for forming a semiconductor device. The method includes forming a first vertical transistor in a first region of a first semiconductor structure of the semiconductor device. The first vertical transistor includes a first semiconductor body and a first gate structure in contact with at least one side of the first semiconductor body. The first vertical transistor is an anti-fuse capacitor of an OTP memory cell. The method also includes forming a transistor in a second semiconductor structure of the semiconductor device; and bonding the first semiconductor structure and the second semiconductor structure via a hybrid bonding structure. The first vertical transistor is coupled to the transistor via the hybrid bonding structure.

[0030] In some embodiments, the method further includes forming a second vertical transistor in a second region of the first semiconductor structure. The second vertical transistor includes a second semiconductor body and a second gate structure in contact with at least one side of the second semiconductor body. The method further includes forming a storage structure coupled to the second vertical transistor along a first direction. The second region is adjacent to the first region in a second direction orthogonal to the first direction.

[0031] In some embodiments, the first vertical transistor and the second vertical transistor are formed during the same operation. The operation includes forming the first semiconductor body of the first vertical transistor in the first region of the first semiconductor structure, and forming the second semiconductor body of the second vertical transistor in the second region of the first semiconductor structure. The first semiconductor body and the second semiconductor body are formed on a first side of the first semiconductor structure. The operation also includes forming the first gate structure of the first vertical transistor and the second gate structure of the second vertical transistor.

[0032] In some embodiments, the method further includes covering the first region of the first semiconductor structure with a mask when forming the storage structure.

[0033] In some embodiments, the method further includes removing a first portion of the first region of the first semiconductor structure from the first side to expose a first end of the first semiconductor body, and forming a first connecting wire and a first contact structure. The first connecting wire connects the first end of the first semiconductor body and the first contact structure, and the first contact structure is coupled to the hybrid bonding structure.

[0034] In some embodiments, the method further includes removing a second portion of the first semiconductor structure from the second side to expose a second end of the first semiconductor body, and forming a second connection line contacting the second end of the first semiconductor body. The second connection line is floating.

[0035] In some embodiments, the method further includes forming a third connection line and a second contact structure, wherein the third connection line connects the first gate structure and the second contact structure, and the second contact structure is coupled to the hybrid bonding structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A side view of a cross section of an example semiconductor device according to aspects of the present disclosure is shown.

[0037] Figures 2A-2B A top view of an example semiconductor device according to some aspects of the present disclosure is shown.

[0038] Figures 3A-3H An example one-time programmable (OTP) memory cell array is shown in accordance with some aspects of the present disclosure.

[0039] Figures 4A-4E A fabrication process for forming an example semiconductor structure according to some aspects of the present disclosure is shown.

[0040] Figure 5 A flowchart illustrating an example method for forming a semiconductor device according to aspects of the present disclosure is shown.

[0041] Figure 6 A block diagram of a system having one or more semiconductor devices according to some aspects of the present disclosure is shown.

[0042] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0043] The semiconductor industry is driven by the need to produce smaller and faster chips. Scaling DRAM devices faces many challenges. For example, manufacturing processes have advanced from 18-nanometer (nm) and 15-nanometer processes to 10-nanometer processes. However, the increased density of memory cells in a chip and the row hammer effect can lead to interference errors. Therefore, advanced technologies are desired to alleviate these problems and improve the scaling of DRAM devices. To reduce the size of memory devices and increase the density of memory cells, vertical transistors can be used to replace the planar transistors in the memory cells of a memory device. The planar transistors in a memory cell can have a horizontal structure with a buried word line in the substrate and a bit line above the substrate. Planar transistors can occupy a larger area in the memory cell because the source and drain of the planar transistor are arranged at different locations laterally. In comparison, vertical transistors typically have a vertically extending semiconductor body. The source and drain of a vertical transistor can be arranged at opposite ends of the semiconductor body. Therefore, replacing planar transistors in a memory cell with vertical transistors can reduce the area occupied by each memory cell and simplify the layout of the interconnect structure of the memory cell, word line, and bit line.

[0044] Embodiments of the present disclosure may provide one or more of the following technical advantages and / or benefits. The gate oxide layer of a metal oxide semiconductor field effect transistor (MOSFET) becomes a conductive channel when receiving a breakdown voltage. Therefore, the anti-fuse storage structure (e.g., an anti-fuse capacitor) of a one-time programmable (OTP) memory cell may be implemented as a MOSFET. Vertical transistors are suitable for use as such anti-fuse storage structures because the thickness of the gate oxide layer of the vertical transistor can be precisely controlled during the manufacturing process. The present disclosure may reduce the chip size of a memory device having an array wafer and a complementary metal oxide semiconductor (CMOS) wafer, the array wafer and the CMOS wafer occupying separate structures and being bonded by a hybrid bonding structure. Specifically, a portion of an OTP memory cell array (e.g., a peripheral circuit of a memory device) may be relocated from a CMOS wafer to an array wafer and may be implemented as a vertical transistor in the array wafer, thereby reducing the area occupied by the peripheral circuit. In addition, the anti-fuse storage structure and the access transistor of the OTP memory cell array may be coupled by a hybrid bonding structure. In this way, interference caused by parasitic capacitance and parasitic resistance may be mitigated, and the performance of the memory device may be improved.

[0045] The technology can be applied to various types of semiconductor devices, volatile memory devices (such as DRAM memory devices) or non-volatile memory (NVM) devices (such as NAND flash memory, NOR flash memory, resistive random-access memory (RRAM), phase-change memory (PCM) (such as phase-change random-access memory (PCRAM)), spin-transfer torque (STT)-magnetoresistive random-access memory (MRAM), etc. The technology can also be applied to charge trapping-based memory devices (for example, silicon-oxide-nitride-oxide-silicon (SONOS) memory devices) and floating gate-based memory devices. These technologies can be applied to three-dimensional (3D) memory devices. The technology can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices, and MLC (multi-level cell) devices. The technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, etc.

[0046] The details of one or more implementations of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims.

[0047] Figure 1 A side view of a cross section of an example semiconductor device 100 according to some aspects of the present disclosure is shown. In some implementations, the semiconductor device 100 can be a memory device such as a dynamic random access memory (DRAM) device.

[0048] It should be noted that in Figure 1The X, Y, and Z axes (also referred to as X, Y, Z directions) are included to further illustrate the spatial relationships of various components in a semiconductor device. The substrate of a semiconductor device includes two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the wafer, on which components of the semiconductor device can be formed; and a bottom surface on the back side opposite the front side of the wafer. The Z direction is orthogonal to the X and Y directions. As used herein, whether a component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of a semiconductor device is determined relative to the substrate in the Z direction when the substrate of the semiconductor device is located in the lowest plane of the semiconductor device in the Z direction (a vertical direction orthogonal to the XY plane, e.g., the thickness direction of the substrate). The same concepts used to describe spatial relationships apply throughout this disclosure.

[0049] The semiconductor device 100 is a bonded chip including a semiconductor structure 102 and a semiconductor structure 104 stacked on the semiconductor structure 102. According to some embodiments, the semiconductor structures 102 and 104 may be bonded at a bonding structure 106 (also referred to as a bonding layer or bonding interface) therebetween. Figure 1 As shown, the semiconductor structure 104 may include one or more memory cell arrays 110. Each memory cell (e.g., a DRAM cell) in the memory cell array 110 may include a vertical transistor 112 extending in a vertical direction (e.g., a Z direction) and a storage structure 113 (e.g., a capacitor) coupled to the vertical transistor 112 in the vertical direction. Figure 1 As shown, the semiconductor structure 102 may include a substrate 108 , which may include silicon (eg, single crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.

[0050] In some embodiments, semiconductor structure 104 is referred to as an array wafer of semiconductor device 100, and semiconductor structure 102 is referred to as a complementary metal-oxide-semiconductor (CMOS) wafer of semiconductor device 100. Semiconductor structure 102 can be bonded to semiconductor structure 104 in a face-to-face manner via a bonding structure 106 extending along the XY plane. In some embodiments, bonding structure 106 is disposed between semiconductor structures 102 and 104 as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive) and can simultaneously obtain metal-metal bonding and dielectric-dielectric bonding. In some embodiments, bonding structure 106 can include a bonding layer in semiconductor structure 102 and a bonding layer in semiconductor structure 104 ( Figure 1 136). The bonding layer in semiconductor structure 104 may include a bonding contact 136 and a dielectric electrically isolating bonding contact 136. Each of bonding contacts 136 and 138 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof.

[0051] Semiconductor device 100 also includes peripheral circuitry in semiconductor structure 102 or semiconductor structure 104, or both. In some embodiments, the peripheral circuitry is configured to control and sense memory cell array 110. The peripheral circuitry can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry for facilitating semiconductor device 100, including, but not limited to, page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0052] In some embodiments, the peripheral circuit includes one or more one-time programmable (OTP) memory cell arrays 114. The OTP memory cell array 114 may include a vertical transistor 116 in the semiconductor structure 104 and a transistor 118 in the semiconductor structure 102. In some embodiments, the transistor 118 is a planar transistor. Each OTP memory cell in the OTP memory cell array 114 includes one vertical transistor 116 and one transistor 118 coupled together. Figure 1As shown, a terminal (source or drain) of the vertical transistor 116 can be coupled to the transistor 118 (e.g., the source or drain of the transistor 118) via a connecting line (e.g., 146) extending in a horizontal direction and a contact structure (e.g., 148 and 150) extending in a vertical direction. In some embodiments, as described with respect to Figures 3B-3F As described in further detail in the accompanying drawings, vertical transistor 116 is an anti-fuse structure (e.g., an anti-fuse capacitor) of the OTP memory cell, and transistor 118 coupled to vertical transistor 116 is an access transistor of the OTP memory cell. In some other embodiments, as described with respect to Figures 3G-3H As described in further detail, vertical transistor 116 may be an access transistor of the OTP memory cell, and transistor 118 coupled to vertical transistor 116 may be an anti-fuse structure of the OTP memory cell.

[0053] Memory cell array 110 may be located in region 120 of semiconductor structure 104. Region 120 may be referred to as an array region. Vertical transistor 116 may be located in region 122 of semiconductor structure 104. Region 122 may be referred to as a dummy region or peripheral region. Region 122 may be adjacent to region 120 along the X-direction. In some embodiments, vertical transistor 116 and vertical transistor 112 in memory cell array 110 are formed during the same vertical transistor fabrication process.

[0054] like Figure 1 As shown, the vertical transistor 116 includes a semiconductor body 124 having a substrate ( Figure 1 1 and 2. The semiconductor body 124 extends vertically (in the z-direction) above the substrate (not shown). It should be understood that the semiconductor body 124 can have any suitable 3D shape, such as a polyhedron or a cylindrical shape. That is, the cross-section of the semiconductor body 124 in a plan view (e.g., in the xy plane) can have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other suitable shape. In some embodiments, the semiconductor body 124 can be formed from a substrate (e.g., by etching or epitaxy) and thus has the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate).

[0055] like Figure 1As shown, the vertical transistor 116 may further include a gate structure 126 in contact with one or more sides of the semiconductor body 124. The gate structure 126 extends along a horizontal direction (e.g., Y direction) orthogonal to the X direction and the Z direction. The gate structure 126 may include a gate dielectric 128 on one or more sides of the semiconductor body 124. The gate structure 126 may further include a gate electrode 132 on the gate dielectric 128 and in contact with the gate dielectric 128. The gate dielectric 128 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. The gate electrode 132 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode 132 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, as Figure 1 As shown, the gate structure 126 may include a TiN layer (eg, layer 130 ) between a gate dielectric 128 and a gate electrode 132 (eg, a W layer).

[0056] The vertical transistor 116 may also include a pair of source and drain (S / D, doped regions, also known as source electrode and drain electrode) formed at both ends of the semiconductor body 124 in the vertical direction (z direction), respectively. The source and drain may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant (such as phosphorus (P) or arsenic (As)). The source and drain may be separated in the vertical direction (z direction) by the gate structure 126. In planar transistors and some lateral multi-gate transistors (e.g., fin field-effect transistors (FinFETs)), the active region, such as the semiconductor body (e.g., fin), extends laterally (in the XY plane), and the source and drain are arranged at different positions in the same lateral plane (XY plane). In contrast, according to some embodiments, in the vertical transistor 116, the semiconductor body 124 extends vertically (in the Z direction), and the source and drain are arranged in different lateral planes. In some embodiments, the source and drain are formed at both ends of the semiconductor body 124 in the vertical direction (Z direction) so as to overlap in a planar view. As a result, the area occupied by the vertical transistor 116 (in the XY plane) can be reduced compared to planar transistors and lateral multi-gate transistors. In addition, the metal wiring coupled to the vertical transistor 116 can be simplified.

[0057] In some embodiments, the vertical transistor 116 is a multi-gate transistor. That is, the gate structure 126 can contact more than one side of the semiconductor body 124. In some other embodiments, such as Figure 1As shown in some other figures of the present disclosure, the vertical transistor 116 is a single-gate transistor. That is, the gate structure 126 can be in contact with a single side of the semiconductor body 124, for example, for the purpose of increasing the density of transistors and memory cells. In some embodiments, as shown in FIG. Figure 1 As shown, a conductive layer 134 (eg, Ti metal) is located between two adjacent vertical transistors 116. The conductive layer 134 may be configured to have a low voltage level, thereby improving the coupling effect between the two adjacent vertical transistors.

[0058] In some embodiments, as Figure 1 As shown, the semiconductor device 100 further includes one or more contact structures 140 extending along the Z direction in the semiconductor structure 104 and one or more contact pads 152 extending in the XY plane proximate to a surface 144 of the semiconductor structure 104. The contact structures 140 may be coupled to contact pads 152 for pad-outs, which may provide connections from the interior of the semiconductor device 100 (e.g., through an interconnect layer 154 as described below) to external components (e.g., on the surface 144 of the semiconductor structure 104).

[0059] In some embodiments, the semiconductor structure 104 further includes one or more interconnect layers (e.g., Figure 1 154 as shown) for routing electrical signals between different components of the semiconductor structure 104. For example, the interconnect layer 154 can connect each of the contact structure 150 and the gate structure 126 to a corresponding bonding contact (e.g., one of the bonding contacts 136) on the surface 142 of the semiconductor structure 104, and can connect appropriate components to the contact structure 140 for pad lead-out. Each interconnect layer may include lateral interconnect lines and vertical interconnect structures such as vertical interconnect path (VIA) contacts or contact structures. As used herein, the term "interconnect" can broadly include any suitable type of interconnect, such as middle-end of line (MEOL) interconnect and back-end of line (BEOL) interconnect. The interconnect lines and VIA contacts in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof.

[0060] Figures 2A-2B 1 and 2 show top views of example semiconductor devices 200a and 200b, respectively, according to aspects of the present disclosure. The semiconductor device 200a may be Figure 1 The semiconductor device 200a includes a CMOS wafer and an array wafer ( Figure 2A (not shown). The semiconductor device 200a includes a memory cell array 202a in an array wafer. The memory cell array 202a may be Figure 1The semiconductor device 200a further includes an OTP memory cell array 204a, which may be an example of a memory cell array 110. Figure 1 1. The semiconductor device 200a further includes a control circuit 210a for the OTP memory cell array 204a. In some embodiments, each of the OTP memory cell arrays 204a can be divided into two parts 206 and 208, one in the array wafer and the other in the CMOS wafer. Part 208 can include vertical transistors (e.g., Figure 1 Component 206 (e.g., vertical transistor 116) and located in the array wafer. Figure 1 The control circuit 210a for the OTP memory cell array 204a is in the CMOS die of the semiconductor device 200a.

[0061] The semiconductor device 200b may be another semiconductor device (eg, a DRAM device) formed in a different structure. The semiconductor device 200b further includes a CMOS wafer and an array wafer ( Figure 2B (not shown in FIG. 2 ). The semiconductor device 200b includes a memory cell array 202b in an array wafer and an OTP memory cell array 204b in a CMOS wafer. The CMOS wafer of the semiconductor device 200b further includes a control circuit 210b for the OTP memory cell array 204b.

[0062] The structures of semiconductor devices 200a and 200b differ in that a portion of the OTP memory cell array in semiconductor device 200a (e.g., portion 208 of OTP memory cell array 204a) is located in the array wafer of semiconductor device 200a, while the OTP memory cell array in semiconductor device 200b is located in the CMOS wafer of semiconductor device 200b. As a result, the peripheral circuits in semiconductor device 200b occupy more chip space (e.g., in the XY plane). In other words, compared to semiconductor device 200b, by relocating a portion of the OTP memory cell array from the CMOS wafer of semiconductor device 200a to the array wafer of semiconductor device 200a, the chip size of semiconductor device 200a is reduced.

[0063] Figures 3A-3H An example OTP memory cell array according to some aspects of the present disclosure is shown. Figure 3ASchematic diagram 300a of an example OTP memory cell array according to some aspects of the present disclosure is shown. The OTP memory cell array shown in Figure 300a includes OTP memory cells 0, 1, 2, and 3 coupled to a programming line (PL) 0 and OTP memory cells 4, 5, 6, and 7 coupled to PL 1. Figure 300a also includes word lines (WL) 0, 1, 2, and 3 and bit lines (BL) 0 and 1. OTP memory cells 0-7 can be 2-T OTP cells. That is, each OTP memory cell includes an access transistor and an antifuse structure coupled together. The antifuse structure can be an antifuse capacitor and can be implemented, for example, by an N-type metal-oxide-semiconductor (NMOS) transistor. OTP memory cell 0 includes access transistor 0 and antifuse structure 0. A terminal (e.g., source) of access transistor 0 is coupled to a terminal (e.g., source) of antifuse structure 0. Another terminal (e.g., drain) of access transistor 0 is coupled to a bit line (e.g., as shown in FIG. 1 ). Figure 3A BL0 is shown. The other terminal of antifuse structure 0 is floating. The gate of antifuse structure 0 is coupled to a programming line (e.g., PL0), and the gate of access transistor 0 is coupled to a word line (e.g., WL0). OTP memory cells 1-7 have a structure similar to OTP memory cell 0. OTP memory cells 0, 1, 4, and 5 are coupled to BL0, and OTP memory cells 2, 3, 6, and 7 are coupled to BL1. In addition, OTP memory cells 0 and 4 are coupled to WL0 via the gates of their respective access transistors, OTP memory cells 1 and 5 are coupled to WL1 via the gates of their respective access transistors, OTP memory cells 2 and 6 are coupled to WL2 via the gates of their respective access transistors, and OTP memory cells 3 and 7 are coupled to WL3 via the gates of their respective access transistors.

[0064] It should be understood that although Figure 3A Diagram 300a shows two PLs, two BLs, four WLs, and eight OTP memory cells, but the OTP memory array can include any suitable number of PLs, BLs, WLs, and OTP memory cells.

[0065] Figure 3B According to some aspects of the present disclosure, Figure 3A Schematic diagram 300a is formed of a perspective view of an example OTP memory cell array 300b. Figure 3C A top view 300c of an OTP memory cell array 300b is shown. The OTP memory cell array 300b may be used to form a memory device (eg, Figure 1The OTP memory cell array 300b includes a vertical transistor array 301a, a vertical transistor array 301b, a planar transistor array 303a, and a planar transistor array 303b. Each of the vertical transistor arrays 301a and 301b may also be referred to as a vertical transistor block. In some embodiments, the vertical transistor arrays 301a and 301b may be located on an array wafer (e.g., Figure 1 The planar transistor arrays 303a and 303b may be located in a CMOS wafer of a memory device (eg, Figure 1 In the semiconductor structure 102).

[0066] The vertical transistor array 301a includes an array of vertical transistors extending along the Z direction (such as vertical transistors 306a, 306b, and 306c). The drains of each row of vertical transistors in the vertical transistor array 301a (arranged along the X direction) are coupled to a connection line (also called a terminal line) extending along the X direction. The gates of each column of vertical transistors in the vertical transistor array 301a are coupled to a connection line (also called a gate line) extending along the Y direction. Figure 3B and Figure 3C As shown, each vertical transistor in the vertical transistor array 301a is located at the intersection of a corresponding terminal line and a corresponding gate line. The terminal lines of the vertical transistor array 301a include 302a, 302b, and 302c. The gate lines of the vertical transistor array 301a include 304a, 304b, and 304c.

[0067] Similarly, the vertical transistor array 301b also includes an array of vertical transistors extending along the Z direction (such as vertical transistors 306d, 306e, and 306f). The drains of the vertical transistors in each row (arranged along the X direction) in the vertical transistor array 301b are coupled to a terminal line extending along the X direction. The gates of the vertical transistors in each column of the vertical transistor array 301b are coupled to a gate line extending along the Y direction. Figure 3B and Figure 3C As shown, each vertical transistor in vertical transistor array 301b is located at the intersection of a corresponding terminal line and a corresponding gate line. The terminal lines of vertical transistor array 301b include 302d, 302e, and 302f. The gate lines of vertical transistor array 301b include 304d, 304e, and 304f. In some embodiments, the terminal lines and gate lines in vertical transistor arrays 301a and 301b are made of a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. Each terminal line in vertical transistor arrays 301a and 301b is floating.

[0068] In some embodiments, the antifuse structure shown in FIG300a, whose gates are coupled to the same PL, can be implemented using a column of vertical transistors in a vertical transistor array (with their gates coupled to the same gate line). For example, gate line 304a in vertical transistor array 301a of OTP memory cell array 300b can be PL 0 of FIG300a. Vertical transistor 306a in vertical transistor array 301a of OTP memory cell array 300b can be antifuse structure 0 of FIG300a. Vertical transistor 306b in vertical transistor array 301a of OTP memory cell array 300b can be antifuse structure 1 of FIG300a. Vertical transistor 306c in vertical transistor array 301a of OTP memory cell array 300b can be antifuse structure 2 of FIG300a. Planar transistor 308a (in a CMOS wafer) in OTP memory cell array 300b can be access transistor 0 of FIG300a. The planar transistor 308b in the OTP memory cell array 300b (in the CMOS wafer) may be the access transistor 1 of FIG. 300a. The planar transistor 308c in the OTP memory cell array 300b (in the CMOS wafer) may be the access transistor 2 of FIG. 300a. Figure 3B As shown, a terminal (e.g., source) of each of the vertical transistors 306a, 306b, and 306c is coupled to a terminal (e.g., source) of a corresponding one of the planar transistors 308a, 308b, and 308c via a contact structure (e.g., 310a) extending along the Z direction, a connection line (e.g., 312a) extending in the XY plane (e.g., along the X direction), another contact structure (e.g., 314a) extending along the Z direction, and a bonding contact (e.g., 316a) in a hybrid bonding structure between the array wafer and the CMOS wafer.

[0069] Similarly, gate line 304d in vertical transistor array 301b of OTP memory cell array 300b may be PL 1 of FIG. 300a . Vertical transistor 306d in vertical transistor array 301b of OTP memory cell array 300b may be antifuse structure 4 of FIG. 300a . Vertical transistor 306e in vertical transistor array 301b of OTP memory cell array 300b may be antifuse structure 5 of FIG. 300a . Vertical transistor 306f in vertical transistor array 301b of OTP memory cell array 300b may be antifuse structure 6 of FIG. 300a . Planar transistor 308d in OTP memory cell array 300b (in a CMOS wafer) may be access transistor 4 of FIG. 300a . Planar transistor 308e in OTP memory cell array 300b (in a CMOS wafer) may be access transistor 5 of FIG. 300a . The planar transistor 308f in the OTP memory cell array 300b (in a CMOS wafer) may be the access transistor 6 of FIG. 300a. Figure 3B As shown, a terminal (e.g., source) of each of the vertical transistors 306 d, 306 e, and 306 f is coupled to a terminal (e.g., source) of a corresponding one of the planar transistors 308 d, 308 e, and 308 f via a contact structure (e.g., 310 b) extending along the Z direction, a connection line (e.g., 312 b) extending in the XY plane (e.g., along the X direction), another contact structure (e.g., 314 b) extending along the Z direction, and a bonding contact (e.g., 316 b) in a hybrid bonding structure between the array wafer and the CMOS wafer.

[0070] Figure 3D According to some aspects of the present disclosure, Figure 3A 300a is formed. The OTP memory cell array 300d can be used to form a memory device (e.g., Figure 1 The OTP memory cell array 300d has the same top view 300c as the OTP memory cell array 300b. Similar to the OTP memory cell array 300b, the OTP memory cell array 300d also includes an array wafer (eg, Figure 1 The vertical transistor arrays 301a and 301b in the semiconductor structure 104) and the CMOS wafer of the memory device (eg, Figure 11 . The planar transistor arrays 303a and 303b in the semiconductor structure 102 of FIG. The OTP memory cell array 300d differs from the OTP memory cell array 300b in that the source of each vertical transistor in the OTP memory cell array 300d coupled to the corresponding planar transistor is directly coupled to a connection line extending in the XY plane, rather than being coupled to the connection line through a contact structure extending in the Z direction. For example, the source of the vertical transistor 306a in the vertical transistor array 301a is directly coupled to the connection line 312a extending in the XY plane (e.g., along the X direction). Similarly, the source of the vertical transistor 306d in the vertical transistor array 301b is directly coupled to the connection line 312b extending in the XY plane (e.g., along the X direction). In this way, the connection lines 312a and 312b and the storage structure of the memory cell array, which is also located in the array wafer of the memory device, can be formed in the same manufacturing process (e.g., using double patterning), thereby reducing manufacturing costs.

[0071] Figure 3E According to some aspects of the present disclosure, Figure 3A 300a is a perspective view of another example OTP memory cell array 300e formed from the schematic diagram. Figure 3F A top view 300f of an OTP memory cell array 300e is shown. The OTP memory cell array 300e may be used to form a memory device (e.g., Figure 1 The OTP memory cell array 300e also includes an array wafer of memory devices (eg, Figure 1 The vertical transistor arrays 301a and 301b in the semiconductor structure 104) and the CMOS wafer of the memory device (eg, Figure 1 1. Planar transistor arrays 303a and 303b in the semiconductor structure 102).

[0072] In some embodiments, the antifuse structure of FIG. 300 a can be implemented using vertical transistors on different columns of a vertical transistor array whose gates are coupled to the same PL. For example, the gate lines (e.g., 304 a, 304 b, and 304 c) in the vertical transistor array 301 a of the OTP memory cell array 300 e can be connected (e.g., Figure 3F 300a). In some cases, the antifuse structure whose gate is coupled to PL 0 of FIG. 300a can be arranged on a diagonal line of the vertical transistor array. Figure 3FAs shown, for example, the vertical transistor 306a in the vertical transistor array 301a of the OTP memory cell array 300b can be the antifuse structure 0 of FIG. 300a. The vertical transistor 306g in the vertical transistor array 301a of the OTP memory cell array 300b can be the antifuse structure 1 of FIG. 300a. The vertical transistor 306h in the vertical transistor array 301a of the OTP memory cell array 300b can be the antifuse structure 2 of FIG. 300a. The planar transistor 308a (in a CMOS wafer) in the OTP memory cell array 300b can be the access transistor 0 of FIG. 300a. The planar transistor 308b (in a CMOS wafer) in the OTP memory cell array 300b can be the access transistor 1 of FIG. 300a. The planar transistor 308c (in a CMOS wafer) in the OTP memory cell array 300b can be the access transistor 2 of FIG. 300a. Figure 3B As shown, a terminal (e.g., source) of each of the vertical transistors 306a, 306g, and 306h is coupled to a terminal (e.g., source) of a corresponding one of the planar transistors 308a, 308b, and 308c via a contact structure (e.g., 310a) extending along the Z direction, a connection line (e.g., 312a) extending in the XY plane (e.g., along the X direction), another contact structure (e.g., 314a) extending along the Z direction, and a bonding contact (e.g., 316a) in a hybrid bonding structure between the array wafer and the CMOS wafer.

[0073] Similarly, the gate lines (eg, 304d, 304e, and 304f) in the vertical transistor array 301b of the OTP memory cell array 300e may be connected (eg, Figure 3F 300a ). The vertical transistor 306d in the vertical transistor array 301b in the OTP memory cell array 300e may be the antifuse structure 4 in FIG. 300a . The vertical transistor 306i in the vertical transistor array 301b in the OTP memory cell array 300e may be the antifuse structure 5 in FIG. 300a . The vertical transistor 306j in the vertical transistor array 301b in the OTP memory cell array 300e may be the antifuse structure 6 in FIG. 300a . The planar transistor 308d in the OTP memory cell array 300e (in a CMOS wafer) may be the access transistor 4 in FIG. 300a . The planar transistor 308e in the OTP memory cell array 300e (in a CMOS wafer) may be the access transistor 5 in FIG. 300a . The planar transistor 308f in the OTP memory cell array 300e (in a CMOS wafer) may be the access transistor 6 in FIG. 300a . Figure 3EAs shown, a terminal (e.g., source) of each of the vertical transistors 306 d, 306 i, and 306 j is coupled to a terminal (e.g., source) of a corresponding one of the planar transistors 308 d, 308 e, and 308 f via a contact structure (e.g., 310 b) extending along the Z direction, a connection line (e.g., 312 b) extending in the XY plane (e.g., along the X direction), another contact structure (e.g., 314 b) extending along the Z direction, and a bonding contact (e.g., 316 b) in a hybrid bonding structure between the array wafer and the CMOS wafer.

[0074] In some embodiments, vertical transistors (e.g., Figure 3E and 3F ) can create more space and make it easier to route interconnects between vertical transistors and other components.

[0075] Figure 3G According to some aspects of the present disclosure, Figure 3A 300a is a perspective view of another example OTP memory cell array 300g formed from the schematic diagram. Figure 3H A top view 300h of an OTP memory cell array 300g is shown. The OTP memory cell array 300g may be used to form a memory device (e.g., Figure 1 The OTP memory cell array 300g also includes an array wafer of memory devices (eg, Figure 1 The vertical transistor arrays 301a and 301b in the semiconductor structure 104) and the CMOS wafer of the memory device (eg, Figure 1 1. Planar transistor arrays 303a and 303b in the semiconductor structure 102).

[0076] In some embodiments, the access transistors in FIG. 300 a can be implemented using vertical transistors in an array wafer, and the antifuse structure in FIG. 300 a can be implemented using planar transistors in a CMOS wafer. Specifically, the access transistors in FIG. 300 a whose terminals (e.g., drains) are coupled to the same BL can be implemented using vertical transistors in two adjacent columns in a vertical transistor array. For example, the terminal lines (e.g., 302 a, 302 b, and 302 c) in the vertical transistor array 301 a of the OTP memory cell array 300 g can be connected (e.g., Figure 3H300a). The terminal line in the vertical transistor array 301a of the OTP memory cell array 300g is still floating. The gate lines 304a and 304b in the vertical transistor array 301a of the OTP memory cell array 300g may be WL0 and WL1, respectively, of FIG. 300a. The vertical transistor 306a in the vertical transistor array 301a of the OTP memory cell array 300g may be the access transistor 0 of FIG. 300a. The vertical transistor 306k in the vertical transistor array 301a of the OTP memory cell array 300g may be the access transistor 1 of FIG. 300a. The vertical transistor 306b in the vertical transistor array 301a of the OTP memory cell array 300g may be the access transistor 4 of FIG. 300a. The vertical transistor 306g in the vertical transistor array 301a of the OTP memory cell array 300g may be the access transistor 5 of FIG. 300a. The planar transistor 308a in the OTP memory cell array 300g (in a CMOS wafer) may be the antifuse structure 0 of FIG. 300a. The planar transistor 308b in the OTP memory cell array 300g (in a CMOS wafer) may be the antifuse structure 4 of FIG. 300a. Figure 3G As shown, a terminal (e.g., source) of each of the vertical transistors 306 a and 306 b is coupled to a terminal (e.g., source) of a corresponding one of the planar transistors 308 a and 308 b via a contact structure (e.g., 310 a) extending along the Z direction, a connection line (e.g., 312 a) extending in the XY plane (e.g., along the X direction), another contact structure (e.g., 314 a) extending along the Z direction, and a bonding contact (e.g., 316 a) in a hybrid bonding structure between the array wafer and the CMOS wafer.

[0077] Similarly, the terminal lines (eg, 302d, 302e, and 302f) in the vertical transistor array 301b of the OTP memory cell array 300g may be connected (eg, Figure 3H300a). The terminal line in the vertical transistor array 301b of the OTP memory cell array 300g remains floating. The gate lines 304d and 304e in the vertical transistor array 301b of the OTP memory cell array 300g may be WL2 and WL3, respectively, of FIG300a. The vertical transistor 306d in the vertical transistor array 301b of the OTP memory cell array 300g may be the access transistor 2 of FIG300a. The vertical transistor 306l in the vertical transistor array 301b of the OTP memory cell array 300g may be the access transistor 3 of FIG300a. The vertical transistor 306e in the vertical transistor array 301b of the OTP memory cell array 300g may be the access transistor 6 of FIG300a. The vertical transistor 306i in the vertical transistor array 301b of the OTP memory cell array 300g may be the access transistor 7 of FIG300a. The planar transistor 308d in the OTP memory cell array 300g (in the CMOS wafer) may be the antifuse structure 2 of FIG. 300a. The planar transistor 308e in the OTP memory cell array 300g (in the CMOS wafer) may be the antifuse structure 6 of FIG. 300a. Figure 3G As shown, a terminal (e.g., source) of each of the vertical transistors 306 d and 306 e is coupled to a terminal (e.g., source) of a corresponding one of the planar transistors 308 d and 308 e via a contact structure (e.g., 310 b) extending along the Z direction, a connection line (e.g., 312 b) extending in the XY plane (e.g., along the X direction), another contact structure (e.g., 314 b) extending along the Z direction, and a bonding contact (e.g., 316 b) in a hybrid bonding structure between the array wafer and the CMOS wafer.

[0078] Figures 4A-4E A fabrication process for forming an example semiconductor structure according to some aspects of the present disclosure is shown. Figures 4A-4E The structure shown in may be similar to or identical to Figure 1 The semiconductor device 100 and Figure 2A The semiconductor device 200a, or a structure in an intermediate manufacturing process of the semiconductor devices 100 and 200a.

[0079] like Figure 4A As shown, an array of vertical transistors 402 is formed on a substrate 404. Each vertical transistor 402 may be Figure 1 Another array of vertical transistors (eg, memory cell array 110) used to form a DRAM memory cell (eg, memory cell array 110) may be an example of a vertical transistor 116. Figure 1 The vertical transistor 112, which is not in Figure 4A) may also be formed on the substrate 404. The vertical transistor 402 may be formed in a peripheral region (eg, Figure 1 122), and vertical transistors for forming DRAM memory cells may be formed in the array region (eg, Figure 1 In some embodiments, the vertical transistors in both the peripheral region and the array region (including the vertical transistor 402 and the vertical transistor used to form the DRAM memory cell) can be formed during the same manufacturing process. In an example manufacturing process of the vertical transistor, a semiconductor body (e.g., a vertical transistor extending in a vertical direction (e.g., a Z direction) is formed on the substrate 404. Figure 1 The semiconductor body 124 of the vertical transistor may be formed by forming trenches extending in lateral directions (e.g., X and Y directions) during an etching process. In some embodiments, the semiconductor body of the vertical transistor may be doped with a dopant (e.g., a P-type dopant or an N-type dopant). The manufacturing process of the vertical transistor may further include forming a gate structure of the vertical transistor by depositing a gate dielectric layer and a conductive layer on each semiconductor body (e.g., Figure 1 gate structure 126).

[0080] In some embodiments, the isolation structure 406 is formed on the substrate 404, for example, by depositing a dielectric (such as silicon oxide) using one or more film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0081] Although storage structures (e.g. Figure 1 The storage structure 113 is formed in the array region and coupled to the vertical transistor in the array region to form a DRAM memory cell, but no storage structure needs to be formed in the peripheral region and coupled to the vertical transistor 402. In some embodiments, the vertical transistor 402 in the peripheral region can be covered with a mask during the fabrication process of the storage structure in the array region.

[0082] like Figure 4A As shown, contact structures 408 can be formed and connected to a group of vertical transistors selected from the vertical transistors 402 in the peripheral region. Each contact structure 408 can extend along the Z direction and can be connected to a terminal (e.g., source) of a corresponding vertical transistor in the group of vertical transistors. In some embodiments, the group of vertical transistors can be as described with respect to Figures 3A-3G4. The array of vertical transistors 402 depicted may be a column, a diagonal, or two adjacent columns of the array of vertical transistors 402. The contact structures 408 may be formed, for example, by an etching process followed by deposition of a conductive material. The etching process may remove portions of the isolation structures 406 to form holes or trenches, thereby exposing the terminals of each vertical transistor 402 (e.g., the source, which is the end of the semiconductor body of each vertical transistor 402). In addition, connection lines 410 may be formed (e.g., using double patterning) extending in a lateral direction (e.g., in the XY plane). Each connection line 410 may be coupled to a corresponding contact structure 408.

[0083] like Figure 4C As shown, substrate 404 can be removed. In some embodiments, substrate 404 can be thinned. Carrier wafer 412 can be bonded to surface 428 of isolation structure 406. The bonded carrier wafer 412 and isolation structure 406 (including vertical transistors 402, contact structures 408, and connecting wires 410 in isolation structure 406) can be flipped upside down. Terminal wires 414 (e.g., Figures 3B-3H Each terminal line 414 is connected to a row of vertical transistors of the array of vertical transistors 402. Contact structures 416 and 418 may be formed and connected to the connection line 410 and the gate line 420 (eg, Figures 3B-3H One or more interconnect layers 422 (e.g., Figure 1 An interconnect layer 154 (e.g., an interconnect layer 154) is formed on top of the surface 430 of the isolation structure 406. A bonding layer 424 may be formed on top of the interconnect layer 422. The bonding layer 424 may include bonding contacts 426 and a dielectric that electrically isolates the bonding contacts 426. The interconnect layer 422 may be used, for example, to route electrical signals between the contact structures 416 and 418 and the bonding contacts 426. In some embodiments, as described with respect to FIG. Figure 4E As described in further detail, the interconnect layer 422 may be used to route electrical signals for lead-out to pads.

[0084] like Figure 4D As shown, the semiconductor structure 438 is stacked on the bonding layer 424. The semiconductor structure 438 may be Figure 1 The semiconductor structure 438 includes a substrate 440, a transistor 436 (eg, Figure 1432 ). The bonding layer 432 may include a bonding contact 434 and a dielectric electrically isolating the bonding contact 434 . A hybrid bonding technique may be used to form a bond between the bonding layer 432 and the bonding layer 424 , and may simultaneously achieve metal-to-metal bonding (bonding contacts 426 and 434 ) and dielectric-to-dielectric bonding (dielectric in each of the bonding layers 424 and 432 ). The transistor 436 and some selected vertical transistors 402 may be coupled via the bonding contacts 426 and 434 and form one or more OTP memory cell arrays (e.g., Figure 1 Each transistor 436 and the corresponding vertical transistor 402 can form an OTP memory cell in one or more OTP memory cell arrays. In some embodiments, the transistor 436 can be an access transistor of the OTP memory cell, and the corresponding vertical transistor 402 can be an antifuse structure of the OTP memory cell (e.g., as described with respect to FIG. Figures 3B-3F In some other embodiments, transistor 436 may be an antifuse structure of an OTP memory cell, and the corresponding vertical transistor 402 may be an access transistor of the OTP memory cell (e.g., as described with respect to Figures 3G-3H described).

[0085] like Figure 4E As shown, the carrier wafer 412 can be removed or debonded. A semiconductor structure 442 including the vertical transistor 402, the isolation structure 406, the interconnect layer 422, the bonding layer 424, and the semiconductor structure 438 is formed. The semiconductor structure 442 can be turned upside down and the substrate 440 of the semiconductor structure 438 can be used as a carrier structure. The semiconductor structure 442 can be Figure 1 In some embodiments, as shown in FIG. Figure 4E As shown, the semiconductor structure 442 further includes one or more contact structures 444 (eg, Figure 1 and one or more contact pads 446 (eg, contact structure 140) proximate to surface 428 of isolation structure 406 and extending in the XY plane. Figure 1 Contact structure 444 may be coupled to contact pad 446 for pad extraction, which may provide a connection from the interior of semiconductor structure 442 (e.g., through interconnect layer 422) to external components (e.g., on surface 428 of isolation structure 406).

[0086] Figure 5 A flowchart of an example method 500 for forming a semiconductor device according to some aspects of the present disclosure is shown. The semiconductor device may be similar to or the same as Figure 1 The semiconductor device 100, Figure 2A The semiconductor device 200a and Figure 4E The semiconductor structure 442, or the semiconductor devices 100 and 200a and the semiconductor structure 442, or the structure at the intermediate manufacturing process of the semiconductor devices 100 and 200a and the semiconductor structure 442. Figures 4A-4E The method 500 may include forming Figures 4A-4E It should be understood that the operations shown in method 500 are not exhaustive and that other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in parallel. Figure 5 The execution order is different as shown.

[0087] In operation 502, a first semiconductor structure (eg, Figure 1 The first region (eg, Figure 1 A first vertical transistor (eg, Figure 1 The vertical transistor 116 or Figure 4A The first vertical transistor may include a first semiconductor body (eg, Figure 1 and a first gate structure (eg, a semiconductor body 124) in contact with at least one side of the first semiconductor body. Figure 1 The first vertical transistor may be an anti-fuse structure (eg, an anti-fuse capacitor) of the OTP memory cell.

[0088] In operation 504, a second semiconductor structure (eg, Figure 1 The semiconductor structure 102 or Figure 4D A transistor (eg, Figure 4D The transistor 436 may be an access transistor of an OTP memory cell. In some embodiments, the transistor may be a planar transistor.

[0089] At operation 506, a hybrid bonding structure (e.g., Figure 1 The bonding structure 106 or Figure 4D The first semiconductor structure is bonded to the second semiconductor structure by bonding layers 424 and 432. The first vertical transistor is bonded to the second semiconductor structure by a hybrid bonding structure (e.g., by bonding layers 424 and 432). Figure 4D The bonding contacts 426 and 434) are coupled to the transistor.

[0090] In some embodiments, a second region (eg, Figure 1The second vertical transistor (eg, Figure 1 The second vertical transistor may include a second semiconductor body and a second gate structure in contact with at least one side of the second semiconductor body. A storage structure (e.g., Figure 1 The storage structure 113 may be coupled to the second vertical transistor along a first direction (eg, Z direction). The second region may be adjacent to the first region in a second direction (eg, X direction) orthogonal to the first direction.

[0091] In some embodiments, the first vertical transistor and the second vertical transistor are formed during the same operation. For example, the operation may include forming a first semiconductor body of the first vertical transistor in a first region of the first semiconductor structure, and forming a second semiconductor body of the second vertical transistor in a second region of the first semiconductor structure. The first semiconductor body and the second semiconductor body may be formed on a first side of the first semiconductor structure. The operation may also include forming a first gate structure for the first vertical transistor and a second gate structure for the second vertical transistor.

[0092] In some embodiments, the first region of the first semiconductor structure may be covered with a mask while the storage structure is formed.

[0093] In some embodiments, the method 500 further includes removing a first portion of the first region of the first semiconductor structure from the first side to expose a first end (eg, source) of the first semiconductor body, and forming a first connecting line (eg, Figure 4C ) and a first contact structure (eg, Figure 4C The first connection line may connect the first end of the first semiconductor body and the first contact structure, and the first contact structure may be coupled to the hybrid bonding structure (eg, via Figure 4C bonding contact portion 426).

[0094] In some embodiments, the method 500 further includes removing a second portion of the first semiconductor structure from the second side to expose a second end (e.g., a drain) of the first semiconductor body, and forming a second connection line (e.g., a drain) in contact with the second end of the first semiconductor body. Figure 4C The second connection line may be floating.

[0095] In some embodiments, method 500 further includes forming a third connection and a second contact structure (eg, Figure 4C The third connection may connect the first gate structure and the second contact structure. The second contact structure may be coupled to a hybrid bonding structure (e.g., via Figure 4C bonding contact portion 426).

[0096] Figure 6 A block diagram of a system 600 having one or more semiconductor devices (e.g., memory devices) according to some aspects of the present disclosure is shown. The system 600 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 6 As shown, system 600 may include a host device 608 and a memory system 602, wherein the memory system 602 has one or more memory devices 604 and a memory controller 606. The host device 608 may include a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host device 608 may be configured to send data to or receive data from the one or more memory devices 604.

[0097] The memory device 604 may be any memory device disclosed herein, such as a memory device based on Figure 1 The semiconductor device 100, Figure 2A The semiconductor device 200a or Figure 4E 4. The memory device 604 includes a semiconductor structure 442. In some embodiments, the memory device 604 may be a DRAM device. A memory controller 606 (also referred to as a controller circuit) is coupled to the memory device 604 and the host device 608. Consistent with embodiments of the present disclosure, the memory device 604 may include a plurality of conductive interconnects passing through the cover layer, the plurality of conductive interconnects contacting the conductive pads in the conductive pad layer, and the memory controller 606 may be coupled to the memory device 604 via at least one of the plurality of conductive interconnects. The memory controller 606 is configured to control the memory device 604. For example, the memory controller 606 may be configured to operate a plurality of channel structures via word lines. The memory controller 606 may manage data stored in the memory device 604 and communicate with the host device 608.

[0098] In some embodiments, the memory controller 606 is designed / configured to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices (such as personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 606 is designed / configured to operate in high duty cycle environments, such as SSDs or embedded multi-media cards (eMMCs) and enterprise storage arrays, which are used as data storage for mobile devices (such as smartphones, tablets, laptops, etc.). The memory controller 606 can be configured to control operations of the memory device 604, such as read, erase, and program (or write) operations. The memory controller 606 can also be configured to manage various functions related to data stored or to be stored in the memory device 604, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some implementations, the memory controller 606 is also configured to process error correction code (ECC) on data read from or written to the memory device 604. The memory controller 606 may also perform any other suitable functions, such as formatting the memory device 604.

[0099] The memory controller 606 can communicate with an external device (e.g., the host device 608) according to a specific communication protocol. For example, the memory controller 606 can communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, etc.

[0100] The memory controller 606 and one or more memory devices 604 can be integrated into various types of storage devices, for example, included in the same package (such as a universal Flash storage (UFS) package or an eMMC package). That is, the memory system 602 can be implemented and packaged into different types of terminal electronic products. Figure 6 In one example shown, the memory controller 606 and the single memory device 604 may be integrated into a memory card 602. The memory card 602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.

[0101] The subject matter described in this disclosure and the implementation of the actions and operations can be implemented in digital electronic circuit systems, tangibly embodied computer software or firmware, computer hardware (including the structures disclosed in this disclosure and their structural equivalents, or in a combination of one or more of them). The implementation of the subject matter described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier, for execution by a data processing device or for controlling the operation of the data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively, or in addition, the carrier can be an artificially-generated propagating signal, for example, a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them, or a portion thereof. A computer storage medium is not a propagating signal.

[0102] It should be noted that references in this disclosure to "one embodiment," "an embodiment," "example embodiment," "some embodiments," "implementations," etc., indicate that the described embodiments may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of a person skilled in the relevant art to affect that feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0103] In general, terms can be understood, at least in part, from usage in context. For example, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in the singular, or can be used to describe a combination of features, structures, and characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" can be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Furthermore, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and to the contrary, can allow for the presence of other factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0104] It should be readily understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest possible manner, such that “on” not only means “directly on” something, but also includes the meaning of being “on” something with intervening features or layers therebetween. Furthermore, “over” or “over” not only means being “over” or “above” something, but also includes the meaning of being “over” or “above” something with no intervening features or layers therebetween (i.e., directly on something).

[0105] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or process steps in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0106] As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of a substrate is typically where semiconductor devices are formed, and therefore, unless otherwise specified, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite the top surface, and therefore, the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0107] As used herein, the term "layer" refers to a material portion comprising an area having a thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. A layer may extend over the entire underlying or overlying structure, or may have a range that is smaller than the range of the underlying or overlying structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure, the thickness of which is smaller than the thickness of the continuous structure. For example, a layer may be located between or between any set of horizontal planes between the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above, and / or below. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and a contact layer (wherein contact portions, interconnect lines, and / or vertical interconnect paths (VIAs) are formed) and one or more dielectric layers.

[0108] As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter of a component or process step that is set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. As used herein, a range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" refers to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" may indicate a value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0109] In the present disclosure, the terms “horizontal / horizontally / lateral / laterally” refer to fingers nominally parallel to a lateral surface of a substrate, and the terms “vertical” or “vertically” refer to fingers nominally orthogonal to a lateral surface of a substrate.

[0110] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate.

[0111] The present disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, the formation of a first feature above or on a second feature may include embodiments in which the first feature and the second feature may be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature is not in direct contact with the first feature. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not, in itself, dictate the relationship between the various embodiments and / or configurations discussed.

[0112] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0113] Although this disclosure contains many specific implementation details, these should not be interpreted as limitations on the scope of what is claimed, as defined by the claims themselves, but rather as descriptions of features that may be specific to a particular implementation of a particular invention. Certain features described in this disclosure in the context of separate implementations may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments, either individually or in any suitable subcombination. Furthermore, although features may be described above as functioning in certain combinations, and even initially claimed as such, in some cases one or more features from a claimed combination may be deleted from that combination, and the claim may be directed to a subcombination or variant of a subcombination.

[0114] Similarly, although operations are described in the drawings and recited in the claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in the sequential order shown, or that all illustrated operations be performed, in order to achieve the desired results. In certain circumstances, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated into a single software product or packaged into multiple software products.

[0115] Particular embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the particular order or sequential sequence shown to achieve the desired results. In certain circumstances, multitasking and parallel processing may be advantageous.

[0116] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: a first array of memory cells, the first array of memory cells comprising at least a first memory cell, wherein the first memory cell comprises a first vertical transistor and a storage structure coupled to the first vertical transistor in a first direction, and wherein the first array of memory cells is in a first region of a first semiconductor structure of the semiconductor device; and a second array of memory cells, the second array of memory cells comprising at least a second memory cell, wherein the second memory cell comprises a second vertical transistor in a second region of the first semiconductor structure, and wherein the second region is adjacent to the first region in a second direction orthogonal to the first direction.

2. The semiconductor device according to claim 1, wherein The second memory cell is a one-time programmable (OTP) memory cell and further includes an access transistor coupled to the second vertical transistor, and wherein the access transistor is in a second semiconductor structure of the semiconductor device.

3. The semiconductor device according to claim 1, wherein The second memory cell is a one-time programmable (OTP) memory cell, the second vertical transistor is an access transistor of the OTP memory cell, the OTP memory cell further includes an anti-fuse capacitor coupled to the second vertical transistor, and the anti-fuse capacitor is in the second semiconductor structure of the semiconductor device.

4. The semiconductor device according to claim 1 or claim 2, wherein: A source of the access transistor is coupled to a source of the second vertical transistor.

5. The semiconductor device according to claim 1 or claim 2, wherein: the second array of memory cells comprising a first set of vertical transistors coupled to a first programming line via a gate of each vertical transistor in the first set of vertical transistors; The first set of vertical transistors includes the second vertical transistor; and The first group of vertical transistors is included in a first array of vertical transistors in the second region of the first semiconductor structure.

6. The semiconductor device according to claim 5, wherein: each vertical transistor in the first set of vertical transistors is coupled to a corresponding access transistor in the second semiconductor structure through a first terminal of the vertical transistor; and The second terminal of the vertical transistor is floating.

7. The semiconductor device according to claim 5, wherein: The second array of memory cells further includes a second set of vertical transistors coupled to a second programming line via a gate of each vertical transistor in the second set of vertical transistors; and The second group of vertical transistors is included in a second array of vertical transistors in the second region of the first semiconductor structure.

8. The semiconductor device according to any one of claims 1 to 5, wherein: The first group of vertical transistors are included in the same row or the same column of the first array of vertical transistors; and The gate of each vertical transistor of the first group of vertical transistors is part of a same connection line of the first array of vertical transistors.

9. The semiconductor device according to claim 8, wherein: A terminal of each vertical transistor of the first set of vertical transistors is directly connected to a contact structure extending along a first direction; and The contact structure is further connected to a conductive line comprising metal, the conductive line extending in a direction orthogonal to the first direction.

10. The semiconductor device according to claim 8, wherein: a terminal of each vertical transistor of the first set of vertical transistors is directly connected to a conductive line extending in a direction orthogonal to the first direction; and The conductive wire includes metal.

11. A semiconductor device, comprising: An array of one-time programmable (OTP) memory cells, the array of one-time programmable (OTP) memory cells comprising at least an OTP memory cell, wherein the OTP memory cell comprises a vertical transistor in a first semiconductor structure of the semiconductor device and an access transistor in a second semiconductor structure of the semiconductor device, wherein the first semiconductor structure and the second semiconductor structure are bonded by a hybrid bonding structure, and wherein the access transistor is coupled to the vertical transistor.

12. The semiconductor device according to claim 11, wherein: The semiconductor device further includes an array of dynamic random access memory (DRAM) cells, the array of dynamic random access memory cells including at least a DRAM cell, wherein the DRAM cell includes a first vertical transistor and a storage structure coupled to the first vertical transistor in a first direction, and wherein the array of DRAM cells is in a first region of a first semiconductor structure of the semiconductor device; The vertical transistor of the OTP memory cell is a second vertical transistor in the second region of the first semiconductor structure; and The second region is adjacent to the first region in a second direction orthogonal to the first direction.

13. The semiconductor device according to claim 11 or claim 12, wherein: A source of the access transistor is coupled to a source of the second vertical transistor.

14. The semiconductor device according to claim 11 or claim 12, wherein: The array of OTP memory cells includes a first set of vertical transistors coupled to a first programming line via a gate of each vertical transistor in the first set of vertical transistors; The first set of vertical transistors includes the second vertical transistor; and The first group of vertical transistors is included in a first array of vertical transistors in the second region of the first semiconductor structure.

15. The semiconductor device according to any one of claims 11 to 14, wherein: each vertical transistor in the first set of vertical transistors is coupled to a corresponding access transistor in the second semiconductor structure through a first terminal of the vertical transistor; and The second terminal of the vertical transistor is floating.

16. The semiconductor device according to claim 14, wherein: The array of OTP memory cells further includes a second set of vertical transistors coupled to a second programming line via a gate of each vertical transistor in the second set of vertical transistors; and The second group of vertical transistors is included in a second array of vertical transistors in the second region of the first semiconductor structure.

17. The semiconductor device according to claim 14, wherein: The first group of vertical transistors are included in the same row or the same column of the first array of vertical transistors; and The gate of each vertical transistor of the first group of vertical transistors is part of a same connection line of the first array of vertical transistors.

18. A method for forming a semiconductor device, the method comprising: forming a first vertical transistor in a first region of a first semiconductor structure of the semiconductor device, wherein the first vertical transistor includes a first semiconductor body and a first gate structure in contact with at least one side of the first semiconductor body, and the first vertical transistor is an anti-fuse capacitor of a one-time programmable (OTP) memory cell; forming a transistor in the second semiconductor structure of the semiconductor device; and The first semiconductor structure and the second semiconductor structure are bonded by a hybrid bonding structure, wherein the first vertical transistor is coupled to the transistor by the hybrid bonding structure.

19. The method according to claim 18, further comprising: forming a second vertical transistor in a second region of the first semiconductor structure, wherein the second vertical transistor includes a second semiconductor body and a second gate structure contacting at least one side of the second semiconductor body; and A storage structure is formed, the storage structure coupled to the second vertical transistor along a first direction, wherein the second region is adjacent to the first region in a second direction orthogonal to the first direction.

20. The method according to claim 19, wherein The first vertical transistor and the second vertical transistor are formed during a same operation, the same operation comprising: forming the first semiconductor body of the first vertical transistor in the first region of the first semiconductor structure, and forming the second semiconductor body of the second vertical transistor in the second region of the first semiconductor structure, wherein the first semiconductor body and the second semiconductor body are formed on a first side of the first semiconductor structure; and The first gate structure of the first vertical transistor and the second gate structure of the second vertical transistor are formed.

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