Chip testing system and method

Abstract

The invention provides a chip testing system and method. The chip test system comprises a memory chip, a test device and a test interface. The memory chip is provided with a power supply connecting pad and a driving connecting pad coupled to the power supply connecting pad. The testing device is used for providing a testing signal. The test interface is used for providing a plurality of signal transmission paths. The testing device transmits a testing signal to the power supply connecting pad of the memory chip through the testing interface, obtains a monitoring voltage generated by the driving connecting pad, and adjusts a testing voltage value of the testing signal according to the monitoring voltage.

Description

Technical Field

[0001] The present invention relates to a wafer test, and in particular to a chip testing system and method capable of reducing the influence of contact impedance. Background Art

[0002] With the continuous advancement of process technology and the development of new applications, new memory products are required to have lower voltages, higher speeds, and higher operating currents. It is foreseeable that there will be more and more memory products with smaller signal margins in the future. This makes memory testing, especially known good die (KGD) testing through wafer-level probe testing, increasingly critical, and testing costs are also increasing.

[0003] For memory testing, one of the key factors affecting test accuracy is the voltage loss (also referred to herein as voltage drop) caused by the contact impedance between the test fixture and the device under test (DUT). In addition, in actual applications, the contact impedance between the test fixture and the DUT may cause variations in voltage drop due to factors such as the test environment and the contact conditions between the probe and the pad (such as the contact area and the cumulative number of contacts), which may lead to overkilling and a decrease in the yield of the memory. Especially on the power pad, since the transmitted current is large, the voltage drop effect generated by the contact impedance between the test fixture and the DUT is also greater. In order to improve the contact impedance problem between the test fixture and the DUT, the prior art focuses on the fact that when the cumulative number of contacts between the probe and the pad increases, the contact impedance between the test fixture and the DUT also increases, and thus it is proposed to increase the cleaning frequency of the probe. However, if the cleaning frequency of the probe is simply increased, the service life of the probe will be reduced, and the test time will be increased, thereby significantly increasing the test cost. Therefore, how to avoid the reduction of test accuracy due to voltage drop while maintaining test quality and productivity and reducing test costs has become an increasingly important issue. Summary of the Invention

[0004] The present invention provides a chip testing system and method, which can compensate for the voltage drop caused by contact impedance and increase the tolerance to contact impedance.

[0005] The chip testing system of the present invention includes a memory chip, a test device, and a test interface. The memory chip has a power pad and a drive pad coupled to the power pad. The test device is configured to provide a test signal. The test interface is coupled between the memory chip and the test device to provide multiple signal transmission paths. The test device transmits a test signal to the power pad of the memory chip via the test interface, obtains a monitoring voltage generated by the drive pad, and adjusts the test voltage value of the test signal based on the monitoring voltage.

[0006] The chip testing method of the present invention is applicable to the aforementioned memory chip. The chip testing method includes the following steps: providing a test interface to provide multiple signal transmission paths; transmitting a test signal to the power pads of the memory chip via the test interface, obtaining a monitoring voltage generated by the driving pads, and adjusting the test voltage value of the test signal based on the monitoring voltage.

[0007] Based on the above, the chip testing system of the present invention can monitor the voltage of the test signal transmitted to the power pads via the driver pads on the memory chip and adjust the test voltage accordingly. This appropriately compensates for the voltage drop caused by contact impedance, preventing the degradation of test accuracy caused by this voltage drop while maintaining test quality and productivity and reducing testing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram of a chip testing system according to an embodiment of the present invention is shown;

[0009] Figure 2 A schematic diagram showing a chip testing system according to an embodiment of the present invention;

[0010] Figure 3 A schematic diagram showing a chip testing system according to another embodiment of the present invention;

[0011] Figure 4 An example of a truth table showing an embodiment of the present invention;

[0012] Figure 5 A flowchart showing the steps of a chip testing method according to an embodiment of the present invention;

[0013] Figure 6 A flowchart showing the steps of a chip testing method according to another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0014] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0015] In order to make the content of the present invention more clearly understood, the following embodiments are given as examples of how the present invention can be implemented. In addition, components / members / steps with the same reference numerals in the drawings and embodiments may represent the same or similar components.

[0016] Please refer to Figure 1The chip testing system 100 includes a memory chip 110, a testing device 120, and a test interface 130. Memory chip 110 is, for example, a semiconductor chip selected from a semiconductor wafer to be tested for testing. The semiconductor wafer may be made of silicon or other semiconductor materials. Memory chip 110 may include logic circuits, memory circuits, analog component circuits, the like, or a combination thereof, but the present invention is not limited thereto. For example, memory chip 110 may be a DRAM chip.

[0017] like Figure 1 As shown, memory chip 110 has a power pad PVDD and a driving pad PDR coupled to the power pad PVDD. The power pad PVDD and the driving pad PDR are made of a metal material, such as aluminum, an aluminum alloy, or a combination thereof. The power pad PVDD and the driving pad PDR can be interconnected with the metal circuit layer within the memory chip 110. The power pad PVDD is, for example, a pad for receiving a power supply voltage, and the driving pad PDR is, for example, a pad for transmitting a driving signal or an input / output signal. In practical applications, a pad closer to the power pad PVDD can be selected as the driving pad PDR.

[0018] The test device 120 can be used to provide a test signal Stest. The test interface 130 includes, for example, a test fixture such as a probe card, which is coupled between the memory chip 110 and the test device 120 to provide multiple signal transmission paths, such as a first signal transmission path Path1 and a second signal transmission path Path2. The first signal transmission path Path1 has a first contact impedance Cres1, and the second signal transmission path Path2 has a second contact impedance Cres2. In actual applications, the test interface 130 can contact the corresponding pins to the power pad PVDD and the drive pad PDR to form the first signal transmission path Path1 and the second signal transmission path Path2.

[0019] In this embodiment, the test device 120 can transmit the test signal Stest to the power pad PVDD of the memory chip 110 through the test interface 130, and obtain the monitoring voltage Vm generated by the driving pad PDR, and adjust the test voltage value Vp of the test signal Stest according to the monitoring voltage Vm. The test voltage value Vp refers to the voltage value of the test signal Stest on the test device 120 side, which can be regarded as the voltage value of the test signal Stest before any loss (voltage drop) is suffered. Specifically, in a specific test mode, the test device 120 can set the initial test voltage value Vp of the test signal Stest to be the same as the target voltage value corresponding to the current test mode. The test device 120 can transmit the test signal Stest to the power pad PVDD via the first signal transmission path Path1. The test signal Stest transmitted to the power pad PVDD will generate a voltage drop Vcres according to the first contact impedance Cres1. Therefore, the voltage received on the power pad PVDD is the test voltage value Vp minus the voltage drop Vcres. Since the driving pad PDR and the power pad PVDD have the same potential, the monitoring voltage Vm generated by the driving pad PDR is equal to the test voltage Vp minus the voltage drop Vcres. In this embodiment, the target voltage is, for example, the default voltage value of the test signal Stest to be transmitted to the power pad PVDD for a specific test mode.

[0020] Furthermore, the testing device 120 can obtain a monitoring voltage Vm via the second signal transmission path Path2. Since the monitoring current Im on the second signal transmission path Path2 is substantially zero (almost close to zero), no voltage drop occurs despite the presence of the second contact impedance Cres2 on the second signal transmission path Path2. Therefore, the testing device 120 can accurately obtain the monitoring voltage Vm. When the monitoring voltage Vm is less than the target voltage value, the testing device 120 can increase the test voltage value Vp of the test signal Stest to compensate for the voltage drop Vcres caused by the first contact impedance Cres1, so that the voltage value of the test signal Stest transmitted to the power pad PVDD is equal to or close to the target voltage value. In some embodiments, the testing device 120 can repeatedly increase the test voltage value Vp of the test signal Stest until the monitoring voltage Vm is equal to or close to the target voltage value.

[0021] It should be noted that in this embodiment, the test modes are pre-planned for various test items performed by the test device 120 on the memory chip 110. Due to the different test items, the target voltage value in each test mode is also different. In addition, the memory chip 110 may also need to enter different test states depending on the test mode.

[0022] The following is another example to illustrate the chip testing system of the present invention. Figure 2 The chip testing system 200 includes a memory chip 210, a testing device 220, and a testing interface 230. Figure 2 As shown, memory chip 210 includes a power pad PVDD, a driving pad PDR coupled to the power pad PVDD, and a ground pad PGND. The ground pad PGND is, for example, a pad coupled to a ground potential and is made of a metal material, such as aluminum, an aluminum alloy, or a combination thereof. The power pad PVDD, the driving pad PDR, and the ground pad PGND can interconnect with metal circuit layers within the memory chip 210.

[0023] The test device 220 can be used to provide a test signal Stest. The test interface 230 is coupled between the memory chip 210 and the test device 220. In addition to providing a first signal transmission path Path1 and a second signal transmission path Path2, it also provides a third signal transmission path Path3. The third signal transmission path Path3 is coupled between the ground pad PGND and the test device 220 and is coupled to the ground potential. The first signal transmission path Path1 has a first contact impedance Cres1, the second signal transmission path Path2 has a second contact impedance Cres2, and the third signal transmission path Path3 has a third contact impedance Cres3.

[0024] exist Figure 2 In the example, the first signal transmission path Path1 also has a transmission impedance Tres. The transmission impedance Tres is equivalent to the loss caused by the test signal Stest when it is transmitted through the test interface 230. Furthermore, the memory chip 210 includes an internal load 212. The internal load 212 is coupled between the power pad PVDD and the ground potential. The internal load 212 can be, for example, any power-consuming electronic component or circuit device within the memory chip 210, but the present invention is not limited thereto.

[0025] In this embodiment, the testing device 220 includes a programmable power supply (PPS) 222. The PPS 222 is coupled to a first signal transmission path Path1 and a second signal transmission path Path2 and can be used to generate a test signal Stest. In a specific test mode, the PPS 222 can set the initial test voltage value Vp of the test signal Stest to be the same as the target voltage value corresponding to the current test mode. The PPS 222 can transmit the test signal Stest to the power pad PVDD of the memory chip 210 via the first signal transmission path Path1. The test signal Stest transmitted to the power pad PVDD generates voltage drops Vcres and Vt according to the first contact resistance Cres1 and the transmission resistance Tres, respectively. Therefore, the voltage received on the power pad PVDD is the test voltage value Vp minus the voltage drops Vcres and Vt, and the monitoring voltage Vm generated by the driving pad PDR is also equal to the test voltage value Vp minus the voltage drops Vcres and Vt.

[0026] Furthermore, the programmable power supply 222 can receive the monitoring voltage Vm via the second signal transmission path Path2. Since the monitoring current Im on the second signal transmission path Path2 is substantially zero (almost close to zero), no voltage drop occurs despite the second contact resistance Cres2 on the second signal transmission path Path2. Therefore, the testing device 220 can accurately obtain the monitoring voltage Vm.

[0027] The programmable power supply 222 can compare the monitoring voltage Vm with a target voltage. When the monitoring voltage Vm is lower than the target voltage, the programmable power supply 222 can increase the test voltage Vp of the test signal Stest to compensate for the voltage drops Vcres and Vt caused by the first contact resistance Cres1 and the transmission resistance Tres, thereby ensuring that the voltage of the test signal Stest transmitted to the power pad PVDD is equal to or close to the target voltage. In some embodiments, the programmable power supply 222 can repeatedly increase the test voltage Vp of the test signal Stest until the monitoring voltage Vm is equal to or close to the target voltage.

[0028] With the above structure, when the test device 220 tests the memory chip 210, the loss (voltage drop) suffered by the test signal Stest can be appropriately compensated through the feedback loop formed by the second signal transmission path Path2, thereby ensuring that the voltage value of the test signal Stest transmitted to the power pad PVDD is equal to or close to the target voltage value.

[0029] The following is another example to illustrate the chip testing system of the present invention. Figure 3 The chip testing system 300 includes a memory chip 310, a testing device 320, and a testing interface 330. Figure 3 As shown, memory chip 310 has a power pad PVDD, a driving pad PDR, and a ground pad PGND. The power pad PVDD, the driving pad PDR, and the ground pad PGND can be interconnected with the metal wiring layer within memory chip 310. In addition, memory chip 310 includes a first switch element SW1. The first switch element SW1 is coupled between the power pad PVDD and the driving pad PDR.

[0030] The test device 320 can be used to provide a test signal Stest. The test interface 330 is coupled between the memory chip 310 and the test device 320, providing a first signal transmission path Path1, a second signal transmission path Path2, and a third signal transmission path Path3. The first signal transmission path Path1 has a first contact impedance Cres1 and a transmission impedance Tres, the second signal transmission path Path2 has a second contact impedance Cres2, and the third signal transmission path Path3 has a third contact impedance Cres3. Furthermore, the memory chip 310 includes an internal load 312. The internal load 312 is coupled between the power pad PVDD and the ground potential.

[0031] In this embodiment, the test device 320 includes a programmable power supply 322, a precision measurement unit 324, and a controller 326. The programmable power supply 322 is coupled to the first signal transmission path Path1. The programmable power supply 322 can be used to generate a test signal Stest and measure a test current Idd flowing through the first signal transmission path Path1. Figure 3 As shown, the test current Idd can flow to the internal load 312 via the first signal transmission path Path1. The programmable power supply 322 can also obtain the sense voltage Vs at the output end of the test interface 330 on the first signal transmission path Path1 via the fourth signal transmission path Path4.

[0032] The precision measurement unit (PMU) 324 is coupled to the second signal transmission path Path2 and can measure the monitoring voltage Vm via the second signal transmission path Path2 and regard it as equivalent to the voltage value of the test signal Stest transmitted to the power pad PVDD.

[0033] The controller 326 may be, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor, programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device, or a combination of these devices. Alternatively, the controller 326 may be a hardware circuit designed using a hardware description language or any other digital circuit design method known to those skilled in the art, and implemented using a field programmable gate array (FPGA) or complex programmable logic device (CPLD). The controller 326 is coupled to the programmable power supply 322 and the precision measurement unit 324. Furthermore, the test device 320 further includes a second switch element SW2 and a third switch element SW3. The second switch element SW2 is coupled between the precision measurement unit 324 and the second signal transmission path Path2. The third switch element SW3 is coupled between the second signal transmission path Path2 and the transmission path Dpath of other drive signals (e.g., the frequency enable signal CKE, etc.). Thus, by switching the switch elements, the monitoring voltage Vm can be measured using the existing built-in signal channels, thereby reducing chip area.

[0034] In this embodiment, the controller 326 can be used to set the test signal Stest via the programmable power supply 322 in a specific test mode, setting the initial test voltage value Vp of the test signal Stest to the same as the target voltage value corresponding to the current test mode. Furthermore, the controller 326 can control the programmable power supply 322 based on the monitoring voltage Vm, the first contact resistance Cres, and the test current Idd to adjust the test voltage value Vp of the test signal Stest.

[0035] Specifically, in the test mode, the memory chip 310 can be set to a state corresponding to the current test mode, and when the memory chip 310 begins to be tested, the controller 326 turns on the first switch component SW1 and the second switch component SW2 and turns off the third switch component SW3.

[0036] Then, the controller 326 can control the programmable power supply 322 to generate a test signal Stest having the same target voltage value as the current test mode on the first signal transmission path Path1. In addition, the programmable power supply 322 can also measure the test current Idd flowing through the first signal transmission path Path1.

[0037] The controller 326 can obtain the current monitoring voltage Vm from the precision measurement unit 324 and calculate the impedance value of the first contact impedance Cres1. Specifically, the controller 326 can obtain the current monitoring voltage Vm and test current Idd from the precision measurement unit 324, obtain the sensed voltage Vs at the output end of the test interface 330 on the first signal transmission path Path1 from the programmable power supply 322, and calculate the impedance value of the first contact impedance Cres1 by subtracting the monitoring voltage Vm from the sensed voltage Vs and dividing it by the test current Idd.

[0038] Next, the controller 326 can determine whether the difference between the monitoring voltage Vm and the target voltage is less than or equal to a voltage threshold, or whether the number of adjustments to the test voltage Vp has exceeded a threshold. Specifically, the controller 326 can first determine whether the difference between the monitoring voltage Vm and the target voltage is less than or equal to a voltage threshold. If so, this indicates that the voltage of the test signal Stest transmitted to the power pad PVDD meets the requirements of the current test mode. At this point, the controller 326 can disconnect the first and second switch elements SW1 and SW2, and connect the third switch element SW3 to stop measuring the monitoring voltage Vm and allow the test device 320 to continue testing the memory chip 310.

[0039] If not, controller 326 can determine whether the number of times the test voltage Vp has been adjusted exceeds a threshold (e.g., 5 times). If so, this indicates that the number of adjustments has exceeded the limit, and no further adjustment of the test voltage Vp is required. At this point, controller 326 can disconnect first and second switch elements SW1 and SW2 and connect third switch element SW3 to stop measuring monitoring voltage Vm. This allows test device 320 to continue or stop testing memory chip 310, depending on the situation.

[0040] If not, this indicates that the difference between the monitored voltage Vm and the target voltage is not less than or equal to the voltage threshold, and the number of adjustments to the test voltage Vp is not greater than the threshold. In this case, the controller 326 may multiply the calculated impedance value of the first contact impedance Cres1 by the measured current test current Idd to calculate an adjustment amount for adjusting the test voltage Vp. The programmable power supply 322 then increases the test voltage Vp of the test signal Stest by the calculated adjustment amount.

[0041] After the test voltage value Vp is increased by the calculated adjustment amount, the monitoring voltage Vm and the test current Idd will also change accordingly. The controller 326 can measure the current monitoring voltage Vm and the test current Idd again, and continue to judge between the monitoring voltage Vm and the target voltage value. In addition, the controller 326 can repeatedly update the adjustment amount according to the current monitoring voltage Vm and the test current Idd in the same calculation method as described above, and increase the test voltage value Vp of the test signal Stest by the updated adjustment amount until the difference between the monitoring voltage Vm and the target voltage value is less than or equal to the voltage threshold or the number of adjustments is greater than the number threshold. It should be noted that those skilled in the art can set the above-mentioned voltage threshold and number threshold according to their actual accuracy requirements.

[0042] Through this embodiment, when the test device 320 tests the memory chip 310, it can utilize the original built-in signal channel to measure the monitoring voltage Vm, and cooperate with the programmable power supply 322 and precision measurement unit 324 of the test device 320 to appropriately compensate for the loss (voltage drop) suffered by the test signal Stest, thereby reducing testing costs.

[0043] In one embodiment, the controller 326 may collect data on the test voltage value Vp, the monitoring voltage Vm, the first contact impedance Cres1, and the test current Idd during the process of adjusting the test voltage value Vp for multiple target voltage values ​​Vtarget corresponding to multiple test modes to establish a truth table. Figure 4 In truth table 400, the leftmost column lists multiple target voltage values ​​Vtarget. The data for the test voltage Vp, monitoring voltage Vm, first contact resistance Cres1, and test current Idd during the adjustment process are recorded in the order of the number of times (n) the test voltage Vp is adjusted. This allows the appropriate test voltage Vp to be found in truth table 400 when testing memory chip 310 using the target voltage Vtarget recorded in truth table 400, allowing for quick adjustment of test signal Stest.

[0044] Please refer to Figure 5 The chip testing method of this embodiment includes the following steps. A test interface is provided to provide multiple signal transmission paths (step S502). Then, a test signal is transmitted to the power pad of the memory chip through the test interface, and a monitoring voltage generated by the driving pad is obtained, and the test voltage value of the test signal is adjusted according to the monitoring voltage (step S504). Figures 1 to 3 The chip testing method of this embodiment is performed by a chip testing system, and the relevant description is not repeated here.

[0045] Please also refer to Figure 3 and Figure 6 Another embodiment of the chip testing method of the present invention is applicable to Figure 3 The chip testing system 300 is provided. The following describes the various steps of the erasing method according to the embodiment of the present invention with reference to the various components in the chip testing system 300.

[0046] In step S602, the controller 326 sets the adjustment count (n) to 1 and sets the initial test voltage value Vp of the test signal Stest to the same target voltage value corresponding to the test mode. In step S604, the memory chip is set to a state corresponding to the test mode. In step S606, the controller 326 turns on the first switch element SW1 and the second switch element SW2 and turns off the third switch element SW3.

[0047] Next, in step S608, the programmable power supply 322 measures the test current Idd flowing through the first signal transmission path Path1. In step S610, the controller 326 obtains the monitoring voltage Vm generated by the driving pad PDR via the second signal transmission path Path2 through the precision measurement unit 324. In step S612, the controller 326 determines whether the difference between the monitoring voltage Vm and the target voltage value is less than or equal to the voltage threshold. If so, the controller 326 disconnects the first switch component SW1 and the second switch component SW2 and turns on the third switch component SW3 (step S614) to continue the test. If not, the controller 326 determines whether the number of times the test voltage value Vp has been adjusted is greater than the number threshold (step S616).

[0048] If the test voltage Vp is adjusted more than the threshold, the controller 326 turns off the first switch SW1 and the second switch SW2 and turns on the third switch SW3 (step S614 ) to continue or stop the test.

[0049] If the number of times the test voltage Vp has been adjusted is not greater than the threshold, the controller 326 multiplies the resistance value of the first contact resistance Cres1 by the test current Idd to calculate an adjustment amount for adjusting the test voltage Vp (step S618). Next, in step S620, the programmable power supply 322 increases the test voltage Vp of the test signal Stest by the calculated adjustment amount and increments the number of adjustments (n=n+1).

[0050] Then, the controller 326 returns to step S608 to repeatedly update the adjustment amount according to the current monitoring voltage Vm and the test current Idd in the same calculation method as above and increase the test voltage value Vp of the test signal Stest by the updated adjustment amount until the difference between the monitoring voltage Vm and the target voltage value is less than or equal to the voltage threshold or the number of adjustments is greater than the number threshold. For the implementation details of the above steps S602, S604, S606, S608, S610, S612, S614, S616, S618, and S620, please refer to Figure 3 The relevant description will not be repeated here.

[0051] In addition, the chip testing system and method according to the present invention can be applied to low-power memory, vertical stack chips or KGD, and can be applied to applications in the fields of artificial intelligence, electric vehicles, mobile devices, etc., but the present invention is not limited thereto.

[0052] In summary, when testing a memory chip, the chip testing system of the present invention can appropriately compensate for the loss (voltage drop) suffered by the test signal due to contact impedance through a feedback loop formed by the drive pads on the memory chip to ensure that the voltage value of the test signal transmitted to the power pad is equal to or close to the target voltage value. In this way, it is possible to avoid a decrease in test accuracy due to voltage drop, increase the tolerance for contact impedance, and at the same time maintain test quality and productivity, and reduce test costs. Therefore, the present invention provides a green semiconductor technology.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip testing system, characterized in that: include: A memory chip having a power pad and a driving pad coupled to the power pad; A test device for providing a test signal; a test interface coupled between the memory chip and the test device to provide a plurality of signal transmission paths; The test device transmits the test signal to the power pad of the memory chip through the test interface, obtains the monitoring voltage generated by the driving pad, and adjusts the test voltage value of the test signal according to the monitoring voltage.

2. The chip testing system according to claim 1, characterized in that: The plurality of signal transmission paths include a first signal transmission path having a first contact impedance, The testing device transmits the testing signal to the power pad via the first signal transmission path, wherein the testing signal transmitted to the power pad generates a voltage drop according to the first contact impedance.

3. The chip testing system according to claim 2, characterized in that: The plurality of signal transmission paths further include a second signal transmission path having a second contact impedance, The testing device obtains the monitoring voltage generated by the driving pad via the second signal transmission path, wherein the monitoring current on the second signal transmission path is substantially zero.

4. The chip testing system according to claim 3, characterized in that: The testing device comprises: The programmable power supply is coupled to the first signal transmission path and the second signal transmission path, and is used for generating the test signal and receiving the monitoring voltage.

5. The chip testing system according to claim 4, characterized in that: The programmable power supply compares the monitoring voltage with a target voltage value. When the monitoring voltage is lower than the target voltage value, the programmable power supply increases the test voltage value of the test signal.

6. The chip testing system according to claim 5, characterized in that: The initial test voltage value of the test signal is set to be the same as the target voltage value.

7. The chip testing system according to claim 3, characterized in that: The testing device comprises: a programmable power supply coupled to the first signal transmission path, configured to generate the test signal and measure a test current flowing through the first signal transmission path; a precision measurement unit, coupled to the second signal transmission path, for measuring the monitoring voltage; and A controller is coupled to the programmable power supply and the precision measurement unit, and is used to set the test signal through the programmable power supply in a test mode, set the initial test voltage value of the test signal to be the same as the target voltage value corresponding to the test mode, and control the programmable power supply according to the monitoring voltage, the first contact impedance and the test current to adjust the test voltage value of the test signal.

8. The chip testing system according to claim 7, characterized in that: The memory chip includes a first switch component, which is coupled between the power pad and the drive pad. The testing device further includes a second switch component and a third switch component, the second switch component is coupled between the precision measurement unit and the second signal transmission path, and the third switch component is coupled between the second signal transmission path and the drive signal transmission path. When the memory chip starts to be tested, the controller turns on the first switch component and the second switch component and turns off the third switch component.

9. The chip testing system according to claim 7, characterized in that: The controller obtains a sensed voltage at the output end of the test interface on the first signal transmission path from the programmable power supply, and calculates an impedance value of the first contact impedance by subtracting the monitoring voltage from the sensed voltage and dividing the difference by the test current.

10. The chip testing system according to claim 9, characterized in that: The controller determines whether the difference between the monitoring voltage and the target voltage value is less than or equal to a voltage threshold or whether the number of times the test voltage value is adjusted is greater than a number threshold. If not, the controller multiplies the impedance value by the test current to calculate an adjustment amount for adjusting the test voltage value, and increases the test voltage value of the test signal by the adjustment amount through the programmable power supply. The controller repeatedly updates the adjustment amount according to the current monitoring voltage and the test current and increases the test voltage value of the test signal with the updated adjustment amount until the difference between the monitoring voltage and the target voltage value is less than or equal to the voltage threshold or the number of adjustments is greater than the number threshold.

11. The chip testing system according to claim 3, characterized in that: The memory chip includes an internal load coupled between the power pad and a ground potential.

12. The chip testing system according to claim 3, characterized in that: The memory chip further has a ground pad. The plurality of signal transmission paths further include a third signal transmission path having a third contact impedance. The third signal transmission path is coupled between the ground pad and the testing device and coupled to a ground potential.

13. The chip testing system according to claim 7, wherein: The controller collects data of the test voltage value, the monitoring voltage, the first contact impedance, and the test current during the process of adjusting the test voltage value for the multiple target voltage values ​​corresponding to the multiple test modes to establish a truth table.

14. A chip testing method, applicable to a memory chip having a power pad and a driving pad coupled to the power pad, the chip testing method comprising the following steps: Providing a test interface to provide multiple signal transmission paths; and A test signal is transmitted to the power pad of the memory chip through the test interface, and a monitoring voltage generated by the driving pad is obtained, and a test voltage value of the test signal is adjusted according to the monitoring voltage.

15. The chip testing method according to claim 14, characterized in that: The plurality of signal transmission paths include a first signal transmission path having a first contact impedance, The step of transmitting the test signal to the power pad of the memory chip through the test interface includes: The test signal is transmitted to the power pad via the first signal transmission path, wherein the test signal transmitted to the power pad generates a voltage drop according to the first contact impedance.

16. The chip testing method according to claim 15, characterized in that: The plurality of signal transmission paths further include a second signal transmission path having a second contact impedance, The step of obtaining the monitoring voltage generated by the driving pad includes: The monitoring voltage generated by the driving pad is obtained via the second signal transmission path, wherein a monitoring current on the second signal transmission path is substantially zero.

17. The chip testing method according to claim 16, characterized in that: The step of adjusting the test voltage value of the test signal according to the monitoring voltage includes: The monitoring voltage is compared with a target voltage value, and when the monitoring voltage is less than the target voltage value, the test voltage value of the test signal is increased.

18. The chip testing method according to claim 16, wherein: Also includes: Setting the test signal in a test mode, and setting the initial test voltage value of the test signal to be the same as the target voltage value corresponding to the test mode; as well as measuring a test current flowing through the first signal transmission path, The step of adjusting the test voltage value of the test signal according to the monitoring voltage includes: The test voltage value of the test signal is adjusted according to the monitoring voltage, the first contact impedance, and the test current.

19. The chip testing method according to claim 18, characterized in that: The step of adjusting the test voltage value of the test signal according to the monitoring voltage, the first contact impedance and the test current includes: obtaining a sensed voltage at an output end of the test interface on the first signal transmission path; and A difference obtained by subtracting the monitoring voltage from the sensing voltage is divided by the test current to calculate an impedance value of the first contact impedance.

20. The chip testing method according to claim 19, wherein: The step of adjusting the test voltage value of the test signal according to the monitoring voltage, the first contact impedance and the test current further includes: Determine whether the difference between the monitoring voltage and the target voltage value is less than or equal to a voltage threshold or whether the number of times the test voltage value is adjusted is greater than a number threshold; If not, multiplying the impedance value by the test current to calculate an adjustment amount for adjusting the test voltage value, and increasing the test voltage value of the test signal by the adjustment amount; and The adjustment amount is repeatedly updated according to the current monitoring voltage and the test current, and the test voltage value of the test signal is increased by the updated adjustment amount until the difference between the monitoring voltage and the target voltage value is less than or equal to the voltage threshold or the number of adjustments is greater than the number threshold.

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