Power amplifier

Abstract

The application provides a power amplifier, comprising: a power divider configured to obtain an input signal and divide the input signal into multiple signals; a first-stage amplifier connected to the power divider, the first-stage amplifier comprising a plurality of first-stage branches, each of the first-stage branches comprising at least one sub-amplifier; and a second-stage amplifier connected to the first-stage amplifier, the second-stage amplifier comprising a plurality of second-stage branches, each of the second-stage branches comprising at least one sub-amplifier; wherein the number of the first-stage branches is greater than the number of the second-stage branches. By forming a branch parallel structure in the first-stage amplifier, the parallel branches are in an always-on state and an always-off state respectively, thereby reducing the static power consumption of the first-stage amplifier; by forming a Doherty architecture in the first-stage amplifier, the efficiency of the first-stage amplifier is improved, thereby improving the overall efficiency of the power amplifier.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a power amplifier. Background Technology

[0002] A wireless base station, as a radio frequency signal transceiver, amplifies the input signal through a power amplifier (PA), and then transmits the amplified input signal through a transmitter. The power amplifier is the most power-consuming component in a wireless base station, and its efficiency directly affects the overall power consumption of the base station.

[0003] A power amplifier consists of a driver stage amplifier and a final stage driver. Since the efficiency of the driver stage amplifier is only around 10%, it drags down the overall efficiency of the base station under high load. Therefore, it is necessary to improve the efficiency of the driver stage amplifier to improve the overall efficiency of the power amplifier. Summary of the Invention

[0004] Therefore, it is necessary to provide a power amplifier to address the problems mentioned in the background art, so as to improve the efficiency of the driver stage amplifier.

[0005] To achieve the above and other related objectives, one aspect of this application provides a power amplifier, comprising:

[0006] A power divider is used to acquire an input signal and split it into multiple signals.

[0007] The first-stage amplifier is connected to the power divider. The first-stage amplifier includes multiple first-stage branches, and each first-stage branch includes at least one sub-amplifier.

[0008] The second-stage amplifier is connected to the first-stage amplifier. The second-stage amplifier includes multiple second-stage branches, and each second-stage branch includes at least one sub-amplifier.

[0009] The number of first-level branches is greater than the number of second-level branches.

[0010] In one embodiment, at least one first-stage branch is connected in series with at least one second-stage branch to form a series path. The number of series paths is equal to the number of second-stage branches, and the number of series paths is less than the number of first-stage branches. The first-stage amplifier includes at least one first-stage parallel unit, which is formed by connecting at least two first-stage branches in parallel.

[0011] In one embodiment, multiple sub-amplifiers in the first-stage amplifier are packaged as a whole, and the number of pins of the first-stage amplifier is set based on the number of first-stage branches or the number of series paths; multiple sub-amplifiers in the second-stage amplifier are packaged as a whole, and the number of pins of the second-stage amplifier is set based on the number of second-stage branches or the number of series paths.

[0012] In one embodiment, the pins include an input pin and an output pin, wherein the input pin is connected to the gate of the sub-amplifier, the output pin is connected to the drain of the sub-amplifier, and the source of the sub-amplifier is connected to a zero potential point.

[0013] In one embodiment, one of the first-stage parallel units is used as the first-stage main circuit, and one of the second-stage branches is used as the second-stage main circuit. The first-stage main circuit and the second-stage main circuit are connected in series. The first-stage main circuit includes a first-stage main amplifier and at least one first-stage main auxiliary amplifier, and the second-stage main circuit includes a second-stage main amplifier.

[0014] In one embodiment, one of the first-level branches is used as a first-level auxiliary circuit, and one of the second-level branches is used as a second-level auxiliary circuit. The first-level auxiliary circuit and the second-level auxiliary circuit are connected in series. The first-level auxiliary circuit includes a first-level auxiliary circuit amplifier, and the second-level auxiliary circuit includes a second-level auxiliary circuit amplifier.

[0015] In one embodiment, the first-stage main amplifier is set to Class AB bias, the first-stage main auxiliary amplifier and the first-stage auxiliary amplifier are both set to Class C bias, the second-stage main amplifier is set to Class AB bias, and the second-stage auxiliary amplifier is set to Class C bias.

[0016] In one embodiment, the ratio of the sum of the output power of the first-stage main amplifier and the output power of the first-stage main auxiliary amplifier to the output power of the second-stage main amplifier ranges from 1:3 to 1:8, the ratio of the output power of the first-stage main amplifier to the output power of the first-stage main auxiliary amplifier ranges from 1:1 to 1:2, the ratio of the output power of the first-stage auxiliary amplifier to the output power of the second-stage auxiliary amplifier ranges from 1:3 to 1:6, and the ratio of the output power of the second-stage main amplifier to the output power of the second-stage auxiliary amplifier ranges from 1:1 to 1:2.

[0017] In one embodiment, a transmission line is provided on the first-stage main circuit so that the first-stage main amplifier and the first-stage main auxiliary amplifier form a Doherty architecture; a transmission line is provided between the second-stage amplifier and the radio frequency signal output interface so that the second-stage main amplifier and the second-stage auxiliary amplifier form a Doherty architecture.

[0018] In one embodiment, the first-stage amplifier includes a first-stage main path and two first-stage auxiliary paths, and the second-stage amplifier includes a second-stage main path and two second-stage auxiliary paths, wherein the first-stage main path includes two first-stage branches, the second-stage main path branch includes one second-stage branch, each first-stage auxiliary path includes one first-stage branch, and each second-stage auxiliary path includes one second-stage branch.

[0019] The power amplifier provided by the present invention includes a first-stage amplifier and a second-stage amplifier connected together. By making the number of branches in the first-stage amplifier greater than the number of branches in the second-stage amplifier, a branch parallel structure is formed in the first-stage amplifier. The parallel branches are respectively in normally open and normally closed states, which reduces the static power consumption of the first-stage amplifier. By forming a Doherty architecture in the first-stage amplifier, the efficiency of the first-stage amplifier is improved, thereby improving the overall efficiency of the power amplifier. Attached Figure Description

[0020] To better describe and illustrate embodiments and / or examples of the applications disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, or the best mode of conduct of these applications as currently understood.

[0021] Figure 1 This is a schematic diagram of the structure of a power amplifier provided in the prior art;

[0022] Figure 2 This is a schematic diagram of the structure and packaging method of a power amplifier provided in one embodiment;

[0023] Figure 3 This is a schematic diagram of the structure of a power amplifier provided in one embodiment and another packaging method;

[0024] Figure 4 This is a schematic diagram of the structure of a power amplifier and another packaging method provided in one embodiment. Detailed Implementation

[0025] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0028] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation, the form, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0029] Reference Figure 1 As shown, the power amplifier's power amplifier chain includes a gain module, a pre-driver, a driver amplifier, and a final stage amplifier. The power amplifier employs a multi-channel Doherty architecture to improve back-off efficiency, which includes a main amplifier branch and several auxiliary amplifier branches, each branch equipped with a driver amplifier D and a final stage amplifier F.

[0030] exist Figure 1 In the illustrated scheme, the driver amplifier D and the final amplifier F are configured in a one-to-one correspondence, i.e., N:N. Typically, the size of the driver amplifier is kept to be 1 / 5 to 1 / 4 of the size of the final amplifier to achieve better linearity. For the main amplifier branch, on the one hand, a large driver amplifier will generate a large amount of quiescent current, thus increasing the static power consumption of the base station under low load; on the other hand, the efficiency of a large driver amplifier is only about 10%, thus dragging down the overall efficiency of the base station under high load.

[0031] Taking a 2.1GHz macro base station as an example, assuming the average power of the final stage amplifier is 50.5dBm, the gain is 15dB, and the efficiency is 58%, then the DC power consumption of the final stage amplifier is approximately 193W. The average power of the driver stage amplifier is 35.5dBm, and the efficiency is 10%, so the DC power consumption of the driver stage amplifier is 35.5W, accounting for more than 18% of the DC power consumption of the final stage amplifier. The calculated overall system efficiency is 49.01%. Therefore, it is necessary to improve the efficiency of the driver stage amplifier to reduce static power consumption and improve the overall system efficiency.

[0032] To address the problem of low efficiency in driver-stage amplifiers, this invention provides a power amplifier, comprising:

[0033] A power divider is used to acquire an input signal and split it into multiple signals.

[0034] The first-stage amplifier is connected to the power divider. The first-stage amplifier includes multiple first-stage branches, and each first-stage branch includes at least one sub-amplifier.

[0035] The second-stage amplifier is connected to the first-stage amplifier. The second-stage amplifier includes multiple second-stage branches, and each second-stage branch includes at least one sub-amplifier.

[0036] The number of first-level branches is greater than the number of second-level branches.

[0037] In one embodiment, at least one first-level branch is connected in series with at least one second-level branch to form a series path. Specifically, at least one first-level branch is connected in series with one of the second-level branches to form a series path. Therefore, the number of series paths formed is equal to the number of second-level branches, and thus the number of series paths formed is less than the number of first-level branches.

[0038] In one embodiment, since the number of first-level branches is greater than the number of series paths formed, each first-level branch includes at least one first-level parallel unit, and each first-level parallel unit is formed by at least two first-level branches connected in parallel. For example, when the difference between the number of first-level branches and the number of second-level branches is 1, the first-level amplifier includes one first-level parallel unit, and this first-level parallel unit is formed by two first-level branches connected in parallel. When the difference between the number of first-level branches and the number of second-level branches is 2, the first-level amplifier may include one first-level parallel unit formed by three first-level branches connected in parallel, or it may include two first-level parallel units formed by two first-level branches connected in parallel. Therefore, depending on the difference between the number of first-level branches and the number of second-level branches, the number of first-level parallel units formed and the number of first-level branches in each first-level parallel unit can be adjusted as needed. In this embodiment, the difference between the number of first-level branches and the number of second-level branches is 1, so the ratio of the number of first-level branches in the first-level amplifier to the number of second-level branches in the second-level amplifier is N+1:N. In this embodiment, both the first-stage branch and the second-stage branch include only one sub-amplifier. Therefore, the ratio of the number of sub-amplifiers in the first-stage amplifier to the number of sub-amplifiers in the second-stage amplifier is N+1:N.

[0039] In one embodiment, the power divider includes a primary power divider for dividing the input signal received by the radio frequency signal input interface (RFIN) into multiple signals based on the number of series paths. Specifically, a first-stage amplifier is connected to the primary power divider. When the first-stage amplifier includes *a* first-stage branches, where *b* first-stage branches form *c* first-stage parallel units, and the remaining *ab* first-stage branches do not form first-stage parallel units, the primary power divider divides the input signal received by the radio frequency signal input interface (RFIN) into (c+ab) in-phase input signals.

[0040] In one embodiment, the power divider further includes a secondary power divider, which is used to divide the input signal provided by the primary power divider into multiple signals based on the number of first-stage branches connected in parallel in the first-stage parallel unit. Specifically, the number of secondary power dividers is the same as the number of first-stage parallel units, that is, one secondary power divider is provided for each first-stage parallel unit. When a first-stage parallel unit includes d first-stage branches, the secondary power divider corresponding to the first-stage parallel unit will divide the input signal received from the primary power divider into d in-phase input signals.

[0041] In one embodiment, since the first-stage amplifier includes at least one first-stage parallel unit, one of the first-stage parallel units is used as the main circuit of the first-stage amplifier. The main circuit of the first-stage amplifier is formed by connecting one first-stage main circuit amplifier and at least one first-stage main circuit auxiliary amplifier in parallel. When the power amplifier is operating, the first-stage main circuit amplifier and the first-stage main circuit auxiliary amplifier need to be set to different bias states. Specifically, the first-stage main circuit amplifier is set to a Class AB bias state (i.e., Class-AB state), and the first-stage main circuit auxiliary amplifier is set to a Class C bias state (i.e., Class-C state). The first-stage amplifier includes only one first-stage main circuit, and all other first-stage branches are first-stage auxiliary circuits. Each first-stage auxiliary circuit includes one first-stage auxiliary circuit amplifier, which is set to a Class C bias state (i.e., Class-C state).

[0042] In one embodiment, a second-stage branch connected in series with the first-stage main circuit is used as the second-stage main circuit, and each second-stage main circuit includes a second-stage main circuit amplifier. Similarly, a second-stage branch connected in series with the first-stage auxiliary circuit is used as the second-stage auxiliary circuit, and each second-stage auxiliary circuit includes a second-stage auxiliary circuit amplifier. When the power amplifier is operating, the second-stage main circuit amplifier and the second-stage auxiliary circuit amplifier need to be set to different bias states. Specifically, the second-stage main circuit amplifier is set to a Class AB bias state (i.e., Class-AB state), and the second-stage auxiliary circuit amplifier is set to a Class C bias state (i.e., Class-C state).

[0043] In one embodiment, in a series path formed by connecting a first-stage main circuit and a second-stage main circuit in series, the ratio of the sum of the output power of the first-stage main circuit main amplifier and the output power of the first-stage main circuit auxiliary amplifier to the output power of the second-stage main circuit amplifier ranges from 1:3 to 1:8, and the ratio of the output power of the first-stage main circuit main amplifier to the output power of the first-stage main circuit auxiliary amplifier ranges from 1:1 to 1:2. In a series path formed by connecting a first-stage auxiliary circuit and a second-stage auxiliary circuit in series, the ratio of the output power of the first-stage auxiliary circuit amplifier to the output power of the second-stage auxiliary circuit amplifier ranges from 1:3 to 1:6. Furthermore, the ratio of the output power of the second-stage main circuit amplifier to the output power of the second-stage auxiliary circuit amplifier ranges from 1:1 to 1:2. In the first-stage amplifier, the ratio between the output powers of different first-stage auxiliary circuit amplifiers ranges from 1:0.5 to 1:1.5.

[0044] In one embodiment, a transmission line is provided on the first-stage main circuit to enable the first-stage main amplifier and the first-stage main auxiliary amplifier to form a Doherty architecture. Specifically, a transmission line is provided between the first-stage main amplifier and the second-stage main amplifier, and a transmission line is provided between the first-stage main auxiliary amplifier and the secondary power divider to align the phase between the first-stage main amplifier and the first-stage main auxiliary amplifier, thereby forming a Doherty architecture and improving the efficiency of the first-stage amplifier. Furthermore, a transmission line is provided between the first-stage auxiliary amplifier and the second-stage auxiliary amplifier connected in series. Optionally, a transmission line is provided between the first-stage auxiliary amplifier and the primary power divider to align the phase between different first-stage auxiliary amplifiers.

[0045] In one embodiment, a transmission line is provided between the second-stage amplifier and the RF signal output interface, so that the second-stage main amplifier and the second-stage auxiliary amplifier form a Doherty architecture. Specifically, a transmission line is provided between the second-stage main amplifier and the RF signal output interface (RFOUT), and a transmission line is provided between the second-stage auxiliary amplifier and the RF signal output interface (RFOUT), so that the second-stage amplifier forms a multi-channel Doherty architecture.

[0046] In one embodiment, multiple sub-amplifiers in the first-stage amplifier are packaged as a single unit, and the number of pins of the first-stage amplifier is set based on the number of first-stage branches or the number of series paths. The input pins of the first-stage amplifier are connected to the gates of the sub-amplifiers in the first-stage amplifier, the output pins of the first-stage amplifier are connected to the drains of the sub-amplifiers in the first-stage amplifier, and the sources of the sub-amplifiers in the first-stage amplifier are connected to zero potential. The sub-amplifiers in the first-stage amplifier include a first-stage main amplifier, a first-stage main auxiliary amplifier, and a first-stage auxiliary amplifier. Further, the multiple sub-amplifiers in the first-stage amplifier are packaged as a single unit with the primary power divider and / or the secondary power divider. Further, the multiple sub-amplifiers in the first-stage amplifier are packaged as a single unit with the transmission line.

[0047] In one embodiment, the multiple sub-amplifiers in the second-stage amplifier are packaged as a single unit, and the number of pins of the second-stage amplifier is set based on the number of second-stage branches or the number of series paths. The input pins of the second-stage amplifier are connected to the gates of the sub-amplifiers in the second-stage amplifier, the output pins of the second-stage amplifier are connected to the drains of the sub-amplifiers in the second-stage amplifier, and the sources of the sub-amplifiers in the second-stage amplifier are connected to zero potential.

[0048] The power amplifier provided by the present invention includes a first-stage amplifier and a second-stage amplifier connected together. By making the number of branches in the first-stage amplifier greater than the number of branches in the second-stage amplifier, a branch parallel structure is formed in the first-stage amplifier. The parallel branches are respectively in normally open and normally closed states, which reduces the static power consumption of the first-stage amplifier. By forming a Doherty architecture in the first-stage amplifier, the efficiency of the first-stage amplifier is improved, thereby improving the overall efficiency of the power amplifier.

[0049] In one embodiment, refer to Figures 2 to 4 As shown, the first stage amplifier can be a driver stage amplifier 200, which includes multiple driver stage branches, each of which includes a sub-amplifier; the second stage amplifier can be a final stage amplifier 300, which includes multiple final stage branches, each of which includes a sub-amplifier.

[0050] In one embodiment, refer to Figures 2 to 4 As shown, the driver stage amplifier 200 includes four driver stage branches, each including one sub-amplifier; the final stage amplifier 300 includes three final stage branches, each including one sub-amplifier. The driver stage amplifier 200 includes one driver stage parallel unit, which is formed by two driver stage branches connected in parallel. Furthermore, this driver stage parallel unit serves as the driver stage main path. Thus, the driver stage amplifier 200 includes a driver stage main path, a first driver stage auxiliary path, and a second driver stage auxiliary path. (Refer to...) Figures 2 to 4 As shown, the main driver stage includes a main driver amplifier (Driver_M_M) and an auxiliary driver amplifier (Driver_M_P) connected in parallel. The first auxiliary driver stage includes a first auxiliary driver amplifier (Driver_P1), and the second auxiliary driver stage includes a second auxiliary driver amplifier (Driver_P2). The final stage amplifier 300 includes a final stage main stage, a first final stage auxiliary stage, and a second final stage auxiliary stage. (Refer to...) Figures 2 to 4 As shown, the final stage main circuit includes the final stage main circuit amplifier Final_M, the first final stage auxiliary circuit includes the first final stage auxiliary circuit amplifier Final_P1, and the second final stage auxiliary circuit includes the second final stage auxiliary circuit amplifier Final_P2. Specifically, the driver stage main circuit and the final stage main circuit are connected in series to form a series path; that is, the driver stage main circuit amplifier Driver_M_M and the driver stage main circuit auxiliary amplifier Driver_M_P are connected in parallel and then connected in series with the final stage main circuit amplifier Final_M. The first driver stage auxiliary circuit and the first final stage auxiliary circuit are connected in series to form a series path; that is, the first driver stage auxiliary circuit amplifier Driver_P1 and the first final stage auxiliary circuit amplifier Final_P1 are connected in series. The second driver stage auxiliary circuit and the second final stage auxiliary circuit are connected in series to form a series path; that is, the second driver stage auxiliary circuit amplifier Driver_P2 and the second final stage auxiliary circuit amplifier Final_P2 are connected in series.

[0051] In one embodiment, refer to Figures 2 to 4 As shown, between the RF signal input interface (RFIN) and the RF signal output interface (RFOUT), the branch of the driver amplifier 200 and the branch of the final amplifier 300 form a three-way series path. Therefore, the primary power divider 110 adopts a three-way power divider to divide the input signal received through the RF signal input interface (RFIN) into three in-phase input signals, which are respectively provided to the driver stage main path, the first driver stage auxiliary path and the second driver stage auxiliary path of the driver amplifier 200.

[0052] In one embodiment, since the main drive stage includes two parallel drive stage branches, the secondary power divider 120 employs a two-way power divider to split the input signal provided by the primary power divider 110 to the main drive stage into two in-phase input signals, which are respectively provided to the main amplifier Driver_M_M and the auxiliary amplifier Driver_M_P of the main drive stage.

[0053] In one embodiment, when the power amplifier is operating, the main amplifier Driver_M_M in the driver stage is set to Class AB bias (i.e., Class-AB state), and the auxiliary amplifiers Driver_M_P, Driver_P1, and Driver_P2 in the driver stage are all set to Class C bias (i.e., Class-C state). The final main amplifier Final_M is set to Class AB bias (i.e., Class-AB state), and the first and second final auxiliary amplifiers Final_P1 and Final_P2 are both set to Class C bias (i.e., Class-C state).

[0054] In one embodiment, the ratio of the sum of the output power of the main amplifier Driver_M_M and the auxiliary amplifier Driver_M_P in the main drive stage to the output power of the final main amplifier Final_M is between 1:3 and 1:8. The ratio of the output power of the main amplifier Driver_M_M to the auxiliary amplifier Driver_M_P in the main drive stage is between 1:1 and 1:2. The ratio of the output power of the final main amplifier Final_M to the first final auxiliary amplifier Final_P1 is between 1:1 and 1:2. The ratio of the output power of the first auxiliary amplifier Driver_P1 to the second auxiliary amplifier Driver_P2 in the auxiliary drive stage is between 1:0.5 and 1:1.5. The ratio of the output power of the first auxiliary amplifier Driver_P1 to the first final auxiliary amplifier Final_P1 in the auxiliary drive stage is between 1:3 and 1:6, and the ratio of the output power of the second auxiliary amplifier Driver_P2 to the second final auxiliary amplifier Final_P2 in the auxiliary drive stage is between 1:3 and 1:6.

[0055] In one embodiment, refer to Figures 2 to 4As shown, a first transmission line L1 is provided between the main amplifier Driver_M_M in the driver stage and the final amplifier Final_M in the final stage. The input of the first transmission line L1 is connected to the output of the main amplifier Driver_M_M, and the output of the first transmission line L1 is connected to the outputs of the auxiliary amplifier Driver_M_P in the driver stage and the final amplifier Final_M. A second transmission line L2 is provided between the auxiliary amplifier Driver_M_P in the driver stage and the secondary power divider 120. The first end of the second transmission line L2 is connected to the output of the secondary power divider 120, and the second end of the second transmission line is connected to the input of the auxiliary amplifier Driver_M_P in the driver stage. The drains of the main amplifier Driver_M_M and the auxiliary amplifier Driver_M_P in the main drive stage are connected by a combiner formed by the first transmission line L1. The input of the auxiliary amplifier Driver_M_P is configured with the second transmission line L2 to align the phases of the main amplifier Driver_M_M and the auxiliary amplifier Driver_M_P, thus forming a two-way Doherty architecture. A third transmission line L3 is provided between the auxiliary amplifier Driver_P2 in the second drive stage and the primary power divider 110. The first end of the third transmission line L3 is connected to the output of the primary power divider 110, and the second end of the third transmission line L3 is connected to the input of the auxiliary amplifier Driver_P2. The input of the auxiliary amplifier Driver_P2 is configured with the third transmission line L3 to align the phases of the auxiliary amplifier Driver_P2 with the auxiliary amplifier Driver_P1 in the first drive stage. A fourth transmission line L4 is provided between the second driver stage auxiliary amplifier Driver_P2 and the second final stage auxiliary amplifier Final_P2. The first end of the fourth transmission line L4 is connected to the output of the second driver stage auxiliary amplifier Driver_P2, and the second end of the fourth transmission line L4 is connected to the input of the second final stage auxiliary amplifier Final_P2. A fifth transmission line L5 is provided between the first driver stage auxiliary amplifier Driver_P1 and the first final stage auxiliary amplifier Final_P1. The first end of the fifth transmission line L5 is connected to the output of the first driver stage auxiliary amplifier Driver_P1, and the second end of the fifth transmission line L5 is connected to the input of the first final stage auxiliary amplifier Final_P1.

[0056] In one embodiment, refer to Figures 2 to 4As shown, a sixth transmission line L6 is provided between the final stage main amplifier Final_M and the radio frequency signal output interface (RFOUT). The first end of the sixth transmission line L6 is connected to the output terminal of the final stage main amplifier Final_M, and the second end of the sixth transmission line L6 is connected to the radio frequency signal output interface (RFOUT). A seventh transmission line L7 is provided between the second final stage auxiliary amplifier Final_P2 and the radio frequency signal output interface (RFOUT). The first end of the seventh transmission line L7 is connected to the output terminal of the second final stage auxiliary amplifier Final_P2, and the second end of the seventh transmission line L7 is connected to both the radio frequency signal output interface (RFOUT) and the second end of the sixth transmission line L6. An eighth transmission line L8 is provided between the first final stage auxiliary amplifier Final_P1 and the radio frequency signal output interface (RFOUT). The first end of the eighth transmission line L8 is connected to the output terminal of the first final stage auxiliary amplifier Final_P1, and the second end of the eighth transmission line L8 is connected to both the output terminal of the second final stage auxiliary amplifier Final_P2 and the first end of the seventh transmission line L7. The sixth transmission line L6, the seventh transmission line L7, and the eighth transmission line L8 can be selected as transmission lines with an electrical length of 70 to 110 degrees or equivalent transmission lines, for example, transmission lines with an electrical length of 90 degrees. By connecting the final stage drive unit with the sixth transmission line L6, the seventh transmission line L7, and the eighth transmission line L8, a three-way Doherty architecture is formed.

[0057] In one embodiment, refer to Figure 2 As shown, the main amplifier Driver_M_M, the auxiliary amplifier Driver_M_P, the auxiliary amplifier Driver_P1, and the auxiliary amplifier Driver_P2 in the first stage amplifier are packaged into a single unit. The package includes four input pins and four output pins. The four input pins are connected to the gates of the main amplifier Driver_M_M, the auxiliary amplifier Driver_M_P, the first auxiliary amplifier Driver_P1, and the second auxiliary amplifier Driver_P2, respectively. The four output pins are connected to the drains of the main amplifier Driver_M_M, the auxiliary amplifier Driver_M_P, the first auxiliary amplifier Driver_P1, and the second auxiliary amplifier Driver_P2, respectively. The sources of the main amplifier Driver_M_M, the auxiliary amplifier Driver_M_P, the first auxiliary amplifier Driver_P1, and the second auxiliary amplifier Driver_P2 are all grounded.

[0058] In one embodiment, refer to Figure 3As shown, the main driver amplifier (Driver_M_M), auxiliary driver amplifier (Driver_M_P), auxiliary driver amplifier (Driver_P1), and auxiliary driver amplifier (Driver_P2) in the first-stage amplifier are packaged together with the primary power divider 110, the secondary power divider 120, the second transmission line L2, and the third transmission line L3 into a single package. This package includes one input pin and four output pins. The input pin is connected to the primary power divider 110, and the four output pins are connected to the drains of the main driver amplifier (Driver_M_M), auxiliary driver amplifier (Driver_M_P), auxiliary driver amplifier (Driver_P1), and auxiliary driver amplifier (Driver_P2), respectively. The sources of the main driver amplifier (Driver_M_M), auxiliary driver amplifier (Driver_M_P), auxiliary driver amplifier (Driver_P1), and auxiliary driver amplifier (Driver_P2) are all grounded.

[0059] In one embodiment, refer to Figure 4 As shown, the main amplifier Driver_M_M, auxiliary amplifier Driver_M_P, auxiliary amplifier Driver_P1, and auxiliary amplifier Driver_P2 of the first-stage amplifier are packaged together with the primary power divider 110, the secondary power divider 120, and the first transmission line L1, the second transmission line L2, the third transmission line L3, the fourth transmission line L4, and the fifth transmission line L5 into a single package. This package includes one input pin and three output pins. The input pin is connected to the primary power divider 110, and the three output pins are connected to the first transmission line L1, the fourth transmission line L4, and the fifth transmission line L5, respectively.

[0060] In one embodiment, refer to Figures 2 to 4 As shown, the final stage main amplifier Final_M, the first final stage auxiliary amplifier Final_P1, and the second final stage auxiliary amplifier Final_P2 in the second-stage amplifier are packaged into a single unit. This package includes three input pins and three output pins. The three input pins are connected to the gates of the final stage main amplifier Final_M, the first final stage auxiliary amplifier Final_P1, and the second final stage auxiliary amplifier Final_P2, respectively. The three output pins are connected to the drains of the final stage main amplifier Final_M, the first final stage auxiliary amplifier Final_P1, and the second final stage auxiliary amplifier Final_P2, respectively. The sources of the final stage main amplifier Final_M, the first final stage auxiliary amplifier Final_P1, and the second final stage auxiliary amplifier Final_P2 are all grounded.

[0061] Taking a 2.1GHz macro base station as an example, when the efficiency of the final stage amplifier is 58% and the gain is 15dB, and the efficiency of the driver stage amplifiers is 20%, 25%, and 30% respectively, the overall efficiency of the power amplifier can be increased from 49.01% to 53%~54.66%.

[0062] The power amplifier provided by the present invention includes a connected driver stage amplifier and a final stage amplifier. By making the main driver stage route in the driver stage amplifier form two driver stage branches connected in parallel, with the two driver stage branches being normally open and normally closed, respectively, the static power consumption is reduced by at least 8%. In addition, by setting a transmission line to form a Doherty architecture for the main driver stage route, the efficiency of the driver stage amplifier is increased from 10% to more than 25%, and the overall efficiency of the power amplifier is improved by 5%.

[0063] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.

[0064] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0065] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0066] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application.

Claims

1. A power amplifier, characterized in that, include: A power divider is used to acquire an input signal and split the input signal into multiple signals; A first-stage amplifier is connected to the power divider. The first-stage amplifier includes a plurality of first-stage branches, and each first-stage branch includes at least one sub-amplifier. A second-stage amplifier is connected to the first-stage amplifier. The second-stage amplifier includes multiple second-stage branches, and each second-stage branch includes at least one sub-amplifier. Wherein, the number of first-level branches is greater than the number of second-level branches; at least one first-level branch is connected in series with at least one second-level branch to form a series path, the number of series paths is equal to the number of second-level branches, the number of series paths is less than the number of first-level branches, the first-level amplifier includes at least one first-level parallel unit, the first-level parallel unit is formed by at least two first-level branches connected in parallel; the parallel branches are respectively in normally open and normally closed states; One of the first-level parallel units is used as the first-level main circuit, and one of the second-level branches is used as the second-level main circuit. The first-level main circuit and the second-level main circuit are connected in series. The first-level main circuit includes a first-level main circuit amplifier and at least one first-level main circuit auxiliary amplifier. The second-level main circuit includes a second-level main circuit amplifier. One of the first-level branches is used as a first-level auxiliary circuit, and one of the second-level branches is used as a second-level auxiliary circuit. The first-level auxiliary circuit and the second-level auxiliary circuit are connected in series. The first-level auxiliary circuit includes a first-level auxiliary circuit amplifier, and the second-level auxiliary circuit includes a second-level auxiliary circuit amplifier.

2. The power amplifier according to claim 1, characterized in that, The first stage amplifier is a driver stage amplifier; the second stage amplifier is a final stage amplifier.

3. The power amplifier according to claim 1, characterized in that, The multiple sub-amplifiers in the first-stage amplifier are packaged as a whole, and the number of pins of the first-stage amplifier is set based on the number of first-stage branches or the number of series paths; the multiple sub-amplifiers in the second-stage amplifier are packaged as a whole, and the number of pins of the second-stage amplifier is set based on the number of second-stage branches or the number of series paths.

4. The power amplifier according to claim 3, characterized in that, The pins include an input pin and an output pin, wherein the input pin is connected to the gate of the sub-amplifier, the output pin is connected to the drain of the sub-amplifier, and the source of the sub-amplifier is connected to a zero potential point.

5. The power amplifier according to claim 1, characterized in that, The power divider also includes a primary power divider and a secondary power divider; The primary power divider is used to divide the input signal received by the radio frequency signal input interface into multiple signals based on the number of serial paths; The secondary power divider is used to divide the input signal provided by the primary power divider into multiple signals based on the number of first-level branches in the first-level parallel unit.

6. The power amplifier according to claim 5, characterized in that, The number of secondary power dividers is the same as the number of first-stage parallel units.

7. The power amplifier according to claim 1, characterized in that, The first-stage main amplifier is set to Class AB bias, the first-stage main auxiliary amplifier and the first-stage auxiliary amplifier are both set to Class C bias, the second-stage main amplifier is set to Class AB bias, and the second-stage auxiliary amplifier is set to Class C bias.

8. The power amplifier according to claim 1, characterized in that, The ratio of the sum of the output power of the first-stage main amplifier and the output power of the first-stage main auxiliary amplifier to the output power of the second-stage main amplifier ranges from 1:3 to 1:

8. The ratio of the output power of the first-stage main amplifier to the output power of the first-stage main auxiliary amplifier ranges from 1:1 to 1:

2. The ratio of the output power of the first-stage auxiliary amplifier to the output power of the second-stage auxiliary amplifier ranges from 1:3 to 1:

6. The ratio of the output power of the second-stage main amplifier to the output power of the second-stage auxiliary amplifier ranges from 1:1 to 1:

2.

9. The power amplifier according to claim 1, characterized in that, A transmission line is provided on the first-stage main circuit so that the first-stage main amplifier and the first-stage main auxiliary amplifier form a Doherty architecture; a transmission line is provided between the second-stage amplifier and the radio frequency signal output interface so that the second-stage main amplifier and the second-stage auxiliary amplifier form a Doherty architecture.

10. The power amplifier according to claim 9, characterized in that, The first-stage amplifier includes a first-stage main circuit and two first-stage auxiliary circuits, and the second-stage amplifier includes a second-stage main circuit and two second-stage auxiliary circuits. The first-stage main circuit includes two first-stage branches, and each second-stage main circuit branch includes one second-stage branch. Each first-stage auxiliary circuit includes one first-stage branch, and each second-stage auxiliary circuit includes one second-stage branch.

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