A method and system for generating a package floorplan based on a LEF file

Abstract

The application relates to a packaging floorplan arrangement method and system based on a LEF file, and the method comprises the following steps: step 1, ensuring that the parameter attribute of the selected IP is matched with the layout requirement of subsequent packaging design through IP selection; step 2, restricting the floorplan design according to the layout requirement of PCB productization, and ensuring that the floorplan design is consistent with the final product application scene by systematically arranging the product form and the layout requirement; step 3, collecting the related design information of chips and third-party IPs, and establishing a preliminary physical model of chip design; the related design information comprises HARD MACRO IP LEF document information; step 4, automatically processing the LEF document of the HARD MACRO IP by using a Python script, and converting the LEF document into a bump map document; step 5, performing scheme design in the Cadence APD software based on the generated bump map document; and step 6, performing pre-wiring and fine adjustment on main modules, and fine adjusting the floorplan according to the result; the main modules comprise SERDES and DDR. The application can improve the design efficiency and scheme reliability.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, and in particular relates to a packaging floorplan layout method and system based on LEF file generation. Background Technology

[0002] With the continuous advancement of semiconductor process technology, modern chip design demands increasingly higher performance, higher density, and faster iteration. FCBGA (Flip Chip Ball Grid Array) packaging, with its excellent signal transmission performance and compact layout, has become the preferred packaging form for high-end processors, graphics processing units (GPUs), and communication chips. In the FCBGA packaging design flow, floorplan is a crucial step connecting internal functional modules to external package pins; its design quality directly affects signal integrity, power distribution efficiency, and the feasibility of subsequent routing designs.

[0003] In traditional FCBGA package design flows, floorplanning is typically performed in the early stages of chip design (e.g., 50% or earlier), based primarily on chip architecture dataflow, back-end placement and routing, and PCB layout. Specifically, chip architecture dataflow provides the logical relationships and signal transmission requirements between functional modules, back-end placement and routing provides initial constraints on physical implementation, and PCB layout defines the external interface requirements of package pins. Based on this information, designers roughly determine the relative positions of internal modules and signal routing directions. This method can meet initial planning needs to some extent, but its ability to evaluate details is very limited due to the lack of detailed signal connection data. For example, critical factors such as the trace path length, number of inter-layer switching (vias), and interaction with power planes of key high-speed modules (e.g., PCIe, DDR, or SerDes) are difficult to analyze accurately at this stage. These detailed evaluations usually need to wait until later in the design process, after obtaining the bump netlist.

[0004] The bump netlist, as the connection mapping between internal chip signals and bump pins in the package layer, is an indispensable data foundation for subsequent routing design and optimization. However, due to the phased nature of the design flow, the bump netlist is usually not fully generated until the chip architecture design reaches 85% completion or later. This results in a significant time gap between floorplan layout and detailed analysis in the traditional process: the initial rough layout based on chip architecture data flow, back-end placement and routing, and PCB product layout often reveals defects in later verification due to issues such as high-speed trace congestion, signal crosstalk, or insufficient power distribution, forcing the design team to scrap the previous work and readjust the layout. This iterative process not only extends the design cycle but also increases development costs.

[0005] To alleviate this problem, existing technologies often employ compromise strategies. For example, designers may rely on experience to reserve a certain amount of routing margin or make preliminary assumptions about high-speed signal paths based on historical data. However, the accuracy and reliability of these methods are insufficient to meet the high standards of modern chip design, especially as operating frequencies and signal rates increase, further exacerbating the sensitivity of high-speed modules to routing constraints. Furthermore, while some automated tools (such as EDA software) can assist in floorplan design, their functionality still depends on complete input data, making them ineffective when initial data is incomplete. Therefore, in FCBGA package design, how to fill the gaps in detailed evaluation caused by missing bump netlists in the early stages of design and quickly generate high-quality floorplan layouts has become a key bottleneck in current technological development.

[0006] In summary, the existing technology has the following technical defects:

[0007] First, existing technologies are severely lacking in their ability to assess details during the floorplanning phase. Traditional design flows rely on chip architecture data flow, backend placement and routing, and PCB product layout for initial planning. While this data provides logical relationships, physical constraints, and external interface requirements between modules, it lacks specific connection information between signals and bump pins because a bump netlist is unavailable in the early stages of design. For example, questions such as whether the trace path lengths of critical high-speed modules (e.g., PCIe, DDR, or SerDes) meet timing requirements, whether the number of inter-layer switching (vias) causes signal attenuation, and whether power plane distribution is balanced cannot be accurately analyzed at this stage. This leaves floorplan solutions at a rough layout level, often revealing defects during subsequent verification.

[0008] Secondly, time gaps in the design flow lead to frequent iterations. Bump netlists, crucial data for signal allocation, are typically generated when chip design reaches 70% completion or later, while floorplans need to be completed at 50% completion or earlier. This time mismatch means that early solutions lack sufficient basis, and problems are frequently discovered when obtaining the bump netlist for routing analysis later. For example, high-speed signal paths may be blocked due to channel congestion, signal integrity may be affected by excessive crosstalk, or even insufficient power distribution may cause local voltage drops. These problems force the design team to scrap the initial floorplan, readjust module locations and pin layouts, significantly extending the design cycle and increasing costs.

[0009] Third, existing technologies rely excessively on experience and assumptions, making it difficult to guarantee accuracy. To compensate for gaps in the bump netlist, designers often predict routing requirements based on historical data or personal experience, such as reserving extra routing channels or assuming signal path lengths. However, as chip frequencies increase (e.g., DDR5 speeds reach several Gbps), the sensitivity of high-speed signals to trace length matching, inter-layer switching, and crosstalk suppression increases significantly, making traditional experience-based methods insufficient. For example, an inappropriate assumption may cause trace length deviations to exceed the timing window, resulting in signal distortion. This unreliability is particularly evident in complex chip designs, leading to a higher error rate.

[0010] The root of the above problems lies in the lack of a systematic method in current technology for rapidly acquiring signal allocation information and performing routing analysis in the early stages of design. Traditional manual estimations or experience-based assumptions, while filling information gaps to some extent, cannot meet the accuracy and reliability requirements of modern high-performance chip design. Therefore, how to efficiently and accurately generate high-quality floorplan layouts when bumpnetlist is unavailable has become a critical technical bottleneck that urgently needs to be addressed in FCBGA package design. Summary of the Invention

[0011] The purpose of this invention is to provide a method and system for packaging floorplan layout based on LEF files. By introducing a systematic data processing and analysis process in the early stages of chip design, this invention solves the problem that the lack of a complete bump netlist in the early stages of chip design leads to insufficient detailed evaluation of floorplan layout, which in turn affects design quality and subsequent development progress, thereby improving design efficiency and solution reliability.

[0012] This invention provides a method for arranging encapsulated floorplans based on LEF files, comprising the following steps:

[0013] Step 1: Ensure that the parameters and attributes of the selected IP match the detailed layout requirements of the subsequent packaging design through IP selection;

[0014] Step 2: Based on the PCB product layout requirements, constrain the floorplan design. By systematically organizing the product form and layout requirements, ensure that the floorplan design is consistent with the final product application scenario.

[0015] Step 3: Collect relevant design information for the chip and third-party IP, and establish a preliminary physical model for the chip design; the relevant design information includes die size estimation information, HARD MACRO IP LEF document information, and backend requirements for IP placement.

[0016] Step 4: Use a Python script to automate the processing of the LEF document of the HARD MACRO IP and convert it into a bumpmap document;

[0017] Step 5: Design the solution in Cadence APD software based on the generated bump map document;

[0018] Step 6: Perform pre-routing and fine-tuning of the main modules, and fine-tune the floorplan based on the results; the main modules include SERDES and DDR.

[0019] Furthermore, the key parameters involved in IP selection in step 1 include IP size, orientation, signal bump depth, number and type of power supplies.

[0020] Further, step 2 includes:

[0021] 1) Define the product form:

[0022] Define the form factor of a half-height, half-length graphics card, or other specific dimensions, including full-height and full-length dimensions, to provide boundary conditions for the layout of external interfaces in the chip package;

[0023] 2) Identify key layout requirements:

[0024] The physical location of the external interface is directly mapped to the chip's bump allocation requirements; the external interface includes interfaces for optical modules, PCIe gold fingers, DRAM memory, critical power supplies, and GPIO.

[0025] 3) Mapping to floorplan requirements:

[0026] Based on the PCB layout, the physical location of the external interface is converted into the signal output direction and power distribution requirements of the internal modules of the chip.

[0027] Furthermore, the die size estimation information mentioned in step 3 is obtained from the backend evaluation based on the block size and MFU optimization of each IP; the HARD MACRO IP LEF document information is obtained from the LEF file obtained from the IP vendor, including the physical layout information of the IP; the backend's requirements for IP placement include the constraints on IP placement imposed by the backend design team.

[0028] Further, step 4 includes:

[0029] 1) The script parses the LEF file and extracts the coordinate information of the signal pins and power pins of the AP layer;

[0030] 2) Based on the extracted data, generate a bump map format file to record the mapping relationship between the signal and power pin bump grids of each IP.

[0031] Further, step 5 includes:

[0032] Design a floorplan scheme based on the following parameters:

[0033] Die size constraint: Set the chip boundary based on the die size estimated in step 3;

[0034] IP Orientation Adjustment: Place each IP module according to the EW or NS orientation determined in step 1;

[0035] PCB product layout mapping: Based on the layout requirements in step 2, allocate bump areas.

[0036] Further, step 6 includes:

[0037] 1) Pre-routing analysis: Trial routing is performed on the signal paths of high-speed modules, including SERDES and DDR, in APD to evaluate the trace length, number of inter-layer switching and crosstalk effects;

[0038] 2) Fine-tuning of location: If congestion or excessively long paths are found in the pre-wiring, adjust the location of the relevant IP addresses;

[0039] 3) Verification and optimization: Analyze signal and power quality through SIPI to clarify design rules.

[0040] The present invention also provides a packaged floorplan layout system based on LEF file generation, including a packaged floorplan layout module, wherein the packaged floorplan layout module executes the packaged floorplan layout method based on LEF file generation.

[0041] The present invention also provides a non-transitory computer-readable storage medium that stores computer instructions, which, when executed by a processor, implement the encapsulated floorplan arrangement method based on LEF file generation.

[0042] The present invention also provides an electronic device, comprising:

[0043] The system includes a memory and a processor, which are interconnected. The memory stores computer instructions, and the processor executes these computer instructions to perform the encapsulated floorplan layout method generated from the LEF file.

[0044] By employing the above approach, a floorplan layout method and system based on LEF files is used to automatically obtain bumpmap information from IP LEF files via scripts. Combined with stitching technology, this allows for rapid analysis of the trylay routing of critical high-speed modules. This generates high-quality floorplan layouts before the early stages of chip architecture design (50% completion), significantly reducing the risk of subsequent design failures due to routing evaluation. This improves design efficiency and package reliability, specifically including the following technical effects:

[0045] (1) Enhanced detailed assessment: By generating a bump map using Python scripts, routing and power distribution can be accurately assessed in the early stages, avoiding the need for later revisions.

[0046] (2) Fewer iterations: Systematic processes and pre-routing verification reduce late-stage design modifications and save time and costs.

[0047] (3) Higher automation: Automatically generate bump maps and optimize design, reducing human error.

[0048] (4) Better high-speed optimization: Pre-routing fine-tuning (e.g., trace <500μm) improves the performance of SERDES, DDR and other modules.

[0049] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0050] Figure 1 This invention relates to a method for arranging encapsulated floorplans based on LEF files;

[0051] Figure 2 This is a PCB product layout in one embodiment of the present invention;

[0052] Figure 3 The HARD MACRO IP LEF document in an embodiment of the present invention;

[0053] Figure 4 Converting LEF to BUMP MAP in an embodiment of the present invention;

[0054] Figure 5 The floorplan scheme in an embodiment of the present invention;

[0055] Figure 6 The structural schematic diagram of an electronic device according to the present invention. Specific embodiments

[0056] The following combines the drawings and embodiments to further describe in detail the specific embodiments of the present invention. The following embodiments are used to illustrate the present invention, but are not used to limit the scope of the present invention.

[0057] Refer Figures 1 to 5 As shown, this embodiment provides a method for arranging the package floorplan generated based on the LEF file, including the following steps:

[0058] Step S1, ensure that the parameter attributes of the selected IP match the detailed layout requirements of the subsequent package design through IP selection.

[0059] In the initial stage of floorplan arrangement, first select the IP (Intellectual Property module) to ensure that the parameter attributes of the selected IP match the detailed layout requirements of the subsequent package design. The following key parameters need to be concerned during selection:

[0060] IP size: including the length and width dimensions of the IP (such as in micrometers) to determine its occupied area on the chip die.

[0061] Orientation (EW or NS): that is, the East-West or North-South placement direction of the IP, which affects the planning of signal extraction and routing paths.

[0062] Signal bump depth: refers to the number of layers or distance from the internal signal pins of the IP to the external bump connection (such as 2-layer or 3-layer bump allocation), which determines the complexity of signal transmission and the requirements for wiring layers.

[0063] Number and types of power supplies: including the types of power supply voltages required by the IP (such as 0.8V, 0.9V, 1.2V) and the number of pins, which affects the design of power plane allocation.

[0064] By strictly controlling these parameters during the selection phase, a reliable foundation can be provided for subsequent packaging layout, avoiding later adjustments due to mismatches between IP attributes and floorplan requirements. For example, selecting smaller IPs can optimize die space utilization, while proper orientation can reduce signal crosstalk; at the same time, it is important to ensure that the power supply type (e.g., 0.8V for low-power modules, 1.2V for high-speed signal modules) matches the overall chip requirements.

[0065] Step S2: Based on the PCB product layout requirements, constrain the floorplan design. By systematically organizing the product form and layout requirements, ensure that the floorplan design is consistent with the final product application scenario.

[0066] After determining the IP selection, the floorplan design needs to be further constrained based on the product layout requirements of the PCB (Printed Circuit Board). Specific steps include:

[0067] Define the product form factor: such as a half-height, half-length graphics card form factor, or other specific dimensions (such as full height and full length), to provide boundary conditions for the layout of external interfaces of the chip package.

[0068] Determine key layout requirements: This includes the specific locations of optical modules (such as QSFP interfaces), PCIe gold fingers, DRAM memory (such as DDR5 slots), critical power supplies (such as VRM modules), and interfaces such as GPIO. The physical locations of these components directly map to the chip's bump allocation requirements.

[0069] Mapping to floorplan requirements: Based on the PCB layout, the location of external interfaces is translated into the signal output direction and power distribution requirements of the internal modules of the chip. For example, when the optical module is close to the top of the chip, relevant high-speed signals need to be preferentially allocated to the upper bump area of ​​the die.

[0070] This stage involves systematically organizing product form and layout requirements to ensure that the floorplan design is consistent with the final product application scenario, laying the foundation for subsequent steps.

[0071] Step S3: Collect relevant design information of the chip and third-party IP, and establish a preliminary physical model of the chip design; the relevant design information includes die size estimation information, HARD MACRO IP LEF document information, and backend requirements for IP placement.

[0072] To generate an accurate floorplan solution, it is necessary to collect relevant design information about the chip and third-party IP, including:

[0073] Die size estimation: mainly comes from backend evaluation based on each IP block size and MFU optimization.

[0074] HARD MACRO IP LEF Document: Obtain the LEF (Library Exchange Format) file from the IP vendor. It contains the IP's physical layout information, such as pin locations and dimensions.

[0075] Backend requirements for IP placement: This includes constraints imposed by the backend design team on IP placement, such as the adjacency requirements between different IPs based on power domain considerations.

[0076] By integrating this information, a preliminary physical model of the chip design is established, providing data support for subsequent bump map generation and module layout.

[0077] Step S4: Use a Python script to automate the processing of the LEF document of the HARD MACRO IP and convert it into a bumpmap document.

[0078] After collecting design information, Python scripts are used to automate the processing of the LEF document for the HARD MACRO IP, converting it into a bump map document. The specific implementation steps are as follows:

[0079] Data extraction: The script parses the LEF file and extracts the coordinate information of the signal pins and power pins of the AP layer.

[0080] Format conversion: Based on the extracted data, generate a bump map format file, which records the mapping relationship between the signal and power pin bump grid of each IP (e.g., coordinate form: X1, Y1 corresponds to signal A).

[0081] Step S5: Design the solution in Cadence APD software based on the generated bump map document.

[0082] Import the generated bump map document into Cadence APD (Advanced Package Designer) software and design the floorplan according to the following parameters:

[0083] Die size constraint: Set the chip boundary based on the die size estimated in step S3.

[0084] IP Orientation Adjustment: Place each IP module according to the EW or NS orientation determined in step S1.

[0085] PCB product layout mapping: Based on the layout requirements of step S2, allocate the bump area (if the optical module is located on the left side of the PCB, prioritize placing the optical module SERDES IP on the left, upper left, and lower left sides of the bump).

[0086] Step S6: Perform pre-routing and fine-tuning of the main modules, and fine-tune the floorplan based on the results; the main modules include SERDES and DDR.

[0087] Perform pre-routing analysis on key modules (such as SERDES, DDR, etc.) and fine-tune the floorplan based on the results. Specific steps include:

[0088] Pre-routing analysis: In the APD, test the signal paths of high-speed modules such as SERDES and DDR to evaluate the trace length (if it needs to be less than 500μm to meet timing requirements), the number of inter-layer switching (if it needs to be controlled within 2 times) and the impact of crosstalk.

[0089] Fine-tuning of locations: If congestion or excessively long paths are found during pre-routing, adjust the locations of the relevant IPs. For example, increase the distance between different DDRPHYs to avoid overlapping traces.

[0090] Verification and optimization: Analyze signal and power quality through SIPI to clarify design rules.

[0091] This step verifies the feasibility of key signals through pre-wiring, avoiding the risk of having to scrap the solution later due to wiring issues.

[0092] This invention, through automated tools and a systematic process, can output a reliable packaging floorplan solution 50% of the way through chip design. It solves the problem of insufficient evaluation of floorplan layout details and frequent iterations caused by the inability to obtain a bump netlist in the early stages of traditional design. Specific effects are as follows:

[0093] Preliminary data generation and analysis: A bumpmap is automatically generated from the LEF document of the HARD MACRO IP using a Python script, filling the gaps in the missing bump netlist in the early stages of the design and enabling rapid mapping of signal and power distribution.

[0094] Systematic design process: from IP selection (focusing on size, orientation, signal bump depth, power type 0.8V / 0.9V / 1.2V), PCB product layout requirement analysis, to die size estimation (back-end optimization based on IP block size and MFU) and pre-routing fine-tuning, forming a complete early floorplan optimization scheme.

[0095] High-speed module optimization: In Cadence APD software, pre-routing analysis and fine-tuning of the positions of SERDES, DDR and other modules are performed to ensure routing feasibility and avoid rework later.

[0096] This embodiment also provides a packaging floorplan layout system generated based on LEF files, including a packaging floorplan layout module, and the packaging floorplan layout module executes the packaging floorplan layout method generated based on LEF files.

[0097] This embodiment also provides a non-transitory computer-readable storage medium, and the non-transitory computer-readable storage medium stores computer instructions, and when the computer instructions are executed by a processor, the packaging floorplan layout method generated based on LEF files is implemented.

[0098] As Figure 6 shown, this embodiment also provides an electronic device, including:

[0099] a memory 201 and a processor 202, the memory 201 and the processor 202 are communicatively connected to each other, computer instructions are stored in the memory 201, and the processor 202 executes the computer instructions to execute the packaging floorplan layout method generated based on LEF files.

[0100] The above is only a preferred embodiment of the present invention and is not used to limit the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A method for arranging encapsulated floorplans based on LEF files, characterized in that, Includes the following steps: Step 1: Ensure that the parameters and attributes of the selected IP match the detailed layout requirements of the subsequent packaging design through IP selection; Step 2: Based on the PCB product layout requirements, constrain the floorplan design. By systematically organizing the product form and layout requirements, ensure that the floorplan design is consistent with the final product application scenario. Step 3: Collect relevant design information for the chip and third-party IP, and establish a preliminary physical model for the chip design; the relevant design information includes die size estimation information, HARD MACRO IP LEF document information, and backend requirements for IP placement. Step 4: Use a Python script to automate the processing of the LEF document of the HARD MACRO IP and convert it into a bump map document; Step 5: Design the solution in Cadence APD software based on the generated bump map document; Step 6: Perform pre-routing and fine-tuning of the main modules, and fine-tune the floorplan based on the results; the main modules include SERDES and DDR. Step 4 includes: 1) The script parses the LEF file and extracts the coordinate information of the signal pins and power pins of the AP layer; 2) Based on the extracted data, generate a bump map format file to record the mapping relationship between the signal and power pin bump grids of each IP.

2. The encapsulated floorplan layout method based on LEF file generation according to claim 1, characterized in that, The key parameters involved in IP selection in step 1 include IP size, orientation, signal bump depth, number and type of power supply.

3. The encapsulation floorplan layout method based on LEF file generation according to claim 2, characterized in that, Step 2 includes: 1) Define the product form: Clearly define the form factor of a half-height, half-length graphics card, or its full-height, full-length dimensions, to provide boundary conditions for the layout of external interfaces in the chip package; 2) Identify key layout requirements: The physical location of the external interface is directly mapped to the chip's bump allocation requirements; the external interface includes interfaces for optical modules, PCIe gold fingers, DRAM memory, critical power supplies, and GPIO. 3) Mapping to floorplan requirements: Based on the PCB layout, the physical location of the external interface is converted into the signal output direction and power distribution requirements of the internal modules of the chip.

4. The encapsulation floorplan layout method based on LEF file generation according to claim 3, characterized in that, The die size estimation information mentioned in step 3 comes from the backend's evaluation based on the block size and MFU optimization of each IP; the HARD MACRO IP LEF document information is obtained from the LEF file obtained from the IP vendor, including the physical layout information of the IP; the backend's requirements for IP placement include the constraints on IP placement imposed by the backend design team.

5. The encapsulation floorplan layout method based on LEF file generation according to claim 4, characterized in that, Step 5 includes: Design a floorplan scheme based on the following parameters: Die size constraint: Set the chip boundary based on the die size estimated in step 3; IP Orientation Adjustment: Place each IP module according to the EW or NS orientation determined in step 1; PCB product layout mapping: Based on the layout requirements in step 2, allocate bump areas.

6. The encapsulation floorplan layout method based on LEF file generation according to claim 5, characterized in that, Step 6 includes: 1) Pre-routing analysis: In the APD, trial routing is performed on the signal paths of high-speed modules including SERDES and DDR to evaluate the trace length, number of inter-layer switching and crosstalk effects; 2) Fine-tuning of location: If congestion or excessively long paths are found in the pre-wiring, adjust the location of the relevant IP addresses; 3) Verification and optimization: Analyze signal and power quality through SIPI to clarify design rules.

7. A floorplan layout system based on LEF file generation, characterized in that, It includes a floorplan layout module, which performs the floorplan layout method based on LEF file generation as described in any one of claims 1-6.

8. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer instructions, which, when executed by a processor, implement the encapsulated floorplan arrangement method based on LEF file generation as described in any one of claims 1-6.

9. An electronic device, characterized in that, include: A memory and a processor are interconnected, the memory stores computer instructions, and the processor executes the computer instructions to perform the encapsulation floorplan layout method based on LEF file generation as described in any one of claims 1-6.

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