Pixel generation techniques

Abstract

The invention discloses a pixel generation technique. Apparatuses, systems, and techniques for representing polygon data as pixels as part of a rasterization process. In at least one embodiment, a processor causes a pixel within a polygon to be identified based at least in part on one or more prefix sums of an amount of edges of the pixel covered by the polygon.

Description

Technical Field

[0001] At least one embodiment is directed to using processing resources for conversion during rasterization to convert data into pixels. For example, one or more processors may include one or more circuits for converting polygon data into pixels based at least in part on performing a prefix sum on the amount of pixel edges covered by the polygon edges. Background Art

[0002] Rasterization uses a lot of computing resources. For example, a processor can use thousands of processing cores to convert polygon data into pixels. Therefore, rasterization performance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A system for identifying one or more pixels within one or more polygons according to at least one embodiment is shown;

[0004] Figure 2 A system for identifying one or more pixels within one or more polygons by using a prefix and a partial coverage module is shown in accordance with at least one embodiment;

[0005] Figure 3 A system for identifying one or more pixels within one or more polygons by using a prefix and a partial coverage module is shown in accordance with at least one embodiment;

[0006] Figure 4 A system for identifying one or more pixels within one or more polygons by using the amount of pixels covered by the polygons is shown in accordance with at least one embodiment;

[0007] Figure 5 A system for identifying one or more pixels within one or more polygons by using the amount of pixels covered by the polygons is shown in accordance with at least one embodiment;

[0008] Figure 6 A system for identifying one or more pixels within one or more polygons by using the amount of pixels covered by the polygons is shown in accordance with at least one embodiment;

[0009] Figure 7 A system for identifying one or more pixels within one or more polygons by using fractional coverage is shown in accordance with at least one embodiment;

[0010] Figure 8 A system for identifying one or more pixels within one or more polygons by using fractional coverage is shown in accordance with at least one embodiment;

[0011] Figure 9A system for identifying one or more pixels within one or more polygons by using fractional coverage is shown in accordance with at least one embodiment;

[0012] Figure 10 A system for identifying one or more pixels within one or more polygons by using fractional coverage is shown in accordance with at least one embodiment;

[0013] Figure 11 A system for identifying one or more pixels within one or more polygons by using fractional coverage is shown in accordance with at least one embodiment;

[0014] Figure 12 A system for identifying one or more pixels within one or more polygons by using fractional coverage is shown in accordance with at least one embodiment;

[0015] Figure 13 A system for identifying one or more pixels within one or more polygons by using fractional coverage is shown in accordance with at least one embodiment;

[0016] Figure 14 A system for identifying one or more pixels within one or more polygons by using fractional coverage is shown in accordance with at least one embodiment;

[0017] Figure 15 A system for identifying one or more pixels within one or more polygons by using bottom pixel edge coverage is shown in accordance with at least one embodiment;

[0018] Figure 16 A system for identifying one or more pixels within one or more polygons by using bottom pixel edge coverage is shown in accordance with at least one embodiment;

[0019] Figure 17 A system for identifying one or more pixels within one or more polygons by using one or more prefix sums of bottom pixel edge coverages is shown in accordance with at least one embodiment;

[0020] Figure 18 A system for identifying one or more pixels within one or more polygons by using partial coverage and prefix-summed bottom pixel edge coverage is shown in accordance with at least one embodiment;

[0021] Figure 19 A system for identifying one or more pixels by using a sum of partial coverage and prefix-summed bottom pixel edge coverage is shown in accordance with at least one embodiment;

[0022] Figure 20 A system for identifying one or more pixels by using a sum of partial coverage and prefix-summed bottom pixel edge coverage is shown in accordance with at least one embodiment;

[0023] Figure 21 A block diagram illustrating a process for outputting a coverage fraction of a pixel according to at least one embodiment;

[0024] Figure 22 A block diagram illustrating a process for enabling an application programming interface (API) to identify a coverage ratio of a pixel in accordance with at least one embodiment;

[0025] Figure 23 A block diagram illustrating a driver and / or runtime for identifying pixels within a polygon according to at least one embodiment is shown;

[0026] Figure 24 An exemplary data center is shown in accordance with at least one embodiment;

[0027] Figure 25 A processing system according to at least one embodiment is shown;

[0028] Figure 26 A computer system according to at least one embodiment is shown;

[0029] Figure 27 A system according to at least one embodiment is shown;

[0030] Figure 28 An exemplary integrated circuit according to at least one embodiment is shown;

[0031] Figure 29 A computing system according to at least one embodiment is shown;

[0032] Figure 30 An APU is shown according to at least one embodiment;

[0033] Figure 31 A CPU according to at least one embodiment is shown;

[0034] Figure 32 An exemplary accelerator integrated slice is shown in accordance with at least one embodiment;

[0035] Figure 33A and Figure 33B An exemplary graphics processor is shown in accordance with at least one embodiment;

[0036] Figure 34A A graphics core according to at least one embodiment is shown;

[0037] Figure 34BGPGPU according to at least one embodiment is shown;

[0038] Figure 35A A parallel processor according to at least one embodiment is shown;

[0039] Figure 35B illustrates a processing cluster according to at least one embodiment;

[0040] Figure 35C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0041] Figure 36 A graphics processor according to at least one embodiment is shown;

[0042] Figure 37 A processor according to at least one embodiment is shown;

[0043] Figure 38 A processor according to at least one embodiment is shown;

[0044] Figure 39 illustrates a graphics processor core according to at least one embodiment;

[0045] Figure 40 illustrates a PPU according to at least one embodiment;

[0046] Figure 41 shows a GPC according to at least one embodiment;

[0047] Figure 42 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0048] Figure 43 A software stack for a programming platform according to at least one embodiment is shown;

[0049] Figure 44 According to at least one embodiment, Figure 43 CUDA implementation of the software stack;

[0050] Figure 45 According to at least one embodiment, Figure 43 ROCm implementation of the software stack;

[0051] Figure 46 According to at least one embodiment, Figure 43 OpenCL implementation of the software stack;

[0052] Figure 47 illustrates software supported by a programming platform according to at least one embodiment;

[0053] Figure 48According to at least one embodiment, Figures 43-46 Compiled code executed on the programming platform;

[0054] Figure 49 According to at least one embodiment, Figures 43-46 More detailed compiled code executed on the programming platform;

[0055] Figure 50 Transforming source code before compiling it according to at least one embodiment is shown;

[0056] Figure 51A A system configured to compile and execute CUDA source code using different types of processing units is shown in accordance with at least one embodiment;

[0057] Figure 51B A method configured to compile and execute a program using a CPU and a CUDA-enabled GPU according to at least one embodiment is shown. Figure 51A CUDA source code system;

[0058] Figure 51C A method configured to compile and execute using a CPU and a non-CUDA enabled GPU according to at least one embodiment is shown. Figure 51A CUDA source code system;

[0059] Figure 52 According to at least one embodiment, Figure 51C An example kernel converted by the CUDA to HIP conversion tool;

[0060] Figure 53 More details are shown according to at least one embodiment. Figure 51C a non-CUDA-enabled GPU; and

[0061] Figure 54 shows how threads of an exemplary CUDA grid are mapped to Figure 53 Different computing units;

[0062] Figure 55 shows how to migrate existing CUDA code to data parallel C++ code according to at least one embodiment; and

[0063] Figure 56 Components of a system for accessing large language models in accordance with at least one embodiment are shown. DETAILED DESCRIPTION

[0064] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to those skilled in the art that the inventive concepts described herein can be practiced without one or more of these specific details, and that two or more aspects of any one or more embodiments described herein can be combined.

[0065] In at least one embodiment, one or more processors, including one or more circuits, are configured to identify one or more pixels within one or more polygons based, at least in part, on whether the one or more pixels within the polygon are adjacent to one or more pixels that cross one or more polygon boundaries. In at least one embodiment, the one or more processors, including one or more circuits, perform operations to identify one or more fractions (or proportions) of pixels within the polygon that do not cross one or more polygon edges by using information about the edges of other pixels that cross one or more polygon edges. In at least one embodiment, the one or more processors, including one or more circuits, identify portions of pixel edges within the polygon to use as width values ​​to calculate the area of ​​other pixels within the polygon. In at least one embodiment, the information about the pixel edges used as width values ​​corresponds to common pixel edges shared between adjacent pixels. In at least one embodiment, the one or more processors, including one or more circuits, perform operations using the information about the pixel edges as width values ​​for pixels within a column or row of a pixel grid. In at least one embodiment, the one or more processors, including one or more circuits, output a total amount for each pixel within the polygon using, at least in part, a prefix sum of the width values.

[0066] In at least one embodiment, for example, pixel A intersects an edge of a polygon, while pixel B does not intersect an edge of the polygon. In at least one embodiment, the common pixel edge shared between pixel A and pixel B is completely surrounded by the polygon, and the polygon edge completely covers the common pixel edge when intersecting pixel A. In at least one embodiment, one or more processors comprising one or more circuits perform operations to identify that pixel B must be completely within the polygon because the polygon edge completely covers the common pixel edge when intersecting pixel A. In at least one embodiment, the processor comprising one or more circuits performs operations that use information about how the polygon edge covers the common edge to also calculate the portion of other pixels within the polygon that share a column or row with pixels A and B. In at least one embodiment, by performing the techniques described herein, one or more processors comprising one or more circuits are able to calculate the amount of pixel B within the polygon without having to compare pixel B to every edge of the polygon.

[0067] In at least one embodiment, a pixel is a two-dimensional (2D) element that represents a corresponding display element in a display device, such as a screen of a mobile device, a computer monitor, or a television. In at least one embodiment, a pixel represents a corresponding printing element in a printing device, such as a mask writer used in computational lithography. In at least one embodiment, one or more processors including one or more circuits are used to identify one or more pixels within one or more polygons to generate, display, or otherwise activate on a display and / or printing device. In at least one embodiment, a pixel is within a polygon if the amount of time a pixel is within the polygon reaches or exceeds a threshold (e.g., 0.50 or 50%). In at least one embodiment, pixels adjacent to another pixel share a common pixel edge (pixel boundary) with the other pixel. In at least one embodiment, a polygon boundary (polygon edge) intersects a pixel if the polygon passes through the pixel, intersects the pixel, and / or enters the pixel if the polygon is superimposed or placed within a grid of pixels (e.g., a pixel grid).

[0068] In at least one embodiment, one or more processors including one or more circuits are configured to perform mathematical operations of an algorithm, including a prefix sum operation, to identify the amount of a pixel within a polygon. In at least one embodiment, one or more processors including one or more circuits are configured to identify the amount of a pixel within a polygon based at least in part on the amount of one or more sides of the pixel covered by one or more sides of the polygon. In at least one embodiment, the amount of a pixel within a polygon is a value representing the area of ​​the pixel within the polygon. In at least one embodiment, the amount of a pixel within a polygon is referred to as the amount inside the polygon and / or the amount covered by the polygon. In at least one embodiment, the amount of a pixel side (e.g., a pixel edge) covered by one or more sides of a polygon is a portion of the pixel side output by or similar to one or more mathematical operations for performing scalar and / or vector projections onto horizontal pixel edges. In at least one embodiment, the amount of a pixel side (pixel edge or pixel boundary) covered by one or more sides of a polygon is referred to as a pixel edge coverage value, pixel edge coverage, or edge coverage. In at least one embodiment, the amount of pixel edges covered by the polygon edges is a value expressed as a ratio, percentage, length, or some combination thereof.

[0069] In at least one embodiment, pixel edge coverage is the amount of a pixel's edge that is shared with an adjacent pixel above and covered by one or more portions of one or more polygon edges that intersect the adjacent pixel above. In at least one embodiment, a pixel adjacent to another pixel is a pixel next to the other pixel. In at least one embodiment, the pixel edge coverage value of a pixel is used, at least in part, to identify the amount of other pixels below (adjacent or otherwise) and within the pixel's column that are within a polygon.

[0070] In at least one embodiment, an advantage of the techniques described herein includes reading a data value for pixel edge coverage to at least partially identify the amount of a pixel within a polygon even if the pixel does not intersect an edge of the polygon. In at least one embodiment, an advantage of the techniques described herein includes reading a data value for pixel edge coverage to at least partially identify the amount of a pixel within a polygon without requiring reference to information about the polygon edges (e.g., direction, starting coordinates, ending coordinates) to perform the calculation. In at least one embodiment, an advantage of the techniques described herein includes parallelization of computational operations based on each segment of a polygon edge within a pixel. In at least one embodiment, an advantage of the techniques described herein includes the accuracy of the computations being dependent on the accuracy of the data values ​​used for mathematical operations (e.g., addition, multiplication) rather than on the resolution of the pixel grid.

[0071] Figure 1 A block diagram of a system 100 including one or more processors including one or more circuits for identifying one or more pixels within one or more polygons based at least in part on whether the one or more pixels within the one or more polygons are adjacent to one or more pixels that intersect (cross) one or more polygon edges is shown in accordance with at least one embodiment. Figure 1 One or more aspects of one or more embodiments described herein may be combined with one or more aspects of one or more embodiments described herein, including at least one combination thereof. Figures 2 to 23 In at least one embodiment, one or more processors perform one or more operations of system 100. In at least one embodiment, any one or more processors described herein include one or more circuits. In at least one embodiment, the one or more processors performing one or more operations of system 100 are any one or combination of processors described herein, including Figure 1 processor 104, Figure 31 CPU 3100, Figure 33B Graphics processor 3340, Figure 34B General-Purpose Graphics Processing Unit (GPGPU) 3430 and Figure 40In at least one embodiment, the processor 104 performs operations used by the system 100, such as loading / storing pixel edge coverage in the arithmetic logic unit (ALU), e.g. Figure 37 ALU 3716 and ALU 3718. In at least one embodiment, processor 104 performs a combination of Figure 21 In at least one embodiment, the processor 104 performs one or more operations described in the process 2100, such as calculating the bottom edge pixel coverage. Figure 22 In at least one embodiment, the processor 104 performs one or more operations described in the process 2200, such as executing an API function to calculate pixel coverage using a prefix sum of bottom pixel edge coverages. Figure 23 One or more operations described, such as executing driver / runtime 2304.

[0072] In at least one embodiment, the system 100 includes and / or otherwise obtains polygonal data as input data, which is depicted as polygonal input data 102. In at least one embodiment, the polygonal input data 102 includes vertex data and / or vector data. In at least one embodiment, the processor 104 is used to perform operations to convert any representation of an environment, model, object, or some combination thereof into a pixel representation. In at least one embodiment, when the processor 104 performs operations to at least partially convert any data representation of an environment, model, object, or some combination thereof into a pixel representation, performing such operations is referred to as rasterization. In at least one embodiment, one or more aspects of the rasterization process are referred to as shading. In at least one embodiment, the processor 104 performs operations to at least partially identify one or more pixels within a polygon for rasterization. In at least one embodiment, one or more operations described herein are performed by one or more shader cores, such as Figure 33B Shader cores 3355A-3355N of the graphics processor 3340.

[0073] In at least one embodiment, polygon input data 102 includes information about polygons (e.g., triangles) used to represent 3D models and / or objects. In at least one embodiment, polygon input data 102 includes data representing the edges and vertices of the polygons. In at least one embodiment, polygon input data 102 defines all polygon edges to be represented by pixels of a pixel grid. In at least one embodiment, polygon input data 102 includes data that at least partially defines the polygon edges based at least in part on properties (characteristics) of the polygon edges (e.g., location, start point, end point, direction, attributes, or some combination thereof), as well as other information described herein. In at least one embodiment, polygon input data 102 includes information about vertices, such as their location, color, reflectivity, texture, or some combination thereof. In at least one embodiment, polygon input data 102 uses vertices to represent the edges of the polygons to be represented as pixels. In at least one embodiment, polygon input data 102 represents polygon edges as vectors with directions. In at least one embodiment, polygon input data 102 includes information about edge directions, which, by convention, indicates whether space and / or pixels located in one direction or on one side of the edge are inside or outside the polygon containing the edge. In at least one embodiment, polygon input data 102 is stored as one or more tensors.

[0074] In at least one embodiment, polygon input data 102 includes data representing one or more polygons, each polygon being represented by one or more triangles. In at least one embodiment, polygon input data 102 includes two-dimensional (2D) coordinates of the vertices of the polygon, for example:

[0075] Polygon 1: (0,10), (0,20), (10,20);

[0076] Polygon 2: (-200,-200), (-200,-100), (-100,-100), (-100,-200); and

[0077] Polygon 3: (-150,-150), (-150,-100), (-120,-150).

[0078] In at least one embodiment, the data input to the processor 104 includes one or more pixel grids. In at least one embodiment, the pixel grid uses a convention where the origin of the pixel grid is located in the lower left position of the grid. In at least one embodiment, the input data representing the pixel grid includes information about the spacing between pixels and dimensions such as width and height.

[0079] In at least one embodiment, processor 104 is any one of the processors described herein or a combination of processors, including Figure 1 processor 104, Figure 31 CPU 3100, Figure 33B Graphics processor 3340, Figure 34B General-Purpose Graphics Processing Unit (GPGPU) 3430 and Figure 40 In at least one embodiment, any module described as being implemented on processor 104 is implemented on any one processor or combination of processors. In at least one embodiment, processor 104 performs any operations at least in part for rasterization. In at least one embodiment, any one or more modules of processor 104 are implemented as part of one or more other modules of processor 104. In at least one embodiment, any one or more processors 104 are implemented as Figure 1 any one or more modules depicted in .

[0080] In at least one embodiment, as used in any embodiment described herein, unless the context clearly dictates otherwise or clearly contradicts, terms such as "system," "device," "component," or "module," and nominalized verbs (e.g., compiler, shader, and / or other terms) each refer to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment, any system, device, component, and module described herein is combined and / or communicatively connected with at least one other component, system, device, component, and module, regardless of how these components are described as combined and / or communicatively connected in other embodiments. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions. In at least one embodiment, hardware, alone or in any combination, includes hardwired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution unit circuitry, and / or firmware that stores instructions executed by programmable circuitry. In at least one embodiment, modules may be collectively or individually embodied as circuitry that constitutes part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), and the like. In at least one embodiment, any one or more architectures of any circuits of one or more modules are represented as a register transfer level (RTL) representation and / or another fabless representation that can be licensed and / or used for tape-out, which is the final stage in IC design before it is used to manufacture the IC.

[0081] In at least one embodiment, the processor 104 executes the operations of the polygon transformation module 106 to transform (or modify) the polygon input data 102 into a data array (or tensor) that can later be converted into pixels. In at least one embodiment, the processor 104 executes the operations of the polygon transformation module 106 to convert the three-dimensional (3D) position coordinates of the vertices of the polygon input data 102 into two-dimensional (2D) position coordinates corresponding to a pixel grid, a display device, a printing device, or some combination thereof. In at least one embodiment, the processor 104 executes the operations of the polygon transformation module 106 to transform the polygon input data 102 into a format suitable for processing by other tasks of the rasterization process, such as lighting, projection, and clipping. In at least one embodiment, the processor 104 executes the operations of the polygon transformation module 106 and outputs the transformed polygon information to be received and / or otherwise obtained by the prefix and pixel coverage module 108.

[0082] In at least one embodiment, the processor 104 executes the operations of the prefix and pixel coverage module 108 to identify one or more pixels within the polygon based at least in part on whether the one or more pixels within the polygon are adjacent to one or more pixels that intersect (cross) one or more polygon boundaries. In at least one embodiment, the processor 104 executes the operations of the prefix and pixel coverage module 108 to identify portions of one or more sides of the polygon that pass through the one or more pixels. In at least one embodiment, the prefix and pixel coverage module 108 is at least in part a component of the present invention in conjunction with Figures 2 to 20 In at least one embodiment, reference to a module that performs one or more operations (e.g., prefix and pixel coverage module 108) refers to the processor 104 that performs the one or more operations of the module. In at least one embodiment, reference to a module that performs one or more operations (e.g., prefix and pixel coverage module 108) refers to the processor implemented on the module for performing those one or more operations.

[0083] In at least one embodiment, the prefix and pixel coverage module 108 executes a prefix and pixel coverage algorithm that includes a set of operations for identifying one or more pixels within a polygon. In at least one embodiment, identifying one or more values ​​and / or objects refers to the processor 104 performing operations to calculate, compute, and / or otherwise determine those one or more values ​​and / or objects. In at least one embodiment, identifying a value or object includes calculating and / or computing one or more mathematical and / or logical operations.

[0084] In at least one embodiment, the prefix and pixel coverage algorithm performed by the prefix and pixel coverage module 108 includes steps such as:

[0085] Step 1: Calculate partial coverage;

[0086] Step 2: Calculate pixel edge coverage;

[0087] Step 3: Calculate the prefix sum along the pixel column;

[0088] Step 4: Add the results of step 1 and step 3;

[0089] In at least one embodiment, the prefix and pixel coverage module executes an algorithm to output values, each value representing an amount of a pixel that lies within a pixel, wherein the values ​​are used to generate a rasterized image of the polygon input data 102 .

[0090] In at least one embodiment, the steps of the algorithm are performed in any order. In at least one embodiment, any one or more steps of the algorithm are omitted. In at least one embodiment, any one or more steps of the algorithm include one or more operations performed in any order. In at least one embodiment, the prefix and pixel coverage module 108 parallelizes the calculations described herein, such as calculating the bottom pixel edge coverage by two or more portions of one or more edges of the polygon, as further described herein. In at least one embodiment, the prefix and pixel coverage module 108 parallelizes the calculation of the amount of one or more pixels covered by a polygon by two or more edges of the polygon, as further described herein.

[0091] In at least one embodiment, the prefix and pixel coverage module 108 performs step 1 of the prefix and pixel coverage algorithm, which includes the operation of calculating partial coverage. In at least one embodiment, the prefix and pixel coverage module 108 performs an operation to identify the area (amount) of the one or more pixels within the polygon based at least in part on one or more sections of one or more sides of the polygon that intersect the one or more pixels, as further described herein. In at least one embodiment, the area of ​​the one or more pixels within the polygon based at least in part on one or more sections of one or more sides of the polygon that intersect the one or more pixels is referred to as partial coverage. In at least one embodiment, calculating partial coverage includes parallelizing the calculation of one or more amounts of the one or more pixels within the polygon across two or more sections of one or more sides of the polygon. In at least one embodiment, identifying partial coverage means calculating partial coverage. In at least one embodiment, partial coverage is calculated for pixels having one or more polygon sides (polygon boundaries) that intersect (pass through) the pixel. In at least one embodiment, partial coverage is the amount of the pixel covered by the polygon, e.g., the area or portion of the pixel. In at least one embodiment, the amount of pixels covered by a polygon refers to the amount of pixels that are within or inside the polygon. In at least one embodiment, the prefix and pixel coverage module 108 performs operations to calculate partial coverage of pixels, where each of the pixels intersects one or more polygon edges, and as further described herein. In at least one embodiment, pixels that intersect one or more polygon edges are pixels that have one or more polygon edges that intersect the pixels. In at least one embodiment, the prefix and pixel coverage module 108 calculates pixel coverage by using one or more polygon edges and one or more pixel edges (pixel boundaries) as boundaries for calculating the area covered by the polygon.

[0092] In at least one embodiment, polygon edges pointing from right to left are used to generate the partial coverage, in accordance with the convention for defining the properties of polygons. In at least one embodiment, polygon edges pointing from left to right are used to identify negative partial coverage, which is the area outside the polygon. In at least one embodiment, the partial coverage is added to the other pixel areas covered by the polygon to output one or more total areas of one or more pixels covered by the polygon. In at least one embodiment, the prefix sum pixel coverage module 108 calculates the other pixel areas when the corresponding pixels do not have polygon edges that intersect those pixels.

[0093] In at least one embodiment, the prefix and pixel coverage module 108 identifies a portion of a pixel intersected by a polygon edge by identifying one or more locations or points where the polygon edge intersects any pixel edge. In at least one embodiment, the boundary used to calculate the partial coverage of a pixel spans the length between the intersection location or point of the polygon edge with the pixel edge and the bottom edge of the pixel, such as at least Figure 8 and Figure 13 In at least one embodiment, this article is at least combined with Figures 7 to 13 The operations performed by the prefix and pixel coverage module 108 to calculate the partial coverage are further described.

[0094] In at least one embodiment, the prefix and pixel coverage module 108 performs step 2 of the prefix and pixel coverage algorithm, which includes the operation of calculating the bottom pixel edge coverage. In at least one embodiment, the prefix and pixel coverage module 108 identifies portions of one or more edges of a polygon, such as the bottom edge coverage, based at least in part on intersections between the one or more edges of the polygon and one or more adjacent pixels, as described herein in conjunction with at least one embodiment. Figure 13 In at least one embodiment, the prefix and pixel coverage module 108 identifies portions of one or more sides of a polygon, such as bottom edge coverage, based at least in part on one or more locations (e.g., vertices) where two or more sides of the polygon meet, as described herein in at least conjunction with Figure 13 In at least one embodiment, the prefix and pixel coverage module 108 performs operations to identify the area of ​​one or more pixels within a polygon based at least in part on information about one or more other pixels in the column (e.g., bottom pixel edge coverage), as further described herein. In at least one embodiment, the prefix and pixel coverage module 108 performs operations to identify the amount of one or more pixels within a polygon based at least in part on the amount of one or more edges of the one or more pixels covered by one or more edges of the polygon, as further described herein. In at least one embodiment, the bottom pixel edge coverage is the amount of pixel edges covered by the polygon. In at least one embodiment, the bottom pixel edge is the bottom pixel edge of a pixel that intersects one or more polygon edges. In at least one embodiment, the amount of the bottom pixel edge is the length or proportion of the bottom pixel edge that is covered by a portion of the polygon edge that intersects the pixel.

[0095] In at least one embodiment, the bottom pixel edge coverage is based on polygon edges pointing from right to left. In at least one embodiment, in accordance with the convention of defining polygon properties based on the direction in which the polygon edges point, the bottom pixel edge coverage based on polygon edges pointing from right to left is used to calculate the pixel area covered by the polygon, as further described herein. In at least one embodiment, the bottom pixel edge coverage based on polygon edges pointing from left to right is used to calculate the pixel area outside the polygon. In at least one embodiment, the bottom pixel edge coverage based on polygon edges pointing from left to right is referred to as negative bottom pixel edge coverage. In at least one embodiment, the amount of bottom pixel edge covered by a polygon edge is calculated by using a scalar projection of a portion (segment) of the polygon edge onto the bottom pixel edge. In at least one embodiment, such a projection is a projection of one or more portions of one or more polygon edges onto the edges of one or more adjacent pixels, as further described herein. In at least one embodiment, the bottom pixel edge coverage is equivalent to the scalar x-component of a vector representing the portion of the polygon edge that intersects the pixel. In at least one embodiment, the bottom pixel edge coverage is based on the portion of the polygon edge that is within the pixel. In at least one embodiment, the bottom pixel edge coverage is based on a portion of a polygon edge defined by one or more locations where the polygon edge intersects one or more pixel edges, at least in Figure 15 and Figure 16 In at least one embodiment, the bottom pixel edge coverage is based on a portion of a polygon edge defined by one or more locations where the polygon edge meets another polygon edge (e.g., at a vertex), which is at least Figure 15 and Figure 16 Depicted in.

[0096] In at least one embodiment, the bottom pixel edge coverage used in part to identify the amount of pixels covered by the polygon is a common pixel edge shared by adjacent pixels. In at least one embodiment, the algorithm defines an adjacent pixel as being above another pixel. In at least one embodiment, the algorithm defines an adjacent pixel by being below, to the left, or to the right of another pixel. In at least one embodiment, the prefix and pixel coverage module 108 identifies whether an adjacent pixel intersects a polygon edge. In at least one embodiment, the prefix and pixel coverage module 108 performs operations to identify whether one or more pixels are adjacent to one or more other pixels that intersect one or more polygon edges (polygon boundaries), and as further described herein. In at least one embodiment, identifying whether an adjacent pixel intersects a polygon edge is used to determine whether the bottom pixel edge coverage of the common or shared pixel edge between the adjacent pixel and another pixel will be used to calculate the amount of the other pixel covered by the polygon. In at least one embodiment, the bottom pixel edge coverage is used to calculate the amount of a pixel covered by a polygon that is below but not adjacent to a pixel corresponding to the bottom pixel edge coverage. In at least one embodiment, the operations for calculating the bottom pixel edge coverage are at least combined with Figures 15 and 16 and Figure 18 Further described herein.

[0097] In at least one embodiment, the prefix and pixel coverage module 108 performs an operation to calculate a width value using the bottom pixel edge coverage, and then uses the width value to calculate the area of ​​the pixels covered by the polygon. In at least one embodiment, the prefix and pixel coverage module 108 performs an operation to identify the amount of one or more pixels within the polygon by using one or more portions of one or more edges of the polygon, as described herein. In at least one embodiment, the prefix and pixel coverage module 108 performs an operation to identify the amount of one or more pixels within the polygon based at least in part on one or more portions of one or more edges of the polygon to calculate the width value, as further described herein. In at least one embodiment, the prefix and pixel coverage module 108 performs an operation to calculate a width value using the negative bottom pixel edge coverage, and then uses the width value to calculate the area of ​​the pixels outside the polygon. In at least one embodiment, the bottom pixel edge coverage value, expressed as a fraction of the bottom pixel edge covered by the polygon, is also used as the width value when the pixel width is equal to 1. In at least one embodiment, the bottom pixel edge coverage is propagated to one or more calculations of the area of ​​pixels covered by the polygon, where these pixels are located below the bottom pixel edge. In at least one embodiment, the bottom pixel edge coverage is used as a width value to calculate the area corresponding to one or more pixels below the pixel edge corresponding to the bottom pixel edge coverage. Figures 15 to 17 The operation of calculating the area using the bottom pixel edge coverage is further described.

[0098] In at least one embodiment, the pixel area covered by the polygon calculated using partial edge coverage is referred to as edge-based pixel coverage. In at least one embodiment, the pixel area outside the polygon calculated using negative bottom pixel edge coverage is referred to as negative edge-based pixel coverage. In at least one embodiment, when the pixel width is 1 and the pixel height is 1, the pixel area calculated using bottom pixel edge coverage is equal to the bottom pixel edge coverage. In at least one embodiment, when both the pixel width and height are 1, the pixel area calculated using bottom pixel edge coverage is referred to as bottom pixel edge coverage because the two values ​​are equal to each other.

[0099] In at least one embodiment, the prefix sum pixel coverage module 108 performs the operations of step 3 of the prefix sum pixel coverage algorithm, which includes an operation for performing a prefix sum on the bottom pixel edge coverage along the pixel column. In at least one embodiment, the prefix sum pixel coverage module 108 performs operations to identify the amount of one or more pixels within the polygon using one or more prefix sums along one or more dimensions, and as further described herein. In at least one embodiment, the dimensions refer to columns or rows of the pixel grid. In at least one embodiment, the prefix sum pixel coverage module 108 performs a prefix sum operation on the edge-based pixel coverage (or bottom pixel edge coverage) corresponding to the pixels in the pixel column from top to bottom. In at least one embodiment, the operations for calculating the edge-based pixel coverage and performing the prefix sum are at least described herein in conjunction with Figures 16 to 19 Further description.

[0100] In at least one embodiment, the prefix and pixel coverage module 108 performs step 4 of the prefix and pixel coverage algorithm, which includes adding together the fractional coverage, negative area, edge-based pixel coverage (or bottom pixel edge coverage), and negative edge-based pixel coverage (or negative bottom pixel edge coverage) of each pixel. In at least one embodiment, the sum of the fractional coverage, negative area, edge-based pixel coverage (or bottom pixel edge coverage), and negative edge-based pixel coverage (or negative bottom pixel edge coverage) of each pixel equals the total amount of pixels covered by the polygon. In at least one embodiment, the total amount of pixels covered by the polygon is referred to as the pixel's coverage fraction or total pixel coverage.

[0101] In at least one embodiment, the prefix and pixel coverage module 108 performs operations that compare the total pixel coverage to a threshold value (e.g., 0.5, 50%) to identify whether a pixel is covered by a polygon (is within the polygon). In at least one embodiment, the processor 104 performs operations of the prefix and pixel coverage module 108 to use one or more pixels identified as being within the polygon to at least partially perform rasterization and / or computational lithography tasks. In at least one embodiment, the pixels identified as being within the polygon are generated, displayed, printed, and / or otherwise activated on a display and / or printer to output a rasterized image of the polygon input data 102. In at least one embodiment, the rasterized image of the polygon input data 102 is used, at least in part, to generate a lithography mask for a computational lithography process.

[0102] In at least one embodiment, the processor 104 executes the operations of the prefix and pixel coverage module 108 to receive and / or otherwise obtain data regarding polygon edges that constitute one or more polygons. In at least one embodiment, the processor 104 executes the operations of the prefix and pixel coverage module 108 to receive and / or otherwise obtain data regarding the edges that constitute one or more polygons, wherein the data indicates whether the area to the left or right of the edge is inside or outside the polygon. In at least one embodiment, the processor executes the operations of the prefix and pixel coverage module 108 to identify each portion (segment) of the polygon edge that passes through a pixel of a pixel grid. In at least one embodiment, the processor executes the operations of the prefix and pixel coverage module 108 to identify the portion of the pixel edge covered by the polygon edge that passes through the corresponding pixel. In at least one embodiment, the pixel grid is a grid of pixel points. In at least one embodiment, a pixel point is a point on a pixel that represents a portion of a pixel. In at least one embodiment, a pixel point is a corner of the pixel. In at least one embodiment, any number of pixel points is used to identify pixel portions. In at least one embodiment, for example, a pixel is represented by 144 equally spaced points, 16 of which are located in 9 equally sized portions of the pixel. In at least one embodiment, pixel grid resolution refers to the number of pixels used to represent each pixel of the pixel grid. In at least one embodiment, the portion of pixels represented by points is called a sub-pixel map, and the pixel grid that depicts the pixels is called a pixel grid or sub-pixel map. In at least one embodiment, the pixels are called grid points.

[0103] In at least one embodiment, the processor 104 calls, invokes, or otherwise executes the API of the prefix and pixel coverage API module 110. In at least one embodiment, the API is combined with at least Figure 23 The API functions are further described herein. In at least one embodiment, the API is Figure 23In at least one embodiment, the processor executes the operations of the prefix and pixel coverage module 108 to execute the prefix and pixel coverage API module 110. In at least one embodiment, the prefix and pixel coverage API module 110 is implemented as part of the prefix and pixel coverage module 108. In at least one embodiment, the prefix and pixel coverage API module 110 includes an API function library for performing any one or more operations described herein. In at least one embodiment, a user or software (e.g., Figure 23 The software program 2302 in the processor 104 causes the processor 104 to call, invoke and / or otherwise execute Figure 23 In at least one embodiment, the processor 104 executes the operations and / or functions of the API to call, invoke, and / or otherwise execute the API. In at least one embodiment, the processor 104 executes the operations and / or functions of the API to receive and / or otherwise obtain the polygon input data 102 as input. In at least one embodiment, the processor 104 executes the operations and / or functions of the API to output at least a pixel grid, partial coverage, negative area, edge coverage, negative edge coverage, coverage ratio of a pixel, an indication that a pixel is within a polygon, or some combination thereof.

[0104] In at least one embodiment, the processor 104 outputs a pixel coverage ratio 112, which is data generated by the prefix and pixel coverage module 108 and / or the prefix and pixel coverage API module 110 for generating a rasterized image of the polygon input data 102. In at least one embodiment, the polygon input data 102 is referred to as a polygon dataset. In at least one embodiment, the pixel coverage ratio 112 is data that includes, for each pixel, one or more indications indicating which portion and / or amount of the pixel is covered by one or more polygons.

[0105] According to at least one embodiment, Figure 2 A block diagram of a system 200 including a prefix and pixel coverage module is shown for identifying one or more pixels within one or more polygons based at least in part on whether the one or more pixels within the one or more polygons are adjacent to one or more pixels that intersect one or more polygon edges. In at least one embodiment, one or more figures depicted herein are not drawn to scale. In at least one embodiment, the prefix and pixel coverage module 202 is at least partially implemented by Figure 1The prefix and pixel coverage module 108 is executed by the processor 104. In at least one embodiment, the prefix and pixel coverage module 202 receives and / or otherwise obtains a pixel grid 204 as input data. In at least one embodiment, the prefix and pixel coverage module 202 generates the pixel grid 204.

[0106] In at least one embodiment, the prefix and pixel coverage module 202 uses the pixel grid and polygon data to identify the location, orientation, position, or some combination thereof of the portion of the polygon edge that passes through the pixel. In at least one embodiment, the polygon includes oriented polygon edges, such as polygon edge 206.

[0107] In at least one embodiment, pixel grid 204 includes pixel points representing corners of pixels, such as pixel point 208. In at least one embodiment, prefix and pixel coverage module 202 identifies pixel edges for each pixel of pixel grid 204. In at least one embodiment, the pixel edges (or pixel boundaries) of the pixels are depicted as dark lines of pixel 210.

[0108] In at least one embodiment, Figure 2 Depicted by Figure 1 The polygon input data 102 represents a polygon that follows the convention of defining the area to the left of the polygon edge as being inside the polygon. In at least one embodiment, the convention defines the area completely enclosed by the polygon edges arranged in a counterclockwise manner as being inside the polygon. In at least one embodiment, the convention defines the area completely enclosed by the polygon edges arranged in a clockwise manner as being outside the polygon, and therefore, these areas represent holes. In at least one embodiment, the convention defines polygons arranged in a counterclockwise manner as regular polygons. In at least one embodiment, the convention defines polygons arranged in a clockwise manner as negative polygons. In at least one embodiment, the left side of a polygon edge is determined by the perspective of the end or arrow end of the polygon edge from the origin of the polygon edge. In at least one embodiment, the input polygon data defines the left side of the polygon edge pointing upward as being inside the polygon and the left side of the edge pointing downward as being outside the polygon. In at least one embodiment, any one or more aspects of one or more conventions for characterizing polygon data may be used with the techniques described herein. In at least one embodiment, Figure 2 The polygons are visualized as covering the pixel grid 204 for explanation purposes. In at least one embodiment, the prefix and pixel covering module 202 performs the operations of the system 200 to generate objects such as the pixel grid 204 and one or more polygons using data representing such objects without visualizing or displaying the objects.

[0109] Figure 3Another version of a block diagram of a system 300 is shown that includes a prefix and pixel coverage module for identifying one or more pixels within one or more polygons based at least in part on whether the one or more pixels within the one or more polygons are adjacent to one or more pixels that intersect one or more polygon edges, in accordance with at least one embodiment. Figure 3 Only one polygon is depicted, but more than one polygon may be used to identify the one or more pixels.) In at least one embodiment, the prefix and pixel coverage module 302 is at least partially implemented by Figure 1 The processor 104 executes the prefix and pixel coverage module 108. In at least one embodiment, Figure 3 Another visualization of a pixel grid is depicted, pixel grid 312, which uses dashed lines as pixel edges, such as pixel edge 306, and pixel corners as pixel points, such as pixel point 308. In at least one embodiment, a pixel grid (e.g., Figure 3 The pixel grid depicted in Figure 13 、 Figure 14 and Figure 20 In at least one embodiment, the pixel grid 304 includes pixels having N columns and N rows, and is not limited to Figure 3 The pixel columns and rows are shown. In at least one embodiment, the prefix and pixel coverage module 302 performs calculations that identify pixel coverage in parallel by each portion of a polygon edge that passes through the pixel.

[0110] Figure 4 A block diagram of a system 400 is shown, according to at least one embodiment, that includes a prefix sum pixel coverage module for identifying an amount of one or more pixels within a polygon by using, at least in part, a prefix sum of pixel edge coverages. In at least one embodiment, the prefix sum pixel coverage module 402 is at least partially implemented by Figure 1 The processor 104 executes the prefix and pixel coverage module 108. In at least one embodiment, Figure 4 An overview of how regions may be identified as covered by polygons based, at least in part, on the portion of polygon edges that pass through pixels is depicted, as further described herein. In at least one embodiment, the prefix and pixel coverage module 402 receives or generates one or more pixel grids. In at least one embodiment, the prefix and pixel coverage module 402 receives or generates two or more blank pixel grids, one of which is used to calculate partial coverage, as further described herein. In at least one embodiment, the pixel grid used to calculate partial coverage is referred to as a covered pixel grid. In at least one embodiment, another blank pixel grid is used to calculate pixel edge coverage, as further described herein in conjunction with at least one embodiment. Figures 15 to 17In at least one embodiment, the blank pixel grid used to calculate the pixel edge coverage is referred to as the used pixel edge, such as the left pixel grid or the bottom pixel grid, wherein the used pixel edge is at least combined with Figures 15 to 17 Further description.

[0111] In at least one embodiment, the prefix and pixel coverage module 402 performs the same Figure 1 Combined with the described algorithm or as a combination with Figure 1 In conjunction with an alternative algorithm to the described algorithm, one begins with two blank (zeroed) pixel grids (referred to as the overlay and left pixel grids). In at least one embodiment, the prefix sum pixel coverage module 402 determines, for each polygon edge, which pixels the polygon edges pass through. In at least one embodiment, the prefix sum pixel coverage module 402 performs an algorithm to determine, for each of the pixels determined to pass through the polygon edge, what fraction of the pixel is to the left of the polygon edge, and then adds that fraction to the overlay pixel grid. In at least one embodiment, the prefix sum pixel coverage module 402 performs an algorithm to determine, for each of the pixels determined to pass through the polygon edge, what fraction of the pixel's left is to the left of the polygon edge, and then adds that fraction to the left pixel grid. In at least one embodiment, the prefix sum pixel coverage module 402 performs the algorithm by calculating the prefix sum of each ratio for each horizontal row of the left grid. In at least one embodiment, the prefix sum pixel coverage module 402 performs an algorithm to sum (add) the ratios and / or other values ​​corresponding to each corresponding pixel in the overlay pixel grid and the left pixel grid. In at least one embodiment, the prefix and pixel coverage module 402 implements an algorithm that allows the rasterization method to parallelize steps (e.g., initial steps) across polygon edges. In at least one embodiment, the operations (e.g., addition) performed by the prefix and pixel coverage module 402 on the coverage and left grids are atomic, such that each operation on the polygon edges is independent of each other. In at least one embodiment, the operations performed by the prefix and pixel coverage module 402 along a dimension (e.g., row or column) are independent of any operations on other rows or columns.

[0112] In at least one embodiment, as further described herein, an algorithm defines an order in which prefix and pixel coverage modules determine, calculate, compute, identify, or some combination thereof using any combination of dimensions, directions, and / or orientations of pixels, pixel edges, polygon edges, or some combination thereof. In at least one embodiment, the dimensions, directions, and / or orientations include left, right, top, bottom, column, row, or some combination thereof. In at least one embodiment, the prefix and pixel coverage modules determine based on a ratio of pixels or a row of pixels to the left of a polygon edge, but rather based on a ratio of pixels and a column of pixels below a polygon edge, rather than determining based on a ratio of pixels or a row of pixels to the left of a polygon edge.

[0113] In at least one embodiment, the prefix and pixel coverage module 402 identifies different pixel coverages, as depicted by the pixel grids 404a-c. In at least one embodiment, partial coverage refers to the area of ​​a pixel that is defined by: a portion of a polygon edge that passes through the pixel; any pixel edge directly below the polygon edge; and a vertical boundary extending from the polygon edge to the bottom pixel edge of the pixel, such as Figure 4 In at least one embodiment, the areas identified in pixel grids 404a and 404b (depicted as darkened areas) are positive contributions because they are based on polygon edges pointing from right to left. In at least one embodiment, the area identified in pixel grid 404c is a negative contribution because it is based on polygon edges pointing from left to right. In at least one embodiment, positive contributing areas are referred to as positive coverage, positive pixel coverage, positive coverage, or positive area. In at least one embodiment, negative contributing areas are referred to as negative coverage, negative pixel coverage, negative coverage, or negative area.

[0114] Figure 5 A block diagram of a system 500 is shown, according to at least one embodiment, that includes a prefix sum pixel coverage module for identifying one or more pixels within a polygon by using, at least in part, a prefix sum of pixel edge coverages. In at least one embodiment, the prefix sum pixel coverage module 502 is configured at least in part by Figure 1 The processor 104 executes the prefix and pixel coverage module 108. In at least one embodiment, Figure 5 , which is further described herein. In at least one embodiment, prefix and pixel coverage module 502 identifies different pixel coverages depicted in pixel grids 504a-d. In at least one embodiment, negative contribution areas are depicted as empty space in the pixels of pixel grid 504a. In at least one embodiment, positive contribution areas fill or add to the negative contribution areas of pixel grid 504a based on left-to-right polygon edges that share vertices with right-to-left polygon edges, as shown in pixel grids 504b-d.

[0115] Figure 6 A block diagram of a system 600 including a prefix and pixel coverage module for identifying an amount of one or more pixels within a polygon based at least in part on one or more pixels intersecting one or more polygon edges is shown in accordance with at least one embodiment. In at least one embodiment, the prefix and pixel coverage module 602 is implemented at least in part by Figure 1 The processor 104 executes the prefix and pixel coverage module 108. In at least one embodiment, Figure 6 An overview of how the areas identified as covered by polygons are used to calculate the total area of ​​pixels covered by polygons is depicted, which is further described herein. In at least one embodiment, the prefix and pixel coverage module 602 combines different positive contributing areas and negative contributing areas (e.g., Figure 4 and Figure 5 ) are added together to identify the total area covered by the polygons, which is depicted as darkened areas in the pixel grid 604.

[0116] Figure 7 A block diagram of a system 700 is shown, according to at least one embodiment, that includes a prefix and pixel coverage module configured, at least in part, to execute the steps of an algorithm for identifying one or more pixels within a polygon based, at least in part, on one or more pixels intersecting one or more polygon edges. In at least one embodiment, the prefix and pixel coverage module 702 is configured, at least in part, by Figure 1 The prefix and pixel coverage module 108 is executed by the processor 104 of the processor. In at least one embodiment, the area covered by the polygon edge passing through the pixel is referred to as the partial coverage. In at least one embodiment, one or more partial coverages are added with other pixel coverage values ​​further described herein to identify the total area of ​​one or more pixels covered by the polygon.

[0117] In at least one embodiment, the prefix and pixel coverage module 702 performs one or more operations of step 1 of an algorithm comprising at least one or more of the following steps:

[0118] Step 1: Calculate partial coverage;

[0119] Step 2: Calculate pixel edge coverage;

[0120] Step 3: Calculate the prefix sum along the pixel column;

[0121] Step 4: Sum the results of step 1 and step 3;

[0122] In at least one embodiment, a step of an algorithm includes one or more operations that are performed within that step or with any step in any order. In at least one embodiment, one or more steps of an algorithm described herein and / or one or more operations thereof are performed in any order. In at least one embodiment, one or more steps of an algorithm described herein and / or one or more operations thereof are omitted and not performed.

[0123] In at least one embodiment, prefix and pixel coverage module 702 calculates the partial coverage corresponding to the darker, thicker arrow polygon side depicted as pixel grid 704a. In at least one embodiment, the portion of this polygon side is shown as an independent edge in pixel grid 704b. In at least one embodiment, these independent edges are based on the position where the polygon side intersects (or intersects) with the pixel side. In at least one embodiment, prefix and pixel coverage module 702 calculates the partial coverage depicted in pixel grid 704c based on the formula for calculating the area of ​​the trapezoid and those independent edges depicted in pixel grid 704b. In at least one embodiment, the partial coverage formula is as follows:

[0124]

[0125] In at least one embodiment, σ traps refers to the sum of the trapezoidal areas within a pixel. In at least one embodiment, h1+h2 refers to the height of the trapezoidal area being calculated. In at least one embodiment, w refers to the width of the trapezoidal area being calculated. In at least one embodiment, the height and width of a pixel are equal to 1 to simplify the calculation. In at least one embodiment, partial coverage is calculated only for pixels that intersect one or more polygon edges.

[0126] Figure 8 A block diagram of a system 800 including a prefix and pixel coverage module is shown for performing, at least in part, the steps of an algorithm for identifying one or more pixels within a polygon based, at least in part, on one or more pixels intersecting one or more polygon edges, in accordance with at least one embodiment. In at least one embodiment, the prefix and pixel coverage module 802 is implemented, at least in part, by Figure 1 The processor 104 executes the prefix and pixel coverage module 108. In at least one embodiment, Figure 8 A prefix and pixel coverage module 802 is shown that calculates the positive and negative contribution areas of a pixel, as shown in pixel grids 804a-c. In at least one embodiment, a portion of a polygon edge from left to right at least partially creates a negative coverage area of ​​-0.16 in one pixel and a negative coverage area of ​​-0.05 in another pixel, as depicted in pixel grid 804a. In at least one embodiment, a positive coverage area of ​​0.7 is created at least in part by a portion of a polygon edge from right to left. In at least one embodiment, the total area of ​​the pixels covered by the polygon is calculated by adding positive coverage area 806 to the positive coverage area 0.7 and the negative coverage area -0.16 (as shown in pixel grid 804c). In at least one embodiment, positive coverage area 806 is calculated using pixel edge coverage values ​​further described herein.

[0127] Figure 9 A block diagram of a system 900 is shown, according to at least one embodiment, that includes a prefix and pixel coverage module configured, at least in part, to execute the steps of an algorithm for identifying one or more pixels within a polygon based, at least in part, on one or more pixels intersecting one or more polygon edges. In at least one embodiment, the prefix and pixel coverage module 902 is configured, at least in part, by Figure 1 The processor 104 executes the prefix and pixel coverage module 108. In at least one embodiment, Figure 9 Exemplary partial coverage values ​​are shown. In at least one embodiment, the partial coverage value of 0.29 for pixel 906 is based on the areas bounded boundaries represented by the pixel edges and arrows. In at least one embodiment, the boundaries represented by the arrows originate at the location where a polygon edge intersects a pixel edge or where two polygon edges meet at a vertex, as depicted by pixel grid 904. In at least one embodiment, the boundaries represented by the arrows end at the bottom pixel edge, as depicted by pixel grid 904. In at least one embodiment, the partial coverage is stored in an array.

[0128] Figure 10 A block diagram of a system 1000 is shown, according to at least one embodiment, comprising a prefix and pixel coverage module configured at least in part to execute the steps of an algorithm for identifying one or more pixels within a polygon based at least in part on one or more pixels intersecting one or more polygon edges. In at least one embodiment, the prefix and pixel coverage module 1002 is configured at least in part by Figure 1 The processor 104 executes the prefix and pixel coverage module 108. In at least one embodiment, Figure 10 In at least one embodiment, the partial coverage value does not indicate the total amount of pixels covered by the polygon, for example, as indicated by the question marks depicted in the pixel grid 1004. In at least one embodiment, the partial coverage value is not indicated by the total amount of pixels covered by the polygon, for example, as indicated by the question marks depicted in the pixel grid 1004. Figures 15 to 17 Describes a technique to compute the rest of the pixel covered by a polygon.

[0129] Figure 11 A block diagram of a system 1100 including a prefix and pixel coverage module for performing, at least in part, the steps of an algorithm to identify one or more pixels within a polygon based, at least in part, on one or more pixels intersecting one or more polygon edges is shown in accordance with at least one embodiment. In at least one embodiment, the prefix and pixel coverage module 1102 is at least partially implemented by Figure 1 The processor 104 executes the prefix and pixel coverage module 108. In at least one embodiment, Figure 11 Example partial coverage values ​​and example partial coverage ratios are shown, such as partial coverage ratios 1106a, 1106b, and 1106c. In at least one embodiment, partial coverage ratios 1106a, 1106b, and 1106c are based at least in part on Figure 10 In at least one embodiment, the boundaries indicated by the arrows are identified. Figure 11 Depicted is a negative coverage area 1108 overlapping with a positive coverage 1106c.

[0130] Figure 12 A block diagram of a system 1200 including a prefix and pixel coverage module is shown for performing, at least in part, the steps of an algorithm for identifying one or more pixels within a polygon based, at least in part, on one or more pixels intersecting one or more polygon edges, in accordance with at least one embodiment. In at least one embodiment, the prefix and pixel coverage module 1202 is configured, at least in part, by Figure 1 The processor 104 executes the prefix and pixel coverage module 108. In at least one embodiment, Figure 12 Exemplary partial coverage values ​​and exemplary negative partial coverage are shown, such as negative partial coverage 1206 created by a polygon edge running from left to right. In at least one embodiment, the value of negative partial coverage 1206 is -0.28.

[0131] Figure 13 A block diagram of a system 1300 including a prefix and pixel coverage module is shown for performing, at least in part, the steps of an algorithm for identifying one or more pixels within a polygon based, at least in part, on one or more pixels intersecting one or more polygon edges, in accordance with at least one embodiment. In at least one embodiment, the prefix and pixel coverage module 1302 is implemented, at least in part, by Figure 1 The processor 104 executes the prefix and pixel coverage module 108. In at least one embodiment, Figure 13 The partial coverage created by the polygon edges from right to left is shown. In at least one embodiment, Figure 13 The partial coverages depicted in FIG (e.g., partial coverages 1306a and 1306b) are positive contributions. In at least one embodiment, pixel grid 1304 depicts each partial coverage based on the right-to-left polygon edge of the polygon as a patterned line, which is also shown in FIG. Figure 13 In at least one embodiment, the dashed arrow pointing downward represents the limit for calculating the partial coverage and is equivalent to Figure 9 . Click the down arrow in the

[0132] Figure 14A block diagram of a system 1400 is shown, according to at least one embodiment, that includes a prefix and pixel coverage module configured, at least in part, to execute the steps of an algorithm for identifying one or more pixels within a polygon based, at least in part, on one or more pixels intersecting one or more polygon edges. In at least one embodiment, the prefix and pixel coverage module 1402 is configured, at least in part, by Figure 1 The processor 104 executes the prefix and pixel coverage module 108. In at least one embodiment, Figure 14 The negative area created by the polygon edges from left to right is shown. In at least one embodiment, Figure 14 The negative areas identified in (eg, negative areas 1406a and 1406b) are based on left-to-right polygon edges passing through the pixel.

[0133] Figure 15 A block diagram of a system 1500 including a prefix and pixel coverage module is shown for performing, at least in part, the steps of an algorithm for identifying one or more pixels within a polygon by using the amount of one or more edges of one or more pixels covered by one or more edges of the polygon, in accordance with at least one embodiment. In at least one embodiment, the prefix and pixel coverage module 1502 is at least in part provided by Figure 1 The processor 104 executes the prefix and pixel coverage module 108. In at least one embodiment, Figure 15The bottom pixel edge coverage and the negative bottom pixel edge coverage are shown. In at least one embodiment, the pixel intersects two parts of two different polygon edges pointing from right to left, and therefore, it includes two partial coverages of 0.36 and 0.11, as depicted in pixel grid 1504a. In at least one embodiment, 0.36 and 0.11 represent fractions of the total width of the pixel. In at least one embodiment, each pixel of the pixel grid has a height and width of 1.00, as depicted in pixel grid 1504a. In at least one embodiment, the prefix and pixel coverage module 1502 performs an operation to use the bottom pixel edge coverage as the width value to calculate the edge-based pixel coverage. In at least one embodiment, the prefix and pixel coverage module 1502 performs an operation to generate a projection of the scalar x component of the polygon edge portion 1506 on the bottom pixel edge, which is used as the bottom pixel edge coverage. In at least one embodiment, the prefix and pixel coverage module 1502 performs an operation to multiply the bottom pixel edge coverage (0.36) and the pixel height (1.00) to generate an edge-based pixel coverage of 0.36. In at least one embodiment, the prefix and pixel coverage module 1502 performs an operation to calculate the negative edge-based pixel coverage using the same operation as used to calculate the edge-based pixel coverage area (except that -1 is multiplied by a value such as a negative bottom pixel edge coverage or a negative edge-based pixel coverage). In at least one embodiment, the pixel point grid 1504b depicts the bottom pixel edge coverage as a solid black line and the negative bottom pixel edge coverage as a dashed line.

[0134] Figure 16 A block diagram of a system 1600 including a prefix and pixel coverage module is shown for performing, at least in part, the steps of an algorithm for identifying one or more pixels within a polygon by using the amount of one or more edges of one or more pixels covered by one or more edges of the polygon, in accordance with at least one embodiment. In at least one embodiment, the prefix and pixel coverage module 1602 is at least in part provided by Figure 1 The processor 104 executes the prefix and pixel coverage module 108. In at least one embodiment, Figure 16 A negative bottom pixel edge coverage of -0.2 and a corresponding negative edge-based pixel coverage are shown.In at least one embodiment, pixel grid 1604b depicts the partial coverage and edge-based pixel coverage calculated as a result of two polygon edge portions 1606a and 1606b.

[0135] Figure 17A block diagram of a system 1700 is shown, according to at least one embodiment, that includes a prefix sum pixel coverage module configured, at least in part, to perform one or more prefix sum operations along one or more dimensions to identify an amount of one or more pixels within a polygon. In at least one embodiment, the prefix sum pixel coverage module 1702 is configured, at least in part, by Figure 1 17. The processor 104 of FIG. 17 shows a prefix sum pixel coverage module 108 executed by the processor 104. In at least one embodiment, the non-italicized numbers shown in the pixel grid 1704 represent the bottom pixel edge coverage of each pixel. In at least one embodiment, the italicized numbers shown in the pixel grid 1704 represent the prefix sum of the bottom pixel edge coverage. In at least one embodiment, the prefix sum pixel coverage module 1702 performs the prefix sum of the bottom pixel edge coverage by advancing each column of pixels downward (shown by the dotted line pointing downward). In at least one embodiment, the prefix sum pixel coverage module 1702 performs the prefix sum of the bottom edge coverage by performing the prefix sum on the amount of pixels covered by the polygon edge.

[0136] In at least one embodiment, prefix sum is an algorithm that includes one or more summation operations. In at least one embodiment, prefix sum is referred to as cumulative sum, inclusive scan, or scan. In at least one embodiment, prefix sum (or multiple prefix sums) is a sequence of digits (values) in which, at least in part, each digit is the sum of the digits preceding it. In at least one embodiment, prefix sum pixel coverage module 1702 performs any type of prefix sum, such as inclusive and / or exclusive prefix sums. In at least one embodiment, prefix sum pixel coverage module 1702 performs any type of prefix sum, such as inclusive and / or exclusive prefix sums. In at least one embodiment, prefix sum pixel coverage module 1702 performs any one or more techniques of any type of prefix sum.

[0137] In at least one embodiment, the prefix sum pixel coverage module 1704 stores the bottom pixel edge coverage in an indexed array such that each bottom pixel edge coverage is associated with its corresponding pixel. In at least one embodiment, the prefix sum pixel coverage module 1704 stores the prefix sum values ​​in an indexed array such that each prefix sum value is associated with its corresponding pixel. In at least one embodiment, the bottom pixel edge coverage is referred to as the raw input, and the prefix sum value is referred to as the sum output. In at least one embodiment, the prefix sum pixel coverage module 1702 assigns a default initial prefix sum value of 0.0 to each pixel at the top of each column of pixels. In at least one embodiment, for each pixel at the top of each column, the prefix sum pixel coverage module 1702 adds the bottom pixel edge coverage to the default initial prefix sum value of 0.0. In at least one embodiment, for the top left pixel of the pixel grid 1704, the prefix sum pixel coverage module 1702 adds the bottom pixel edge coverage (0.2) to the default initial prefix sum value (0.0) to generate another next prefix sum value of 0.2. In at least one embodiment, for pixels adjacent to and below the top left corner pixel of the pixel grid 1704, the prefix sum pixel coverage module 1702 adds a negative bottom pixel edge coverage (-0.2) to the prefix sum value of 0.2 to generate another next prefix sum value of 0.0. In at least one embodiment, the prefix sum pixel coverage module 1702 calculates prefix sum values ​​based on the bottom pixel edge coverage of each pixel, wherein these prefix sum values ​​at least partially indicate the amount of the pixel covered by the polygon. In at least one embodiment, the prefix sum values ​​(sum output) calculated by the prefix sum pixel coverage module 1702 each represent the proportion of the top edge of each pixel that is partially covered by one or more polygon edges above each pixel.

[0138] Figure 18 A block diagram of a system 1800 is shown that includes a prefix sum pixel coverage module configured, at least in part, to perform an operation of adding a fractional coverage to a summed output of a prefix sum operation to identify an amount of one or more pixels within a polygon, in accordance with at least one embodiment. In at least one embodiment, the prefix sum pixel coverage module 1802 is configured, at least in part, by Figure 1 In at least one embodiment, the prefix and pixel coverage module 1802 receives and / or otherwise obtains the partial coverages stored as one or more arrays in one or more storage locations and the prefix summed edge coverage values. In at least one embodiment, the sum output is depicted as an italicized number and is the result of performing a prefix sum on the bottom pixel edge coverages, as described herein at least in conjunction with Figure 17In at least one embodiment, the non-italicized numbers shown in the pixel grid 1804 represent the partial coverage of each pixel. In at least one embodiment, the prefix sum pixel coverage module 1802 performs a summation of the partial coverage with the sum output of the previously calculated bottom pixel edge coverage (prefix sum value), as combined with Figure 17 In at least one embodiment, summing the partial coverage with the sum output for each pixel can generate a total pixel coverage, as further described herein. In at least one embodiment, the prefix sum pixel coverage module 1802 performs the summation operation in parallel per pixel.

[0139] Figure 19 A block diagram of a system 1900 is shown that includes a prefix and pixel coverage module configured, at least in part, to perform operations to generate a total pixel coverage ratio for identifying an amount of one or more pixels within a polygon. In at least one embodiment, the total pixel coverage ratio is referred to as a coverage fraction of the pixel. In at least one embodiment, Figure 19 The values ​​depicted in are coverage ratios that have been rounded up and / or down according to rounding conventions. In at least one embodiment, Figure 19 The values ​​depicted in are coverage ratios that have not been rounded up or down. In at least one embodiment, the prefix and pixel coverage module 1902 is at least partially composed of Figure 1 The prefix sum pixel coverage module 108 is executed by the processor 104 of the processor 104. In at least one embodiment, the prefix sum pixel coverage module 1902 performs an operation to sum (add) the partial coverage with the prefix summed edge coverage. In at least one embodiment, summing the partial coverage with the prefix summed edge coverage includes summing the negative area with the prefix summed negative pixel edge coverage. In at least one embodiment, the numbers depicted in the pixel grid 1904 are the total pixel coverage. In at least one embodiment, the non-italic numbers shown in the pixel grid 1804 represent the partial coverage of each pixel. In at least one embodiment, the prefix sum pixel coverage module 1802 performs the summation of the partial coverage with the previously calculated sum output of the bottom pixel edge coverage (the prefix sum value), as combined Figure 17 In at least one embodiment, summing the partial coverage with the sum output for each pixel can generate a total pixel coverage, as further described herein. In at least one embodiment, the prefix and pixel coverage module 1802 performs the summation operation in parallel per pixel.

[0140] Figure 20A block diagram of a system 2000 is shown, according to at least one embodiment, comprising a prefix and pixel coverage module configured, at least in part, to perform operations to calculate total pixel coverage by combining partial coverage, negative area, edge-based pixel coverage, and edge-based negative pixel coverage. In at least one embodiment, the prefix and pixel coverage module 2002 is configured, at least in part, by Figure 1 The prefix and pixel coverage module 108 is executed by the processor 104. In at least one embodiment, the pixel grids 2004a-c depict a column of pixels, wherein the prefix and pixel coverage module 2002 has calculated one or more pixel coverage, negative area, edge-based pixel coverage, and edge-based negative pixel coverage, or some combination thereof. In at least one embodiment, the pixel grids 2004a-c depict at least a portion of a pixel grid and at least a portion of a polygon, such as Figure 3 、 Figure 13 and Figure 14 In at least one embodiment, the pixel grids 2004a-c use Figure 3 、 Figure 13 and Figure 14 One or more visual representations of one or more aspects of one or more embodiments used in the present invention depict at least a portion of a grid of pixels and at least a portion of a polygon.

[0141] In at least one embodiment, the pixel grid 2004a depicts the portion of pixels with positive contributions using positive (plus) signs. In at least one embodiment, the pixel grid 2004a depicts the partial coverage calculated by the prefix and pixel coverage module 2002, such as partial coverage 2006. In at least one embodiment, the partial coverage is represented by Figure 20 In at least one embodiment, the pixel grid 2004a depicts edge-based pixel coverage calculated by the prefix and pixel coverage module 2002, such as edge-based pixel coverage 2008. In at least one embodiment, the edge-based pixel coverage is represented by Figure 20 In at least one embodiment, the pixel grid 2004a depicts a portion of a pixel having at least two positive contributions with at least two positive symbols. In at least one embodiment, the portion of a pixel having at least two positive contributions is depicted in Figure 20In at least one embodiment, the prefix and pixel coverage module 2002 calculates a positive coverage that includes an edge-based pixel coverage and a partial coverage based on the right-to-left polygon edge 2012b, such as the positive coverage 2010. In at least one embodiment, the prefix and pixel coverage module 2002 calculates a positive coverage that includes two separate edge-based pixel coverages, such as the positive coverage 2011, where one such coverage is based on the right-to-left polygon edge 2012a and another such coverage is based on the right-to-left polygon edge 2012b.

[0142] In at least one embodiment, pixel grid 2004b uses a negative (minus) sign to represent a portion of pixels with negative contributions. Figure 20 2014. In at least one embodiment, the pixel grid 2004b depicts negative areas calculated by the prefix and pixel coverage module 2010, such as negative area 2014. In at least one embodiment, the pixel grid 2004b depicts negative edge-based pixel coverages. In at least one embodiment, the pixel grid 2004b depicts negative edge-based pixel coverages, such as negative edge-based pixel coverage 2015. In at least one embodiment, the pixel grid 2004b depicts areas where two or more negative edge-based pixel coverages overlap, such as negative edge-based pixel coverage 2016, which is indicated by two negative (minus) signs.

[0143] In at least one embodiment, pixel grid 2004c depicts the total pixel coverage for each pixel in a column of the pixel grid. In at least one embodiment, prefix sum pixel coverage module 2002 calculates the total pixel coverage by summing any partial coverages, negative areas, edge-based pixel coverages, and edge-based negative pixel coverages calculated in conjunction with the pixels, such as total pixel coverages 2018a and 2018b. In at least one embodiment, the sum of the positive and negative coverages for pixel grids 2004a and 2004b results in a single positive contribution value or zero corresponding to each pixel of the pixel grids. In at least one embodiment, each single positive contribution of pixel grid 2004c represents the total pixel coverage for each pixel used to identify whether each pixel is within a polygon. In at least one embodiment, the sum or combination of two or more positive and / or negative coverages based on edge-based pixel coverages is referred to as a total edge coverage, such as total edge coverage 2020.

[0144] Figure 21A block diagram of process 2100 is shown for identifying one or more pixels within a polygon by determining whether the one or more pixels within the polygon are adjacent to one or more pixels that intersect one or more polygon boundaries, in accordance with at least one embodiment. In at least one embodiment, any operation of process 2100 includes one or more operations. In at least one embodiment, the operations of process 2100 are performed in a different order. In at least one embodiment, at least one operation of process 2100 is omitted. In at least one embodiment, in conjunction with Figure 21 One or more aspects of one or more embodiments described herein may be combined with one or more aspects of one or more embodiments described herein (including at least one embodiment in combination with Figures 1-20 and Figure 22-23 In at least one embodiment, one or more processors perform one or more operations of process 2100. In at least one embodiment, any one or more processors described herein include one or more circuits. In at least one embodiment, the one or more processors performing one or more operations of process 2100 are any one or combination of processors described herein, including Figure 1 processor 104, Figure 31 CPU 3100, Figure 33B Graphics processor 3340, Figure 34B General-Purpose Graphics Processing Unit (GPGPU) 3430 and Figure 40 In at least one embodiment, the processor 104 performs operations used by the system 100, such as loading / storing the sum output of the prefix-summed bottom edge pixel coverage calculated using operation 2106 in the arithmetic logic unit (ALU), for example Figure 37 ALU 3716 and ALU 3718. In at least one embodiment, processor 104 performs at least one operation of process 2100, such as the operation for calculating bottom pixel edge coverage, as described with operation 2106. In at least one embodiment, one or more processors perform the operation of process 2100 by using Figure 1 The one or more processors perform one or more operations of process 2100 by using one or more API functions to calculate coverage using a prefix sum of coverages, such as in combination with at least one of the one or more API functions of the one or more processors. Figure 22 and Figure 23 described.

[0145] In at least one embodiment, one or more processors begin process 2100 by executing operation 2102 to receive polygon input data. In at least one embodiment, the polygon data includes data representing one or more polygons to be rasterized into pixel representations. In at least one embodiment, the polygon data is to be rasterized for display on a display device and / or printed by a printing device. In at least one embodiment, the polygon data is used to design and / or manufacture semiconductors using computational lithography. In at least one embodiment, one or more operations in operation 2102 are combined with at least Figure 1 Further described herein.

[0146] In at least one embodiment, one or more processors continue process 2100 by performing operation 2104 to calculate the partial coverage of the pixel. In at least one embodiment, calculating the partial coverage of the pixel includes calculating the negative area. In at least one embodiment, calculating the partial coverage of the pixel is combined with at least Figures 8-14 Further described herein.

[0147] In at least one embodiment, the one or more processors continue process 2100 by performing operation 2106 to calculate bottom pixel edge coverage. In at least one embodiment, the one or more processors use the bottom pixel edge coverage to calculate pixel coverage for those pixels that do not have polygon edges that intersect the pixel. Figure 15-17 The calculation of bottom pixel edge coverage is further described.

[0148] In at least one embodiment, the one or more processors continue process 2100 by performing operation 2108 to perform a prefix sum of the bottom pixel edge coverage by column. In at least one embodiment, the one or more processors perform operation 2018 by calculating a prefix sum by a dimension other than column (e.g., row dimension). In at least one embodiment, the one or more processors perform operation 2018 to perform a prefix sum of the pixel edge coverage of pixel edges other than the bottom pixel edge (e.g., right pixel edge, left pixel edge, or top pixel edge). In at least one embodiment, at least one Figure 17 Performing a prefix sum of bottom pixel edge coverage is further described.

[0149] In at least one embodiment, one or more processors continue process 2100 by performing operation 2010 to sum the partial coverage with the prefix-summed bottom pixel edge coverage. In at least one embodiment, operation 2010 includes summing the partial coverage with the negative area. In at least one embodiment, operation 2010 includes prefix summing the prefix sum including the negative bottom pixel edge coverage and the bottom pixel edge coverage. Figure 19and Figure 20 Further description is made of summing the partial coverage and the prefix-summed bottom pixel edge coverage.

[0150] In at least one embodiment, the one or more processors continue process 2100 by performing operation 2012 to output a coverage fraction (fraction) of the pixel. In at least one embodiment, the coverage fraction of the pixel is referred to as the total pixel coverage. In at least one embodiment, the one or more processors output the coverage fraction of each pixel of the pixel grid. In at least one embodiment, each coverage fraction of the pixel is used to identify whether the pixel is within the polygon and should therefore be generated, displayed, printed and / or otherwise activated as part of the process of rasterizing the polygon data. In at least one embodiment, outputting the coverage fraction of the pixel is at least combined with Figure 1 and Figure 19 Further described herein.

[0151] Figure 22 A block diagram of a process 2200 for using a processor to execute one or more API functions that causes the one or more processors to perform operations to identify one or more pixels within one or more polygons by determining whether the one or more pixels within the one or more polygons are adjacent to one or more pixels that intersect one or more polygon boundaries. In at least one embodiment, the present invention is combined with Figure 22 One or more aspects of one or more embodiments described herein may be combined with one or more aspects of one or more embodiments described herein, including at least one aspect of one or more embodiments described herein. Figures 1-21 and Figure 23 In at least one embodiment, one or more processors perform one or more operations of process 2200. In at least one embodiment, any one or more processors described herein include one or more circuits. In at least one embodiment, the one or more processors performing one or more operations of process 2200 are any one or combination of processors described herein, including Figure 1 processor 104, Figure 31 CPU 3100, Figure 33B Graphics processor 3340, Figure 34B General-Purpose Graphics Processing Unit (GPGPU) 3430 and Figure 40 In at least one embodiment, Figure 1The processor 104 of the system performs one or more operations of process 2200, such as executing an API function to calculate a prefix sum of bottom edge prefix coverage, as further described herein. In at least one embodiment, the one or more processors for performing process 2200 perform one or more operations of system 100 to identify one or more pixels within one or more polygons, as further described herein. In at least one embodiment, the one or more processors for performing process 2200 perform one or more operations of prefix sum pixel coverage API module 110 to execute an API function to calculate pixel coverage using the prefix sum of bottom pixel edge coverage of operation 2204.

[0152] In at least one embodiment, one or more processors perform process 2200 by performing operation 2202 to input polygon data into an API function called by software or a user. In at least one embodiment, the polygon data includes data representing one or more polygons to be rasterized into pixel representations. In at least one embodiment, the polygon data will be rasterized for display on a display device and / or printed by a printing device. In at least one embodiment, the polygon data is used to design and / or manufacture semiconductors using computational lithography. In at least one embodiment, the present invention is at least in conjunction with Figure 1 One or more operations of operation 2102 are further described.

[0153] In at least one embodiment, the one or more processors continue with operation 2204 of process 2200 by causing execution of one or more API functions to calculate pixel coverage using a prefix sum of bottom pixel edge coverage. In at least one embodiment, the one or more API functions that calculate pixel coverage using a prefix sum of bottom pixel edge coverage are one or more functions executed by the one or more processors to identify partial coverage, negative area, bottom pixel edge coverage, negative bottom pixel edge coverage, total pixel coverage, a prefix sum, or some combination thereof. In at least one embodiment, the one or more API functions that calculate pixel coverage using a prefix sum of bottom pixel edge coverage cause the one or more processors to allocate a memory location in one or more data storage locations to store the partial coverage, negative bottom pixel edge coverage, total pixel coverage, a prefix sum, or some combination thereof. In at least one embodiment, the one or more API functions executed using operation 2204 perform, at least in part, any one or more operations for identifying one or more pixels within a polygon, as further described herein.

[0154] In at least one embodiment, the one or more processors continue process 2200 by performing one or more operations to output the coverage ratio of the pixel. In at least one embodiment, the one or more processors execute one or more API functions to output the coverage ratio of the pixel for use by the one or more processors to identify whether the pixel is within the polygon. In at least one embodiment, the one or more processors identifying the one or more pixels within the polygon cause the one or more pixels to be generated, displayed, printed, and / or otherwise manipulated as described elsewhere herein.

[0155] Figure 23 A block diagram of a driver and / or runtime according to at least one embodiment is shown, which includes one or more libraries for providing one or more application programming interfaces (APIs). In at least one embodiment, any one processor or combination of processors executes API 2310, including Figure 1 processor 104, Figure 31 CPU 3100, Figure 33B Graphics processor 3340, Figure 34B General-Purpose Graphics Processing Unit (GPGPU) 3430 and Figure 40 In at least one embodiment, the API 2310 is further described herein. In at least one embodiment, the call of the API 2310 causes one or more processors to perform one or more operations of any one or more modules described herein (e.g., prefix and pixel coverage module 108). In at least one embodiment, the call of the API 2310 causes one or more processors to perform operations in conjunction with Figure 1-Figure 22 In at least one embodiment, the API 2310 receives polygon input data or an indication thereof as input and causes Figure 1 The prefix sum pixel coverage module 108, and thus any prefix sum pixel coverage module described herein, performs operations for identifying one or more pixels within a polygon by, at least in part, determining whether neighboring pixels intersect one or more polygon edges. In at least one embodiment, one or more APIs 2310 and / or functions for calculating pixel coverage using prefix sum 2312 are executed by one or more processors to perform one or more operations of process 2200, including operation 2204.

[0156] In at least one embodiment, software program 2302 is a software module. In at least one embodiment, software program 2302 includes one or more software modules. In at least one embodiment, one or more APIs 2310 are software instruction sets that, if executed, cause one or more processors to perform one or more computing operations. In at least one embodiment, one or more APIs 2310 are distributed or otherwise provided as part of one or more libraries 2306, runtimes 2304, drivers 2304, and / or any other grouping of software and / or executable code described further herein. In at least one embodiment, one or more APIs 2310 perform one or more computing operations in response to a call from software program 2302. In at least one embodiment, software program 2302 is a collection of software code, commands, instructions, or other text sequences that instruct a computing device to perform one or more computing operations and / or call one or more other instruction sets (e.g., APIs 2310 or functions 2312) for execution. In at least one embodiment, the functionality provided by the one or more APIs 2310 includes software functions, such as software functions that can be used to accelerate one or more portions of the software program 2302 using one or more parallel processing units (PPUs), such as graphics processing units (GPUs). In at least one embodiment, the software program is a compiler.

[0157] In at least one embodiment, the API 2310 is a hardware interface to one or more circuits for performing one or more computing operations. In at least one embodiment, the one or more software APIs 2310 described herein are implemented as one or more circuits for performing one or more techniques described herein. In at least one embodiment, the one or more software programs 2302 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform one or more techniques further described herein.

[0158] In at least one embodiment, a software program 2302 (e.g., a user-implemented software program) utilizes one or more application programming interfaces (APIs) 230 to perform various computational operations, such as memory reservations, matrix multiplications, arithmetic operations, or any computational operations performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, one or more APIs 2310 provide a set of callable functions 2312 (referred to herein as APIs, API functions, and / or functions) that each perform one or more computational operations, such as computational operations associated with parallel computing. For example, in one embodiment, one or more APIs 2310 provide functions 2312 that enable a scheduler to schedule instructions for execution by a processor based on the latency of an interconnect coupled to the processors. In at least one embodiment, the API 2310 provides one or more functions 2312 that are one or more neural networks, such as neural networks trained to improve processor efficiency during rasterization. In at least one embodiment, the API 2310 is stored in memory 2314. In at least one embodiment, API 2310 includes API functions that enable one or more processors to receive and / or otherwise obtain Figure 1 In at least one embodiment, the API functions of API 2310 enable one or more processors to receive and / or otherwise obtain vertex data from a vertex buffer, such as In at least one embodiment, the API function of API 2310 causes one or more processors to output a rasterized image of input polygon data and / or geometric primitives by at least partially writing data to buffers and / or arrays, the rasterized image indicating which geometric primitives should be represented by pixels and / or how these primitives should be represented by pixels. In at least one embodiment, the API function of API 2310 causes one or more processors to output a rasterized image of input polygon data and / or geometric primitives by at least partially writing data to buffers and / or arrays. The fragment shader module of the API library uses the API to output a rasterized image of the input polygon data.

[0159] In at least one embodiment, one or more software programs 2302 interact with or otherwise communicate with one or more APIs 2310 to perform one or more computing operations using one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more computing operations using the one or more PPUs include at least one or more groups of computing operations that are accelerated by being performed at least in part by the one or more PPUs. In at least one embodiment, the one or more software programs 2302 interact with the one or more APIs 2310 to facilitate parallel computing using remote or local interfaces.

[0160] In at least one embodiment, an interface is software instructions that, if executed, provide access to one or more functions 2312 provided by one or more APIs 2310. In at least one embodiment, a software program 2302 uses a native interface when a software developer compiles one or more software programs 2302 in conjunction with one or more libraries 2306 that include or otherwise provide access to one or more APIs 2310. In at least one embodiment, one or more libraries 2306 are API libraries used in graphics processing (e.g., and In at least one embodiment, the one or more software programs 2302 are statically compiled with precompiled libraries 2306 or uncompiled source code including instructions for executing the one or more APIs 2310. In at least one embodiment, the one or more software programs 2302 are dynamically compiled and linked to the one or more precompiled libraries 2306 including the one or more APIs 2310 using a linker.

[0161] In at least one embodiment, a software program 2302 uses a remote interface when a software developer executes a software program that utilizes a library 2306 including one or more APIs 2310 or otherwise communicates with a library 2306 including one or more APIs 2310 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 2306 including one or more APIs 2310 are executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, the one or more libraries 2306 including one or more APIs 2310 are executed by any other computing host that provides the one or more APIs 2310 to the one or more software programs 2302.

[0162] In at least one embodiment, a processor executing or using one or more software programs 2302 calls, uses, executes, or otherwise implements one or more APIs 2310 to allocate and otherwise manage memory to be used by the software programs 2302. In at least one embodiment, one or more software programs 2302 utilize one or more APIs 2310 to allocate and otherwise manage memory to be used by one or more portions of the software programs 2302 for acceleration using one or more PPUs (e.g., GPUs or any other accelerators or processors described further herein). These software programs 2302 can be executed by one or more processors using functions 2312, which in one embodiment are provided by one or more APIs 2310, based at least in part on the latency of an interconnect coupling to the one or more processors.

[0163] In at least one embodiment, API 2310 is an API for facilitating parallel computing. In at least one embodiment, API 2310 is any other API described further herein. In at least one embodiment, API 2310 is provided by a driver and / or runtime 2304. In at least one embodiment, API 2310 is provided by a CUDA user-mode driver. In at least one embodiment, API 2310 is provided by a CUDA runtime. In at least one embodiment, driver 2304 is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 2312 of API 2310 during the loading and execution of one or more portions of software program 2302. In at least one embodiment, runtime 2304 is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 2312 of API 2310 during the execution of software program 2302. In at least one embodiment, one or more software programs 2302 utilize one or more APIs 2310 implemented or otherwise provided by a driver and / or runtime 2304 to perform combined arithmetic operations by the one or more software programs 2302 during execution by one or more PPUs (e.g., GPUs).

[0164] In at least one embodiment, one or more software programs 2302 utilize one or more APIs 2310 provided by a driver and / or runtime 2304 to perform combinatorial arithmetic operations for one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more APIs 2310 provide combinatorial arithmetic operations through the driver and / or runtime 2304, as described above. In at least one embodiment, one or more software programs 2302 utilize one or more APIs 2310 provided by the driver and / or runtime 2304 to allocate or otherwise reserve one or more blocks of memory 2314 for one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 2302 utilize one or more APIs 2310 provided by the driver and / or runtime 2304 to allocate or otherwise reserve blocks of memory. In at least one embodiment, the one or more APIs 2310 are used to perform the combinatorial mathematical functions described herein.

[0165] In at least one embodiment, to improve the usability of the software program 2302 and / or optimize one or more portions of the software program 2302 for acceleration by one or more PPUs (e.g., GPUs), one or more APIs 2310 provide one or more API functions 2312 to implement a scheduling system that can be used or utilized by one or more computing devices as described herein. In at least one embodiment, a processor executes one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, the processor uses the API to cause a scheduler to select a thread selection mechanism and / or otherwise perform operations as described herein. In at least one embodiment, the API calls a scheduler to perform resource allocation. In at least one embodiment, the processor uses the exemplary API to schedule one or more instructions for execution by one or more processors based at least in part on the latency of one or more interconnects coupled to the one or more processors.

[0166] In at least one embodiment, the memory 2314 is the system memory 2904 of the computing system 2900. In at least one embodiment, the memory 2314 is any form of hardware that stores data and is referred to as storage or data storage. In at least one embodiment, the memory 2314 is Figure 1 In at least one embodiment, the memory 2314 is installed in the Figure 1 Components on the processor 104. In at least one embodiment, the memory 2314 is installed Figure 1Prefix and pixel coverage API module 110 components. In at least one embodiment, the memory 2314 stores data used in various operations described herein, including Figure 1 In at least one embodiment, the memory 2314 stores data used in various operations described herein, including partial coverage, negative area, bottom pixel edge coverage, negative bottom pixel edge coverage, total pixel coverage, and at least one embodiment of the present invention. Figure 1 and Figure 7-Figure 22 Other data as described.

[0167] In at least one embodiment, the memory 2314 is a computer-readable storage medium and / or code stored on the computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. Figure 1 At least some of the computer-readable instructions for the related operations are not stored using only transient signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuits (e.g., buffers, caches, and queues) within a transceiver of transient signals. In at least one embodiment, the memory 2314 is implemented as a non-transitory computer-readable storage medium storing executable instructions that, if executed by one or more processors of a computer system, cause the computer system to infer the instructions for performing at least one operation in conjunction with the operation. Figure 1-Figure 22 Describes the architectural design of a computer system for one or more operations.

[0168] Data Center

[0169] Figure 24 An example data center 2400 is shown in accordance with at least one embodiment. In at least one embodiment, the data center 2400 includes, but is not limited to, a data center infrastructure layer 2410, a framework layer 2420, a software layer 2430, and an application layer 2440.

[0170] In at least one embodiment, Figure 24As shown, the data center infrastructure layer 2410 may include a resource coordinator 2412, grouped computing resources 2414, and node computing resources ("node CRs") 2416(1)-2416(N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 2416(1)-2416(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), data processing units ("DPUs") in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 2416(1)-2416(N) may be servers having one or more of the above-mentioned computing resources.

[0171] In at least one embodiment, Figure 24 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, node computing resources ("node CRs") 716(1)-716(N) perform one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0172] In at least one embodiment, the grouped computing resources 2414 may include separate groups of node CRs housed in one or more racks (not shown), or may include many racks (also not shown) housed in data centers at various geographic locations. The separate groups of node CRs within the grouped computing resources 2414 may include computing, networking, memory, or storage resources that may be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0173] In at least one embodiment, resource coordinator 2412 may configure or otherwise control one or more nodes CR 2416(1)-2416(N) and / or grouped computing resources 2414. In at least one embodiment, resource coordinator 2412 may comprise a software design infrastructure ("SDI") management entity for data center 2400. In at least one embodiment, resource coordinator 2412 may comprise hardware, software, or some combination thereof.

[0174] In at least one embodiment, Figure 24 As shown, the framework layer 2420 includes, but is not limited to, a job scheduler 2432, a configuration manager 2434, a resource manager 2436, and a distributed file system 2438. In at least one embodiment, the framework layer 2420 may include a framework that supports the software 2452 of the software layer 2430 and / or one or more applications 2442 of the application layer 2440. In at least one embodiment, the software 2452 or the application 2442 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 2420 may be, but is not limited to, a free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 2438 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 2432 may include a Spark driver to facilitate scheduling of workloads supported by the various layers of the data center 2400. In at least one embodiment, the configuration manager 2434 may be capable of configuring the various layers, such as the software layer 2430 and the framework layer 2420 including Spark and a distributed file system 2438 for supporting large-scale data processing. In at least one embodiment, the resource manager 2436 may be capable of managing the mapping or allocation of clustered or grouped computing resources used to support the distributed file system 2438 and the job scheduler 2432. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 2414 on the data center infrastructure layer 2410. In at least one embodiment, the resource manager 2436 may coordinate with the resource coordinator 2412 to manage these mapped or allocated computing resources.

[0175] In at least one embodiment, the software 2452 included in the software layer 2430 may include software used by at least a portion of the node CRs 2416(1)-2416(N), the grouped computing resources 2414, and / or the distributed file system 2438 of the framework layer 2420. The one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0176] In at least one embodiment, the one or more applications 2442 included in the application layer 2440 may include one or more types of applications used by at least a portion of the node CRs 2416(1)-2416(N), the grouped computing resources 2414, and / or the distributed file system 2438 of the framework layer 2420. In at least one embodiment, the one or more types of applications may include, but are not limited to, CUDA applications.

[0177] In at least one embodiment, any of configuration manager 2434, resource manager 2436, and resource coordinator 2412 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 2400 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0178] Computer-based systems

[0179] The following figures set forth, but are not limiting of, exemplary computer-based systems that can be used to implement at least one embodiment.

[0180] Figure 25 A processing system 2500 is shown according to at least one embodiment. In at least one embodiment, system 2500 includes one or more processors 2502 and one or more graphics processors 2508, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2502 or processor cores 2507. In at least one embodiment, processing system 2500 is a processing platform contained within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices. In at least one embodiment, processor cores 2507 are referred to as computational units or arithmetic units.

[0181] In at least one embodiment, Figure 25 At least one component shown or described is used to implement the combination Figure 1-23In at least one embodiment, the processing system 2500 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0182] In at least one embodiment, the processing system 2500 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console, including a gaming and media console. In at least one embodiment, the processing system 2500 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 2500 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2500 is a television or set-top box device having one or more processors 2502 and a graphical interface generated by one or more graphics processors 2508.

[0183] In at least one embodiment, one or more processors 2502 each include one or more processor cores 2507 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2507 is configured to process a specific instruction set 2509. In at least one embodiment, the instruction set 2509 can facilitate complex instruction set computing ("CISC"), reduced instruction set computing ("RISC"), or computing via very long instruction words ("VLIW"). In at least one embodiment, multiple processor cores 2507 can each process a different instruction set 2509, which can include instructions that facilitate emulating other instruction sets. In at least one embodiment, the processor cores 2507 can also include other processing devices, such as a digital signal processor ("DSP").

[0184] In at least one embodiment, the processor 2502 includes a cache memory (cache) 2504. In at least one embodiment, the processor 2502 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared among various components of the processor 2502. In at least one embodiment, the processor 2502 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may share this logic among the processor cores 2507 using known cache coherence techniques. In at least one embodiment, the processor 2502 further includes a register file 2506. The processor 2502 may include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. In at least one embodiment, the register file 2506 may include general purpose registers or other registers.

[0185] In at least one embodiment, one or more processors 2502 are coupled to one or more interface buses 2510 to transmit communication signals, such as address, data, or control signals, between the processors 2502 and other components in the system 2500. In at least one embodiment, the interface bus 2510 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 2510 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express ("PCIe")), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2502 includes an integrated memory controller 2516 and a platform controller hub 2530. In at least one embodiment, the memory controller 2516 facilitates communication between storage devices and other components of the processing system 2500, while the platform controller hub ("PCH") 2530 provides connectivity to input / output ("I / O") devices via a local I / O bus. In at least one embodiment, the one or more peripheral component interconnect buses include PCIe Gen 5, which provides an interface to the processors.

[0186] In at least one embodiment, the storage device 2520 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or a device having suitable performance for use as processor memory. In at least one embodiment, the storage device 2520 can be used as system memory for the processing system 2500 to store data 2522 and instructions 2521 for use when one or more processors 2502 execute applications or processes. In at least one embodiment, the memory controller 2516 is also coupled to an optional external graphics processor 2512, which can communicate with one or more graphics processors 2508 in the processor 2502 to perform graphics and media operations. In at least one embodiment, a display device 2511 can be connected to the processor 2502. In at least one embodiment, the display device 2511 can include one or more internal display devices, such as in a mobile electronic device or portable computer device, or an external display device connected via a display interface (such as a DisplayPort, etc.). In at least one embodiment, the display device 2511 may include a head-mounted display (“HMD”), such as a stereoscopic display device used in virtual reality (“VR”) applications or augmented reality (“AR”) applications.

[0187] In at least one embodiment, the platform controller hub 2530 enables peripheral devices to be connected to the storage device 2520 and the processor 2502 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 2546, a network controller 2534, a firmware interface 2528, a wireless transceiver 2526, a touch sensor 2525, and a data storage device 2524 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 2524 can be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2525 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2526 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2528 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, a network controller 2534 can enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2510. In at least one embodiment, the audio controller 2546 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 2500 includes an optional legacy I / O controller 2540 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the processing system 2500. In at least one embodiment, the platform controller hub 2530 can also be connected to one or more universal serial bus (USB) controllers 2542 that connect input devices such as a keyboard and mouse 2543 combination, a camera 2544, or other USB input devices.

[0188] In at least one embodiment, instances of the memory controller 2516 and the platform controller hub 2530 may be integrated into a discrete external graphics processor, such as the external graphics processor 2512. In at least one embodiment, the platform controller hub 2530 and / or the memory controller 2516 may be external to one or more processors 2502. For example, in at least one embodiment, the processing system 2500 may include an external memory controller 2516 and a platform controller hub 2530, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 2502.

[0189] Figure 2626. A computer system 2600 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 2600 may be a system of interconnected devices and components, a SOC, or some combination thereof. In at least one embodiment, the computer system 2600 is formed by a processor 2602, which may include an execution unit for executing instructions. In at least one embodiment, the computer system 2600 may include, but is not limited to, components such as the processor 2602, which employs an execution unit including logic to execute algorithms for processing data. In at least one embodiment, the computer system 2600 may include a processor such as the Intel® processor available from Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 2600 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0190] In at least one embodiment, Figure 26 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, computer system 2600 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0191] In at least one embodiment, the computer system 2600 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications can include microcontrollers, digital signal processors ("DSPs"), SoCs, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system that can execute one or more instructions according to at least one embodiment.

[0192] In at least one embodiment, computer system 2600 may include, but is not limited to, a processor 2602, which may include, but is not limited to, one or more execution units 2608, which may be configured to execute Compute Unified Device Architecture ("CUDA") ( Developed by NVIDIA Corporation of Santa Clara, California) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 2600 is a single-processor desktop or server system. In at least one embodiment, computer system 2600 may be a multi-processor system. In at least one embodiment, processor 2602 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 2602 may be coupled to a processor bus 2610 that may transmit data signals between processor 2602 and other components in computer system 2600.

[0193] In at least one embodiment, processor 2602 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 2604. In at least one embodiment, processor 2602 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 2602. In at least one embodiment, processor 2602 may include a combination of internal and external caches. In at least one embodiment, register file 2606 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0194] In at least one embodiment, an execution unit 2608, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 2602. The processor 2602 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 2608 may include logic for processing a packed instruction set 2609. In at least one embodiment, by including the packed instruction set 2609 in the instruction set of the general-purpose processor 2602, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 2602. In at least one embodiment, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0195] In at least one embodiment, execution unit 2608 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, or other types of logic circuits. In at least one embodiment, computer system 2600 may include, but is not limited to, memory 2620. In at least one embodiment, memory 2620 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. Memory 2620 may store instructions 2619 and / or data 2621 represented by data signals that may be executed by processor 2602.

[0196] In at least one embodiment, the system logic chip can be coupled to the processor bus 2610 and the memory 2620. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 2616, and the processor 2602 can communicate with the MCH 2616 via the processor bus 2610. In at least one embodiment, the MCH 2616 can provide a high-bandwidth memory path 2618 to the memory 2620 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 2616 can initiate data signals between the processor 2602, the memory 2620, and other components in the computer system 2600, and bridge data signals between the processor bus 2610, the memory 2620, and the system I / O 2622. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 2616 may be coupled to the memory 2620 via a high-bandwidth memory path 2618 , and the graphics / video card 2612 may be coupled to the MCH 2616 via an Accelerated Graphics Port (“AGP”) interconnect 2614 .

[0197] In at least one embodiment, the computer system 2600 may use the system I / O 2622 as a proprietary hub interface bus to couple the MCH 2616 to the I / O controller hub ("ICH") 2630. In at least one embodiment, the ICH 2630 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 2620, chipset, and processor 2602. Examples may include, but are not limited to, an audio controller 2629, a firmware hub ("Flash BIOS") 2628, a wireless transceiver 2626, a data store 2624, a traditional I / O controller 2623 including user input 2625 and a keyboard interface, a serial expansion port 2627 (e.g., USB), and a network controller 2634. The data store 2624 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0198] In at least one embodiment, Figure 26 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 26 An exemplary SoC may be shown. In at least one embodiment, Figure 26The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 2600 are interconnected using a Compute Express Link (CXL) interconnect.

[0199] Figure 27 A system 2700 is shown in accordance with at least one embodiment. In at least one embodiment, the system 2700 is an electronic device that utilizes a processor 2710. In at least one embodiment, the system 2700 can be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more local or cloud service providers, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0200] In at least one embodiment, Figure 27 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, system 2700 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0201] In at least one embodiment, the system 2700 may include, but is not limited to, a processor 2710 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, the processor 2710 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a USB (versions 1, 2, 3), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Figure 27 A system is shown that includes interconnected hardware devices or "chips". In at least one embodiment, Figure 27 An exemplary SoC may be shown. In at least one embodiment, Figure 27 The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 27 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0202] In at least one embodiment, Figure 27The components may include a display 2724, a touch screen 2725, a touchpad 2730, a near field communication unit ("NFC") 2745, a sensor hub 2740, a thermal sensor 2746, a fast chipset ("EC") 2735, a trusted platform module ("TPM") 2738, a BIOS / firmware / flash memory ("BIOS, FW Flash") 2727, a DSP 2760, a solid-state disk ("SSD") or a hard disk drive ("HDD") 2720, a wireless local area network unit ("WLAN") 2750, a Bluetooth unit 2752, a wireless wide area network unit ("WWAN") 2756, a global positioning system (GPS) 2755, a camera ("USB 3.0 camera") 2754 (e.g., a USB 3.0 camera), or a low-power double data rate ("LPDDR") memory unit ("LPDDR3") 2715 implemented using, for example, the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0203] In at least one embodiment, other components may be communicatively coupled to the processor 2710 through the components discussed above. In at least one embodiment, an accelerometer 2741, an ambient light sensor (“ALS”) 2742, a compass 2743, and a gyroscope 2744 may be communicatively coupled to the sensor hub 2740. In at least one embodiment, a thermal sensor 2739, a fan 2737, a keyboard 2736, and a touchpad 2730 may be communicatively coupled to the EC 2735. In at least one embodiment, a speaker 2763, an earpiece 2764, and a microphone (“mic”) 2765 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 2762, which in turn may be communicatively coupled to the DSP 2760. In at least one embodiment, the audio unit 2762 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a SIM card (“SIM”) 2757 may be communicatively coupled to the WWAN unit 2756. In at least one embodiment, components such as the WLAN unit 2750 and the Bluetooth unit 2752 and the WWAN unit 2756 may be implemented as a next generation form factor (NGFF).

[0204] Figure 28An exemplary integrated circuit 2800 according to at least one embodiment is shown. In at least one embodiment, the exemplary integrated circuit 2800 is a SoC, which can be manufactured using one or more IP cores. In at least one embodiment, the integrated circuit 2800 includes one or more application processors 2805 (e.g., CPU, DPU), at least one graphics processor 2810, and may additionally include an image processor 2815 and / or a video processor 2820, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 2800 includes peripheral or bus logic, including a USB controller 2825, a UART controller 2830, an SPI / SDIO controller 2835, and an I2S / I2C controller 2840. In at least one embodiment, the integrated circuit 2800 can include a display device 2845 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 2850 and a Mobile Industry Processor Interface (MIPI) display interface 2855. In at least one embodiment, storage can be provided by a flash memory subsystem 2860, including flash memory and a flash memory controller. In at least one embodiment, a memory interface for accessing SDRAM or SRAM memory devices may be provided via memory controller 2865. In at least one embodiment, some integrated circuits also include an embedded security engine 2870.

[0205] In at least one embodiment, Figure 28 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, IC 2800 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0206] Figure 29A computing system 2900 is shown in accordance with at least one embodiment. In at least one embodiment, computing system 2900 includes a processing subsystem 2901 having one or more processors 2902 and system memory 2904 communicating via an interconnect path that may include a memory hub 2905. In at least one embodiment, memory hub 2905 may be a separate component within a chipset assembly or integrated within one or more processors 2902. In at least one embodiment, memory hub 2905 is coupled to an I / O subsystem 2911 via a communication link 2906. In at least one embodiment, I / O subsystem 2911 includes an I / O hub 2907, which enables computing system 2900 to receive input from one or more input devices 2908. In at least one embodiment, I / O hub 2907 may enable a display controller, included in one or more processors 2902, to provide output to one or more display devices 2910A. In at least one embodiment, the one or more display devices 2910A coupled to the I / O hub 2907 may include local, internal, or embedded display devices.

[0207] In at least one embodiment, Figure 29 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, the computing system 2900 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0208] In at least one embodiment, the processing subsystem 2901 includes one or more parallel processors 2912 coupled to the memory hub 2905 via a bus or other communication link 2913. In at least one embodiment, the communication link 2913 can be one of many standard-based communication link technologies or protocols, such as, but not limited to, PCIe, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 2912 form a parallel or vector processing system in a computational cluster that can include a large number of processing cores and / or processing clusters, such as multi-core processors or compute units. In at least one embodiment, the one or more parallel processors 2912 form a graphics processing subsystem that can output pixels to one of one or more display devices 2910A coupled via the I / O hub 2907. In at least one embodiment, the one or more parallel processors 2912 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 2910B.

[0209] In at least one embodiment, a system storage unit 2914 can be connected to the I / O hub 2907 to provide a storage mechanism for the computing system 2900. In at least one embodiment, an I / O switch 2916 can be used to provide an interface mechanism to enable connections between the I / O hub 2907 and other components, such as a network adapter 2918 and / or a wireless network adapter 2919 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 2920. In at least one embodiment, the network adapter 2918 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2919 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more radios.

[0210] In at least one embodiment, computing system 2900 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 2907. Figure 29 The communication paths that interconnect the various components in the system can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocol).

[0211] In at least one embodiment, one or more parallel processors 2912 include circuits optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2912 include circuits optimized for general-purpose processing. In at least one embodiment, the components of computing system 2900 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2912, memory hub 2905, processor 2902, and I / O hub 2907 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 2900 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2900 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system. In at least one embodiment, the I / O subsystem 2911 and display device 2910B are omitted from computing system 2900. In at least one embodiment, one or more parallel processors 2912 include one or more tensor memory accelerator (TMA) units that can transfer blocks of data between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, such as from global memory to shared memory and vice versa.

[0212] Processing system

[0213] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment.

[0214] Figure 30An accelerated processing unit ("APU") 3000 is shown in accordance with at least one embodiment. In at least one embodiment, the APU 3000 was developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the APU 3000 can be configured to execute application programs, such as CUDA programs. In at least one embodiment, the APU 3000 includes, but is not limited to, a core complex 3010, a graphics complex 3040, a fabric 3060, an I / O interface 3070, a memory controller 3080, a display controller 3092, and a multimedia engine 3094. In at least one embodiment, the APU 3000 can include, but is not limited to, any combination of any number of core complexes 3010, any number of graphics complexes 3050, any number of display controllers 3092, and any number of multimedia engines 3094. For purposes of illustration, multiple instances of similar objects are referred to herein by reference numerals, where the reference numeral identifies the object and a number in parentheses identifies the desired instance.

[0215] In at least one embodiment, Figure 30 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, the APU 3000 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0216] In at least one embodiment, core complex 3010 is a CPU, graphics complex 3040 is a GPU, and APU 3000 is a processing unit that is not limited to integrating 3010 and 3040 onto a single chip. In at least one embodiment, some tasks may be assigned to core complex 3010, while other tasks may be assigned to graphics complex 3040. In at least one embodiment, core complex 3010 is configured to execute primary control software associated with APU 3000, such as an operating system. In at least one embodiment, core complex 3010 is the main processor of APU 3000, controlling and coordinating the operations of the other processors. In at least one embodiment, core complex 3010 issues commands that control the operations of graphics complex 3040. In at least one embodiment, core complex 3010 may be configured to execute host executable code derived from CUDA source code, and graphics complex 3040 may be configured to execute device executable code derived from CUDA source code.

[0217] In at least one embodiment, core complex 3010 includes, but is not limited to, cores 3020(1)-3020(4) and L3 cache 3030. In at least one embodiment, core complex 3010 may include, but is not limited to, any number of cores 3020 and any combination of any number and type of caches. In at least one embodiment, cores 3020 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 3020 is a CPU core. In at least one embodiment, cores 3020 are referred to as computational units or arithmetic units.

[0218] In at least one embodiment, each core 3020 includes, but is not limited to, a fetch / decode unit 3022, an integer execution engine 3024, a floating-point execution engine 3026, and an L2 cache 3028. In at least one embodiment, the fetch / decode unit 3022 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 3024 and the floating-point execution engine 3026. In at least one embodiment, the fetch / decode unit 3022 can simultaneously dispatch one micro-op to the integer execution engine 3024 and another micro-op to the floating-point execution engine 3026. In at least one embodiment, the integer execution engine 3024 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 3026 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 3022 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 3024 and the floating-point execution engine 3026.

[0219] In at least one embodiment, each core 3020(i) can access an L2 cache 3028(i) included in the core 3020(i), where i is an integer representing a specific instance of the core 3020. In at least one embodiment, each core 3020 included in a core complex 3010(j) is connected to the other cores 3020 included in the core complex 3010(j) via an L3 cache 3030(j) included in the core complex 3010(j), where j is an integer representing a specific instance of the core complex 3010. In at least one embodiment, a core 3020 included in a core complex 3010(j) can access all L3 caches 3030(j) included in the core complex 3010(j), where j is an integer representing a specific instance of the core complex 3010. In at least one embodiment, the L3 cache 3030 can include, but is not limited to, any number of slices.

[0220] In at least one embodiment, graphics complex 3040 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, graphics complex 3040 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex 3040 is configured to perform operations that are not graphics-related. In at least one embodiment, graphics complex 3040 is configured to perform both graphics-related operations and graphics-independent operations.

[0221] In at least one embodiment, graphics complex 3040 includes, but is not limited to, any number of compute units 3050 and L2 cache 3042. In at least one embodiment, compute units 3050 share L2 cache 3042. In at least one embodiment, L2 cache 3042 is partitioned. In at least one embodiment, graphics complex 3040 includes, but is not limited to, any number of compute units 3050 and any number (including zero) and type of cache. In at least one embodiment, graphics complex 3040 includes, but is not limited to, any amount of specialized graphics hardware.

[0222] In at least one embodiment, each compute unit 3050 includes, but is not limited to, any number of SIMD units 3052 and shared memory 3054. In at least one embodiment, each SIMD unit 3052 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each compute unit 3050 can execute any number of thread blocks, but each thread block executes on a single compute unit 3050. In at least one embodiment, a thread block includes, but is not limited to, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 3052 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized and communicated via shared memory 3054. In at least one embodiment, each compute unit 3050 includes one or more thread block clusters, where thread block clusters can implement programmatic control of locality at a greater granularity than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, thread block clusters (also referred to as "clusters") enable multiple thread blocks running concurrently across a streaming multiprocessor to synchronously and cooperatively acquire, exchange, or otherwise use data.

[0223] In at least one embodiment, fabric 3060 is a system interconnect that facilitates data and control transfers across core complex 3010, graphics complex 3040, I / O interface 3070, memory controller 3080, display controller 3092, and multimedia engine 3094. In at least one embodiment, APU 3000 may include, but is not limited to, any number and type of system interconnects in addition to or in lieu of fabric 3060 that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to APU 3000. In at least one embodiment, I / O interface 3070 represents any number and type of I / O interfaces (e.g., PCI, PCI-Extended ("PCI-X"), PCIe, Gigabit Ethernet ("GBE"), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 3070. In at least one embodiment, peripheral devices coupled to I / O interface 3070 may include, but are not limited to, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0224] In at least one embodiment, display controller AMD92 displays images on one or more display devices, such as liquid crystal display ("LCD") devices. In at least one embodiment, multimedia engine 3094 includes, but is not limited to, any number and type of multimedia-related circuits, such as video decoders, video encoders, image signal processors, and the like. In at least one embodiment, memory controller 3080 facilitates data transfers between APU 3000 and unified system memory 3090. In at least one embodiment, core complex 3010 and graphics complex 3040 share unified system memory 3090.

[0225] In at least one embodiment, the APU 3000 implements a memory subsystem including, but not limited to, any number and type of memory controllers 3080 and memory devices that can be dedicated to a component or shared among multiple components (e.g., shared memory 3054). In at least one embodiment, the APU 3000 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 3128, L3 cache 3030, and L2 cache 3042), each of which can be private to a component or shared among any number of components (e.g., core 3020, core complex 3010, SIMD units 3052, compute units 3050, and graphics complex 3040).

[0226] Figure 31A CPU 3100 is shown according to at least one embodiment. In at least one embodiment, the CPU 3100 is developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the CPU 3100 can be configured to execute application programs. In at least one embodiment, the CPU 3100 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 3100 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 3100 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 3100 includes, but is not limited to, any number of core complexes 3110, fabric 3160, I / O interfaces 3170, and memory controller 3180.

[0227] In at least one embodiment, Figure 31 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, the CPU 3100 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0228] In at least one embodiment, core complex 3110 includes, but is not limited to, cores 3120(1)-3120(4) and L3 cache 3130. In at least one embodiment, core complex 3110 may include, but is not limited to, any number of cores 3120 in any combination and any number and type of caches. In at least one embodiment, cores 3120 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 3120 is a CPU core.

[0229] In at least one embodiment, each core 3120 includes, but is not limited to, a fetch / decode unit 3122, an integer execution engine 3124, a floating-point execution engine 3126, and an L2 cache 3128. In at least one embodiment, the fetch / decode unit 3122 fetches instructions, decodes these instructions, generates micro-ops, and dispatches separate micro-ops to the integer execution engine 3124 and the floating-point execution engine 3126. In at least one embodiment, the fetch / decode unit 3122 can simultaneously dispatch one micro-op to the integer execution engine 3124 and another micro-op to the floating-point execution engine 3126. In at least one embodiment, the integer execution engine 3124 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 3126 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 3122 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 3124 and the floating-point execution engine 3126.

[0230] In at least one embodiment, each core 3120(i) can access an L2 cache 3128(i) included in the core 3120(i), where i is an integer representing a specific instance of the core 3120. In at least one embodiment, each core 3120 included in a core complex 3110(j) is connected to the other cores 3120 in the core complex 3110(j) via an L3 cache 3130(j) included in the core complex 3110(j), where j is an integer representing a specific instance of the core complex 3110. In at least one embodiment, a core 3120 included in a core complex 3110(j) can access all L3 caches 3130(j) included in the core complex 3110(j), where j is an integer representing a specific instance of the core complex 3110. In at least one embodiment, the L3 cache 3130 can include, but is not limited to, any number of slices.

[0231] In at least one embodiment, fabric 3160 is a system interconnect that facilitates data and control transfers across core complexes 3110(1)-3110(N) (where N is an integer greater than zero), I / O interface 3170, and memory controller 3180. In at least one embodiment, CPU 3100 may include, in addition to or in lieu of fabric 3160, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to CPU 3100. In at least one embodiment, I / O interface 3170 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripherals are coupled to I / O interface 3170. In at least one embodiment, peripherals coupled to I / O interface 3170 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, and the like.

[0232] In at least one embodiment, the memory controller 3180 facilitates data transfers between the CPU 3100 and the system memory 3190. In at least one embodiment, the core complex 3110 and the graphics complex 3140 share the system memory 3190. In at least one embodiment, the CPU 3100 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 3180 and memory devices that can be dedicated to a component or shared among multiple components. In at least one embodiment, the CPU 3100 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 3128 and L3 cache 3130), each of which can be private to a component or shared among any number of components (e.g., core 3120 and core complex 3110).

[0233] Figure 32An exemplary accelerator integrated slice 3290 is shown according to at least one embodiment. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines in multiple graphics acceleration modules. The graphics processing engines may each include a separate GPU. Optionally, the graphics processing engines may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

[0234] In at least one embodiment, Figure 32 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, the accelerated integrated slicer 3290 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0235] The application effective address space 3282 within system memory 3214 stores a process element 3283. In one embodiment, a process element 3283 is stored in response to a GPU call 3281 from an application 3280 executing on processor 3207. The process element 3283 contains the processing state of the corresponding application 3280. The work descriptor (WD) 3284 contained in the process element 3283 can be a single job requested by the application or may contain a pointer to a job queue. In at least one embodiment, the WD 3284 is a pointer to a job request queue in the application effective address space 3282.

[0236] Graphics acceleration module 3246 and / or each graphics processing engine can be shared by all or part of the processes in the system.In at least one embodiment, an infrastructure for establishing a processing state and sending WD 3284 to graphics acceleration module 3246 to start a job in a virtualized environment can be included.

[0237] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns the graphics acceleration module 3246 or individual graphics processing engine. Because the graphics acceleration module 3246 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owning partition, and the operating system initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 3246 is allocated.

[0238] In operation, the WD fetch unit 3291 in the accelerator integrated slice 3290 fetches the next WD 3284, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 3246. Data from the WD 3284 can be stored in registers 3245 for use by the memory management unit (MMU) 3239, the interrupt management circuit 3247, and / or the context management circuit 3248, as shown. For example, one embodiment of the MMU 3239 includes segment / page roaming circuitry for accessing the segment / page tables 3286 within the OS virtual address space 3285. The interrupt management circuit 3247 can handle interrupt events ("INT") 3292 received from the graphics acceleration module 3246. When executing a graphics operation, the effective address 3293 generated by the graphics processing engine is converted into a real address by the MMU 3239.

[0239] In one embodiment, the same register set 3245 is replicated for each graphics processing engine and / or graphics acceleration module 3246 and can be initialized by the system hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 3290. Table 1 shows exemplary registers that can be initialized by the hypervisor.

[0240] Table 1 - Registers initialized by the hypervisor

[0241] 1 Slice Control Register 2 Real address (RA) plan processing area pointer 3 Authorization Mask Override Register 4 Interrupt vector table input offset 5 Interrupt vector table entry restriction 6 Status Register 7 Logical partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0242] Example registers that may be initialized by the operating system are shown in Table 2.

[0243] Table 2 - Operating System Initialization Registers

[0244] 1 Process and thread identification 2 Effective Address (EA) environment save / restore pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) stores the segment table pointer 5 Mask of Authority 6 Job Descriptor

[0245] In one embodiment, each WD 3284 is specific to a particular graphics acceleration module 3246 and / or a particular graphics processing engine. It contains all the information the graphics processing engine needs to do its work or work, or it can be a pointer to a memory location where the application has set up a command queue for work to be done.

[0246] Figures 33A-33BAn exemplary graphics processor according to at least one embodiment of the present disclosure is shown. In at least one embodiment, any exemplary graphics processor can be manufactured using one or more IP cores. In addition to the illustrated diagram, in at least one embodiment, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is used within a SoC.

[0247] Figure 33A An exemplary graphics processor 3310 of a SoC integrated circuit that can be fabricated using one or more IP cores in accordance with at least one embodiment is shown. Figure 33B An additional exemplary graphics processor 3340 of a SoC integrated circuit that can be manufactured using one or more IP cores according to at least one embodiment is shown. In at least one embodiment, Figure 33A The graphics processor 3310 is a low power graphics processor core. In at least one embodiment, Figure 33B The graphics processor 3340 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 3310, 3340 can be Figure 28 A variant of the graphics processor 2810.

[0248] In at least one embodiment, Figures 33A-33B At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, graphics processor 3340 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0249] In at least one embodiment, the graphics processor 3310 includes a vertex processor 3305 and one or more fragment processors 3315A-3315N (e.g., 3315A, 3315B, 3315C, 3315D through 3315N-1 and 3315N). In at least one embodiment, the graphics processor 3310 can execute different shader programs via separate logic, such that the vertex processor 3305 is optimized to perform operations for the vertex shader program, while one or more fragment processors 3315A-3315N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 3305 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processors 3315A-3315N use the primitives and vertex data generated by the vertex processor 3305 to generate a frame buffer for display on a display device. In at least one embodiment, the fragment processors 3315A-3315N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0250] In at least one embodiment, the graphics processor 3310 additionally includes one or more MMUs 3320A-3320B, caches 3325A-3325B, and circuit interconnects 3330A-3330B. In at least one embodiment, the one or more MMUs 3320A-3320B provide a mapping of virtual to physical addresses for the graphics processor 3310, including for the vertex processor 3305 and / or the fragment processors 3315A-3315N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 3325A-3325B. In at least one embodiment, the one or more MMUs 3320A-3320B may synchronize with other MMUs within the system, including with Figure 28 One or more MMUs associated with one or more application processors 2805, image processor 2815, and / or video processor 2820 enable each processor 2805-2820 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 3330A-3330B enable the graphics processor 3310 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0251] In at least one embodiment, graphics processor 3340 includes Figure 33A3320A-3320B, caches 3325A-3325B, and circuit interconnects 3330A-3330B of the graphics processor 3310. In at least one embodiment, the graphics processor 3340 includes one or more shader cores 3355A-3355N (e.g., 3355A, 3355B, 3355C, 3355D, 3355E, 3355F, through 3355N-1 and 3355N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 3340 includes an inter-core task manager 3345 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 3355A-3355N and a tiling unit 3358 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0252] Figure 34A FIG34 shows a graphics core 3400 according to at least one embodiment. In at least one embodiment, the graphics core 3400 may include Figure 28 In at least one embodiment, the graphics core 3400 may be Figure 33B3355N. In at least one embodiment, graphics core 3400 includes a shared instruction cache 3402, texture units 3418, and cache / shared memory 3420, which are common to execution resources within graphics core 3400. In at least one embodiment, graphics core 3400 may include multiple slices 3401A-3401N or partitions of each core, and a graphics processor may include multiple instances of graphics core 3400. Slices 3401A-3401N may include support logic including local instruction caches 3404A-3404N, thread schedulers 3406A-3406N, thread dispatchers 3408A-3408N, and a set of registers 3410A-3410N. In at least one embodiment, slices 3401A-3401N may include a set of additional function units ("AFUs") 3412A-3412N, floating point units ("FPUs") 3414A-3414N, integer arithmetic logic units ("ALUs") 3416A-3416N, address calculation units ("ACUs") 3413A-3413N, double precision floating point units ("DPFPUs") 3415A-3415N, and matrix processing units ("MPUs") 3417A-3417N. In at least one embodiment, graphics core 3400 is referred to as a compute unit or arithmetic unit.

[0253] In one embodiment, the FPUs 3414A-3414N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 3415A-3415N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 3416A-3416N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 3417A-3417N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 3417A-3417N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 3412A-3412N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0254] Figure 34BA general purpose graphics processing unit (GPGPU) 3430 is shown in at least one embodiment. In at least one embodiment, GPGPU 3430 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 3430 can be configured to enable highly parallel computational operations to be performed by an array of GPUs. In at least one embodiment, GPGPU 3430 can be directly linked to other instances of GPGPU 3430 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU 3430 includes a host interface 3432 to enable connection to a host processor. In at least one embodiment, host interface 3432 is a PCIe interface. In at least one embodiment, host interface 3432 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 3430 receives commands from the host processor and dispatches execution threads associated with those commands to a set of compute clusters 3436A-3436H using a global scheduler 3434. In at least one embodiment, compute clusters 3436A-3436H share cache memory 3438. In at least one embodiment, cache memory 3438 can serve as a higher level cache for cache memory within compute clusters 3436A-3436H.

[0255] In at least one embodiment, Figures 34A-34B At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, the GPGPU 3430 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0256] In at least one embodiment, GPGPU 3430 includes memory 3444A-3444B coupled to a compute cluster 3436A-3436H via a set of memory controllers 3442A-3442B. In at least one embodiment, memory 3444A-3444B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0257] In at least one embodiment, computing clusters 3436A-3436H each include a set of graphics cores, such as Figure 34AThe graphics core 3400, which may include multiple types of integer and floating-point logic units, can perform computational operations at various precisions, including computations suitable for use with CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each compute cluster 3436A-3436H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0258] In at least one embodiment, multiple instances of GPGPU 3430 can be configured to operate as a compute cluster. Compute clusters 3436A-3436H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 3430 communicate via host interface 3432. In at least one embodiment, GPGPU 3430 includes an I / O hub 3439 that couples GPGPU 3430 to a GPU link 3440, enabling direct connections to other instances of GPGPU 3430. In at least one embodiment, GPU link 3440 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 3430. In at least one embodiment, GPU link 3440 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 3430 are located in separate data processing systems and communicate via a network device accessible via host interface 3432. In at least one embodiment, GPU link 3440 may be configured to connect to a host processor, in addition to or in place of host interface 3432. In at least one embodiment, GPGPU 3430 may be configured to execute CUDA programs.

[0259] Figure 35A A parallel processor 3500 in accordance with at least one embodiment is shown. In at least one embodiment, the various components of the parallel processor 3500 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or an FPGA.

[0260] In at least one embodiment, parallel processor 3500 includes parallel processing unit 3502. In at least one embodiment, parallel processing unit 3502 includes an I / O unit 3504 that enables communication with other devices, including other instances of parallel processing unit 3502. In at least one embodiment, I / O unit 3504 can be directly connected to other devices. In at least one embodiment, I / O unit 3504 connects to other devices using a hub or switch interface (e.g., memory hub 3505). In at least one embodiment, the connection between memory hub 3505 and I / O unit 3504 forms a communication link. In at least one embodiment, I / O unit 3504 is connected to a host interface 3506 and a memory crossbar switch 3516, where host interface 3506 receives commands for performing processing operations and memory crossbar switch 3516 receives commands for performing memory operations.

[0261] In at least one embodiment, when host interface 3506 receives command buffers via I / O unit 3504, host interface 3506 can direct work operations to execute those commands to front end 3508. In at least one embodiment, front end 3508 is coupled to scheduler 3510, which is configured to dispatch commands or other work items to processing array 3512. In at least one embodiment, scheduler 3510 ensures that processing array 3512 is properly configured and in a valid state before dispatching tasks to processing array 3512. In at least one embodiment, scheduler 3510 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 3510 can be configured to perform complex scheduling and work dispatch operations at both coarse and fine granularity, thereby enabling rapid preemption and context switching of threads executing on processing array 3512. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 3512 through one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed across the processing array 3512 by scheduler 3510 logic within a microcontroller that includes scheduler 3510.

[0262] In at least one embodiment, the processing array 3512 can include up to "N" processing clusters (e.g., cluster 3514A, cluster 3514B, through cluster 3514N). In at least one embodiment, each cluster 3514A-3514N of the processing array 3512 can execute a large number of concurrent threads. In at least one embodiment, the scheduler 3510 can allocate work to the clusters 3514A-3514N of the processing array 3512 using various scheduling and / or work distribution algorithms, which can vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling can be handled dynamically by the scheduler 3510 or can be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing array 3512. In at least one embodiment, different clusters 3514A-3514N of the processing array 3512 can be assigned to process different types of programs or to perform different types of computations.

[0263] In at least one embodiment, processing array 3512 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 3512 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing array 3512 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0264] In at least one embodiment, the processing array 3512 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 3512 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 3512 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing units 3502 may transfer data from the system memory via the I / O units 3504 for processing. In at least one embodiment, during processing, the transferred data may be stored in an on-chip memory (e.g., parallel processor memory 3522) during processing and then written back to the system memory.

[0265] In at least one embodiment, when parallel processing unit 3502 is used to perform graph processing, scheduler 3510 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 3514A-3514N of processing array 3512. In at least one embodiment, portions of processing array 3512 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 3514A-3514N can be stored in a buffer to allow the intermediate data to be transferred between clusters 3514A-3514N for further processing.

[0266] In at least one embodiment, the processing array 3512 can receive processing tasks to be executed via the scheduler 3510, which receives commands defining the processing tasks from the front end 3508. In at least one embodiment, the processing tasks can include an index of the data to be processed, which can include, for example, surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 3510 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 3508. In at least one embodiment, the front end 3508 can be configured to ensure that the processing array 3512 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0267] In at least one embodiment, each of one or more instances of parallel processing unit 3502 can be coupled to parallel processor memory 3522. In at least one embodiment, parallel processor memory 3522 can be accessed via memory crossbar 3516, which can receive memory requests from processing array 3512 and I / O unit 3504. In at least one embodiment, memory crossbar 3516 can access parallel processor memory 3522 via memory interface 3518. In at least one embodiment, memory interface 3518 can include multiple partition units (e.g., partition unit 3520A, partition unit 3520B, through partition unit 3520N), which can each be coupled to a portion of parallel processor memory 3522 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 3520A-3520N are configured to be equal to the number of memory cells, such that the first partition unit 3520A has a corresponding first memory cell 3524A, the second partition unit 3520B has a corresponding memory cell 3524B, and the Nth partition unit 3520N has a corresponding Nth memory cell 3524N. In at least one embodiment, the number of partition units 3520A-3520N may not be equal to the number of memory devices.

[0268] In at least one embodiment, memory units 3524A-3524N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 3524A-3524N may also include 3D stacked memory, including but not limited to high bandwidth memory ("HBM"). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 3524A-3524N, allowing partition units 3520A-3520N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 3522. In at least one embodiment, local instances of parallel processor memory 3522 may be eliminated in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0269] In at least one embodiment, any of the clusters 3514A-3514N of the processing array 3512 can process data to be written to any memory unit 3524A-3524N within the parallel processor memory 3522. In at least one embodiment, the memory crossbar 3516 can be configured to transmit the output of each cluster 3514A-3514N to any partition unit 3520A-3520N or another cluster 3514A-3514N, which can perform other processing operations on the output. In at least one embodiment, each cluster 3514A-3514N can communicate with a memory interface 3518 via the memory crossbar 3516 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 3516 has connections to memory interface 3518 for communicating with I / O unit 3504, as well as connections to local instances of parallel processor memory 3522, thereby enabling processing units within different processing clusters 3514A-3514N to communicate with system memory or other memory that is not local to parallel processing unit 3502. In at least one embodiment, memory crossbar switch 3516 may use virtual channels to separate traffic flows between clusters 3514A-3514N and partition units 3520A-3520N.

[0270] In at least one embodiment, multiple instances of parallel processing unit 3502 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 3502 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 3502 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 3502 or parallel processor 3500 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0271] Figure 35B FIG35 illustrates a processing cluster 3594 according to at least one embodiment. In at least one embodiment, the processing cluster 3594 is included within a parallel processing unit. In at least one embodiment, the processing cluster 3594 is Figure 35AIn at least one embodiment, processing cluster 3594 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster 3594.

[0272] In at least one embodiment, Figures 35A-35B At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, processing cluster 3594 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0273] In at least one embodiment, the operation of the processing cluster 3594 can be controlled by a pipeline manager 3532 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 3532 Figure 35A The scheduler 3510 receives instructions and manages the execution of these instructions by the graphics multiprocessor 3534 and / or the texture unit 3536. In at least one embodiment, the graphics multiprocessor 3534 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 3594. In at least one embodiment, one or more instances of the graphics multiprocessor 3534 may be included within the processing cluster 3594. In at least one embodiment, the graphics multiprocessor 3534 may process data, and the data crossbar 3540 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 3532 may facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossbar 3540.

[0274] In at least one embodiment, each graphics multiprocessor 3534 within a processing cluster 3594 may include the same set of function execution logic (e.g., an arithmetic logic unit, a load store unit ("LSU"), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where a new instruction may be issued before a previous instruction has completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0275] In at least one embodiment, instructions transmitted to the processing cluster 3594 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 3534. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 3534. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop by the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 3534. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 3534, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 3534.

[0276] In at least one embodiment, the graphics multiprocessor 3534 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 3534 can abandon the internal cache and use cache memory within the processing cluster 3594 (e.g., L1 cache 3548). In at least one embodiment, each graphics multiprocessor 3534 can also access partition units (e.g., Figure 35AL2 cache within partition units 3520A-3520N) of the graphics multiprocessor 3534 is shared across all processing clusters 3594 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 3534 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 3502 can be used as global memory. In at least one embodiment, processing cluster 3594 includes multiple instances of graphics multiprocessor 3534, which can share common instructions and data, which can be stored in L1 cache 3548.

[0277] In at least one embodiment, each processing cluster 3594 may include an MMU 3545 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 3545 may reside in Figure 35A 35. In at least one embodiment, the MMU 3545 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles (more on tiles below) and optionally to cache line indices. In at least one embodiment, the MMU 3545 may include a translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 3534 or L1 cache 3548 or processing cluster 3594. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0278] In at least one embodiment, the processing clusters 3594 can be configured such that each graphics multiprocessor 3534 is coupled to a texture unit 3536 to perform texture mapping operations, which may involve, for example, determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 3534, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 3534 outputs processed tasks to a data crossbar 3540 to provide the processed tasks to another processing cluster 3594 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 3516. In at least one embodiment, a pre-raster operations unit (preROP) 3542 is configured to receive data from the graphics multiprocessor 3534, direct the data to a ROP unit, which may communicate with a partitioning unit (e.g., Figure 35A In at least one embodiment, the PreROP 3542 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0279] Figure 35C A graphics multiprocessor 3596 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 3596 is Figure 35B In at least one embodiment, the graphics multiprocessor 3596 is coupled to the pipeline manager 3532 of the processing cluster 3594. In at least one embodiment, the graphics multiprocessor 3596 has an execution pipeline that includes, but is not limited to, an instruction cache 3552, an instruction unit 3554, an address mapping unit 3556, a register file 3558, one or more GPGPU cores 3562, and one or more LSUs 3566. The GPGPU cores 3562 and LSUs 3566 are coupled to cache memory 3572 and shared memory 3570 via a memory and cache interconnect 3568. One or more

[0280] In at least one embodiment, the instruction cache 3552 receives a stream of instructions to be executed from the pipeline manager 3532. In at least one embodiment, the instructions are cached in the instruction cache 3552 and dispatched for execution by the instruction unit 3554. In one embodiment, the instruction unit 3554 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 3562. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 3556 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the LSU 3566.

[0281] In at least one embodiment, register file 3558 provides a set of registers for the functional units of graphics multiprocessor 3596. In at least one embodiment, register file 3558 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 3562, LSU 3566) connected to graphics multiprocessor 3596. In at least one embodiment, register file 3558 is divided between each functional unit such that a dedicated portion of register file 3558 is allocated to each functional unit. In at least one embodiment, register file 3558 is divided between the different thread groups being executed by graphics multiprocessor 3596.

[0282] In at least one embodiment, the GPGPU cores 3562 may each include an FPU and / or ALU for executing instructions of the graphics multiprocessor 3596. The GPGPU cores 3562 may be architecturally similar or the architectures may differ. In at least one embodiment, a first portion of the GPGPU core 3562 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core 3562 includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-3008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 3596 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 3562 may also include fixed-function or special-function logic.

[0283] In at least one embodiment, the GPGPU core 3562 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 3562 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core 3562 can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0284] In at least one embodiment, the memory and cache interconnect 3568 is an interconnect network that connects each functional unit of the graphics multiprocessor 3596 to the register file 3558 and shared memory 3570. In at least one embodiment, the memory and cache interconnect 3568 is a crossbar interconnect that allows the LSU 3566 to implement load and store operations between the shared memory 3570 and the register file 3558. In at least one embodiment, the register file 3558 can operate at the same frequency as the GPGPU core 3562, resulting in very low latency for data transfers between the GPGPU core 3562 and the register file 3558. In at least one embodiment, the shared memory 3570 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 3596. In at least one embodiment, the cache memory 3572 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 3536. In at least one embodiment, the shared memory 3570 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 3572, threads executing on GPGPU core 3562 may also programmatically store data in shared memory.

[0285] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0286] Figure 36 Graphics processor 3600 is shown in accordance with at least one embodiment. In at least one embodiment, graphics processor 3600 includes ring interconnect 3602, pipeline front end 3604, media engine 3637, and graphics cores 3680A-3680N. In at least one embodiment, ring interconnect 3602 couples graphics processor 3600 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 3600 is one of many processors integrated within a multi-core processing system.

[0287] In at least one embodiment, Figure 36 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, graphics processor 3600 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0288] In at least one embodiment, the graphics processor 3600 receives batches of commands via a ring interconnect 3602. In at least one embodiment, the input commands are interpreted by a command streamer 3603 in a pipeline front end 3604. In at least one embodiment, the graphics processor 3600 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 3680A-3680N. In at least one embodiment, for 3D geometry processing commands, the command streamer 3603 provides the commands to a geometry pipeline 3636. In at least one embodiment, for at least some media processing commands, the command streamer 3603 provides the commands to a video front end 3634, which is coupled to a media engine 3637. In at least one embodiment, the media engine 3637 includes a video quality engine (VQE) 3630 for video and image post-processing, and a multi-format encoding / decoding (MFX) 3633 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 3636 and the media engine 3637 each generate execution threads for thread execution resources provided by at least one graphics core 3680A.

[0289] In at least one embodiment, graphics processor 3600 includes scalable thread execution resources featuring modular graphics cores 3680A-3680N (sometimes referred to as core slices), each of which has multiple sub-cores 3650A-3650N, 3660A-3660N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 3600 can have any number of graphics cores 3680A-3680N. In at least one embodiment, graphics processor 3600 includes graphics core 3680A having at least a first sub-core 3650A and a second sub-core 3660A. In at least one embodiment, graphics processor 3600 is a low-power processor having a single sub-core (e.g., 3650A). In at least one embodiment, graphics processor 3600 includes multiple graphics cores 3680A-3680N, each of which includes a set of first sub-cores 3650A-3650N and a set of second sub-cores 3660A-3660N. In at least one embodiment, each of the first sub-cores 3650A-3650N includes at least a first set of execution units (EUs) 3652A-3652N and media / texture samplers 3654A-3654N. In at least one embodiment, each of the second sub-cores 3660A-3660N includes at least a second set of execution units 3662A-3662N and samplers 3664A-3664N. In at least one embodiment, each of the sub-cores 3650A-3650N, 3660A-3660N shares a set of shared resources 3670A-3670N. In at least one embodiment, the shared resources 3670 include a shared cache and pixel operation logic.

[0290] Figure 37A processor 3700 is shown according to at least one embodiment. In at least one embodiment, the processor 3700 may include, but is not limited to, logic circuitry to execute instructions. In at least one embodiment, the processor 3700 may execute instructions including x86 instructions, ARM instructions, specialized instructions for ASICs, and the like. In at least one embodiment, the processor 3710 may include registers for storing packed data, such as the 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, the MMX registers, available in integer and floating point form, may operate with packed data elements with SIMD and Streaming SIMD Extensions ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as "SSEx") technology may hold such packed data operands. In at least one embodiment, the processor 3710 may execute instructions to accelerate CUAD programs. One or more

[0291] In at least one embodiment, Figure 37 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, the processor 3700 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0292] In at least one embodiment, processor 3700 includes an in-order front end ("Front End") 3701 to fetch instructions for execution and prepare them for later use in the processor pipeline. In at least one embodiment, Front End 3701 may include several units. In at least one embodiment, instruction prefetcher 3726 retrieves instructions from memory and provides them to instruction decoder 3728, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 3728 decodes received instructions into one or more operations, called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions"), for execution. In at least one embodiment, instruction decoder 3728 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 3730 can assemble the decoded microinstructions into a program-ordered sequence or trace in microinstruction queue 3734 for execution. In at least one embodiment, when trace cache 3730 encounters a complex instruction, microcode ROM 3732 provides the microinstructions necessary to complete the operation.

[0293] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 3728 may access the microcode ROM 3732 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 3728. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 3732. In at least one embodiment, the trace cache 3730 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 3732 to complete one or more instructions in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 3732 completes the micro-op sequencing for the instruction, the front end 3701 of the machine may resume fetching micro-ops from the trace cache 3730.

[0294] In at least one embodiment, an out-of-order execution engine ("OOO engine") 3703 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. The OOO engine 3703 includes, but is not limited to, an allocator / register renamer 3740, a memory microinstruction queue 3742, an integer / floating-point microinstruction queue 3744, a memory scheduler 3746, a fast scheduler 3702, a slow / general floating-point scheduler ("slow / general FP scheduler") 3704, and a simple floating-point scheduler ("simple FP scheduler") 3706. In at least one embodiment, the fast scheduler 3702, the slow / general floating-point scheduler 3704, and the simple floating-point scheduler 3706 are also collectively referred to as "microinstruction schedulers 3702, 3704, 3706." The allocator / register renamer 3740 allocates the machine buffers and resources required for each microinstruction to execute in order. In at least one embodiment, the allocator / register renamer 3740 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 3740 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 3742 for memory operations and an integer / floating point microinstruction queue 3744 for non-memory operations, preceding the memory scheduler 3746 and the microinstruction schedulers 3702, 3704, 3706. In at least one embodiment, the microinstruction schedulers 3702, 3704, 3706 determine when a microinstruction is ready to execute based on the readiness of its dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 3702 of at least one embodiment can schedule on every half of the main clock cycle, while the slow / general floating point scheduler 3704 and the simple floating point scheduler 3706 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 3702, 3704, 3706 arbitrate on dispatch ports to schedule microinstructions for execution.

[0295] In at least one embodiment, execution block 3711 includes, but is not limited to, integer register file / branch network 3708, floating point register file / branch network ("FP register file / branch network") 3710, address generation units ("AGUs") 3712 and 3714, fast arithmetic logic units ("fast ALUs") 3716 and 3718, slow ALU 3720, floating point ALU ("FP") 3722, and floating point move unit ("FP move") 3724. In at least one embodiment, integer register file / branch network 3708 and floating point register file / bypass network 3710 are also referred to herein as "register files 3708, 3710." In at least one embodiment, ALUs 3712 and 3714, fast ALUs 3716 and 3718, slow ALU 3720, floating-point ALU 3722, and floating-point move unit 3724 are also referred to herein as "execution units 3712, 3714, 3716, 3718, 3720, 3722, and 3724." In at least one embodiment, an execution block may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0296] In at least one embodiment, register files 3708 and 3710 may be arranged between microinstruction schedulers 3702, 3704, and 3706 and execution units 3712, 3714, 3716, 3718, 3720, 3722, and 3724. In at least one embodiment, integer register file / branch network 3708 performs integer operations. In at least one embodiment, floating-point register file / branch network 3710 performs floating-point operations. In at least one embodiment, each of register files 3708 and 3710 may include, but is not limited to, a branch network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register files 3708 and 3710 may communicate data with each other. In at least one embodiment, integer register file / branch network 3708 may include, but is not limited to, two separate register files: one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 3710 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0297] In at least one embodiment, execution units 3712, 3714, 3716, 3718, 3720, 3722, and 3724 can execute instructions. In at least one embodiment, register files 3708 and 3710 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 3700 can include, but is not limited to, any number of execution units 3712, 3714, 3716, 3718, 3720, 3722, and 3724, and combinations thereof. In at least one embodiment, floating-point ALU 3722 and floating-point move unit 3724 can execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 3722 can include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 3716 and 3718. In at least one embodiment, fast ALUs 3716 and 3718 can execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 3720, as slow ALU 3720 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by ALUs 3712 and 3714. In at least one embodiment, fast ALU 3716, fast ALU 3718, and slow ALU 3720 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 3716, fast ALU 3718, and slow ALU 3720 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, the floating point ALU 3722 and floating point shift unit 3724 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 3722 and floating point shift unit 3724 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0298] In at least one embodiment, the microinstruction schedulers 3702, 3704, and 3706 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 3700, processor 3700 can also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0299] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0300] Figure 38 A processor 3800 is shown in accordance with at least one embodiment. In at least one embodiment, processor 3800 includes, but is not limited to, one or more processor cores ("cores") 3802A-3802N, an integrated memory controller 3814, and an integrated graphics processor 3808. In at least one embodiment, processor 3800 may include additional cores, up to and including the additional processor core 3802N represented by the dashed box. In at least one embodiment, each processor core 3802A-3802N includes one or more internal cache units 3804A-3804N. In at least one embodiment, each processor core may also have access to one or more shared cache units 3806. In at least one embodiment, one or more processor cores 3802A-3802N are referred to as one or more computational units or arithmetic units.

[0301] In at least one embodiment, Figure 38 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, the processor 3800 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0302] In at least one embodiment, the internal cache units 3804A-3804N and the shared cache unit 3806 represent a cache memory hierarchy within the processor 3800. In at least one embodiment, the cache memory units 3804A-3804N may include at least one level of instruction and data within each processor core and one or more levels of cache in a shared mid-level cache, such as an L2, L3, level 4 (L4), or other level of cache, with the highest level of cache being categorized as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 3806 and 3804A-3804N.

[0303] In at least one embodiment, processor 3800 may also include a set of one or more bus controller units 3816 and a system agent core 3810. In at least one embodiment, the one or more bus controller units 3816 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, system agent core 3810 provides management functions for various processor components. In at least one embodiment, system agent core 3810 includes one or more integrated memory controllers 3814 to manage access to various external memory devices (not shown).

[0304] In at least one embodiment, one or more processor cores 3802A-3802N include support for simultaneous multithreading. In at least one embodiment, system agent core 3810 includes components for coordinating and operating processor cores 3802A-3802N during multithreaded processing. In at least one embodiment, system agent core 3810 may additionally include a power control unit ("PCU") that includes logic and components to regulate one or more power states of processor cores 3802A-3802N and graphics processor 3808.

[0305] In at least one embodiment, processor 3800 further includes a graphics processor 3808 to perform graphics processing operations. In at least one embodiment, graphics processor 3808 is coupled to a shared cache unit 3806 and a system agent core 3810 including one or more integrated memory controllers 3814. In at least one embodiment, system agent core 3810 also includes a display controller 3811 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, display controller 3811 may also be a separate module coupled to graphics processor 3808 via at least one interconnect, or may be integrated within graphics processor 3808.

[0306] In at least one embodiment, a ring-based interconnect 3812 is used to couple the internal components of processor 3800. In at least one embodiment, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, graphics processor 3808 is coupled to ring interconnect 3812 via I / O link 3813.

[0307] In at least one embodiment, I / O link 3813 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 3818 (e.g., an eDRAM module). In at least one embodiment, each of the processor cores 3802A-3802N and the graphics processor 3808 uses the embedded memory module 3818 as a shared LLC.

[0308] In at least one embodiment, the processor cores 3802A-3802N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 3802A-3802N are heterogeneous in terms of ISA, where one or more processor cores 3802A-3802N execute a common instruction set, while one or more other processor cores 3802A-3802N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 3802A-3802N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 3800 can be implemented on one or more chips or as a SoC integrated circuit.

[0309] Figure 39A graphics processor core 3900 is shown in accordance with at least one described embodiment. In at least one embodiment, graphics processor core 3900 is included within a graphics core array. In at least one embodiment, graphics processor core 3900 (sometimes referred to as a core slice) can be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 3900 is an example of one graphics core slice, and the graphics processors described herein can include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 3900 can include fixed function blocks 3930 coupled to multiple sub-cores 3901A-3901F, also referred to as sub-slices, which include modular blocks of general purpose and fixed function logic.

[0310] In at least one embodiment, Figure 39 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, graphics core 3900 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0311] In at least one embodiment, fixed function block 3930 includes a geometry / fixed function pipeline 3936, which may be shared by all sub-cores in graphics processor 3900, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 3936 includes a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0312] In at least one embodiment, fixed function block 3930 also includes a graphics SoC interface 3937, a graphics microcontroller 3938, and a media pipeline 3939. Graphics SoC interface 3937 provides an interface between graphics core 3900 and other processor cores in the SoC integrated circuit system. In at least one embodiment, graphics microcontroller 3938 is a programmable subprocessor that can be configured to manage various functions of graphics processor 3900, including thread dispatching, scheduling, and preemption. In at least one embodiment, media pipeline 3939 includes logic that facilitates decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 3939 implements media operations via requests to computational or sampling logic within sub-cores 3901-3901F.

[0313] In at least one embodiment, the SoC interface 3937 enables the graphics core 3900 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 3937 may also enable communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enable the use and / or implementation of global memory atomics that can be shared between the graphics core 3900 and the CPU within the SoC. In at least one embodiment, the SoC interface 3937 may also implement power management controls for the graphics core 3900 and enable interfaces between the clock domain of the graphics core 3900 and other clock domains within the SoC. In at least one embodiment, the SoC interface 3937 enables the reception of command buffers from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to the media pipeline 3939 when media operations are to be performed, or may be assigned to the geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 3936, geometry and fixed function pipeline 3914) when graph processing operations are to be performed.

[0314] In at least one embodiment, the graphics microcontroller 3938 can be configured to perform various scheduling and management tasks for the graphics core 3900. In at least one embodiment, the graphics microcontroller 3938 can perform graph and / or compute workload scheduling on the various graphics parallel engines within the execution unit (EU) arrays 3902A-3902F, 3904A-3904F in the sub-cores 3901A-3901F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 3900 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In at least one embodiment, the graphics microcontroller 3938 may also facilitate a low power or idle state for the graphics core 3900, thereby providing the graphics core 3900 with the ability to save and restore registers across low power state transitions within the graphics core 3900 independent of the operating system and / or graphics driver software on the system.

[0315] In at least one embodiment, graphics core 3900 may have more or fewer sub-cores than the sub-cores 3901A-3901F shown, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core 3900 may also include shared function logic 3910, shared and / or cache memory 3912, geometry / fixed function pipelines 3914, and additional fixed function logic 3916 to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic 3910 may include logic units (e.g., samplers, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores within graphics core 3900. Shared and / or cache memory 3912 may be LLC for the N sub-cores 3901A-3901F within graphics core 3900 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 3914 may be included in place of geometry / fixed function pipeline 3936 within fixed function block 3930 and may include the same or similar logic units.

[0316] In at least one embodiment, graphics core 3900 includes additional fixed-function logic 3916, which may include various fixed-function acceleration logic for use by graphics core 3900. In at least one embodiment, additional fixed-function logic 3916 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, a full geometry pipeline and a culling pipeline within geometry / fixed-function pipelines 3916, 3936, which are additional geometry pipelines that may be included in additional fixed-function logic 3916. In at least one embodiment, the culling pipeline is a modified version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate context. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, allowing shading to complete earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 3916 can execute position shaders in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertices without having to perform rasterization and render the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether those triangles are culled. In at least one embodiment, the full pipeline (which in this case may be called a replay pipeline) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0317] In at least one embodiment, the additional fixed function logic 3916 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for implementing slowed down CUAD routines.

[0318] In at least one embodiment, a set of execution resources is included within each graphics sub-core 3901A-3901F that can be used to execute graphics, media, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader programs. In at least one embodiment, the graphics sub-core 3901A-3901F includes a plurality of EU arrays 3902A-3902F, 3904A-3904F, thread dispatch and inter-thread communication ("TD / IC") logic 3903A-3903F, 3D (e.g., texture) samplers 3905A-3905F, media samplers 3906A-3906F, shader processors 3907A-3907F, and shared local memory (SLM) 3908A-3908F. Each EU array 3902A-3902F, 3904A-3904F includes multiple execution units, which are GU GPUs capable of servicing graphics, media, or compute operations, executing floating-point and integer / fixed-point logic operations, including graphics, media, or compute shader programs. In at least one embodiment, TD / IC logic 3903A-3903F performs local thread dispatch and thread control operations for the execution units within the sub-core and facilitates communication between threads executing on the execution units of the sub-core. In at least one embodiment, 3D samplers 3905A-3905F can read texture or other 3D graphics-related data into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, media samplers 3906A-3906F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 3901A-3901F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 3901A-3901F may utilize shared local memory 3908A-3908F within each sub-core, enabling threads executing within a thread group to execute using a common pool of on-chip memory.

[0319] Figure 40A parallel processing unit ("PPU") 4000 is shown in accordance with at least one embodiment. In at least one embodiment, PPU 4000 is configured with machine-readable code that, if executed by PPU 4000, causes PPU 4000 to perform some or all of the processes and techniques described herein. In at least one embodiment, PPU 4000 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a group of instructions configured to be executed by PPU 4000. In at least one embodiment, PPU 4000 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device, such as an LCD device. In at least one embodiment, PPU 4000 is configured to perform computations, such as linear algebra operations and machine learning operations. Figure 40 The example parallel processor is shown for illustrative purposes only and should be construed as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0320] In at least one embodiment, Figure 40 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, the PPU 4000 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0321] In at least one embodiment, one or more PPUs 4000 are configured to accelerate high-performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, one or more PPUs 4000 are configured to accelerate CUDA programs. In at least one embodiment, a PPU 4000 includes, but is not limited to, an I / O unit 4006, a front-end unit 4010, a scheduler unit 4012, a work distribution unit 4014, a hub 4016, a crossbar ("Xbar") 4020, one or more general processing clusters ("GPCs") 4018, and one or more partitioning units ("memory partitioning units") 4022. In at least one embodiment, a PPU 4000 is connected to a host processor or other PPUs 4000 via one or more high-speed GPU interconnects ("GPU interconnects") 4008. In at least one embodiment, a PPU 4000 is connected to a host processor or other peripheral devices via a system bus or interconnect 4002. In one embodiment, PPU 4000 is connected to local memory including one or more memory devices ("memory") 4004. In at least one embodiment, memory device 4004 includes, but is not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high-bandwidth memory ("HBM") subsystem, with multiple DRAM dies stacked within each device.

[0322] In at least one embodiment, the high-speed GPU interconnect 4008 may refer to a wire-based, multi-lane communication link that a system uses to scale and includes one or more PPUs 4000 ("CPUs") in conjunction with one or more CPUs, supporting cache coherency between the PPUs 4000 and the CPUs and CPU mastering. In at least one embodiment, the high-speed GPU interconnect 4008 transmits data and / or commands to other units of the PPU 4000, such as one or more copy engines, video encoders, video decoders, power management units, and / or other processors, via the hub 4016. Figure 40 Other components that may not be explicitly shown.

[0323] In at least one embodiment, the I / O unit 4006 is configured to receive data from the host processor ( Figure 404000). In at least one embodiment, the I / O unit 4006 communicates with the host processor directly via the system bus 4002 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I / O unit 4006 can communicate with one or more other processors (e.g., one or more PPUs 4000) via the system bus 4002. In at least one embodiment, the I / O unit 4006 implements a PCIe interface for communicating via the PCIe bus. In at least one embodiment, the I / O unit 4006 implements an interface for communicating with external devices.

[0324] In at least one embodiment, the I / O unit 4006 decodes packets received via the system bus 4002. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 4000 to perform various operations. In at least one embodiment, the I / O unit 4006 sends the decoded commands to various other units of the PPU 4000 as specified by the commands. In at least one embodiment, the commands are sent to the front end unit 4010 and / or to the hub 4016 or other units of the PPU 4000, such as one or more copy engines, video encoders, video decoders, power management units, etc. ( Figure 40 In at least one embodiment, I / O unit 4006 is configured to route communications between the various logical units of PPU 4000.

[0325] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 4000 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., read / write) by both the host processor and the PPU 4000—the host interface unit can be configured to access the buffer in system memory connected to the system bus 4002 via memory requests transmitted via the I / O unit 4006 over the system bus 4002. In at least one embodiment, the host processor writes a command stream into the buffer and then sends a pointer indicating the beginning of the command stream to the PPU 4000, causing the front end unit 4010 to receive pointers to one or more command streams and manage the one or more command streams, reading commands from the command streams and forwarding the commands to the various units of the PPU 4000.

[0326] In at least one embodiment, the front end unit 4010 is coupled to a scheduler unit 4012, which configures the various GPCs 4018 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 4012 is configured to track state information related to the various tasks managed by the scheduler unit 4012, where the state information may indicate which GPC 4018 the task is assigned to, whether the task is active or inactive, a priority associated with the task, and the like. In at least one embodiment, the scheduler unit 4012 manages multiple tasks that execute on one or more GPCs 4018.

[0327] In at least one embodiment, the scheduler unit 4012 is coupled to a work distribution unit 4014, which is configured to dispatch tasks for execution on GPCs 4018. In at least one embodiment, the work distribution unit 4014 tracks a plurality of scheduled tasks received from the scheduler unit 4012 and manages a pending task pool and an active task pool for each GPC 4018. In at least one embodiment, the pending task pool includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 4018; the active task pool may include a plurality of time slots (e.g., 4 time slots) for tasks actively being processed by GPCs 4018, such that as a task in a GPC 4018 completes execution, the task is evicted from the active task pool of GPC 4018, and one of the other tasks is selected from the pending task pool and scheduled for execution on GPC 4018. In at least one embodiment, if an active task is idle on GPC 4018 , such as while waiting for data dependencies to be resolved, the active task is evicted from GPC 4018 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on GPC 4018 .

[0328] In at least one embodiment, work distribution unit 4014 communicates with one or more GPCs 4018 via XBar 4020. In at least one embodiment, XBar 4020 is an interconnect network that couples many units of PPU 4000 to other units of PPU 4000 and can be configured to couple work distribution unit 4014 to a specific GPC 4018. In at least one embodiment, one or more other units of PPU 4000 can also be connected to XBar 4020 through hub 4016.

[0329] In at least one embodiment, tasks are managed by a scheduler unit 4012 and assigned to one of the GPCs 4018 by a work distribution unit 4014. The GPC 4018 is configured to process tasks and produce results. In at least one embodiment, the results can be consumed by other tasks in the GPC 4018, routed to a different GPC 4018 via an XBar 4020, or stored in memory 4004. In at least one embodiment, the results can be written to memory 4004 via a partition unit 4022, which implements a memory interface for writing data to or reading data from memory 4004. In at least one embodiment, the results can be transferred to another PPU 4004 or a CPU via a high-speed GPU interconnect 4008. In at least one embodiment, the PPU 4000 includes, but is not limited to, U partition units 4022, which equal the number of separate and distinct memory devices 4004 coupled to the PPU 4000.

[0330] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (“API”) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 4000. In one embodiment, multiple computing applications are executed simultaneously by the PPU 4000, and the PPU 4000 provides isolation, quality of service (“QoS”), and independent address spaces for the multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 4000, and the driver core outputs the tasks to one or more streams processed by the PPU 4000. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads that include instructions for executing tasks and exchanging data through shared memory.

[0331] Figure 41 FIG4 shows a GPC 4100 according to at least one embodiment. In at least one embodiment, the GPC 4100 is Figure 40GPC 4018. In at least one embodiment, each GPC 4100 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 4100 includes, but is not limited to, a pipeline manager 4102, a pre-raster operations unit ("PROP") 4104, a raster engine 4108, a work distribution crossbar ("WDX") 4116, a memory management unit ("MMU") 4118, one or more data processing clusters ("DPCs") 4106, and any suitable combination of components.

[0332] In at least one embodiment, Figure 41 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, the GPC 4100 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0333] In at least one embodiment, the operation of the GPC 4100 is controlled by a pipeline manager 4102. In at least one embodiment, the pipeline manager 4102 manages the configuration of one or more DPCs 4106 to process tasks assigned to the GPC 4100. In at least one embodiment, the pipeline manager 4102 configures at least one of the one or more DPCs 4106 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC 4106 is configured to execute vertex shader programs on a programmable streaming multiprocessor ("SM") 4114. In at least one embodiment, the pipeline manager 4102 is configured to route packets received from the work distribution unit to appropriate logic within the GPC 4100, and in at least one embodiment, some packets may be routed to fixed-function hardware units in the PROP 4104 and / or raster engine 4108, while other packets may be routed to the DPC 4106 for processing by the primitive engine 4112 or the SM 4114. In at least one embodiment, pipeline manager 4102 configures at least one of DPCs 4106 to implement a neural network model and / or a computational pipeline. In at least one embodiment, pipeline manager 4102 configures at least one of DPCs 4106 to execute at least a portion of a CUDA program.

[0334] In at least one embodiment, PROP unit 4104 is configured to route data generated by raster engine 4108 and DPC 4106 to a raster operations ("ROP") unit in a partition unit, such as described above in conjunction with Figure 40Memory partitioning unit 4022, etc., described in more detail. In at least one embodiment, PROP unit 4104 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, raster engine 4108 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 4108 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to the coarse raster engine to generate coverage information for the primitives (e.g., an x, y coverage mask for the tile); the output of the coarse raster engine is passed to the culling engine, where fragments associated with primitives that fail the z test are culled, and to the clipping engine, where fragments outside the viewing frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to a fine raster engine to generate properties for the pixel fragments based on a plane equation generated by the setup engine. In at least one embodiment, the output of the raster engine 4108 includes fragments to be processed by any appropriate entity (e.g., by a fragment shader implemented within the DPC 4106).

[0335] In at least one embodiment, each DPC 4106 included in a GPC 4100 includes, but is not limited to, an M-pipeline controller ("MPC") 4110; a primitive engine 4112; one or more SMs 4114; and any suitable combination thereof. In at least one embodiment, the MPC 4110 controls the operation of the DPC 4106, routing packets received from the pipeline manager 4102 to appropriate units within the DPC 4106. In at least one embodiment, packets associated with vertices are routed to the primitive engine 4112, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, packets associated with shader programs may be sent to the SM 4114.

[0336] In at least one embodiment, SM 4114 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, SM 4114 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular thread group and implements a single instruction, multiple data ("SIMD") architecture, in which each thread in a group of threads (e.g., a warp) is configured to process a different data set based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instructions. In at least one embodiment, SM 4114 implements a single instruction, multiple thread ("SIMT") architecture, in which each thread in a group of threads is configured to process a different data set based on the same instruction set, but in which individual threads in a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby enabling concurrency between warps and serial execution within a warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby enabling equal concurrency between all threads within a warp and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instruction can be converged and executed in parallel to improve efficiency. Figure 42 At least one embodiment of SM 4114 is described in more detail.

[0337] In at least one embodiment, the MMU 4118 provides a communication channel between the GPC 4100 and the memory partition unit (e.g., Figure 40 The MMU 4118 provides an interface between the memory and the partition unit 4022, and provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 4118 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0338] Figure 42 Streaming Multiprocessor ("SM") 4200 is shown in accordance with at least one embodiment. In at least one embodiment, SM 4200 is Figure 41SM 4114. In at least one embodiment, SM 4200 includes, but is not limited to, an instruction cache 4202; one or more scheduler units 4204; a register file 4208; one or more processing cores ("cores") 4210; one or more special function units ("SFUs") 4212; one or more load / store units ("LSUs") 4214; an interconnect network 4216; a shared memory / level 1 ("L1") cache 4218; and any suitable combination thereof. In at least one embodiment, a work distribution unit schedules tasks for execution on a general processing cluster ("GPC") of a parallel processing unit ("PPU"), with each task being assigned to a specific data processing cluster ("DPC") within the GPC, and if the task is associated with a shader program, the task is assigned to one of SMs 4200. In at least one embodiment, scheduler unit 4204 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 4200. In at least one embodiment, the scheduler unit 4204 schedules thread blocks for execution as warps of parallel threads, where each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 4204 manages multiple different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from multiple different cooperative groups to various functional units (e.g., processing cores 4210, SFUs 4212, and LSUs 4214) during each clock cycle. In at least one embodiment, the SM 4200 includes one or more thread block clusters, where thread block clusters can implement programmatic control of locality at a finer granularity than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, thread block clusters (also referred to as "clusters") enable multiple thread blocks running concurrently across a streaming multiprocessor to synchronously and cooperatively acquire, exchange, or otherwise use data.

[0339] In at least one embodiment, Figure 42 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, SM 4200 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0340] In at least one embodiment, "cooperative groups" may refer to a programming model for organizing groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling the expression of richer and more efficient decompositions of parallelism. In at least one embodiment, a cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, conventional programming model APIs provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads() function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than a thread block and synchronize within the defined group to achieve higher performance, design flexibility, and software reuse in the form of a collective group-wide function interface. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at sub-block and multi-block granularity and perform collective operations, such as synchronizing threads within a cooperative group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing libraries and utility functions to safely synchronize within their local environment without making assumptions about convergence. In at least one embodiment, the cooperation group primitive enables new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

[0341] In at least one embodiment, the dispatch unit 4206 is configured to send instructions to one or more of the functional units, and the scheduler unit 4204 includes, but is not limited to, two dispatch units 4206 that enable two different instructions from the same warp to be dispatched per clock cycle. In at least one embodiment, each scheduler unit 4204 includes a single dispatch unit 4206 or additional dispatch units 4206.

[0342] In at least one embodiment, each SM 4200 includes, but is not limited to, a register file 4208 that provides a set of registers for the functional units of SM 4200. In at least one embodiment, register file 4208 is partitioned between each functional unit, allocating a dedicated portion of register file 4208 to each functional unit. In at least one embodiment, register file 4208 is partitioned between the different warps executed by SM 4200, and register file 4208 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM 4200 includes, but is not limited to, a plurality of L processing cores 4210. In at least one embodiment, SM 4200 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 4210. In at least one embodiment, each processing core 4210 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, processing core 4210 includes, but is not limited to, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

[0343] In at least one embodiment, the tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing core 4210. In at least one embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0344] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating-point matrices, and the accumulation matrices C and D are 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the tensor core performs a 32-bit floating-point accumulation operation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations and obtains a full-precision product, which is then accumulated with other intermediate products using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as the CUDA-C++ API) exposes specialized matrix load, matrix multiplication and accumulation, and matrix store operations to efficiently use the tensor cores from a CUDA-C++ program. In at least one embodiment, at the CUDA level, the warp-level interface assumes a 16×16 matrix size across all 32 warp threads.

[0345] In at least one embodiment, each SM 4200 includes, but is not limited to, M SFUs 4212 that perform specialized functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs 4212 include, but are not limited to, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs 4212 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., 2D arrays of texels) from memory and sample the texture maps to generate sampled texture values ​​for use by shader programs executed by the SM 4200. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 4218. In at least one embodiment, the texture units implement texture operations (such as filtering operations) using mip-maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM 4200 includes, but is not limited to, two texture units.

[0346] In at least one embodiment, each SM 4200 includes, but is not limited to, N LSUs 4214 that implement load and store operations between shared memory / L1 cache 4218 and register file 4208. In at least one embodiment, each SM 4200 includes, but is not limited to, an interconnection network 4216 that connects each functional unit to register file 4208, and the LSUs 4214 connect to register file 4208 and shared memory / L1 cache 4218. In at least one embodiment, the interconnection network 4216 is a crossbar switch that can be configured to connect any functional unit to any register in register file 4208, and to connect the LSUs 4214 to memory locations in register file 4208 and shared memory / L1 cache 4218.

[0347] In at least one embodiment, shared memory / L1 cache 4218 is an array of on-chip memory that, in at least one embodiment, allows for data storage and communication between the SM 4200 and the primitive engines, as well as between threads within the SM 4200. In at least one embodiment, shared memory / L1 cache 4218 includes, but is not limited to, 128KB of storage capacity and is located in the path from the SM 4200 to the partition unit. In at least one embodiment, shared memory / L1 cache 4218 is used in at least one embodiment to cache reads and writes. In at least one embodiment, one or more of shared memory / L1 cache 4218, L2 cache, and memory is a backing store.

[0348] In at least one embodiment, data cache and shared memory functionality are combined into a single memory block, providing improved performance for both types of memory accesses. In at least one embodiment, capacity is used by programs that do not use the shared memory or use it as a cache. For example, if the shared memory is configured to use half of its capacity, texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 4218 enables the shared memory / L1 cache 4218 to function as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed, creating a simpler programming model. In at least one embodiment, in a general-purpose parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, threads in a block execute the same program, use unique thread IDs in computations to ensure that each thread generates unique results, use SM 4200 to execute the program and perform computations, use shared memory / L1 cache 4218 to communicate between threads, and use LSU 4214 to read and write global memory through shared memory / L1 cache 4218 and a memory partitioning unit. In at least one embodiment, when configured for general-purpose parallel computation, SM 4200 writes commands to scheduler unit 4204 that can be used to start new work on a DPC. In at least one embodiment, SM 4200 includes one or more distributed shared memories (or distributed shared memories) that enable direct SM-to-SM operations, such as loads, stores, and atomic operations performed across memory blocks shared by multiple SMs.

[0349] In at least one embodiment, SM 4200 includes one or more asynchronous execution functions, including a tensor memory accelerator (TMA) unit that can transfer data blocks between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, such as from global memory to shared memory and vice versa. In at least one embodiment, SM 4200 includes one or more TMAs for asynchronously copying between thread blocks in the cluster. In at least one embodiment, SM 4200 includes one or more asynchronous transaction barriers for performing atomic data movement and synchronization. In at least one embodiment, SM 4200 includes a Tensor Core Converter Engine, which includes software and one or more cores for accelerating converter model training and inference. In at least one embodiment, a converter of one or more processor cores executing one or more Tensor Core Converter Engines manages FP8 and 16-bit computations and dynamically selects between FP8 and 16-bit by recasting and scaling between FP8 and 16-bit in each layer of one or more neural networks.

[0350] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), PDA, digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-chip ("SoC") along with one or more other devices (e.g., additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), etc.).

[0351] In at least one embodiment, the PPU can be included on a graphics card that includes one or more storage devices. The graphics card can be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU can be an integrated GPU ("iGPU") included in a chipset on the motherboard.

[0352] Software Construction for General Computing

[0353] The following figures illustrate, but are not limited to, exemplary software architectures for implementing at least one embodiment.

[0354] Figure 43A software stack for a programming platform according to at least one embodiment is shown. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate computing tasks. In at least one embodiment, a software developer can access the programming platform through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform ("ROCm"), OpenCL (OpenCL developed by Khronos group), TM ), SYCL, or Intel One API.

[0355] In at least one embodiment, Figure 43 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, the software stack 4300 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0356] In at least one embodiment, the programming platform's software stack 4300 provides an execution environment for applications 4301. In at least one embodiment, applications 4301 may include any computer software capable of being launched on software stack 4300. In at least one embodiment, applications 4301 may include, but are not limited to, artificial intelligence ("AI") / machine learning ("ML") applications, high performance computing ("HPC") applications, virtual desktop infrastructure ("VDI"), or data center workloads.

[0357] In at least one embodiment, application 4301 and software stack 4300 run on hardware 4307. In at least one embodiment, hardware 4307 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support programming platforms. In at least one embodiment, for example, using CUDA, software stack 4300 may be vendor-specific and compatible only with devices from a specific vendor. In at least one embodiment, for example, using OpenCL, software stack 4300 can be used with devices from different vendors. In at least one embodiment, hardware 4307 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computing tasks. In at least one embodiment, compared to the host within hardware 4307, which may include but is not limited to a CPU (but may also include a computing device) and its memory, the devices within hardware 4307 may include but are not limited to a GPU, FPGA, AI engine, or other computing device (but may also include a CPU) and its memory.

[0358] In at least one embodiment, the programming platform's software stack 4300 includes, but is not limited to, a plurality of libraries 4303, a runtime 4305, and device kernel drivers 4306. In at least one embodiment, each of the libraries 4303 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the libraries 4303 may include, but are not limited to, prewritten code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 4303 include functions optimized for execution on one or more types of devices. In at least one embodiment, the libraries 4303 may include, but are not limited to, functions for performing mathematical, deep learning, and / or other types of operations on the devices. In at least one embodiment, the libraries 4303 are associated with corresponding APIs 4302, which may include one or more APIs that expose the functions implemented in the libraries 4303. In at least one embodiment, a processor (e.g., a CPU, a GPU) executes, calls, or otherwise uses one or more APIs to prioritize kernels. For example, a first kernel (e.g., a parent kernel) can launch a second kernel (e.g., a child kernel), and the second kernel can be used by the processor to launch an additional kernel (e.g., a grandchild kernel) independent of the first kernel. In at least one embodiment, the processor executes an API or calls an API to be executed from memory to support dynamic stream priorities (e.g., updating priorities while a stream is being used to perform an operation). For example, when the processor executes the API, it allows a programmer to copy stream priorities from one stream to one or more other streams.

[0359] In at least one embodiment, the software stack 4300 includes an API for supporting dynamic stream prioritization (e.g., updating the priority while a stream is being used to perform an operation) that allows a programmer to set the priority of a stream at any time after creation. In at least one embodiment, the software stack 4300 includes an API for supporting dynamic stream prioritization (e.g., updating the priority while a stream is being used to perform an operation) that allows a programmer to obtain the current priority of a stream, where the priority is one of multiple attributes of the stream. In at least one embodiment, the software stack 4300 includes an API for supporting dynamic stream prioritization (e.g., updating the priority while a stream is being used to perform an operation) that allows a programmer to obtain the current priority of a stream as a single attribute. In at least one embodiment, the software stack 4300 includes an API for supporting dynamic stream prioritization (e.g., updating the priority while a stream is being used to perform an operation) that allows a programmer to launch a kernel to perform operations on a stream at a set priority (which may be different from the stream priority). In at least one embodiment, the software stack 4300 includes an API for indicating whether an object (e.g., a thread synchronization object such as a barrier) that tracks whether all data movement operations for a set of threads operating on the GPU completes with a specified state after a specified time period, where the specified state can be a state indicating that the data has been moved and is ready for use, and is specified using an expected parity value as input to the API.

[0360] In at least one embodiment, the software stack 4300 includes one or more APIs for updating kernels. In at least one embodiment, the processor that executes the API or calls the API to be executed from memory to update to an existing API supports context-free kernels, which allows the programmer to add kernel nodes to the graph without a graphics context so that the graphics context can be dynamically associated with the kernel at runtime. In at least one embodiment, the software stack 4300 includes one or more APIs that allow the programmer to obtain the kernel identifier and the graphics context as separate parameters from the kernel node, thereby obtaining parameters from the kernel and the context-free kernel. In at least one embodiment, the software stack 4300 includes one or more APIs for launching a task graph (e.g., a task graph) and executing one or more task graphs (e.g., including one or more programs) using a parallel processor (such as, one or more graphics processing units).

[0361] In at least one embodiment, the software stack 4300 includes one or more APIs for associating one or more instructions with one or more memory ordering operations (e.g., fence or bank operations). In at least one embodiment, instructions are associated with one or more domains such that memory ordering operations are performed in association with one or more specific domains without interfering with instructions from other domains. In at least one embodiment, the software stack 4300 includes an API for indicating that a thread has reached (e.g., at a thread synchronization barrier) or completed a stage of work associated with asynchronous data movement operations on the GPU. In at least one embodiment, the software stack 4300 includes one or more APIs for allowing a programmer to manually indicate an expected transaction count when a thread completes a stage of work, which transaction count is used to update an object that tracks whether all data movement operations for a group of threads are complete.

[0362] In at least one embodiment, application 4301 is written as source code that is compiled into executable code as follows: Figures 48-50 4301. In at least one embodiment, the executable code of application 4301 can be run at least in part on an execution environment provided by software stack 4300. In at least one embodiment, during the execution of application 4301, code that needs to be run on the device (as opposed to the host) can be obtained. In this case, in at least one embodiment, runtime 4305 can be called to load and start the necessary code on the device. In at least one embodiment, runtime 4305 can include any technically feasible runtime system capable of supporting the execution of application S01.

[0363] In at least one embodiment, runtime 4305 is implemented as one or more runtime libraries associated with a corresponding API (shown as API 4304). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory, and for transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching a function on the device (sometimes referred to as a "kernel" when the function is a global function callable from the host), and functions for setting property values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0364] In at least one embodiment, the runtime library and corresponding API 4304 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs can expose a low-level set of functions for fine-grained control of a device, while another (or any number of) APIs can expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of a language-independent runtime API.

[0365] In at least one embodiment, one or more processors disclosed in the "processing system" may execute, access, or otherwise use the software stack 4300. For example, the APU 3000, the CPU 3100, Figures 33A-33B The exemplary graphics processor, general-purpose graphics processing unit (“GPGPU”) 3430, parallel processor 3500, processing cluster 3594, graphics multiprocessor 3534, graphics multiprocessor 3596, graphics processor 3600, processor 3700, processor 3800, parallel processing unit (“PPU”) 4000, GPC 4100 and / or streaming multiprocessor (“SM”) 4200 can execute, use, call or otherwise implement (e.g., by accessing memory) one or more APIs included in software stack 4300.

[0366] In at least one embodiment, the device kernel driver 4306 is configured to facilitate communication with the underlying device. In at least one embodiment, the device kernel driver 4306 can provide APIs such as API 4304 and / or low-level functions that other software relies on. In at least one embodiment, the device kernel driver 4306 can be configured to compile intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 4306 can compile non-hardware-specific parallel thread execution ("PTX") IR code into binary code for a specific target device at runtime (caching the compiled binary code), which is sometimes also referred to as "final" code. In at least one embodiment, doing so can allow the final code to run on a target device that may not have existed when the source code was originally compiled into PTX code. Alternatively, in at least one embodiment, the device source code can be compiled into binary code offline without requiring the device kernel driver 4306 to compile the IR code at runtime.

[0367] Figure 44 According to at least one embodiment, Figure 4343. CUDA implementation of software stack 4300. In at least one embodiment, CUDA software stack 4400, on which application 4401 may be launched, includes CUDA libraries 4403, a CUDA runtime 4405, a CUDA driver 4407, and a device kernel driver 4408. In at least one embodiment, CUDA software stack 4400 executes on hardware 4409, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0368] In at least one embodiment, Figure 44 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, application 4401 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0369] In at least one embodiment, application 4401, CUDA runtime 4405, and device kernel driver 4408 may perform similar functions as application 4301, runtime 4305, and device kernel driver 4306, respectively. Figure 434. CUDA Driver 4407 is described in detail below. In at least one embodiment, the CUDA driver 4407 includes a library (libcuda.so) that implements the CUDA driver API 4406. In at least one embodiment, similar to the CUDA runtime API 4404 implemented by the CUDA runtime library (cudart), the CUDA driver API 4406 may expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 4406 differs from the CUDA runtime API 4404 in that the CUDA runtime API 4404 simplifies device code management by providing implicit initialization, context (similar to process) management, and module (similar to dynamically loaded libraries) management. In contrast to the high-level CUDA runtime API 4404, in at least one embodiment, the CUDA driver API 4406 is a low-level API that provides finer-grained control over the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 4406 may expose functions for context management that are not exposed by the CUDA runtime API 4404. In at least one embodiment, the CUDA driver API 4406 is also language-independent and supports, for example, OpenCL in addition to the CUDA runtime API 4404. Furthermore, in at least one embodiment, the development libraries, including the CUDA runtime 4405, can be considered separate from the driver components, including the user-mode CUDA driver 4407 and the kernel-mode device driver 4408 (sometimes also referred to as a "display" driver).

[0370] In at least one embodiment, the CUDA libraries 4403 may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which may be utilized by parallel computing applications (e.g., application 4401). In at least one embodiment, the CUDA libraries 4403 may include mathematical libraries, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subroutines ("BLAS") for performing linear algebra operations; the cuFFT library for computing fast Fourier transforms ("FFTs"), and the cuRAND library for generating random numbers, among others. In at least one embodiment, the CUDA libraries 4403 may include deep learning libraries, such as the cuDNN library for primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference, among others.

[0371] Figure 45 According to at least one embodiment, Figure 4345. In at least one embodiment, the ROCm software stack 4500, on which an application 4501 can be launched, includes a language runtime 4503, a system runtime 4505, thunks 4507, and a ROCm kernel driver 4508. In at least one embodiment, the ROCm software stack 4500 executes on hardware 4509, which may include a ROCm-enabled GPU developed by AMD, Inc. of Santa Clara, California.

[0372] In at least one embodiment, Figure 45 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, the ROCm software stack 4500 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0373] In at least one embodiment, application 4501 may execute a combination of the above Figure 43 In addition, in at least one embodiment, the language runtime 4503 and the system runtime 4505 can perform functions similar to those described above in conjunction with the application 4301. Figure 43 The language runtime 4503 and the system runtime 4505 are similar in functionality to the runtime 4305 discussed above. In at least one embodiment, the language runtime 4503 differs from the system runtime 4505 in that the system runtime 4505 is a language-agnostic runtime that implements the ROCr system runtime API 4504 and leverages the Heterogeneous System Architecture ("HSA") runtime API. In at least one embodiment, the HSA runtime API is a thin user-mode API that exposes interfaces for accessing and interacting with the AMDGPU, including functions for memory management, execution control of kernels dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, compared to the system runtime 4505, the language runtime 4503 is an implementation of a language-specific runtime API 4502 layered on top of the ROCr system runtime API 4504. In at least one embodiment, the language runtime API may include, but is not limited to, a portable heterogeneous compute interface ("HIP") language runtime API, a heterogeneous compute compiler ("HCC") language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes a Figure 44Similar functions to the CUDA runtime API 4404 are discussed, such as those used for memory management, execution control, device management, error handling, and synchronization.

[0374] In at least one embodiment, thunk (ROCt) 4507 is an interface 4506 that can be used to interact with the underlying ROCm driver 4508. In at least one embodiment, the ROCm driver 4508 is a ROCk driver, which is a combination of the AMDGPU driver and the HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs the above combined Figure 43 The HSA kernel driver 4306 may function similarly to the discussed device kernel driver 4306. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to more efficiently share system resources via hardware features.

[0375] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 4500 above the language runtime 4503 and provide Figure 44 The various libraries may include, but are not limited to, math, deep learning, and / or other libraries, such as a hipBLAS library that implements functions similar to CUDA cuBLAS, a rocFFT library similar to CUDA cuFFT for computing FFTs, and the like.

[0376] Figure 46 According to at least one embodiment, Figure 43 4300. In at least one embodiment, the OpenCL software stack 4600, on which the application 4601 can be launched, includes an OpenCL framework 4610, an OpenCL runtime 4606, and a driver 4607. In at least one embodiment, the OpenCL software stack 4600 executes on hardware 4409 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0377] In at least one embodiment, Figure 46 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, application 4601 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0378] In at least one embodiment, the application 4601, the OpenCL runtime 4606, the device kernel driver 4607, and the hardware 4608 can each execute the above combined Figure 43 Similar functionality is discussed for application 4301, runtime 4305, device kernel driver 4306, and hardware 4307. In at least one embodiment, application 4601 also includes an OpenCL kernel 4602 having code to be executed on the device.

[0379] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 4603 and runtime API 4605. In at least one embodiment, runtime API 4605 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device can be associated with a respective context, which runtime API 4605 can use to manage the device's command queue, program and kernel objects, shared memory objects, and the like. In at least one embodiment, platform API 4603 exposes functions that allow device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices. Additionally, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, image processing functions, and the like.

[0380] In at least one embodiment, compiler 4604 is also included in OpenCL framework 4610. In at least one embodiment, source code can be compiled offline before executing the application or compiled online during execution of the application. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment can be compiled online by compiler 4604, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation ("SPIR-V") code) into binary code. Alternatively, in at least one embodiment, OpenCL applications can be compiled offline before executing such applications.

[0381] Figure 47Software supported by a programming platform according to at least one embodiment is shown. In at least one embodiment, programming platform 4704 is configured to support various programming models 4703, middleware and / or libraries 4702, and frameworks 4701 that applications 4700 can rely on. In at least one embodiment, application 4700 can be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which can rely on libraries such as cuDNN, NVIDIA Collective Communications Library ("NCCL"), and / or NVIDIA Developer Data Loading Library ("DALI") CUDA libraries to provide accelerated computation on the underlying hardware.

[0382] In at least one embodiment, Figure 47 At least one component shown or described is used to implement the combination Figure 1-23 In at least one embodiment, application 4702 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0383] In at least one embodiment, the programming platform 4704 can be a combination of the above Figure 44 、 Figure 45 and Figure 46 In at least one embodiment, programming platform 4704 supports one of the CUDA, ROCm, or OpenCL platforms described herein. In at least one embodiment, programming platform 4704 supports multiple programming models 4703, which are abstractions of the underlying computing system that allow the expression of algorithms and data structures. In at least one embodiment, programming model 4703 can expose features of the underlying hardware to improve performance. In at least one embodiment, programming model 4703 can include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multiprocessing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute.

[0384] In at least one embodiment, the library and / or middleware 4702 provides an abstract implementation of the programming model 4704. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those that can be obtained from the programming platform 4704, such middleware also includes software that provides services to the application. In at least one embodiment, the library and / or middleware 4702 may include but is not limited to cuBLAS, cuFFT, cuRAND and other CUDA libraries, or rocBLAS, rocFFT, rocRAND and other ROCm libraries. In addition, in at least one embodiment, the library and / or middleware 4702 may include NCCL and ROCm communication collection libraries ("RCCL") libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0385] In at least one embodiment, application framework 4701 relies on libraries and / or middleware 4702. In at least one embodiment, each application framework 4701 is a software framework for implementing a standard structure for application software. Returning to the AI / ML example discussed above, in at least one embodiment, AI / ML applications can be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning framework.

[0386] Figure 48 Compiled code is shown in accordance with at least one embodiment to Figures 43-46 In at least one embodiment, compiler 4801 receives source code 4800, which includes both host code and device code. In at least one embodiment, compiler 4801 is configured to convert source code 4800 into host executable code 4802 for execution on the host and device executable code 4803 for execution on the device. In at least one embodiment, source code 4800 can be compiled offline before executing the application, or compiled online during execution of the application. In at least one embodiment, compiler 4801 includes or has access to one or more libraries to identify a sequence of API calls for executing a single fusion API, where the single fusion API is a combined API of two or more APIs.

[0387] In at least one embodiment, Figure 48 At least one component shown or described is used to implement the combination Figure 1-23In at least one embodiment, compiler 4801 performs one or more operations to identify one or more pixels within a polygon based on one or more pixels adjacent to the one or more pixels within the polygon and intersecting one or more polygon boundaries, such as in conjunction with Figure 15 as described and as described elsewhere herein.

[0388] In at least one embodiment, source code 4800 may include code in any programming language supported by compiler 4801, such as C++, C, Fortran, etc. In at least one embodiment, source code 4800 may be included in a single-source file having a mixture of host code and device code, with the location of the device code indicated therein. In at least one embodiment, the single-so...

Claims

1. A processor, comprising: One or more circuits for identifying one or more pixels within a polygon based at least in part on whether the one or more pixels within the polygon are adjacent to one or more pixels that intersect one or more polygon boundaries.

2. The processor of claim 1 , wherein the one or more circuits are configured to identify an amount of the one or more pixels within the polygon based at least in part on an amount of the one or more pixels that is covered by one or more sides of the polygon. 3 . The processor of claim 1 , wherein the one or more circuits are configured to use one or more prefix sums along one or more dimensions to identify an amount of one or more pixels within the polygon. 4 . The processor of claim 1 , wherein the one or more circuits are to parallelize calculations of an amount of one or more pixels covered by the polygon by two or more sides of the polygon. 5 . The processor of claim 1 , wherein the one or more circuits are configured to perform, at least in part, a computational lithography task using the identified one or more pixels.

6. The processor of claim 1 , wherein the one or more circuits are configured to identify one or more portions of the one or more edges based at least in part on one or more intersections between the one or more edges of the polygon and one or more pixels adjacent to the one or more pixels.

7. The processor of claim 1, wherein the one or more circuits are configured to identify an amount of one or more pixels within a polygon based at least in part on one or more portions of one or more sides of the polygon.

8. A system comprising: One or more processors for identifying one or more pixels within a polygon based at least in part on whether the one or more pixels within the polygon are adjacent to one or more pixels that intersect one or more polygon boundaries.

9. The system of claim 8, wherein the one or more processors are configured to identify an amount of the one or more pixels within the polygon based at least in part on a proportion of the one or more pixels that is covered by one or more sides of the polygon.

10. The system of claim 8, wherein the one or more processors are configured to use one or more prefix sums along one or more rows of one or more pixels to identify an amount of one or more pixels that is within the polygon.

11. The system of claim 8, wherein the one or more processors are to parallelize calculations of an amount of one or more sides of the polygon of one or more pixels covered by two or more sides of the polygon.

12. The system of claim 8, wherein the one or more processors are configured to identify the one or more pixels within a polygon for computational lithography.

13. The system of claim 8, wherein the one or more processors are configured to identify one or more portions of one or more sides of the polygon based at least in part on one or more locations where two or more sides of the polygon meet.

14. The system of claim 8, wherein the one or more processors are configured to identify an amount of one or more pixels within a polygon by using one or more width values ​​based at least in part on one or more portions of one or more sides of the polygon.

15. A method comprising: One or more pixels within a polygon are identified based at least in part on whether the one or more pixels within the polygon are adjacent to one or more pixels that intersect one or more polygon boundaries.

16. The method according to claim 15, further comprising: An amount of one or more pixels within the polygon is identified based at least in part on a projection of one or more portions of one or more sides of the polygon onto sides of one or more adjacent pixels.

17. The method according to claim 15, further comprising: One or more prefix sums of amounts of the one or more pixels that are covered by one or more sides of the polygon are used.

18. The method according to claim 15, further comprising: The computation of one or more quantities for one or more pixels within the polygon across two or more portions of one or more sides of the polygon is parallelized.

19. The method according to claim 15, further comprising: The one or more pixels within the polygon are identified for rasterization.

20. The method of claim 15, further comprising: One or more portions of the one or more sides of the polygon that pass through one or more pixels are identified.

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