Hammering prevention circuit and memory having same

Abstract

The invention provides a hammering prevention circuit and a memory with the same, and the hammering prevention circuit comprises an enabling module which is configured to receive a first latch control signal and a second latch control signal, and generates a latch enabling signal based on the first latch control signal and the second latch control signal; when the latch module is in an effective activation state based on the latch enable signal, a corresponding input address is latched as a target address, so that subsequent hammering refreshing operation is carried out; the judging module is connected with the enabling module and generates a second latch control signal according to the target address; the second latch control signal is configured based on a preset condition, and the preset condition comprises at least one of the following conditions: whether the input address to be latched is the same as a target address latched in the latch module; or whether the current hammering refreshing operation executed by the current target address is completed is judged, and the scheme is beneficial for improving the protection effect of the hammering prevention circuit on the stored data.

Description

Technical Field

[0001] The disclosed embodiments of the present application relate to the field of storage technology, and more particularly, to a hammer prevention circuit and a memory having the same. Background Art

[0002] In memory circuits, the memory array consists of several rows of storage capacitors. When the memory cells in a row are frequently read, the values ​​of the storage capacitor cells in several adjacent rows may be overwritten due to signal coupling, which is a phenomenon called hammering.

[0003] In order to reduce the impact of hammering on the stored data, a hammering refresh operation needs to be performed on the address where the hammering phenomenon may occur. However, the current hammering prevention circuit does not provide an ideal protection effect on the stored data when performing the hammering refresh operation.

[0004] Therefore, how to improve the protection effect of the hammer prevention circuit on stored data has become an urgent problem to be solved. Summary of the Invention

[0005] According to an embodiment of the present application, the present invention provides a hammer prevention circuit and a memory having the same, so as to at least improve the protection effect of the hammer prevention circuit on stored data.

[0006] According to one aspect of the present application, a hammer prevention circuit is disclosed, comprising an enable module, a latch module and a determination module; the enable module is configured to receive a first latch control signal and a second latch control signal, and generate a latch enable signal based on the first latch control signal and the second latch control signal, and in response to the first latch control signal and the second latch control signal both being in an effective activation state, the latch enable signal is in an effective activation state; the latch module is connected to the enable module, and the latch module latches the corresponding input address as the target address based on the latch enable signal being in an effective activation state, so as to perform subsequent hammer refresh operations; the determination module is connected to the enable module, and generates a second latch control signal according to the target address; wherein the second latch control signal is configured based on preset conditions, and the preset conditions include at least one of the following: whether the input address to be latched is the same as the target address latched in the latch module; or whether the current hammer refresh operation executed by the current target address is completed.

[0007] A second aspect of the present application discloses a memory, which includes the hammer prevention circuit in the first aspect.

[0008] In the above scheme, a second latch control signal is generated by a determination module, and the second latch control signal is configured based on a preset condition, the preset condition including at least one of the following: whether the input address to be latched is the same as the target address latched in the latch module; or whether the current hammer refresh operation performed on the current target address is completed. Therefore, the enabling module can control the latch module to latch the corresponding input address as the target address based on whether the new address is the same as the target address and / or whether the current hammer refresh operation of the current target address is completed, so as to perform a hammer refresh operation on the target address. By determining whether the current hammer refresh operation of the current target address is completed, the determination module is conducive to preventing the hammer refresh operation from being performed on the new address before the current hammer refresh operation of the current target address is completed, thereby improving the protection effect of the hammer prevention circuit on stored data. By determining whether the new address is the same as the target address, repeated hammer refresh operations on the same target address are prevented, thereby facilitating the execution of hammer refresh operations on more different target addresses within the same time, thereby improving the protection effect of the hammer prevention circuit on stored data. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present application will be further described below with reference to the accompanying drawings and implementation methods, in which: Figure 1 1 is a schematic diagram of a hammer prevention circuit in an embodiment of the present application; Figure 2 It is a schematic diagram of the framework of the hammer prevention circuit in the prior art; Figure 3 is a schematic diagram of a framework of a hammer prevention circuit in another embodiment of the present application; Figure 4 is a schematic diagram of a framework of a comparator in one embodiment of the present application; Figure 5 is a schematic diagram of a framework of a hammer prevention circuit in yet another embodiment of the present application; Figure 6 is a schematic diagram of a framework of a hammer prevention circuit in yet another embodiment of the present application; Figure 7 is a schematic diagram of a framework of a hammer prevention circuit in yet another embodiment of the present application; Figure 8 is a schematic diagram of a framework of a hammer prevention circuit in yet another embodiment of the present application; Figure 9 1 is a schematic diagram of a latch unit in a hammer prevention circuit according to an embodiment of the present application; Figure 10 Schematic diagram of a memory frame according to an embodiment of the present application. DETAILED DESCRIPTION

[0010] To help those skilled in the art better understand the technical solutions of this application, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and specific implementation methods. Obviously, the embodiments described are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of this application.

[0011] The terms used in the examples of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a," "the," and "the" used in the examples of this application and the appended claims are also intended to include plural forms. Unless otherwise clearly indicated above, "a plurality" generally includes at least two, but does not exclude the inclusion of at least one.

[0012] It should be understood that the term "and / or" as used herein is merely a description of the association relationship between associated objects, indicating that three possible relationships exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship. The terms "first," "second," etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0013] It should be understood that the terms "comprises," "comprising," or any other variations thereof as used herein are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0014] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0015] In memory circuits, the memory array consists of several rows of storage capacitors. When the memory cells in a row are frequently read, the values ​​of the storage capacitor cells in several adjacent rows may be overwritten due to signal coupling, which is a phenomenon called hammering.

[0016] In order to reduce the impact of hammering on the stored data, a hammering refresh operation needs to be performed on the address where the hammering phenomenon may occur. However, the current hammering prevention circuit does not provide an ideal protection effect on the stored data when performing the hammering refresh operation.

[0017] In order to improve the protection effect of stored data, according to one aspect of the present application, a hammer prevention circuit 100 is disclosed. Figure 1 The hammer prevention circuit 100 includes an enable module 110, a latch module 120 and a determination module 130; the enable module 110 is configured to receive a first latch control signal and a second latch control signal, and generate a latch enable signal based on the first latch control signal and the second latch control signal, and in response to the first latch control signal and the second latch control signal being in a valid activation state, the latch enable signal is in a valid activation state; the latch module 120 is connected to the enable module 110, and the latch module 120 latches the corresponding input address as the target address when the latch enable signal is in a valid activation state, so as to perform a subsequent hammer refresh operation; the determination module 130 is connected to the enable module 110, and generates the second latch control signal according to the target address; wherein the second latch control signal is configured based on a preset condition, and the preset condition includes at least one of the following: whether the input address to be latched is the same as the target address latched in the latch module 120; or whether the current hammer refresh operation executed by the current target address is completed.

[0018] It should be understood that the first latch control signal, the second latch control signal and the latch enable signal can have two states: a logic high level (for example, 3.3V) and a logic low level (for example, 0V). The effective activation state of the first latch control signal, the second latch control signal and the latch enable signal can be one of a logic high level and a logic low level. For example, when the first latch control signal, the second latch control signal and the latch enable signal are at a logic high level, they are deemed to be in an effective activation state; or, the effective activation states of the first latch control signal, the second latch control signal and the latch enable signal can also be different. For example, when the first latch control signal and the second latch control signal are at a logic high level, they are deemed to be in an effective activation state, and when the latch enable signal is at a logic low level, it is deemed to be in an effective activation state, and so on. The present application does not impose any restrictions on this.

[0019] The first latch control signal can be generated based on the latch state of the latch module 120. Exemplarily, the latch state of the latch module 120 includes at least two types, such as a latch occupied state and a latch idle state. The latch idle state indicates that an address is not currently latched in the latch module 120, while the latch occupied state indicates that an address is currently latched in the latch module 120. When the latch module 120 is in the latch occupied state, it will not latch the input address as the target address. When the latch module 120 is in the latch idle state, it can latch the input address as the target address. Therefore, based on the latch state of the latch module 120, a first latch control signal in an effectively activated state (e.g., a high level) and a first latch control signal in an ineffectively activated state (e.g., a low level) can be generated.

[0020] For example, the aforementioned “second latch control signal is configured based on preset conditions” may mean that when all preset conditions are met, the second latch control signal is configured to be in a valid activation state; or, when one of the preset conditions is met, the second latch control signal is configured to be in a valid activation state; or, based on whether each preset condition is met, multiple second latch control signals corresponding to each preset condition are generated, for example, when one of the preset conditions is met, a second latch control signal in a valid activation state (e.g., a high level) is generated, and when one of the preset conditions is not met, a second latch control signal in a non-valid activation state (e.g., a low level) is generated. This application does not limit the configuration of the second latch control signal.

[0021] In the above scheme, the second latch control signal is generated by the determination module 130, and the second latch control signal is configured based on a preset condition, which includes at least one of the following: whether the input address to be latched is the same as the target address latched in the latch module 120; or whether the current hammer refresh operation performed on the current target address is completed. Therefore, the enabling module 110 can control the latching module 120 to latch the corresponding input address as the target address according to whether the new address is the same as the target address and / or whether the current hammer refresh operation of the current target address is completed, so as to perform a hammer refresh operation on the target address; the determining module 130 is helpful in preventing the hammer refresh operation from being performed on the new address before the current hammer refresh operation of the current target address is completed by judging whether the current hammer refresh operation of the current target address is completed, thereby helping to improve the protection effect of the hammer prevention circuit 100 on the stored data; by judging whether the new address is the same as the target address, it is helpful in preventing repeated hammer refresh operations on the same target address, thereby helping to perform hammer refresh operations on more different target addresses within the same time, and further helping to improve the protection effect of the hammer prevention circuit 100 on the stored data.

[0022] Please refer to Figure 2 , the existing latch can latch the input address corresponding to the activation signal when receiving the activation signal to obtain the target address. However, if the activation signal is used only as the control signal to control the latch, as mentioned above, it may cause the old address to be refreshed incompletely or repeatedly latched to the same target address, thereby reducing the protection effect of the hammer prevention circuit on the stored data. In this embodiment, referring to Figure 1 By determining the second latch control signal output by the determination module 130, the enabling module 110 generates a latch enable signal according to the first latch control signal and the second latch control signal, so that the enabling module 110 can control the latch module 120 to latch the corresponding input address as the target address according to whether the new address is the same as the target address and / or whether the current hammer refresh operation of the current target address is completed, thereby facilitating improving the protection effect of the hammer prevention circuit 100 on the stored data.

[0023] In some embodiments, the enabling module 110 may include a logic gate (not shown), such as an AND gate (not shown), a NAND gate (not shown), etc. For example, the enabling module 110 may include an AND gate, which may output a high-level latch enable signal when the first latch control signal and the second latch control signal are both high, thereby controlling the latch module 120 to latch the input address (in this case, the high-level state of the latch enable signal is configured as a valid activation state); as another example, the enabling module 110 may include a NAND gate, which may output a low-level latch enable signal when the first latch control signal and the second latch control signal are both high, thereby controlling the latch module 120 to latch the input address (in this case, the low-level state of the latch enable signal is configured as a valid activation state).

[0024] In some embodiments, please refer to Figure 3 The determination module 130 includes a first determination unit 131 configured to compare the input address to be latched with the target address to determine whether the input address to be latched is the same as the target address latched in the latch module 120.

[0025] It can be understood that in this embodiment, the “new address” is relative to the target address (old address) stored in the latch module 120 , and refers to the “input address” that has not yet been stored in the latch module 120 .

[0026] An address can consist of multiple binary digits. For example, an address can include 15 bits (for example, an address can be represented by "010101010101010"). By comparing the "new address" with the data in the corresponding bits in the target address, it can be determined whether the new address is the same as the target address.

[0027] In some embodiments, the first determination unit 131 includes a comparator 400, and the comparator 400 includes the same number of XEN-OR gates as the bit width of the input address and the target address. Each of the XEN-OR gates compares the corresponding bits of the input address to be latched and the target address, and then outputs the second latch control signal through a NAND gate, an OR gate, an XOR gate, or an integrated circuit with a logic operation function in the comparator.

[0028] Please refer to Figure 4 , the comparator 400 may include an XNOR gate, a NAND gate, a NOR gate, and an OR gate. For example, 15 XNOR gates may be used to access the 15-bit data of the input address and the target address, respectively, where the input address <0> , target address <0> Represents the first bit of the input address and the target address respectively. <1> , target address <1> Represents the second bit of data in the input address and target address respectively, and so on. <14> , target address <14> They represent the 15th bit data in the input address and the target address respectively. Therefore, the input address is compared with the data of the corresponding bit in the target address through the XOR gate to obtain a preliminary comparison result, and then pass through the NAND gate, the NOR gate / NOT gate in sequence, and finally pass through the NAND gate to obtain the second latch control signal for indicating whether the input address to be latched is the same as the target address latched in the latch module 120.

[0029] exist Figure 4 In the implementation method of the comparator 400 shown, the corresponding bit data of the input address and the target address are respectively subjected to the exclusive OR operation, and the exclusive OR operation results are then combined through the exclusive AND operation, the exclusive OR operation, etc. to generate a second latch control signal. When any bit of data in the input address and the target address is different, the output second latch control signal is a high level.

[0030] The implementation of the comparator 400 is not limited to Figure 4 As shown, for example, the number of XENOR gates can be configured according to the number of bits included in the input address and the target address; the NAND gate connected to the XENOR gate can be configured as a 5-input NAND gate, which helps to reduce the number of required logic gates.

[0031] During the normal operation phase of the memory, the row address that was activated during the normal operation phase will be captured, and a hammer refresh operation will be performed on the adjacent addresses of the row address during the refresh phase. However, due to the limited time of the refresh phase, the hammer refresh operation on the adjacent addresses of the row address may not be completed, and the next normal operation phase will be entered. If a new row address is still captured in the next normal operation phase, and a hammer refresh operation is performed on the adjacent addresses of the new row address during the next refresh phase, the last incomplete hammer refresh operation will be overwritten, resulting in the hammer refresh operation on the adjacent addresses of the row address captured in the previous refresh phase being unable to be fully executed, thereby weakening the protection effect on the stored data. In addition, when the same row address is captured one after another, if the hammer refresh operation is repeatedly performed on the same row address, it will not only affect the refresh efficiency, but also reduce the number of addresses that can be protected by the hammer prevention circuit in the same period, thereby weakening the protection effect on the stored data.

[0032] To this end, in some embodiments, please refer to Figure 5 The determination module 130 further includes a second determination unit 132, which is configured to count the hammer refresh operations and determine that the current hammer refresh operation performed on the current target address is completed when the count value reaches a first value. By setting the second determination unit, the integrity of the current hammer refresh operation performed on the target address is improved, thereby facilitating the improvement of the protection effect on the stored data.

[0033] The latch module 120 can send the target address to the refresh module 500 of the memory, so that the refresh module 500 can perform a hammer refresh operation on the adjacent rows of the target address. For example, after the refresh module 500 completes the hammer refresh operation on each row, it can output a pulse signal to the second determination unit 132. The second determination unit 132 can count the received pulse signals, thereby counting the number of hammer refresh operations performed by the refresh module 500. When the count value reaches a first value, it determines that the current hammer refresh operation performed on the current target address is complete. For example, the second determination unit 132 can generate a second latch control signal in an active state (e.g., a high level state) when the count value reaches the first value. When the first latch control signal is also in an active state (e.g., a high level state), the enable module 110 generates a latch enable signal in an active state, thereby controlling the latch module 120 to latch the corresponding input address as the target address.

[0034] The first value can be set according to actual needs. For example, if a hammer refresh operation needs to be performed on the five adjacent rows of the target address during the refresh phase, the first value can be configured as 10; the first value can also be set to any integer value such as 8, 12, 13, 16, etc., and this application does not impose any restrictions on this.

[0035] In some embodiments, the second determination unit 132 includes an adder (not shown), a counter (not shown), or an integrated circuit with a counting function (not shown) to count the hammer refresh operations and output the second latch control signal when the count value reaches a first value.

[0036] The second determination unit 132 may include a reset function, that is, when the count value of the second determination unit 132 reaches a first value, a reset signal may be generated to reset the count value of the second determination unit 132 (eg, reset to 0).

[0037] In the above embodiment, the hammer refresh operations performed on the adjacent units of the target address are counted by the second determination unit 132, and a second latch control signal in an effectively activated state is generated only when the count reaches a first value, thereby causing the enable module 110 to generate a latch enable signal in an effectively activated state when receiving the first latch control signal that is also in an effectively activated state, and controlling the latch module 120 to latch the corresponding input address as the target address, which is beneficial to ensure that the refresh operations on all adjacent addresses that may be affected by the target address are completed and will not be interrupted, that is, it is beneficial to ensure that the new address is allowed to be latched only after the influence of the hammer phenomenon is completely eliminated, which is beneficial to improve the protection effect of the hammer prevention circuit 100 on the stored data.

[0038] In some embodiments, please refer to Figure 6 , the determination unit includes a first determination unit 131 and a second determination unit 132. In combination with the aforementioned embodiment, as an example, the first determination unit 131 is used to compare the input address to be latched with the target address to determine whether the input address to be latched is the same as the target address latched in the latch module 120, and generate a second latch control signal in a valid activation state (e.g., a high level) when the input address to be latched is different from the target address latched in the latch module 120; the second determination unit 132 is used to count the hammer refresh operations, and when the count value reaches a first value, determine that the current hammer refresh operation performed on the current target address is completed, and generate a second latch control signal in a valid activation state (e.g., a high level).

[0039] Therefore, in this embodiment, the hammer prevention circuit 100 can control the latch module 120 to latch the corresponding input address as the target address when the first latch control signal in the valid activation state arrives after the current hammer refresh operation on the current target address is completed and the input address to be latched is different from the target address latched in the latch module 120, so as to perform subsequent hammer refresh operations, thereby preventing the hammer refresh operation from being performed on a new address before the current hammer refresh operation on the current target address is completed, and preventing repeated hammer refresh operations on the same target address, thereby facilitating the execution of hammer refresh operations on more different target addresses within the same time, and further facilitating further improving the protection effect of the hammer prevention circuit 100 on stored data.

[0040] In some embodiments, please refer to Figure 7 The latch module 120 includes a plurality of latch units 121. When the latch enable signal is in a valid activation state, the latch unit 121 sequentially latches the corresponding input address as the target address to perform a subsequent hammer refresh operation.

[0041] In some embodiments, an address selection module 700 is further included, which is connected to the multiple groups of latch units 121 and the determination module 130 and is configured to select at least one target address from the multiple target addresses output by the multiple groups of latch units 121 and provide it to the determination module 130.

[0042] like Figure 7 As shown, the latch module 120 includes N groups of latch units 121 (latch unit 1 to latch unit N), and the enabling module 110 has N logic gates (including but not limited to Figure 7 The inputs of each logic gate in the enable module 110 are connected to the first latch control signal 1 to the first latch control signal N corresponding to each latch unit 121, and are also connected to the second latch control signal. Based on the first latch control signal corresponding to each latch unit 121 and the second latch control signal generated by the determination unit, the latch enable signal 1 to the latch enable signal N corresponding to each latch unit 121 are provided, thereby controlling each latch unit 121 (latch unit 1 to latch unit N) to latch the input address. The address selection module 700 can select one of the target addresses provided by the multiple latch units 121, compare the new address with the target address in the determination module 130, and / or determine whether the current hammer refresh operation performed on the current target address is complete.

[0043] When the latch module 120 includes multiple groups of latch units 121, the address selection module 700 can be configured to select one of the target addresses provided by the multiple latch units 121 in sequence according to the selection signal, so that the determination module 130 compares the input address to be latched with the target address in each latch unit 121. If the input address to be latched is the same as the target address in one of the latch units 121, a second latch control signal in an inactive activation state (for example, a low level) is generated, thereby controlling the latch module 120 not to latch the input address.

[0044] Please refer to Figure 8 In this embodiment, the hammer prevention circuit 100 further includes an address selection module 700, and the determination module 130 includes a first determination unit 131 and a second determination unit. The specific working principle can be referred to the description in the aforementioned embodiment and will not be repeated here.

[0045] In some embodiments, the latch unit 121 includes at least one of a latch (not shown), a register (not shown), and a trigger (not shown), and receives the latch enable signal at the clock signal input end, so as to sequentially latch the corresponding input address as the target address when the latch enable signal is in a valid activation state, so as to perform a subsequent hammer refresh operation.

[0046] In some embodiments, please refer to Figure 9 When the latch unit 121 is the latch, the latch unit 121 includes a transmission gate and a tri-state buffer. The transmission gate is connected to the output end of the enable module 110; the transmission gate is configured to selectively receive the input address to be latched based on the latch enable signal; the tri-state buffer is connected to the output end of the transmission gate and the output end of the enable module 110, and is configured to control the latch module 120 to output or not output data based on the latch enable signal. The latch enable signal and the input address are inverted by the NOT gate and given to the transmission gate. The transmission gate is turned on or off under the control of the latch enable signal. Figure 9 In the example shown, when the latch enable signal is at a high level, the transmission gate is opened and the input address is passed in. When the latch enable signal is at a low level, the latch unit 121 performs latching.

[0047] The second aspect of the present application discloses a memory 1000, please refer to Figure 10 , which includes the hammer prevention circuit 100 in the first aspect above.

[0048] The memory 1000 of the present application can be a dynamic random access memory (DRAM) or other types of memory, including but not limited to SRAM, ROM, PROM, EEPROM, SDRAM, DDR / 2SDRAM, DDR / 3SDRAM, DDR / 4SDRAM, GDDRx, EDO / FPMS, FeRAM, ReRAM, RLDRAM, etc.

[0049] In the above scheme, the second latch control signal is generated by the determination module 130, and the second latch control signal is configured based on a preset condition, which includes at least one of the following: whether the input address to be latched is the same as the target address latched in the latch module 120; or whether the current hammer refresh operation performed on the current target address is completed. Therefore, the enabling module 110 can control the latching module 120 to latch the corresponding input address as the target address according to whether the new address is the same as the target address and / or whether the current hammer refresh operation of the current target address is completed, so as to perform a hammer refresh operation on the target address; the determining module 130 is helpful in preventing the hammer refresh operation from being performed on the new address before the current hammer refresh operation of the current target address is completed by judging whether the current hammer refresh operation of the current target address is completed, thereby helping to improve the protection effect of the hammer prevention circuit 100 on the stored data; by judging whether the new address is the same as the target address, it is helpful in preventing repeated hammer refresh operations on the same target address, thereby helping to perform hammer refresh operations on more different target addresses within the same time, and further helping to improve the protection effect of the hammer prevention circuit 100 on the stored data.

[0050] In some embodiments, the memory 1000 further includes a decoding module (not shown in the figure), which decodes a normal access command received by the memory 1000 from the host end (not shown in the figure) to generate an activation signal (ACTIVE) and the input address in the aforementioned embodiment of the present invention, wherein the first latch control signal in the aforementioned embodiment of the present invention is generated after other internal logic circuits (not shown in the figure) of the memory 1000 process the activation signal (ACTIVE).

[0051] Furthermore, the decoding module decodes the received normal access instructions. Specifically, it can perform instruction decoding on the normal access instructions to generate an activation signal, and perform address decoding on the normal access instructions to generate an input address. The hammer prevention circuit 100 is coupled to the decoding module. Due to the limitation of the memory size, the number of latches in the memory for latching the input address will also be limited. In the case where the number of activation signals is greater than or even much greater than the number of latches, the latch cannot latch the input address corresponding to each activation signal and perform hammer refresh operations on these input addresses. Therefore, the activation signal can be counted by a counter, and after meeting certain conditions (for example, several activation signals correspond to the same address), a first latch control signal is generated to latch the input address corresponding to the corresponding activation signal.

[0052] It is easy for a person skilled in the art to know that many modifications and variations can be made to the apparatus and method while maintaining the teaching content of the present application.Therefore, the above disclosure should be considered as being limited only by the scope of the appended claims.

Claims

1. A hammer prevention circuit for adjusting a hammer refresh operation of a memory, characterized in that: include: an enabling module configured to receive a first latch control signal and a second latch control signal, and generate a latch enable signal based on the first latch control signal and the second latch control signal, wherein the latch enable signal is in a valid active state in response to the first latch control signal and the second latch control signal both being in a valid active state; a latch module connected to the enable module, wherein the latch module latches the corresponding input address as the target address when the latch enable signal is in a valid activation state, so as to perform a subsequent hammer refresh operation; a determination module, connected to the enabling module, and generating the second latch control signal according to the target address; The second latch control signal is configured based on a preset condition, and the preset condition includes at least one of the following: whether the input address to be latched is the same as the target address latched in the latch module; or Whether the current hammer refresh operation executed on the current target address is completed.

2. The hammer prevention circuit according to claim 1, characterized in that The determination module includes: The first determination unit is configured to compare the input address to be latched with the target address to determine whether the input address to be latched is the same as the target address latched in the latch module.

3. The hammer prevention circuit according to claim 2, characterized in that: The first determination unit includes a comparator, which includes an XENO gate with the same number of bit widths as the input address and the target address. Each of the XENO gates compares the corresponding bits of the input address to be latched and the target address, and then outputs the second latch control signal through a NAND gate, an OR gate, an XOR gate in the comparator, or an integrated circuit with a logic operation function.

4. The hammer prevention circuit according to any one of claims 1 to 3, characterized in that: The determination module further includes: The second determination unit is configured to count the hammer refresh operations and determine that the current hammer refresh operation executed at the current target address is completed when the count value reaches a first value.

5. The hammer prevention circuit according to claim 4, characterized in that: The second determination unit includes an adder, a counter, or an integrated circuit with a counting function to count the hammer refresh operations, and outputs the second latch control signal when the count value reaches a first value.

6. The hammer prevention circuit according to any one of claims 1 to 3, characterized in that: The latch module includes a plurality of latch units. When the latch enable signal is in a valid activation state, the latch units sequentially latch corresponding input addresses as target addresses to perform a subsequent hammer refresh operation.

7. The hammer prevention circuit according to claim 6, characterized in that: Also includes: The address selection module is connected to the plurality of latch units and the determination module, and is configured to select at least one target address from the plurality of target addresses output by the plurality of latch units and provide the selected address to the determination module.

8. The hammer prevention circuit according to claim 6, characterized in that The latch unit includes at least one of a latch, a register, and a trigger, and receives the latch enable signal at the clock signal input end, so as to sequentially latch the corresponding input address as the target address when the latch enable signal is in a valid activation state, so as to perform a subsequent hammer refresh operation.

9. The hammer prevention circuit according to claim 8, characterized in that: When the latch unit is the latch, the latch unit includes: a transmission gate connected to an output terminal of the enable module; the transmission gate being configured to selectively receive the input address to be latched based on the latch enable signal; The tri-state buffer is connected to the output terminal of the transmission gate and the output terminal of the enable module, and is configured to control the latch module to output or not output data based on the latch enable signal.

10. A memory, characterized in that: The invention comprises the hammer prevention circuit according to any one of claims 1 to 9.

11. The memory according to claim 10, wherein: The memory further includes a decoding module, which decodes a received normal access instruction to generate an activation signal and the input address, wherein the first latch control signal is generated according to the activation signal.

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