Hammering prevention circuit and memory having same

Abstract

The invention provides a hammering prevention circuit and a memory with the same, the hammering prevention circuit is used for adjusting hammering refreshing operation of the memory, the hammering prevention circuit comprises an activation enabling module and a latch module, the activation enabling module is used for receiving an activation signal and performing frequency division processing on the activation signal to generate an activation enabling signal; the latch module is connected with the activation enabling module so as to latch the corresponding input address according to the activation enabling signal as a clock, and the input address is used as a target address for executing the hammering refreshing operation. According to the scheme, the activation enable signal subjected to frequency division processing can enable the latch module to perform address latching when receiving the input address corresponding to the activation signal and execute the hammering and refreshing operation on the target address, so that the range of the address acted by the hammering and refreshing operation is expanded, and the efficiency of the hammering and refreshing operation is improved. Therefore, the effect of the hammering refreshing operation on improving storage content abnormity caused by line hammering is improved.

Description

Technical Field

[0001] The disclosed embodiments of the present application relate to the field of storage technology, and more particularly, to a hammer prevention circuit and a memory having the same. Background Art

[0002] In memory circuits, the memory array consists of several rows of storage capacitors. When the memory cells in a row are frequently read, the values ​​of the storage capacitors in several adjacent rows may be overwritten due to signal coupling. This phenomenon is called row hammering.

[0003] In order to prevent the memory content from being overwritten due to the row hammer phenomenon, a hammer refresh operation is usually performed on the address where the row hammer phenomenon may occur. However, the current hammer refresh operation is not very effective in improving the memory content abnormality caused by row hammer.

[0004] Therefore, how to improve the effect of hammer refresh operation on improving storage content abnormality caused by row hammering becomes an urgent problem to be solved. Summary of the Invention

[0005] According to an embodiment of the present application, the present invention provides a hammer prevention circuit and a memory having the same, so as to enhance the effect of hammer refresh operation on improving storage content abnormality caused by row hammering.

[0006] According to one aspect of the present application, a hammer prevention circuit is disclosed, which is used to adjust the hammer refresh operation of a memory, including an activation enable module and a latch module. The activation enable module is used to receive an activation signal and perform frequency division processing on the activation signal to generate an activation enable signal; the latch module is connected to the activation enable module to latch the corresponding input address according to the activation enable signal as a clock, so as to serve as the target address for performing a hammer refresh operation, wherein the activation signal is received between two adjacent hammer refresh operations to perform a normal access activation operation on the corresponding input address.

[0007] The activation enabling module includes a frequency dividing unit for performing frequency division processing on the activation signal to generate the activation enabling signal.

[0008] Among them, p activation signals are received between two adjacent hammer refresh operations to perform the normal access activation operation on q corresponding input addresses, wherein p and q are both positive integers, and q≤p; the frequency division unit is used to: among the p activation signals, select one every (m-1) activation signals as the activation enable signal; wherein m is the frequency division coefficient of the frequency division unit determined by the frequency division control signal.

[0009] The frequency division control signal is burned into the electronic fuse of the memory.

[0010] The activation enabling unit receives an activation signal and performs delay and frequency division processing on the activation signal to generate multiple groups of activation enabling signals.

[0011] Among them, the activation enable module includes a delay unit and a frequency division unit; the delay unit receives the activation signal, delays the activation signal, and outputs the delayed component of the activation signal; the frequency division unit is connected to the delay unit, performs frequency division processing on the activation signal and the delay component to generate multiple groups of the activation enable signals.

[0012] The activation enable module further includes a signal selection unit, which selects one of the plurality of activation enable signals and outputs it to the latch module.

[0013] The activation enabling module further includes a signal selecting unit, which selects one of the activation signal and the delayed component of the activation signal and performs frequency division processing.

[0014] The signal selection unit includes a delay control terminal configured to receive a delay control signal and select one of the activation signal and its delayed component based on the delay control signal to output to the frequency division unit.

[0015] A second aspect of the present application discloses a memory, comprising the hammer prevention circuit of the first aspect.

[0016] The above scheme generates an activation enable signal by frequency-dividing the activation signal through the activation enable module. Since the activation enable signal after frequency division can enable the latch module to perform address latching when receiving the input address corresponding to the activation enable signal and perform a hammer refresh operation on the target address, it is beneficial to expand the range of addresses affected by the hammer refresh operation, thereby improving the effect of the hammer refresh operation on improving storage content abnormalities caused by row hammering. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present application will be further described below with reference to the accompanying drawings and implementation methods, in which: Figure 1 It is a schematic diagram of the framework of the hammer prevention circuit in the prior art; Figure 2 It is a schematic diagram of an activation signal when a memory is working in the prior art; Figure 3 It is a schematic diagram of the framework of an embodiment of a hammer prevention circuit of the present application; Figure 4 is a schematic diagram of an activation signal and an activation enable signal of a hammer prevention circuit in an embodiment of the present application; Figure 5is a schematic diagram of a framework of another embodiment of the hammer prevention circuit of the present application; Figure 6 It is a schematic diagram of a framework of another embodiment of the hammer prevention circuit of the present application; Figure 7 is a schematic diagram of an activation signal and an activation enable signal of a hammer prevention circuit in another embodiment of the present application; Figure 8 It is a schematic diagram of a framework of another embodiment of the hammer prevention circuit of the present application; Figure 9 It is a schematic diagram of a framework of another embodiment of the hammer prevention circuit of the present application; Figure 10 It is a schematic diagram of a framework of another embodiment of the hammer prevention circuit of the present application; Figure 11 It is a schematic diagram of the framework of a memory embodiment of the present application. DETAILED DESCRIPTION

[0018] To help those skilled in the art better understand the technical solutions of this application, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and specific implementation methods. Obviously, the embodiments described are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of this application.

[0019] The terms used in the examples of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a," "the," and "the" used in the examples of this application and the appended claims are also intended to include plural forms. Unless otherwise clearly indicated above, "a plurality" generally includes at least two, but does not exclude the inclusion of at least one.

[0020] It should be understood that the term "and / or" as used herein is merely a description of the association relationship between associated objects, indicating that three possible relationships exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship. The terms "first," "second," etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0021] It should be understood that the terms "comprises," "comprising," or any other variations thereof as used herein are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0022] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0023] In memory circuits, the memory array consists of several rows of storage capacitors. When the memory cells in a row are frequently read, the values ​​of the storage capacitors in several adjacent rows may be overwritten due to signal coupling. This phenomenon is called row hammering.

[0024] In order to prevent the memory contents from being overwritten due to the row hammer phenomenon, a hammer refresh operation is usually performed on the address where the row hammer phenomenon may occur. Figure 1 and Figure 2Between two refresh phases, the memory may receive x normal access commands, generating x activation signals (Active signals) and performing activation operations on y different input addresses (one activation signal corresponds to one input address), where y ≤ x. During the refresh phase, it is necessary to select several of the y input addresses for a hammer refresh operation to prevent row hammering from damaging stored data. Due to memory area constraints, it is impossible to record all input addresses that have been activated during normal operation. Only a subset of these addresses can be selected. The prior art hammer prevention circuit includes a latch 100. Each time an activation operation is performed, an activation signal (e.g., a high-level pulse signal) is generated and sent to the clock terminal of latch 100. The data input terminal of latch 100 is used to receive the input address corresponding to the activation signal. Thus, each time an activation operation is performed, latch 100 latches the input address corresponding to the activation signal and uses it as the target address, causing the refresh circuit (not shown) to perform a hammer refresh operation on the target address. However, this hammer prevention circuit will only perform hammer refresh operations on input addresses corresponding to several consecutive activation operations. For example, if the hammer prevention circuit in the prior art has n groups of latches 100, it can latch n consecutive input addresses, and use these n consecutive input addresses as target addresses to perform hammer refresh operations in the refresh circuit. However, due to the limitation of memory size, the number of latches 100 is usually limited, and the number of activation signals sent continuously during the activation phase may be as many as hundreds. For such a large number of input addresses, the hammer prevention circuit can only use a limited number of n consecutive input addresses as target addresses to perform hammer refresh operations. Therefore, the address range that can be covered by the hammer refresh operation is small, and the way in which the latch 100 latches the target address is relatively fixed, which cannot cope with complex scenarios, and the effect of improving the storage content abnormality caused by row hammering is not obvious.

[0025] Therefore, the present application hopes to improve the effect of hammer refresh operation on improving storage content abnormality caused by row hammer.

[0026] One aspect of the present application discloses a hammer prevention circuit 200, please refer to Figure 3 The hammer prevention circuit 200 is used to adjust the hammer refresh operation of the memory, and includes an activation enable module 210 and a latch module 220. The activation enable module 210 is used to receive an activation signal and perform frequency division processing on the activation signal to generate an activation enable signal; the latch module 220 is connected to the activation enable module 210 to latch the corresponding input address according to the activation enable signal as a clock, so as to serve as the target address for performing the hammer refresh operation, wherein the activation signal is received between two adjacent hammer refresh operations to perform a normal access activation operation on the corresponding input address.

[0027] In the above scheme, the activation enable module 210 performs frequency division processing on the activation signal to generate the activation enable signal. Since the activation enable signal after frequency division processing can enable the latch module 220 to latch the address when receiving the input address corresponding to the activation enable signal, and perform a hammer refresh operation on the target address, it is beneficial to expand the range of addresses affected by the hammer refresh operation, thereby improving the effect of the hammer refresh operation on improving the storage content abnormality caused by row hammering.

[0028] Please continue to refer to Figure 3 During the normal working phase between two adjacent hammer refresh operations, the memory generates several activation signals to perform normal access activation operations on several corresponding input addresses; after receiving the activation signal, the activation enable module performs frequency division processing on the activation signal to generate an activation enable signal. In other words, the activation enable signal is selected from a large number of activation signals after frequency division processing, and the activation signals selected as the activation enable signal are not continuous in time with each other; the activation enable signal serves as the clock signal of the latch module. After receiving the activation enable signal, the latch module can latch the corresponding input address. The input address latched by the latch module during the normal working phase serves as the target address of the hammer refresh operation when the hammer refresh operation is subsequently performed. In other words, the hammer refresh operation is performed on the adjacent rows of these target addresses (for example, adjacent row 1, adjacent row 2, etc.).

[0029] Please refer to Figure 4 , Figure 4 The activation enable signal obtained by performing three-frequency division processing on the activation signal is illustrated as an example, wherein the horizontal axis represents time. Figure 3 , assuming that the latch module 220 in the hammer prevention circuit 200 of the present application can perform address latching when the clock terminal CLK receives a high-level activation enable signal, the latch module 220 in the hammer prevention circuit 200 of the present application receives Figure 4 After the activation enable signal shown in , the address can be latched at the moment corresponding to the first, fourth, seventh, tenth, ... activation signal in a group of activation signals, thereby latching the input address corresponding to the first, fourth, seventh, tenth, ... activation signal respectively. Compared with Figure 1 and Figure 2 The hammer prevention circuit 200 in the prior art shown in the figure can only latch the input addresses corresponding to n consecutive activation signals. The hammer prevention circuit 200 provided in this embodiment can expand the range of addresses affected by the hammer refresh operation and improve the flexibility of address selection, thereby facilitating the improvement of the effect of the hammer refresh operation on improving storage content abnormalities caused by row hammering.

[0030] In some embodiments, please refer to Figure 5 The activation enabling module 210 includes a frequency dividing unit 211, which performs frequency division processing on the activation signal to generate the activation enabling signal.

[0031] In some embodiments, the frequency dividing unit 211 includes a D flip-flop; the frequency dividing unit 211 may also include a combination of a D flip-flop, a counter, and a logic gate to achieve odd frequency division, such as three times, five times, etc.

[0032] It is understandable that the frequency division coefficient of the frequency division unit 211 can be configured according to actual needs, such as two-way frequency division, three-way frequency division, etc., and this application does not impose any limitation on this.

[0033] In some embodiments, the frequency division unit 211 may include a frequency division control terminal (not shown), which receives a frequency division control signal, and the frequency division control signal is used to control the frequency division coefficient of the frequency division unit 211 .

[0034] In some embodiments, the frequency division control signal is burned into electronic fuses in the memory.

[0035] In some embodiments, the latch module 220 includes one of a latch, a flip-flop, and a register.

[0036] In some embodiments, p activation signals (Active) are received between two adjacent hammer refresh operations to perform the normal access activation operation on q corresponding input addresses, where p and q are both positive integers and q≤p; the frequency division unit 211 is used to: among the p activation signals, select one every (m-1) activation signals as the activation enable signal; where m is the frequency division coefficient of the frequency division unit 211 determined by the frequency division control signal.

[0037] Between two adjacent hammer refresh operations, p activation signals are received, and one activation signal corresponds to one input address. Different activation signals may correspond to the same input address, so p activation signals may correspond to q input addresses, and q≤p.

[0038] Please continue to refer to Figure 4, assuming that the latch module 220 is a latch, the frequency division coefficient of the frequency division unit 211 is 3, and the latch is configured to be high-level triggered, that is, it latches the input address when receiving the activation enable signal in the high-level state. The frequency division unit 211 selects one of the activation signals as the activation enable signal for every two activation signals from a number of activation signals. Therefore, each activation enable signal corresponds to the 1st, 4th, 7th, 10th... (n-1)m+1th activation signals, respectively, where n is the number of latch groups, and each group of latches is used to store a target address; correspondingly, n groups of latches can latch the input addresses corresponding to the 1st, 4th, 7th, 10th... (n-1)m+1th activation signals, respectively.

[0039] Therefore, in this embodiment, the activation signal is divided by the frequency division unit 211, so that n groups of latches can respectively latch the input addresses corresponding to the 1st, 4th, 7th, 10th...(n-1)m+1th activation signals. Compared with the prior art that can only latch the input addresses corresponding to n consecutive activation signals, the hammer prevention circuit 200 provided in this embodiment can expand the range of addresses affected by the hammer refresh operation and improve the flexibility of address selection, which is conducive to improving the effect of the hammer refresh operation on improving storage content abnormalities caused by row hammering.

[0040] In some embodiments, the activation enabling unit receives an activation signal and performs delay and frequency division processing on the activation signal to generate multiple groups of activation enabling signals.

[0041] In some embodiments, please refer to Figure 6 The activation enable module 210 includes a delay unit 212 and a frequency division unit 211. The delay unit 212 receives the activation signal, performs delay processing on the activation signal, and outputs the delayed component of the activation signal; the frequency division unit 211 is connected to the delay unit 212, performs frequency division processing on the activation signal and the delay component to generate multiple groups of activation enable signals.

[0042] It is understood that, in addition to outputting the delayed component of the activation signal to the activation unit, the delay unit 212 can also transmit the original activation signal to the frequency division unit 211, so that the frequency division unit 211 can perform frequency division processing on the original activation signal and the delayed component of the activation signal. The delay unit 212 can delay the activation signal by 1 to i cycles, where i represents the delay level of the delay unit 212. For example, a two-stage delay unit 212 can delay the activation signal by 1 to 2 cycles, generating the first and second delayed components of the activation signal, respectively.

[0043] Please refer to Figure 7 , Figure 7Taking the delay unit 212 as a 2-stage delay unit 212 and the frequency division coefficient of the frequency division unit 211 as 3 as an example, the activation signal and the activation enable signal after the delay and frequency division processing are exemplified, wherein the horizontal axis represents time. After the activation signal passes through the delay unit 212 and the frequency division unit 211, multiple groups of activation enable signals are generated, namely the first activation enable signal, the second activation enable signal, and the third activation enable signal, wherein the first activation enable signal is the original activation signal (that is, it has not been delayed by the delay unit 212) and is obtained by three-frequency division; the second activation enable signal is the activation signal after the first-stage delay component is divided by three-frequency division; the third activation enable signal is the activation signal after the second-stage delay component is divided by three-frequency division. From Figure 7 It can be seen that the first activation enable signal corresponds to the 1st, 4th, 7th, 10th ... (n-1)m+1th activation signals. After receiving the first activation enable signal, the latch module 220 can latch the input addresses corresponding to the 1st, 4th, 7th, 10th ... (n-1)m+1th activation signals as the target address to perform the hammer refresh operation; the second activation enable signal corresponds to the 2nd, 5th, 8th, 11th ... (n-1)m+2th activation signals. After receiving the first activation enable signal, the latch module 220 can latch the input addresses corresponding to the 1st, 4th, 7th, 10th ... (n-1)m+1th activation signals as the target address to perform the hammer refresh operation; After receiving the first activation enable signal, the latch module 220 can latch the input addresses corresponding to the 2nd, 5th, 8th, 11th... (n-1)m+2th activation signals as the target address to perform a hammer refresh operation; the third activation enable signal corresponds to the 3rd, 6th, 9th, 12th... (n-1)m+3th activation signals, and after receiving the first activation enable signal, the latch module 220 can latch the input addresses corresponding to the 3rd, 6th, 9th, 12th... (n-1)m+3th activation signals as the target address to perform a hammer refresh operation.

[0044] Therefore, in this embodiment, the activation enable unit delays and divides the activation signal to generate multiple groups of activation enable signals, and can latch (n-1)m+i+1 (where i is the delay level of the delay unit 212, n is the number of latch groups, and m is the division coefficient) input addresses as target addresses to perform a hammer refresh operation; compared with other embodiments, the hammer prevention circuit 200 provided in this embodiment can further expand the range of addresses affected by the hammer refresh operation and improve the flexibility of address selection, which is conducive to further improving the effect of the hammer refresh operation on improving storage content abnormalities caused by row hammering.

[0045] In some embodiments, the delay unit 212 is configured to perform multi-stage delay processing on the activation signal and output a plurality of delayed components of the activation signal.

[0046] The delay level of the delay unit 212 can be 1 level, 2 levels, etc., which is not limited in this application.

[0047] In some embodiments, the activation enable module 210 further includes a signal selection unit 213 for selecting one of the plurality of activation enable signals and outputting it to the latch module 220 .

[0048] In some embodiments, please refer to Figure 8 The signal selection unit 213 can be connected to the frequency division unit 211 and select one of the multiple activation enable signals output by the frequency division unit 211 to output to the latch module 220 .

[0049] In some embodiments, the activation enabling module 210 further includes a signal selecting unit 213 for selecting one of the activation signal and the delayed component of the activation signal to perform frequency division processing.

[0050] In some embodiments, please refer to Figure 9 The signal selection unit 213 can be connected to the delay unit 212, and select one of the activation signal output by the delay unit 212 and the delayed component of the activation signal to output to the latch module 220. For example, the original activation signal can be output to the frequency division unit 211 for frequency division processing.

[0051] In some embodiments, please refer to Figure 10 The signal selection unit 213 may include a delay control terminal (not shown) to access the delay control signal, and select one from the activation signal and its delayed component based on the delay control signal to output to the frequency division unit 211.

[0052] In some embodiments, the delay control signal is burned into an electronic fuse in the memory.

[0053] Combine Figure 7The delay control signal can control the signal selection unit 213 to select one of the original activation signal, the first-order delayed component of the activation signal, or the second-order delayed component of the activation signal, and output it to the frequency division unit 211 for frequency division processing. For example, the delay control signal can control the signal selection unit 213 to select the first-order delayed component of the activation signal, and output it to the frequency division unit 211 for frequency division processing, thereby obtaining the second activation enable signal. Assume that in this embodiment, the memory receives 12 activation commands (i.e., 12 activation signals) during the normal operation phase, and the hammer prevention circuit 200 has 4 groups of latches. When the delay control signal selects the original activation signal, the input addresses corresponding to the 1st, 4th, 7th, and 10th activation signals can be used as target addresses to perform a hammer refresh operation; when the delay control signal selects the first-level delay component of the activation signal, the input addresses corresponding to the 2nd, 5th, 8th, and 11th activation signals can be used as target addresses to perform a hammer refresh operation; when the delay control signal selects the second-level delay component of the activation signal, the input addresses corresponding to the 3rd, 6th, 9th, and 12th activation signals can be used as target addresses to perform a hammer refresh operation; therefore, in this embodiment, different groups of activation enable signals are selected by the delay control signal, and when the number of latches is small, the range of addresses affected by the hammer refresh operation is expanded.

[0054] Therefore, this embodiment is beneficial for reducing the size of the hammer prevention circuit 200 and further expanding the range of addresses affected by the hammer refresh operation, thereby further improving the effect of the hammer refresh operation on improving storage content abnormalities caused by row hammering.

[0055] In some embodiments, the activation signal selection unit 213 includes a multiplexer (MUX), a switch array, a cross switch, a programmable logic circuit, a transistor-based switch network, or an integrated circuit with a signal selection function.

[0056] The following combination Figure 10 and Figure 7 The working principle of the hammer prevention circuit 200 in some embodiments is exemplified. Figure 10As shown, the signal selection unit 213 is a multiplexer (MUX), the delay unit 212 is a two-level delay, and the frequency division coefficient of the frequency division unit 211 is 3. Assume that in the normal working stage, the memory receives 12 activation signals, and then performs activation operations on 12 addresses. Then when the multiplexer is configured to select the original activation signal so that the frequency division unit 211 performs three-way frequency division processing on the original activation signal, the first activation enable signal output by the activation enable module 210 corresponds to the 1st, 4th, 7th, and 10th activation signals, and the latch module 220 can latch the input addresses corresponding to the 1st, 4th, 7th, and 10th activation signals as the target address after receiving the first activation enable signal, and perform a hammer refresh operation; similarly, when the multiplexer is configured to select the first-level delay component of the activation signal, the second activation enable signal output by the activation enable module 210 corresponds to the 2nd, 5th, and 6th activation signals. , the 8th and 11th activation signals, after receiving the first activation enable signal, the latch module 220 can latch the input addresses corresponding to the 2nd, 5th, 8th and 11th activation signals as the target address, and perform a hammer refresh operation; when the multiplexer is configured to select the secondary delay component of the activation signal, the third activation enable signal output by the activation enable module 210 corresponds to the 3rd, 6th, 9th and 12th activation signals, after receiving the first activation enable signal, the latch module 220 can latch the input addresses corresponding to the 3rd, 6th, 9th and 12th activation signals as the target address, and perform a hammer refresh operation.

[0057] The second aspect of the present application discloses a memory 1100, please refer to Figure 11 , the memory 1100 includes the hammer prevention circuit 200 of the first aspect described above.

[0058] In the above scheme, the activation enable module 210 performs frequency division processing on the activation signal to generate the activation enable signal. Since the activation enable signal after frequency division processing can enable the latch module 220 to latch the address when receiving the input address corresponding to the activation enable signal, and perform a hammer refresh operation on the target address, it is beneficial to expand the range of addresses affected by the hammer refresh operation, thereby improving the effect of the hammer refresh operation on improving the storage content abnormality caused by row hammering.

[0059] It is easy for a person skilled in the art to know that many modifications and variations can be made to the apparatus and method while maintaining the teaching content of the present application.Therefore, the above disclosure should be considered as being limited only by the scope of the appended claims.

Claims

1. A hammer prevention circuit for adjusting a hammer refresh operation of a memory, characterized in that: include: An activation enabling module receives an activation signal and performs frequency division processing on the activation signal to generate an activation enabling signal; a latch module connected to the activation enable module to latch the corresponding input address according to the activation enable signal as a clock, so as to serve as the target address for performing the hammer refresh operation; The activation signal is received between two adjacent hammer refresh operations to perform an activation operation of normal access on the corresponding input address.

2. The hammer prevention circuit according to claim 1, characterized in that The activation enabling module includes: The frequency division unit performs frequency division processing on the activation signal to generate the activation enable signal.

3. The hammer prevention circuit according to claim 2, characterized in that: receiving p activation signals between two adjacent hammer refresh operations to perform the activation operation of the normal access on q corresponding input addresses, wherein p and q are both positive integers, and q≤p; The frequency division unit is used to: select one of every (m-1) activation signals among the p activation signals as the activation enable signal; wherein m is the frequency division coefficient of the frequency division unit determined by the frequency division control signal.

4. The hammer prevention circuit according to claim 3, characterized in that: in, The frequency division control signal is burned into the electronic fuse of the memory.

5. The hammer prevention circuit according to claim 1, characterized in that The activation enabling unit receives an activation signal, and performs delay and frequency division processing on the activation signal to generate multiple groups of activation enabling signals.

6. The hammer prevention circuit according to claim 5, characterized in that: The activation enabling module includes: a delay unit, receiving the activation signal, performing delay processing on the activation signal, and outputting a delayed component of the activation signal; The frequency division unit is connected to the delay unit and performs frequency division processing on the activation signal and the delay component to generate multiple groups of activation enable signals.

7. The hammer prevention circuit according to claim 5 or 6, characterized in that: The activation enabling module further includes: A signal selection unit selects one of the activation enable signals from the plurality of groups and outputs the selected signal to the latch module.

8. The hammer prevention circuit according to claim 5 or 6, characterized in that: The activation enabling module further includes: The signal selection unit selects one of the activation signal and the delayed component of the activation signal and performs frequency division processing.

9. The hammer prevention circuit according to claim 8, characterized in that: The signal selection unit includes a delay control terminal configured to receive a delay control signal and select one of the activation signal and its delayed component based on the delay control signal to output to the frequency division unit.

10. A memory, characterized in that: The invention comprises the hammer prevention circuit according to any one of claims 1 to 9.

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