Driving chip and display device

Abstract

The invention provides a driving chip and a display device, and belongs to the technical field of display. The driving chip comprises a latch module and a source electrode module. The latch module comprises a receiving sub-module, a cache sub-module and an output sub-module; the receiving sub-module comprises a plurality of primary latch groups and is used for latching data rows; each primary latch group is configured to latch one data group, and the data row comprises at least one data group; the cache sub-module comprises a plurality of secondary latch groups in one-to-one correspondence with the primary latch groups; the secondary latch group is configured to respond to a second enable signal to latch the data latched by the corresponding primary latch group; the output sub-module is used for latching each data group in the secondary latch group one by one; and the source module is used for outputting analog data voltage of each sub-pixel corresponding to the data group according to the data group output by the output sub-module. The driving chip can reduce the cost of the display device.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driver chip and a display device. Background Art

[0002] A display device includes a display panel and a driver chip that applies data voltage to the display panel. Due to limitations in the driver chip's packaging process, the number of output pins on the driver chip is limited, typically no more than 1920 pins per side. High-resolution display panels often require multiple driver chips. For example, a display panel with a 2560 RGB*1440 resolution requires four driver chips, while a display panel with a 3840 RGB*2560 resolution requires six driver chips. This not only increases circuit costs, but the excessive number of driver chips also increases the chip binding defect rate.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, provide a driver chip and a display device, and reduce the cost of the display device.

[0005] According to a first aspect of the present disclosure, a driver chip is provided, comprising a latch module and a source module; the latch module comprises a receiving submodule, a buffer submodule and an output submodule;

[0006] The receiving submodule includes a plurality of primary latch groups, and the receiving submodule is used to latch a data row; each of the primary latch groups is configured to latch a data group, and the data row includes at least one of the data groups;

[0007] The cache submodule includes a plurality of secondary latch groups corresponding to each of the primary latch groups; the secondary latch groups are configured to latch the data latched by the corresponding primary latch groups in response to a second enable signal;

[0008] The output submodule is used to latch each of the data groups in the secondary latch group one by one;

[0009] The source module is configured to output analog data voltages of respective sub-pixels corresponding to the data group according to the data group output by the output sub-module.

[0010] According to one embodiment of the present disclosure, the receiving submodule includes a plurality of latch units, and any one of the latch units includes a plurality of latch subunits corresponding one-to-one to each of the primary latch groups; wherein any one of the primary latch groups has a corresponding latch subunit in any one of the latch units; and the input ends of the latches of the same latch subunit are connected to each other;

[0011] The driver chip further includes a scanning circuit corresponding to each of the latch sub-units one by one, and the scanning circuit is used to sequentially generate a first enable signal for each of the latches in the corresponding latch sub-units.

[0012] According to an embodiment of the present disclosure, the driver chip includes a write control module, and the write control module includes a plurality of receiving control units corresponding one-to-one to each of the latch units;

[0013] The receiving control unit includes a plurality of scanning circuits corresponding one-to-one to each of the latch sub-units in the corresponding latch unit, and a scanning control circuit;

[0014] The scan control circuit is configured to determine the cascade state between the scan circuits in the same receiving control unit and the cascade state between the scan circuits of adjacent receiving control units according to the scan configuration signal.

[0015] According to an embodiment of the present disclosure, the latch unit includes a first latch subunit, a second latch subunit, a third latch subunit, and a fourth latch subunit; the receiving control unit includes a first scanning circuit corresponding to the first latch subunit, a second scanning circuit corresponding to the second latch subunit, a third scanning circuit corresponding to the third latch subunit, and a fourth scanning circuit corresponding to the fourth latch subunit; the scanning control circuit includes first to seventh transistors;

[0016] The receiving control unit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; in two adjacent receiving control units, the first output terminal of the previous receiving control unit is electrically connected to the first input terminal of the next receiving control unit, and the second output terminal of the previous receiving control unit is electrically connected to the second input terminal of the next receiving control unit;

[0017] In which, in the same receiving control unit, the cascade input end of the first scanning circuit is electrically connected to the first input end; the cascade output end of the first scanning circuit, the cascade input end of the third scanning circuit, and the first pole of the first transistor are electrically connected to each other; the cascade output end of the third scanning circuit, the second pole of the first transistor, the first pole of the fourth transistor, and the first pole of the seventh transistor are electrically connected to each other; the second pole of the fourth transistor, the second pole of the sixth transistor are electrically connected to the first output end; the cascade input end of the second scanning circuit, the first pole of the second transistor are electrically connected to the second input end; the cascade output end of the second scanning circuit, the cascade input end of the fourth scanning circuit, the second pole of the second transistor, and the first pole of the third transistor are electrically connected to each other; the cascade output end of the fourth scanning circuit, the second pole of the third transistor, the first pole of the fifth transistor, and the first pole of the sixth transistor are electrically connected to each other; the second pole of the seventh transistor, the second pole of the fifth transistor are electrically connected to the second output end.

[0018] According to one embodiment of the present disclosure, the scan control circuit is configured to be able to assume a first operating mode according to a first scan configuration signal, to be able to assume a second operating mode according to a second scan configuration signal, to be able to assume a third operating mode according to a third scan configuration signal, and to be able to assume a fourth operating mode according to a fourth scan configuration signal;

[0019] In the first operating mode, the first transistor, the second transistor, the third transistor, the sixth transistor and the seventh transistor are in an on state, and the fourth transistor and the fifth transistor are in an off state;

[0020] In the second operating mode, the first transistor, the third transistor, the fourth transistor, and the fifth transistor are in an on state, and the second transistor, the sixth transistor, and the seventh transistor are in an off state;

[0021] In the third operating mode, the third transistor, the sixth transistor, and the seventh transistor are in an on state, and the first transistor, the second transistor, the fourth transistor, and the fifth transistor are in an off state;

[0022] In the fourth operation mode, the first transistor, the second transistor, the third transistor, the sixth transistor, and the seventh transistor are in an off state, and the fourth transistor and the fifth transistor are in an on state.

[0023] According to one embodiment of the present disclosure, the driver chip is provided with one or more data write lines; the latch sub-unit further includes a selection sub-circuit corresponding to each latch sub-unit one by one, and the input end of each latch of the latch sub-unit is electrically connected to each of the data write lines through the corresponding selection sub-circuit; the selection sub-circuit is configured to be able to electrically connect the input end of each latch of the latch sub-unit to at most one of the data write lines according to a selection configuration signal.

[0024] According to an embodiment of the present disclosure, the latch module further includes a buffer control module, the buffer control module being configured to generate a second enable signal for each latch of the cache submodule;

[0025] The buffer control module is configured to simultaneously generate the second enable signal for each latch of the cache submodule, or to generate the second enable signal for a portion of the latches of the cache submodule each time.

[0026] According to an embodiment of the present disclosure, the latch module further includes a multiplexing submodule, and the output end of each of the secondary latch groups is electrically connected to the input end of the output submodule through the multiplexing submodule;

[0027] The multiplexing submodule is configured to connect the input end of the output submodule to one of the output ends of the plurality of secondary latch groups.

[0028] According to an embodiment of the present disclosure, the driver chip further includes a pre-charging module; the pre-charging module includes a pre-charging configuration unit and a comparison unit;

[0029] The multiplexing submodule is configured to output a new data group during the pre-charging phase;

[0030] The comparison unit is configured to compare the new data group output by the multiplexing submodule with the current data group output by the output submodule during the pre-charging phase, and control the pre-charging configuration unit according to the comparison result;

[0031] The pre-charging configuration unit is configured to perform pre-charging control on each operational amplifier of the source module in the pre-charging phase according to the comparison result;

[0032] The output submodule is configured to latch a new data group output by the multiplexing submodule after the pre-charging phase.

[0033] According to a second aspect of the present disclosure, a display device is provided, comprising the aforementioned driving chip and a display panel.

[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0036] Figure 1 Schematic diagram of the structure of a display device in one embodiment of the present disclosure.

[0037] Figure 2 Schematic diagram of the structure of a display unit in one embodiment of the present disclosure.

[0038] Figure 3 Schematic diagram of the structure of a display unit in one embodiment of the present disclosure.

[0039] Figure 4 FIG. 1 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0040] Figure 5 FIG. 1 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0041] Figure 6 FIG. 1 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0042] Figure 7 FIG. 1 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0043] Figure 8 FIG. 1 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0044] Figure 9 Schematic diagram of the driving method principle of the driving module in the related art.

[0045] Figure 10 This is a schematic structural diagram of a driver chip in one embodiment of the present disclosure.

[0046] Figure 11 This is a schematic diagram of the connection between the write control module and the receiving submodule in one embodiment of the present disclosure.

[0047] Figure 12 This is a schematic diagram of the connection between the data writing line and the receiving submodule in one embodiment of the present disclosure.

[0048] Figure 13 1 is a schematic diagram of an equivalent circuit of a control module written by a driver chip in a first working mode in one embodiment of the present disclosure.

[0049] Figure 14 1 is a schematic diagram of signal transmission on a data write line when the driver chip is in the first working mode in one embodiment of the present disclosure.

[0050] Figure 15 FIG1 is a schematic diagram of the operating timing of the driver chip in the first operating mode in one embodiment of the present disclosure.

[0051] Figure 16 1 is a schematic diagram of an equivalent circuit of a control module written into a driver chip in a fourth operating mode in one embodiment of the present disclosure.

[0052] Figure 17 1 is a schematic diagram of signal transmission on a data write line when the driver chip is in a fourth operating mode in one embodiment of the present disclosure.

[0053] Figure 18 FIG1 is a schematic diagram of the operating timing of the driver chip in the fourth operating mode in one embodiment of the present disclosure.

[0054] Figure 19 This is a structural diagram of the cooperation between the latch module and the source module in one embodiment of the present disclosure.

[0055] Figure 20 This is a timing diagram of the cooperation between the latch module and the source module in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0057] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0058] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0059] The present disclosure provides a display device. Figure 1 The display device includes a display panel PNL and a driving module CTR for driving the display panel PNL.

[0060] In one embodiment of the present disclosure, see Figure 1 The display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. For example, the display panel PNL includes the peripheral area BB surrounding the display area AA. The display panel PNL includes a display unit DU for display within the display area AA. The display unit DU includes a sub-pixel PX and a pixel driving circuit PDC for driving the sub-pixel PX. In the peripheral area BB, the display panel PNL does not include a display unit DU, or the display unit DU that is included is not used for display.

[0061] See also Figure 1 The display panel PNL is provided with scan lines GL extending along the row direction DH and data lines DL extending along the column direction DV. The pixel driving circuit PDC is configured to write analog data voltages VD loaded on the data lines DL under the control of the scan lines GL, thereby controlling the display of the sub-pixels PX.

[0062] See also Figure 1The driver module CTR includes a driver chip DIC having an output pin for outputting an analog data voltage VD. Each output pin for outputting the analog data voltage VD represents an output channel. Each data line DL is electrically connected to the output pin of the driver chip DIC. The driver chip DIC can output the analog data voltage VD to the output pin, thereby applying the analog data voltage VD to the data line DL. It is understood that the driver chip DIC may also be provided with other pins.

[0063] In some examples, the driver module CTR also includes a timing controller TCON. The timing controller TCON can receive image data, such as image data for each video frame in a video signal, and then forward the image data to the driver chip DIC according to a preset protocol. For example, the timing controller TCON can forward the image data to the driver chip DIC row by row. The driver chip DIC applies an analog data voltage VD to the data line DL electrically connected to the sub-pixel PX based on the grayscale data of each sub-pixel PX in the received image data.

[0064] In one embodiment of the present disclosure, the display panel PNL is a liquid crystal display panel. In this embodiment, the display panel PNL includes a driving substrate and a color filter substrate arranged in a cell, and a liquid crystal layer located between the driving substrate and the color filter substrate. The display panel PNL also includes a first polarizer located on the side of the driving substrate away from the color filter substrate and a second polarizer located on the side of the color filter substrate away from the driving substrate. Figure 2 Pixel electrodes PEA, corresponding to each subpixel PX, and common electrodes PEB, cooperating with the pixel electrodes PEA, are provided on the driver substrate and color filter substrate. The electric field between the pixel electrodes PEA and PEB can influence the flipping or inversion of the liquid crystal within the subpixel PX, thereby controlling the light transmittance of the subpixel PX. In other words, in this liquid crystal display panel, the subpixel PX acts as a liquid crystal optical switch whose light transmittance is controlled by voltage.

[0065] In some examples, the pixel electrode PEA and the common electrode PEB may both be disposed on the driving substrate, for example, the pixel electrode PEA and the common electrode PEB may be disposed on the same electrode layer of the driving substrate or on two different electrode layers. In other examples, the pixel electrode PEA and the common electrode PEB may be disposed on the driving substrate and the color filter substrate, respectively.

[0066] In some examples, the pixel driving circuit PDC includes a switching transistor SW electrically connected to the pixel electrode PEA. For example, the pixel driving circuit PDC is a switching transistor SW. The display panel PNL is provided with scan lines GL extending along the row direction DH and data lines DL extending along the column direction DV. A first electrode of the switching transistor SW is electrically connected to the data line DL, a gate of the switching transistor SW is electrically connected to the scan line GL, and a second electrode of the switching transistor SW is electrically connected to the pixel electrode PEA. When a scan signal is applied to the scan line GL, the switching transistor SW can be turned on in response to the scan signal, thereby applying the analog data voltage VD applied to the data line DL to the pixel electrode PEA, thereby adjusting the electric field between the pixel electrode PEA and the common electrode PEB, thereby controlling the transmittance of the sub-pixel PX.

[0067] In one example, the display device further includes a backlight module stacked with the display panel PNL, which can provide backlight for the display panel PNL. For example, the backlight module can be disposed on a side of the first polarizer away from the drive substrate. Of course, in other examples of the present disclosure, the display panel PNL may not be provided with a backlight module.

[0068] It is understandable that in some other embodiments of the present disclosure, the display panel PNL may not be a liquid crystal display panel, for example, it may be a self-luminous direct display panel.

[0069] For example, see Figure 3 The sub-pixel PX can be a current-driven, self-luminous light-emitting element, such as an OLED, PLED, QLED, MiniLED, or QLED. The pixel driving circuit PDC can include at least a driving transistor DT, a storage capacitor Cst, and a switching transistor SW. The first terminal of the driving transistor is used to directly or indirectly apply a first power supply voltage V1, the second terminal of the driving transistor is used to directly or indirectly connect to the light-emitting element, the gate of the driving transistor is electrically connected to the storage capacitor Cst, the first terminal of the switching transistor SW is directly or indirectly electrically connected to the data line DL, the gate of the switching transistor SW is electrically connected to the scan line GL, and the second terminal of the switching transistor SW is directly or indirectly electrically connected to the storage capacitor Cst. The other end of the light-emitting element is applied with a second power supply voltage V2. When a scan signal is applied to the scan line GL, the switching transistor SW can be turned on in response to the scan signal, thereby allowing the analog data voltage VD applied to the data line DL to be written into the storage capacitor Cst and stored. The driving transistor DT can achieve voltage-to-current conversion under the control of the voltage on the storage capacitor Cst, outputting a driving current for driving the light-emitting element, thereby controlling the brightness of the light-emitting element.

[0070] See also Figure 4The display units DU on the display panel PNL can be arranged in an array to form a plurality of display unit rows HDU and a plurality of display unit columns VDU. The display unit rows HDU include a plurality of display unit DU sequentially arranged along a row direction DH, and each display unit row HDU is sequentially arranged along a column direction DV. The display unit columns VDU include a plurality of display unit DU sequentially arranged along a column direction DV, and each display unit column VDU is sequentially arranged along the row direction DH.

[0071] With the development of display technology and the increasing variety of application scenarios, the sizes, resolutions and other types of display panels PNL are increasing, and the layout modes of display panels PNL are also becoming more diverse.

[0072] Figure 5 FIG. 1 is a connection diagram of the data lines DL, the scan lines GL and the display units DU on the display panel PNL in the first embodiment; FIG. Figure 5 Only one display unit row HDU is shown in FIG. Figure 5 Each display unit row HDU corresponds to a scan line GL. The gates of each switching transistor SW in the display unit row HDU are electrically connected to the same scan line GL; the second electrodes of each switching transistor SW in the display unit row HDU are electrically connected to their corresponding data lines DL. The display panel PNL of this embodiment adopts a 1-row-1-scan layout. Each data line DL needs to be electrically connected to an output pin of a driver chip DIC to ensure that each display unit DU in the display unit row HDU can be scanned and simultaneously loaded with analog data voltage VD. In other words, the number of display units DU in each display unit row HDU is the same as the total number of output pins of the driver chip DIC.

[0073] Figure 6 FIG. 1 is a connection diagram of the data lines DL, the scan lines GL and the display units DU on the display panel PNL in the second embodiment; FIG. Figure 6 Only one display unit row HDU is shown in FIG. Figure 6Each display unit row HDU corresponds to two scan lines GL. The gates of half the switching transistors SW in this display unit row HDU are electrically connected to one scan line GL, and the gates of the other half are electrically connected to the other scan line GL. The second electrodes of each switching transistor SW in this display unit row HDU are electrically connected to their corresponding data lines DL. The display panel PNL of this embodiment adopts a 1-row, 2-scan layout mode, and the analog data voltage VD is written to the display unit row HDU in two steps. Therefore, the two display units DU in the same display unit row HDU, each electrically connected to two scan lines GL, can have their respective connected data lines DL electrically connected to the same output pin. This allows each output pin of the driver chip DIC to drive two data lines DL, thereby reducing the number of output pins of the driver chip DIC to half the number of data lines DL, thereby reducing the number of driver chips DIC or lowering the cost of the driver chip DIC.

[0074] Figure 7 FIG. 1 is a connection diagram of the data lines DL, the scan lines GL and the display units DU on the display panel PNL in the third embodiment; FIG. Figure 7 Only one display unit row HDU is shown in FIG. Figure 7 Each display unit row HDU corresponds to three scan lines GL. The gates of approximately one-third of the switching transistors SW in this display unit row HDU are electrically connected to the first scan line GL, the gates of approximately one-third of the switching transistors SW are electrically connected to the second scan line GL, and the gates of approximately one-third of the switching transistors SW are electrically connected to the third scan line GL. The second electrodes of each switching transistor SW in this display unit row HDU are electrically connected to a corresponding data line DL. The display panel PNL of this embodiment employs a 1-row, 3-scan layout. The analog data voltage VD is written to the display unit row HDU in three steps. Therefore, the three display units DU in the same display unit row HDU, each electrically connected to the three scan lines GL, can each have their connected data lines DL electrically connected to the same output pin. This allows each output pin of the driver chip DIC to drive three data lines DL, thereby reducing the number of output pins in the driver chip DIC to one-third of the number of data lines DL. This reduces the number of driver chips or reduces the cost of the driver chip DIC.

[0075] Figure 8 FIG4 is a connection diagram of the data lines DL, the scan lines GL and the display units DU on the display panel PNL in the fourth embodiment; FIG4 is a connection diagram of the data lines DL, the scan lines GL and the display units DU on the display panel PNL; Figure 8 Only one display unit row HDU is shown in FIG. Figure 8Each display unit row HDU corresponds to four scan lines GL. The gates of approximately one-quarter of the switching transistors SW in this display unit row HDU are electrically connected to the first scan line GL, the gates of approximately one-quarter of the switching transistors SW are electrically connected to the second scan line GL, the gates of approximately one-quarter of the switching transistors SW are electrically connected to the third scan line GL, and the gates of approximately one-quarter of the switching transistors SW are electrically connected to the fourth scan line GL. The second electrodes of each switching transistor SW in this display unit row HDU are electrically connected to a corresponding data line DL. The display panel PNL of this embodiment employs a 1-row, 4-scan layout. The analog data voltage VD is written to the display unit row HDU in four steps. Therefore, the four display units DU in the same display unit row HDU, each electrically connected to the four scan lines GL, can each have their connected data lines DL electrically connected to the same output pin. This allows each output pin of the driver chip DIC to drive four data lines DL, thereby reducing the number of output pins in the driver chip DIC to one-quarter the number of data lines DL. This reduces the number of driver chips or reduces the cost of the driver chip DIC.

[0076] It is understood that in other embodiments of the present disclosure, the display panel PNL may also adopt other layout modes. For example, the display panel PNL may also adopt a 1-row 5-scan strategy, or a 1-row 6-scan strategy. With reference to the first to fourth embodiments of the display panel PNL described above, the number of output pins of the driver chip DIC required for the display device can be further reduced, thereby further reducing the number of driver chips DIC or further reducing the cost of the driver chip DIC.

[0077] In the related art, when the display panel PNL adopts a 1-row multi-scan layout mode, the driving module CTR requires the timing controller TCON to split the data into multiple pseudo data rows so that the driving chip DIC can be driven normally. Figure 9 Taking 1 line 2 scans as an example, the driving process of the driving module CTR in the related art is exemplarily introduced.

[0078] See also Figure 9In the related art, a timing controller TCON receives image data, which includes grayscale data for each subpixel PX of a display panel PNL. The grayscale data for each subpixel PX is arranged row by row in the order of the display unit rows HDU, with each data row corresponding to a display unit row HDU. Of course, it is understood that if the data format of the image data is inconsistent with the pixel arrangement of the display panel PNL, the timing controller TCON may process the received image data to form data rows that correspond one-to-one to each display unit row HDU. The timing controller TCON needs to process the image data so that each data row is split into two pseudo data rows.

[0079] by Figure 9 For example, before data splitting, the first data row includes the grayscale data of all sub-pixels of the first display unit row HDU, that is, grayscale data G(1,1), grayscale data G(1,2), grayscale data G(1,3) ... grayscale data G(1,N-1), grayscale data G(1,N), etc. Among them, the grayscale data G(1,x) represents the grayscale data of the sub-pixel PX of the x-th display unit DU in the first display unit row HDU, x is a positive integer from 1 to N, and N is the number of display units DU included in a display unit row HDU. Figure 9 , the first data row can be split into two dummy data rows; the first dummy data row includes grayscale data G(1,1), grayscale data G(1,3), ... grayscale data G(1,N-1), and other grayscale data for the odd-numbered display units DU of the first display unit row HDU; the second dummy data row includes grayscale data G(1,2), grayscale data G(1,3), ... grayscale data G(1,N), and other grayscale data for the even-numbered display units DU of the first display unit row HDU. All data in the first and second dummy data rows are used together to drive the first display unit row HDU. Each dummy data row is sequentially sent to the driver chip DIC, which drives the display unit row HDU based on the received dummy data row. In other words, the timing controller TCON treats the first and second dummy data rows as data for two display unit rows HDU and sends them to the driver chip DIC separately.

[0080] Effectively, the number of channels (i.e., the number of output pins) of the driver chip DIC of the driver module CTR can be half the number of data lines DL, and the analog data voltage VD is written to the same display unit row HDU twice. However, from a process and hardware perspective, the driver module CTR treats a display unit row HDU as two interlocking pseudo display unit rows (each pseudo display unit row corresponds to a pseudo data row) for processing. The timing controller TCON sends the grayscale data of one pseudo display unit row (i.e., one pseudo data row) to the driver chip DIC each time, and the driver chip DIC drives the corresponding pseudo display unit row based on the grayscale data of the pseudo display unit row. In other words, the timing controller TCON needs to have the function of splitting the image data to generate pseudo data rows, and the driver chip DIC actually only has the driving capability of one row and one scan. On the one hand, this leads to excessively high cost of the timing controller TCON; on the other hand, the excessive cost of the timing controller TCON makes it unsuitable for display panels with high channel compression ratios. For example, in related technologies, the channel compression ratio (the ratio of the number of data lines DL to the number of output pins) is at most 3. Therefore, the timing controller TCON is only applicable to display panels PNL with layout modes such as 1-row 1-scan, 1-row 2-scan, or 1-row 3-scan. This also reduces the versatility of the timing controller TCON, hindering the rapid development of corresponding display products for increasingly diverse application scenarios.

[0081] Embodiments of the present disclosure provide a driver chip (DIC) that can receive data rows from display unit rows (HDU) one by one and provide targeted driving according to the layout of the display panel (PNL). For example, the driver chip (DIC) inherently drives the display unit rows (HDU) once or multiple times based on a data row. This eliminates the need for the timing controller (TCON) to generate dummy data rows, significantly reducing the cost and improving the versatility of the timing controller (TCON). For example, for a display panel (PNL) with a 1-row, 4-scan layout, a single driver chip (DIC) with 1920 output pins provided by embodiments of the present disclosure can support a 2560 RGB*1440 resolution display. Compared to a timing controller (TCON), the driver chip (DIC) is less expensive and is compatible with multiple layouts, offering high versatility. Furthermore, the driver chip (DIC) uses analog latches to process data rows, eliminating the need for SRAM chips. This results in minimal increase in cost and area for the driver chip (DIC). In this way, the driver chip DIC can be compatible with various types of display panels PNL without substantially increasing the size or cost.

[0082] As follows, the structure and principle of the driver chip DIC according to the embodiment of the present disclosure are exemplarily introduced with reference to the accompanying drawings.

[0083] See also Figure 10 In the embodiment of the present disclosure, the latch module TR and the source module DR are included. The latch module TR includes a receiving submodule LA, a buffer submodule LB and an output submodule LC.

[0084] The receiving submodule LA includes a plurality of primary latch groups GA, and the receiving submodule LA is used to latch a data row HD; each of the primary latch groups GA is configured to latch a data group, and the data row HD includes at least one of the data groups.

[0085] The cache submodule LB includes multiple secondary latch groups GB (secondary latch groups) corresponding one-to-one to each of the primary latch groups GA. The secondary latch groups GB are configured to latch the data latched by the corresponding primary latch groups GA in response to a second enable signal TP2. In other words, the latches of the receiving submodule LA are provided in a one-to-one correspondence with the latches of the cache submodule LB. The outputs of the latches of the receiving submodule LA are interconnected with the inputs of the latches of the cache submodule LB. When the second enable signal TP2 is applied to the cache submodule LB, the outputs of the latches of the cache submodule LB can follow the outputs of the corresponding latches of the receiving submodule LA, thereby latching the data in the receiving submodule LA into the cache submodule LB.

[0086] The output submodule LC is configured to latch each data group in the secondary latch group GB one by one. In other words, the output submodule LC corresponds to multiple secondary latch groups GB and is electrically connected to each of them. Each latch in the output submodule LC is configured in a one-to-one correspondence with each latch in the secondary latch group GB. The output submodule LC can be electrically connected to one of the secondary latch groups GB and, in response to a third enable signal TP3, cause the output of each latch in the output submodule LC to follow the output of the latch in the corresponding secondary latch group GB.

[0087] The source module DR is configured to output analog data voltages VD of respective sub-pixels corresponding to the data group according to the data group output by the output sub-module LC.

[0088] In the disclosed embodiments, a latch latching data means that, while the enable signal is applied to the enable terminal of the latch, the level outputted by the output terminal of the latch (i.e., data 0 or data 1) follows the level of the input terminal of the latch, and the output terminal continues to maintain this level after the enable signal is removed. In this way, the level of the input terminal of the latch when the enable signal is applied is latched in the latch and continuously outputted by the latch until a new latch signal is applied to the latch.

[0089] In this embodiment, a data row HD includes grayscale data corresponding to the subpixels PX of each display unit DU within a display unit row HDU. In this embodiment, a data group is the grayscale data for the subpixels PX of each display unit DU connected to the same scan line GL within a display unit row HDU. Therefore, the output submodule LC can latch each data group one by one, and the source module DR can simultaneously drive each display unit DU corresponding to that data group.

[0090] It is understood that when the layout mode of the display panel PNL is different, the data groups formed by the driver chip DIC are different. For example, when the display panel PNL adopts a 1-row 1-scan layout mode, one data row includes one data group. For another example, when the display panel PNL adopts a 1-row 2-scan layout mode, one data row includes two data groups. When the first scan line GL is loaded with a scan signal, the data group corresponding to the first scan line GL is latched into the output sub-module LC, and the source module DR applies an analog data voltage VD to each data line DL based on the data group latched by the output sub-module LC. Similarly, when the second scan line GL is loaded with a scan signal, the data group corresponding to the second scan line GL is latched into the output sub-module LC, and the source module DR applies an analog data voltage VD to each data line DL based on the data group latched by the output sub-module LC. For another example, when the display panel PNL adopts a 1-row 3-scan layout mode, one data row includes three data groups. For another example, when the display panel PNL adopts a 1-row 4-scan layout mode, one data row includes four data groups.

[0091] In one embodiment of the present disclosure, see Figure 10 The driver chip DIC also includes a buffering and reordering module BR, which can receive data rows from a host computer, such as a timing controller TCON, a microcontroller MCU, or a field-programmable gate array FPGA. After receiving the data rows, the buffering and reordering module BR can cache and, if necessary, reorder the data. Within the rearranged data rows formed after data reordering, the positions of the grayscale data corresponding to at least some display units DU can be adjusted so that after the rearranged data rows are latched in the receiving submodule LA, the data groups are latched in the corresponding primary latch group GA.

[0092] It will be appreciated that the receiving submodule LA of the driver chip DIC according to the embodiment of the present disclosure has multiple primary latch groups GA. When latching a data row into the receiving submodule LA, a data group can be completely latched in a primary latch group GA. In other words, a data group will not be latched across primary latch groups GA. When a primary latch group GA is used to latch a data group, the primary latch group GA latches only one data group.

[0093] In one embodiment of the present disclosure, if the number of data groups in a data row is the same as the number of primary latch groups GA in the receiving submodule LA, then each primary latch group GA is used to latch the data group.

[0094] In one embodiment of the present disclosure, if the number of data groups in a data row is less than the number of primary latch groups GA of the receiving submodule LA, then part of the primary latch groups GA are used to latch the data groups, and part of the primary latch groups GA are not used to latch the data groups. In the embodiment of the present disclosure, for the sake of convenience, the primary latch groups GA used to latch the data groups can be referred to as working primary latch groups GA, and the primary latch groups GA not used to latch the data groups can be referred to as idle primary latch groups GA. The driver chip DIC provided in the embodiment of the present disclosure can set the working primary latch groups GA and the idle primary latch groups GA according to the layout mode of the display panel PNL, thereby enabling the driver chip DIC to match the layout mode of the display panel PNL, so that the driver chip DIC can be compatible with different types of display panels PNL.

[0095] For example, Figure 10 In the example, the receiving submodule LA includes four primary latch groups GA. Therefore, the driver chip DIC is compatible with display panels PNL that operate with 1 row and 1 scan, display panels PNL that operate with 1 row and 2 scans, display panels PNL that operate with 1 row and 3 scans, and display panels PNL that operate with 1 row and 4 scans. When the display panel PNL operates with 1 row and 1 scan, the receiving submodule LA can be configured so that the first primary latch group GA is the working primary latch group GA, and the remaining primary latch groups GA are idle primary latch groups GA. When the display panel PNL operates with 1 row and 2 scans, the receiving submodule LA can be configured so that the first and second primary latch groups GA are the working primary latch groups GA, and the remaining primary latch groups GA are idle primary latch groups GA. When the display panel PNL is a 1-row, 3-scan display panel PNL, the receiving submodule LA can be configured so that the first, second, and third primary latch groups GA are working primary latch groups GA, and the remaining primary latch groups GA are idle primary latch groups GA. When the display panel PNL is a 1-row, 4-scan display panel PNL, the receiving submodule LA can be configured so that all primary latch groups GA are working primary latch groups GA.

[0096] It is understandable that Figure 10In the example, the receiving submodule LA has four primary latch groups GA. In other embodiments of the present disclosure, the receiving submodule LA may have more or fewer primary latch groups GA, for example, the receiving submodule LA has two primary latch groups GA, or has three primary latch groups GA, or has five primary latch groups GA, or has six primary latch groups GA. It is understandable that the more primary latch groups GA the receiving submodule LA has, the more types of display panels PNL the driver chip DIC can be compatible with, and the higher the versatility of the driver chip DIC. In one example, the receiving submodule LA has 4 to 6 primary latch groups GA.

[0097] It is understandable that when writing data rows into the receiving submodule LA, it is not necessarily required to be written in the order of the data groups, nor is it necessarily required to be written in the order of the first-level latch groups GA, so as to ultimately enable each data group to be correctly written into the corresponding first-level latch group GA.

[0098] In one embodiment of the present disclosure, see Figure 11 The receiving submodule LA includes multiple latch units UA, each of which includes multiple latch subunits SUA corresponding one-to-one to each of the primary latch groups GA. Each of the primary latch groups GA has a corresponding latch subunit SUA in each of the latch units UA; the input terminals of the latches in the same latch subunit SUA are interconnected. The driver chip DIC also includes a scanning circuit SR corresponding one-to-one to each of the latch subunits SUA. The scanning circuit SR is configured to sequentially generate a first enable signal TP1 for each latch in the corresponding latch subunit SUA. In response to the respective first enable signals TP1, the latches in the latch subunits SUA cause the data output at the output terminals to follow the data loaded at the input terminals. It is understood that when the first enable signal TP1 is not loaded to the latches in the latch subunit SUA, the data output at the output terminals of the latches in the latch subunit SUA remains unchanged. Thus, when receiving data rows HD, the receiving submodule LA can receive data in units of latch subunits SUA. At the same time, the working scan circuit SR can be adjusted to further adjust the latch subunit SUA for receiving the data row HD, thereby realizing the configuration of the working primary latch group GA and the idle primary latch group GA.

[0099] For example, in Figure 11In the example, the receiving submodule LA includes four primary latch groups GA, namely the first primary latch group GA1, the second primary latch group GA2, the third primary latch group GA3, and the fourth primary latch group GA4. The receiving submodule LA also includes multiple latch units UA, and the latch shared by one latch unit UA and one primary latch group GA forms a latch subunit SUA. In this way, one latch unit UA includes four latch subunits SUA, namely the first latch subunit SUA1 belonging to the first primary latch group GA1, the second latch subunit SUA2 belonging to the second primary latch group GA2, the third latch subunit SUA3 belonging to the third primary latch group GA3, and the fourth latch subunit SUA4 belonging to the fourth primary latch group GA4. The driver chip DIC includes a scanning circuit SR corresponding to each latch subunit SUA. For example, a first scanning circuit SR1 is provided in a one-to-one correspondence with a first latch sub-unit SUA1, and the first scanning circuit SR1 is used to generate a first enable signal TP1 for each latch of the corresponding first latch sub-unit SUA1. For example, the first scanning circuit SR1 can sequentially load the first enable signal TP1 to each latch of the first latch sub-unit SUA1; when the input end of each latch of the first latch sub-unit SUA1 is loaded with data (e.g., a high level or a low level), if the first scanning circuit SR1 sequentially loads the first enable signal TP1 of each latch to the corresponding first latch sub-unit SUA1, each latch of the first latch sub-unit SUA1 can sequentially latch the data at the input end. For another example, a second scanning circuit SR2 is provided in a one-to-one correspondence with a second latch sub-unit SUA2, and the second scanning circuit SR2 is used to generate a first enable signal TP1 for each latch of the corresponding second latch sub-unit SUA2. For another example, the third scan circuit SR3 is provided in a one-to-one correspondence with the third latch sub-unit SUA3, and the third scan circuit SR3 is used to generate the first enable signal TP1 for each latch of the corresponding third latch sub-unit SUA3. For another example, the fourth scan circuit SR4 is provided in a one-to-one correspondence with the fourth latch sub-unit SUA4, and the fourth scan circuit SR4 is used to generate the first enable signal TP1 for each latch of the corresponding fourth latch sub-unit SUA4.

[0100] In one embodiment of the present disclosure, see Figure 10 and Figure 11 The driver chip DIC includes a write control module MSR, which includes a plurality of receiving control units USR corresponding one-to-one to each latch unit UA. The receiving control unit USR includes a plurality of scanning circuits SR corresponding one-to-one to each latch sub-unit SUA in the corresponding latch unit UA, and a scanning control circuit CSR.

[0101] The scan control circuit CSR is configured to determine the cascade state between the scan circuits SR in the same receiving control unit USR and the cascade state between the scan circuits SR in adjacent receiving control units USR according to the scan configuration signal.

[0102] In this way, different scan configuration signals can be used to configure the write control module MSR, thereby configuring the active and idle primary latch groups GA and GA of the receiving submodule LA. Specifically, each scan circuit SR can be configured, thereby configuring the corresponding latch subunit SUA. When a scan circuit SR is short-circuited, it is disconnected from the cascade connection with other scan circuits SR and will not generate the first enable signal TP1. Data will not be written into the corresponding latch subunit SUA.

[0103] In one embodiment of the present disclosure, see Figure 11 The latch unit UA includes a first latch subunit SUA1, a second latch subunit SUA2, a third latch subunit SUA3, and a fourth latch subunit SUA4; the receiving control unit USR includes a first scanning circuit SR1 corresponding to the first latch subunit SUA1, a second scanning circuit SR2 corresponding to the second latch subunit SUA2, a third scanning circuit SR3 corresponding to the third latch subunit SUA3, and a fourth scanning circuit SR4 corresponding to the fourth latch subunit SUA4; the scanning control circuit CSR includes a first transistor T1 to a seventh transistor T7.

[0104] Among them, the receiving control unit USR includes a first input terminal IN1, a second input terminal IN2, a first output terminal OUT1 and a second output terminal OUT2; in two adjacent receiving control units USR, the first output terminal OUT1 of the previous level receiving control unit USR is electrically connected to the first input terminal IN1 of the next level receiving control unit USR, and the second output terminal OUT2 of the previous level receiving control unit USR is electrically connected to the second input terminal IN2 of the next level receiving control unit USR.

[0105] In the same receiving control unit USR, the cascade input terminal of the first scanning circuit SR1 is electrically connected to the first input terminal IN1; the cascade output terminal of the first scanning circuit SR1, the cascade input terminal of the third scanning circuit SR3, and the first electrode of the first transistor T1 are electrically connected to each other; the cascade output terminal of the third scanning circuit SR3, the second electrode of the first transistor T1, the first electrode of the fourth transistor T4, and the first electrode of the seventh transistor T7 are electrically connected to each other; the second electrode of the fourth transistor T4 and the second electrode of the sixth transistor T6 are electrically connected to the first output terminal OUT1; the cascade input terminal of the second scanning circuit SR2 and the first electrode of the second transistor T2 are electrically connected to the second input terminal IN2; the cascade output terminal of the second scanning circuit SR2, the cascade input terminal of the fourth scanning circuit SR4, the second electrode of the second transistor T2, and the first electrode of the third transistor T3 are electrically connected to each other; the cascade output terminal of the fourth scanning circuit SR4, the second electrode of the third transistor T3, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 are electrically connected to each other; and the second electrode of the seventh transistor T7 and the second electrode of the fifth transistor T5 are electrically connected to the second output terminal OUT2.

[0106] In this way, the receiving control unit USR can be controlled by controlling each of the first transistor T1 to the seventh transistor T7. For example, when the first transistor T1 is turned on, the third scanning circuit SR3 is short-circuited, resulting in the third latch sub-unit SUA3 not being used to latch data.

[0107] exist Figure 11 In the example, each latch unit UA includes four latch sub-units SUA; accordingly, the receiving control unit USR includes four scan circuits SR. It is understandable that in other embodiments of the present disclosure, the number of latch sub-units SUA included in the latch unit UA may be greater or lesser, for example, each latch unit UA includes five latch sub-units SUA or six latch sub-units SUA; the scan circuits SR in the receiving control unit USR correspond one-to-one with the latch sub-units SUA in the corresponding latch unit UA, and the number remains consistent. In this case, the scan control circuit CSR may include more or fewer transistors to achieve control of each scan circuit SR.

[0108] For example, the scan control circuit CSR includes a control transistor and a path transistor. Except for the first scan circuit SR1, each scan circuit SR is connected in parallel with a control transistor. The scan circuit SR of the scan control circuit CSR forms two cascade channels, each cascade channel including multiple scan circuits SR (or only one scan circuit SR) cascaded in sequence; the cascade output end of the last scan circuit SR in one cascade channel is electrically connected to the first output end OUT1 and the second output end OUT2 respectively through two path transistors; the cascade output end of the last scan circuit SR in the other cascade channel is electrically connected to the first output end OUT1 and the second output end OUT2 respectively through another two path transistors. In this way, the cascade between the scan circuits SR and the cascade between the receiving control units USR can be controlled by controlling the various control transistors and path transistors.

[0109] In one embodiment of the present disclosure, see Figure 12 The driver chip DIC is provided with one or more data write lines BL; the latch sub-unit SUA further includes a selection sub-circuit BLX corresponding to each latch sub-unit SUA, and the input end of each latch of the latch sub-unit SUA is electrically connected to each data write line BL through the corresponding selection sub-circuit BLX; the selection sub-circuit BLX is configured to electrically connect the input end of each latch of the latch sub-unit SUA to at most one data write line BL according to a selection configuration signal.

[0110] In one embodiment of the present disclosure, each selection sub-circuit BLX includes a selection transistor corresponding to each data write line BL. The first end of each selection transistor is electrically connected to the corresponding data write line BL, and the second end of each selection transistor is electrically connected to the input end of each latch of the corresponding latch sub-unit SUA. By controlling the conduction state of each selection transistor in the selection sub-circuit BLX, one of the selection transistors in the selection sub-circuit BLX can be turned on, or all of them can be turned off.

[0111] For example, in Figure 12In the example, the latch unit UA includes four latch sub-units SUA, each corresponding to a select sub-circuit BLX. The driver chip DIC is provided with two data write lines BL, namely a first data write line BL1 and a second data write line BL2. Each select sub-circuit BLX includes an eighth transistor T8 and a ninth transistor T9. The first electrode of the eighth transistor T8 is electrically connected to the first data write line BL1, the first electrode of the ninth transistor T9 is electrically connected to the second data write line BL2, and the second electrodes of the eighth transistor T8 and the ninth transistor T9 are both electrically connected to the input of the corresponding latch sub-unit SUA. By controlling the eighth transistor T8 and the ninth transistor T9 of the select sub-circuit BLX, one select transistor of the select sub-circuit BLX can be turned on, or both select transistors of the select sub-circuit BLX can be turned off.

[0112] The following describes the compatibility of the driver chip DIC and its compatibility method, taking the example of the driver chip DIC being compatible with a display panel PNL with 1 line and 1 scan and a display panel PNL with 1 line and 4 scans as examples. It is understandable that the driver chip DIC of the embodiment of the present disclosure is compatible with various display panels PNL.

[0113] In one embodiment of the present disclosure, the scan control circuit CSR is configured to be able to assume a first operating mode according to a first scan configuration signal. In the first operating mode, see Figure 11 , the first transistor T1 , the second transistor T2 , the third transistor T3 , the sixth transistor T6 and the seventh transistor T7 are in the on state, and the fourth transistor T4 and the fifth transistor T5 are in the off state. Figure 13 FIG. 1 is a schematic diagram showing a configuration state of the write control module MSR in the first working mode in one embodiment. Figure 13 The write control module MSR includes two cascade channels. The first cascade channel includes the odd-numbered first scan circuits SR1 cascaded in sequence, and the second cascade channel includes the even-numbered first scan circuits SR1 cascaded in sequence. Correspondingly, the first latch subunits SUA1 of the receiving submodule LA are working latch subunits SUA, while the second latch subunit SUA2, the third latch subunit SUA3, and the fourth latch subunit SUA4 are all idle latch subunits SUA. At the same time, the odd-numbered first scan circuit SR1 and the subsequent even-numbered first scan circuit SR1 simultaneously output the cascaded first enable signal TP1, which causes the odd-numbered first latch subunit SUA1 and the subsequent even-numbered first latch subunit SUA1 to latch the data row HD simultaneously.

[0114] In the first working mode of this example, see Figure 12, the ninth transistor T9 of the selection sub-circuit BLX corresponding to the odd-numbered first latch sub-unit SUA1 can be turned on, the eighth transistor T8 of the selection sub-circuit BLX corresponding to the even-numbered first latch sub-unit SUA1 can be turned on, and the remaining selection sub-circuits BLX can be turned off. Figure 14 FIG1 is a schematic diagram showing a connection state between the first latch sub-unit SUA1 and the data write line BL in the first working mode in one embodiment. Figure 14 , each odd-numbered first latch sub-unit SUA1 is electrically connected to the first data write line BL1 , and each even-numbered first latch sub-unit SUA1 is electrically connected to the second data write line BL2 .

[0115] In one example, the second latch sub-unit SUA2, the third latch sub-unit SUA3, and the fourth latch sub-unit SUA4 may not be electrically connected to any data write line BL. In another example, the second latch sub-unit SUA2, the third latch sub-unit SUA3, and the fourth latch sub-unit SUA4 may also be electrically connected to the data write line BL, but because the second scan circuit SR2, the third scan circuit SR3, and the fourth scan circuit SR4 do not output the cascaded first enable signal TP1, the data on the data write line BL will not be latched by the second latch sub-unit SUA2, the third latch sub-unit SUA3, and the fourth latch sub-unit SUA4.

[0116] Figure 15 This is a timing diagram of data reception in the first working mode of this example. Figures 13 to 15 , taking how the receiving submodule LA latches the data row HD(1) corresponding to the first display unit row as an example, the working process of the driver chip DIC is exemplarily described.

[0117] See also Figure 14 Before writing the data row HD(1) corresponding to the first display unit row into the latch module TR, the cascade start signal STV is first loaded into the write control module MSR. In response to the cascade start signal STV corresponding to the data row HD(1) corresponding to the first display unit row, the first scanning circuit SR1 of the first receiving control unit USR and the first scanning circuit SR1 of the second receiving control unit USR then each output a plurality of first enable signals TP1. Figure 14 In the example, data D(1,1) represents data in the data row HD for latching in the first first latch sub-unit SUA1; data D(2,1) represents data in the data row HD for latching in the second first latch sub-unit SUA1; data D(3,1) represents data in the data row HD for latching in the third first latch sub-unit SUA1; data D(4,1) represents data in the data row HD for latching in the fourth first latch sub-unit SUA1.

[0118] During the process in which the first scanning circuit SR1 of the first receiving control unit USR outputs the first enable signals TP1 corresponding to the first first latch sub-unit SUA1, the first scanning circuit SR1 of the second receiving control unit USR outputs the first enable signals TP1 corresponding to the second first latch sub-unit SUA1; the first data write line BL1 loads data D(1,1), and the second data write line BL2 loads data D(2,1); the first first latch sub-unit SUA1 latches data D(1,1); and the second first latch sub-unit SUA1 latches data D(2,1).

[0119] While the first scanning circuit SR1 of the third receiving control unit USR outputs the first enable signals TP1 corresponding to the third first latch sub-unit SUA1, the first scanning circuit SR1 of the fourth receiving control unit USR outputs the first enable signals TP1 corresponding to the fourth first latch sub-unit SUA1; the first data write line BL1 loads data D(3,1), and the second data write line BL2 loads data D(4,1); the third first latch sub-unit SUA1 latches data D(3,1); and the fourth first latch sub-unit SUA1 latches data D(4,1). In this way, the other first scanning circuits SR1 operate in sequence until all the data rows HD(1) corresponding to the first display unit row are written into the first primary latch group GA1.

[0120] See also Figure 15 After the data row HD(1) corresponding to the first display unit row is latched by the receiving submodule LA, a second enable signal TP2 is sent to the cache submodule LB, so that the data row HD(1) corresponding to the first display unit row output by the receiving submodule LA is latched by the cache submodule LB. After the cache submodule LB latches the data row HD(1) corresponding to the first display unit row, a second cascade start signal STV is sent to the write control module MSR, and immediately after the second cascade start signal STV, the data row HD(2) corresponding to the second display unit row is loaded to the first data write line BL1 and the second data write line BL2.

[0121] In another embodiment of the present disclosure, the scan control circuit CSR is configured to be able to assume a fourth operating mode according to a fourth scan configuration signal. In the fourth operating mode, see Figure 11 , the first transistor T1 , the second transistor T2 , the third transistor T3 , the sixth transistor T6 and the seventh transistor T7 are in the off state, and the fourth transistor T4 and the fifth transistor T5 are in the on state. Figure 16 FIG. 1 is a schematic diagram of a configuration state of the write control module MSR in the fourth working mode in one embodiment. Figure 16The write control module MSR includes two cascade channels, each of which includes four scanning circuits SR connected in sequence. Specifically, each first scanning circuit SR1 and each third scanning circuit SR3 are alternately arranged and cascaded to form a cascade channel, and each second scanning circuit SR2 and each fourth scanning circuit SR4 are alternately arranged and cascaded to form a cascade channel. For example, the first cascade channel includes the first first scanning circuit SR1, the first third scanning circuit SR3, the second first scanning circuit SR1, the second third scanning circuit SR3, the third first scanning circuit SR1, the third third scanning circuit SR3, etc., which are connected in sequence in cascade. The second cascade channel includes the first second scanning circuit SR2, the first fourth scanning circuit SR4, the second second scanning circuit SR2, the second fourth scanning circuit SR4, the third second scanning circuit SR2, the third fourth scanning circuit SR4, etc., which are connected in cascade in sequence.

[0122] Correspondingly, each latch subunit SUA of the receiving submodule LA is a working latch subunit SUA. The first cascade channel can cause each latch subunit SUA driven by it to latch data in sequence, for example, the first first latch subunit SUA1, the first third latch subunit SUA3, the second first latch subunit SUA1, the second third latch subunit SUA3, the third first latch subunit SUA1, the third third latch subunit SUA3... the last first latch subunit SUA1, the last third latch subunit SUA3 latch data in sequence. The second cascade channel can enable the various latch sub-units SUA driven by it to latch data in sequence, for example, the first second latch sub-unit SUA2, the first fourth latch sub-unit SUA4, the second second latch sub-unit SUA2, the second fourth latch sub-unit SUA4, the third second latch sub-unit SUA2, the third fourth latch sub-unit SUA4... the last second latch sub-unit SUA2 and the last fourth latch sub-unit SUA4 latch data in sequence.

[0123] In the fourth working mode of this example, see Figure 12 and Figure 17 , the ninth transistor T9 of the selection sub-circuit BLX corresponding to each of the first latch sub-units SUA1 and the third latch sub-unit SUA3 can be turned on, thereby causing the first data write line BL1 to load data to each of the first latch sub-units SUA1 and the third latch sub-unit SUA3; the eighth transistor T8 of the selection sub-circuit BLX corresponding to each of the second latch sub-units SUA2 and the fourth latch sub-unit SUA4 can be turned on, thereby causing the second data write line BL2 to load data to each of the second latch sub-units SUA2 and the fourth latch sub-unit SUA4.

[0124] Figure 18This is a timing diagram of data reception in the fourth working mode of this example. Figures 16 to 18 , taking how the receiving submodule LA latches the data row HD(1) corresponding to the first display unit row as an example, the working process of the driver chip DIC is exemplarily described.

[0125] exist Figure 17 In the example, data D(1,1) represents data in the data row HD for latching in the first first latch sub-unit SUA1; data D(1,2) represents data in the data row HD for latching in the first second latch sub-unit SUA2; data D(1,3) represents data in the data row HD for latching in the first third latch sub-unit SUA3; and data D(1,4) represents data in the data row HD for latching in the first fourth latch sub-unit SUA4. Data D(2,1) represents data in the data row HD for latching in the second first latch sub-unit SUA1; data D(2,2) represents data in the data row HD for latching in the second second latch sub-unit SUA2; data D(2,3) represents data in the data row HD for latching in the second third latch sub-unit SUA3; and data D(2,4) represents data in the data row HD for latching in the second fourth latch sub-unit SUA4. Data D(3,1) represents the data in the data row HD used to be latched in the third first latch sub-unit SUA1; data D(3,2) represents the data in the data row HD used to be latched in the third second latch sub-unit SUA2; data D(3,3) represents the data in the data row HD used to be latched in the third third latch sub-unit SUA3; data D(3,4) represents the data in the data row HD used to be latched in the third fourth latch sub-unit SUA4.

[0126] Before writing the data row HD(1) corresponding to the first display unit row into the latch module TR, the cascade start signal STV is first loaded into the write control module MSR. During the process in which the first scanning circuit SR1 of the first receiving control unit USR outputs the first enable signals TP1 corresponding to the first first latch sub-unit SUA1, the second scanning circuit SR2 of the first receiving control unit USR outputs the first enable signals TP1 corresponding to the first second latch sub-unit SUA2; the first data write line BL1 is loaded with data D(1,1), and the second data write line BL2 is loaded with data D(1,2); the first first latch sub-unit SUA1 latches the data D(1,1); and the first second latch sub-unit SUA2 latches the data D(1,2).

[0127] Subsequently, the third scanning circuit SR3 of the first receiving control unit USR outputs the first enable signals TP1 corresponding to the first third latch sub-unit SUA3, and the fourth scanning circuit SR4 of the first receiving control unit USR outputs the first enable signals TP1 corresponding to the first fourth latch sub-unit SUA4; in this process, the first data write line BL1 loads data D(1,3), and the second data write line BL2 loads data D(1,4); the first third latch sub-unit SUA3 latches data D(1,3); the first fourth latch sub-unit SUA4 latches data D(1,4). Subsequently, the first scanning circuit SR1 of the second receiving control unit USR outputs the first enable signals TP1 corresponding to the second first latch sub-unit SUA1, and the second scanning circuit SR2 of the second receiving control unit USR outputs the first enable signals TP1 corresponding to the second second latch sub-unit SUA2; the first data write line BL1 loads data D(2,1), and the second data write line BL2 loads data D(2,2); the second first latch sub-unit SUA1 latches data D(2,1); the second second latch sub-unit SUA2 latches data D(2,2). Subsequently, the third scanning circuit SR3 of the second receiving control unit USR outputs the first enable signals TP1 corresponding to the second third latch sub-unit SUA3, and the fourth scanning circuit SR4 of the second receiving control unit USR outputs the first enable signals TP1 corresponding to the second fourth latch sub-unit SUA4. During this process, the first data write line BL1 is loaded with data D(2,3), and the second data write line BL2 is loaded with data D(2,4). The second third latch sub-unit SUA3 latches data D(2,3); and the second fourth latch sub-unit SUA4 latches data D(2,4). Similarly, while the third first latch sub-unit SUA1 writes data D(3,1), the third second latch sub-unit SUA2 writes data D(3,2); while the third third latch sub-unit SUA3 writes data D(3,3), the third fourth latch sub-unit SUA4 writes data D(3,4). This continues until all the data rows HD(1) corresponding to the first display unit row are written into the receiving sub-module LA.

[0128] See also Figure 18After the data row HD(1) corresponding to the first display unit row is latched by the receiving submodule LA, a second enable signal TP2 is sent to the cache submodule LB, so that the data row HD(1) corresponding to the first display unit row output by the receiving submodule LA is latched by the cache submodule LB. After the cache submodule LB latches the data row HD(1) corresponding to the first display unit row, a second cascade start signal STV is sent to the write control module MSR, and immediately after the second cascade start signal STV, the data row HD(2) corresponding to the second display unit row is loaded to the first data write line BL1 and the second data write line BL2.

[0129] It is understandable that Figure 11 The illustrated driving chip DIC is compatible with the display panel PNL with 1 line and 1 scan and the display panel PNL with 1 line and 4 scans, as well as the display panel PNL with 1 line and 2 scans and the display panel PNL with 1 line and 3 scans.

[0130] For example, it is further configured to be able to assume the second working mode according to the second scanning configuration signal, and is further configured to be able to assume the third working mode according to the third scanning configuration signal.

[0131] In the second operating mode, the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are in an on state, and the fourth transistor T4 and the fifth transistor T5 are in an off state. Thus, the write control module MSR forms two cascade channels: one cascade channel is a sequential cascade of the first scanning circuits SR1; the other cascade channel is a sequential cascade of the second scanning circuits SR2. In the second operating mode, the driver chip DIC can drive the display panel PNL in a 1-row, 2-scan mode.

[0132] In the third operating mode, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are in the on state, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are in the off state. Thus, the write control module MSR forms two cascade channels. The first cascade channel includes the first scanning circuit SR1 and the third scanning circuit SR3 in the odd-numbered receiving control unit USR, and the second scanning circuit SR2 in the even-numbered receiving control unit USR; the second cascade channel includes the first scanning circuit SR1 and the third scanning circuit SR3 in the even-numbered receiving control unit USR, and the second scanning circuit SR2 in the odd-numbered receiving control unit USR. In the third operating mode, the driver chip DIC can drive a display panel PNL with 1 row and 3 scans.

[0133] In one embodiment of the present disclosure, see Figure 10The latch module TR also includes a buffer control module TP2D, which is used to generate a second enable signal TP2 for each latch of the cache sub-module LB; the buffer control module TP2D is configured to simultaneously generate the second enable signal TP2 for each latch of the cache sub-module LB, or to generate the second enable signal TP2 for some latches of the cache sub-module LB each time until the second enable signal TP2 for all latches of the cache sub-module LB is generated.

[0134] In one example, the buffer control module TP2D is configured to simultaneously generate the second enable signal TP2 for each of the secondary latch groups GB, so that each of the secondary latch groups GB can simultaneously latch the data latched by the corresponding receiving submodule LA.

[0135] In another example, the buffer control module TP2D is configured to sequentially generate the second enable signal TP2 for the latches of each of the secondary latch groups GB. For example, the buffer control module TP2D sequentially generates the second enable signal TP2 for the first secondary latch group GB, the second enable signal TP2 for the second secondary latch group GB, the third secondary latch group GB, the fourth secondary latch group GB, and so on, until the second enable signal TP2 for the last secondary latch group GB is generated. In this manner, the data groups of each primary latch group GA are sequentially latched into the corresponding secondary latch group GB, reducing the amount of data latched each time and thereby reducing analog noise.

[0136] For example, when the buffer control module TP2D drives the cache sub-module LB once, that is, when the receiving sub-module LA transfers all latched data to the cache sub-module LB, the buffer control module TP2D can generate multiple second enable signals TP2, each second enable signal TP2 is used to drive a secondary latch group GB, and the difference between two adjacent second enable signals TP2 is 1 to 10 clock cycles, for example, a difference of 1 clock cycle.

[0137] In one embodiment of the present disclosure, see Figure 10 and Figure 19 The latch module TR further includes a multiplexing submodule MUX, through which the output of each secondary latch group GB is electrically connected to the input of the output submodule LC. The multiplexing submodule MUX is configured to selectively connect the input of the output submodule LC to one of the outputs of the secondary latch groups GB.

[0138] by Figure 19For example, the cache submodule LB includes four secondary latch groups GB: a first secondary latch group GB1, a second secondary latch group GB2, a third secondary latch group GB3, and a fourth secondary latch group GB4. The multiplexing submodule MUX has four input terminals, which are electrically connected to the output terminal of the first secondary latch group GB1, the output terminal of the second secondary latch group GB2, the output terminal of the third secondary latch group GB3, and the output terminal of the fourth secondary latch group GB4, respectively. The multiplexing submodule MUX also has an output terminal, which is electrically connected to the input terminal of the output submodule LC. The multiplexing submodule MUX is configured to electrically connect one of the output terminals of the first secondary latch group GB1, the output terminal of the second secondary latch group GB2, the output terminal of the third secondary latch group GB3, and the output terminal of the fourth secondary latch group GB4 to the output terminal of the multiplexing submodule MUX, thereby selectively connecting the input terminal of the output submodule LC to one of the output terminals of the plurality of secondary latch groups GB. When the third enable signal TP3 is applied to the output submodule LC, the data at the output end of the multiplexing submodule MUX can be latched by the output submodule LC, thereby enabling the data in a certain secondary latch group GB to be read and continuously output by the output submodule LC.

[0139] In one embodiment of the present disclosure, see Figure 19 The source module DR includes a digital-to-analog converter DAC and an operational amplifier OP; the output end of the output sub-module LC can be connected to the digital-to-analog converter DAC to configure the digital-to-analog converter DAC, thereby converting the grayscale data latched by the output sub-module LC into an analog data voltage VD through the digital-to-analog converter DAC; the operational amplifier OP can power-amplify the analog data voltage VD and load it to the pin, and then load it to the data line DL of the display panel PNL through the pin.

[0140] In one embodiment of the present disclosure, see Figure 19 According to the setting of the pins for outputting the analog data voltage VD, the driver chip DIC can be divided into channel processing units E3 corresponding to the pins one by one. Figure 19Each channel processing unit E3 is used to apply an analog data voltage VD to a corresponding pin. The channel processing unit E3 may include at least one digital-to-analog converter (DAC), an operational amplifier (OP), and multiple latches (L3). The outputs of the multiple latches (L3) are electrically connected to the inputs of the DAC, thereby configuring the DAC so that the DAC outputs the analog data voltage VD. The number of latches (L3) in each channel processing unit E3 is related to the number of bits of grayscale data. Each latch (L3) is used to latch one bit of data. If the grayscale data of a subpixel is 8 bits, then the eight latches (L3) used to latch the grayscale data of the same subpixel belong to the same channel processing unit (E3).

[0141] In one embodiment of the present disclosure, see Figure 19 According to the setting of the latch L3, the driver chip DIC can also be divided into multiple data processing units E2 corresponding to each latch L3. Figure 19 The multiplexing submodule MUX includes a plurality of multiplexing circuits E1 corresponding one-to-one to each latch L3, and each secondary latch group GB has a latch corresponding one-to-one to each latch L3 (for example, latch L21, latch L22, latch L23 and latch L24); the latch corresponding to the latch L3 in the secondary latch group GB is electrically connected to the latch L3 through the multiplexing circuit E1.

[0142] For example, in Figure 19In the example, the cache submodule LB includes a first secondary latch group GB1, a second secondary latch group GB2, a third secondary latch group GB3, and a fourth secondary latch group GB4. In a data processing unit E2, the multiplexing circuit E1 includes a tenth transistor T10 corresponding to the latch L21 in the first secondary latch group GB1, an eleventh transistor T11 corresponding to the latch L22 in the second secondary latch group GB2, a twelfth transistor T12 corresponding to the latch L23 in the third secondary latch group GB3, and a thirteenth transistor T13 corresponding to the latch L24 in the fourth secondary latch group GB4. The output end of the latch L21 is electrically connected to the first electrode of the tenth transistor T10, the output end of the latch L22 is electrically connected to the first electrode of the eleventh transistor T11, the output end of the latch L23 is electrically connected to the first electrode of the twelfth transistor T12, and the output end of the latch L24 is electrically connected to the first electrode of the thirteenth transistor T13. The second electrode of the tenth transistor T10, the second electrode of the eleventh transistor T11, the second electrode of the twelfth transistor T12, and the second electrode of the thirteenth transistor T13 are all electrically connected to the output terminal OUT3 of the multiplexing circuit E1. The output terminal OUT3 of the multiplexing circuit E1 is electrically connected to the input terminal of the latch L3; and the output terminal OUT4 of the latch L3 is electrically connected to the input terminal of the digital-to-analog converter DAC.

[0143] In this way, by controlling the tenth transistor T10 to the thirteenth transistor T13 , the data outputted from the output end of the multiplexing submodule MUX can be controlled.

[0144] In one example, see Figure 15In the first working mode, the first secondary latch group GB1 is used to latch the data row HD. After the cache submodule LB responds to the second enable signal TP2 and latches the data row HD (1) corresponding to the first display unit row into the first secondary latch group GB1, a control signal that enables the tenth transistor T10 can be loaded to the multiplexing submodule MUX, thereby enabling the output end of the first secondary latch group GB1 to be output to the output submodule LC through the multiplexing submodule MUX. During the conduction of the tenth transistor T10, a third enable signal TP3 can be loaded to the output submodule LC, thereby enabling the output submodule LC to latch the data at the output end of the multiplexing submodule MUX, that is, latch the data row HD (1) corresponding to the first display unit row of the first secondary latch group GB1. After the output submodule LC latches the data row HD(1) corresponding to the first display unit row, the digital-to-analog converter DAC generates the analog data voltage VD of each sub-pixel PX of the first display unit row HDU according to the data at the output end of the output submodule LC, and after power amplification by the operational amplifier OP, it is loaded to the data line DL of the display panel PNL through the pin; at this time, the display panel PNL loads a selection signal to the scan line GL(1) of the first display unit row HDU to turn on the switch transistor SW of the first display unit row HDU, thereby making the data line DL electrically connected to the switch transistor SW and the scan line GL coordinated in timing.

[0145] In another example, see Figure 18 In the fourth working mode, the first secondary latch group GB1 to the fourth secondary latch group GB4 are all used to latch the data row HD. After the cache submodule LB responds to the second enable signal TP2 and latches the data row HD(1) corresponding to the first display unit row into the cache submodule LB, the first data group (data D(1,1), data D(2,1), data D(3,1) etc.) latched by the first primary latch group GA1 is latched into the first secondary latch group GB1; the second data group (data D(1,2), data D(2,2), data D(3,2) etc.) latched by the second primary latch group GA2 is latched into the second secondary latch group GB2; the third data group (data D(1,3), data D(2,3), data D(3,3) etc.) latched by the third primary latch group GA3 is latched into the third secondary latch group GB3; the fourth data group (data D(1,4), data D(2,4), data D(3,4) etc.) latched by the fourth primary latch group GA4 is latched into the fourth secondary latch group GB4.

[0146] The first data group of the data row HD(1) corresponding to the first display unit row is the grayscale data of each sub-pixel PX driven by the first scan line GL(1,1) of the first display unit row HDU; the second data group of the data row HD(1) corresponding to the first display unit row is the grayscale data of each sub-pixel PX driven by the second scan line GL(1,2) of the first display unit row HDU; the third data group of the data row HD(1) corresponding to the first display unit row is the grayscale data of each sub-pixel PX driven by the third scan line GL(1,3) of the first display unit row HDU; the fourth data group of the data row HD(1) corresponding to the first display unit row is the grayscale data of each sub-pixel PX driven by the fourth scan line GL(1,4) of the first display unit row HDU.

[0147] In the first phase, a control signal that turns on the tenth transistor T10 can be applied to the multiplexing submodule MUX, thereby causing the output end of the first secondary latch group GB1 to be output to the output submodule LC through the multiplexing submodule MUX. While the tenth transistor T10 is turned on, a third enable signal TP3 can be applied to the output submodule LC, thereby causing the output submodule LC to latch the data at the output end of the multiplexing submodule MUX, that is, latch the first data group of the data row HD(1) corresponding to the first display unit row in the first secondary latch group GB1. After the output submodule LC latches the first data group of the data row HD(1) corresponding to the first display unit row, the digital-to-analog converter DAC generates the analog data voltage VD of each sub-pixel PX driven by the first scan line GL(1,1) of the first display unit row HDU according to the data at the output end of the output submodule LC and mixes it to the data line DL. At the same time, the display panel PNL loads a selection signal to the first scan line GL(1,1) of the first display unit row HDU, thereby driving each sub-pixel PX driven by the first scan line GL(1,1) of the first display unit row HDU.

[0148] In a second phase following the first phase, a control signal may be applied to the multiplexing submodule MUX to enable the eleventh transistor T11, thereby enabling the output end of the second secondary latch group GB2 to be output to the output submodule LC via the multiplexing submodule MUX. While the eleventh transistor T11 is conducting, a third enable signal TP3 may be applied to the output submodule LC, thereby enabling the output submodule LC to latch data at the output end of the multiplexing submodule MUX, i.e., latch the second data group of the data row HD(1) corresponding to the first display cell row in the second secondary latch group GB2. After the output submodule LC latches the second data group of the data row HD(1) corresponding to the first display unit row, the digital-to-analog converter DAC generates the analog data voltage VD of each sub-pixel PX driven by the second scan line GL(1,2) of the first display unit row HDU according to the data at the output end of the output submodule LC and mixes it to the data line DL. At the same time, the display panel PNL loads the selection signal to the second scan line GL(1,2) of the first display unit row HDU, thereby driving each sub-pixel PX driven by the second scan line GL(1,2) of the first display unit row HDU.

[0149] Similarly, in the third stage after the second stage, the twelfth transistor T12 is turned on and the third enable signal TP3 is applied to the output submodule LC, thereby causing the third data group of the data row HD(1) corresponding to the first display unit row to be latched into the output submodule LC. After the output submodule LC latches the third data group of the data row HD(1) corresponding to the first display unit row, the third scan line GL(1,3) of the first display unit row HDU is loaded with a selection signal, thereby driving each subpixel PX driven by the third scan line GL(1,3) of the first display unit row HDU. In the fourth stage after the third stage, the thirteenth transistor T13 is turned on and the third enable signal TP3 is applied to the output submodule LC, thereby causing the fourth data group of the data row HD(1) corresponding to the first display unit row to be latched into the output submodule LC. After the output submodule LC latches the fourth data group of the data row HD(1) corresponding to the first display unit row, the fourth scan line GL(1,4) is loaded with a selection signal, thereby driving each sub-pixel PX driven by the fourth scan line GL(1,4).

[0150] In one embodiment of the present disclosure, see Figure 10 The driver chip DIC is further provided with an output control module TP3D, and the output control module TP3D is used to generate a third enable signal TP3 of the output sub-module LC.

[0151] In an example, the output control module TP3D may simultaneously generate the third enable signal TP3 for each latch of the output sub-module LC, so that each latch simultaneously latches the data at the output end of the multiplexing sub-module MUX.

[0152] In another example, the output control module TP3D can divide the latches of the output sub-module LC into multiple groups and sequentially generate the third enable signal TP3 for each group. For example, the third enable signal TP3 for each group is generated every 10 clock cycles. This can reduce the amount of data latched at a single time by the output sub-module LC, thereby reducing analog noise.

[0153] For example, the latches of the output submodule LC can be divided into eight groups. The output control module TP3D sequentially generates the third enable signal TP3 for each of the eight groups, with the subsequent third enable signal TP3 being delayed by 10 clock cycles compared to the transition third enable signal TP3. Accordingly, the operational amplifier OP is also divided into eight groups based on the division of the latches of the output submodule LC, with the outputs of each group sequentially delayed by 10 clock cycles.

[0154] In one embodiment of the present disclosure, the driver chip DIC further includes a pre-charging module MD (pre-charging module); the pre-charging module MD includes a pre-charging configuration unit UD2 (pre-charging configuration unit) and a comparison unit UD1 (comparison unit);

[0155] The multiplexing submodule MUX is configured to output a new data group in the pre-charging stage;

[0156] The comparison unit UD1 is configured to compare the new data group output by the multiplexing submodule MUX with the current data group output by the output submodule LC during the pre-charging phase, and control the pre-charging configuration unit UD2 according to the comparison result;

[0157] The pre-charge configuration unit UD2 is configured to perform pre-charge control on each operational amplifier OP of the source module DR during the pre-charge phase according to the comparison result;

[0158] The output submodule LC is configured to latch the new data group output by the multiplexing submodule MUX after the pre-charging phase.

[0159] In this way, the driver chip DIC can predict whether the analog data voltage VD loaded on the data line DL is likely to change based on the change trend of the data group latched by the output sub-module LC; when the analog data voltage VD loaded on the data line DL is likely to change, the data line DL is pre-charged by driving the operational amplifier OP of the data line DL, thereby avoiding the problem of insufficient charging rate caused by insufficient voltage on the data line DL, thereby improving the display quality of the display panel PNL.

[0160] In one embodiment of the present disclosure, see Figure 19 The comparison unit UD1 includes a comparison circuit D1 corresponding to each latch L3, and the precharge configuration unit UD2 includes a precharge configuration circuit D2 corresponding to each latch L3. Thus, each data processing unit E2 also includes a comparison circuit D1 and a precharge configuration circuit D2. The comparison circuit D1 is electrically connected to a precharge control signal terminal for loading the precharge control signal STB, an output terminal OUT3 of the multiplexing circuit E1, and an output terminal OUT4 of the latch L3. The comparison circuit D1 can determine whether to output the precharge control signal STB to the precharge configuration circuit D2 based on whether the data at the output terminal OUT3 of the multiplexing circuit E1 and the output terminal OUT4 of the latch L3 are consistent.

[0161] See also Figure 20 The precharge control signal STB includes a precharge control level corresponding to each precharge stage (in Figure 20 In the example, the level is high), and the duration of the pre-charge control level exceeds the pre-charge stage. In the pre-charge stage, the multiplexing submodule MUX can first load a control signal (for example, a control signal that turns on any one of the tenth transistor T10 to the thirteenth transistor T13). Figure 20 The output terminal of a secondary latch group GB is electrically connected to the output terminal of the multiplexing sub-module MUX via the multiplexing sub-module MUX. At this time, the data group latched by the secondary latch group GB is a new data group to be latched into the output sub-module LC. During this pre-charging phase, the third enable signal TP3 is not applied to the output sub-module LC. Therefore, the output sub-module LC does not latch the new data group but continues to output the old data group.

[0162] In one example, during the precharge phase, for any data processing unit E2, the comparison circuit D1 can perform an exclusive OR operation based on the level of the output terminal OUT3 of the multiplexing circuit E1 and the level of the output terminal OUT4 of the latch L3, and then perform an AND operation based on the result of the operation and the precharge control signal STB. The comparison circuit D1 can determine that the data output by the multiplexing circuit E1 is the same as the data output by the latch L3 when the level of the output terminal OUT3 of the multiplexing circuit E1 and the level of the output terminal OUT4 of the latch L3 are both high or low, and in this case, the comparison circuit D1 does not apply the precharge control signal STB to the precharge configuration circuit D2. The comparison circuit D1 can determine that the data output by the multiplexing circuit E1 is different from the data output by the latch L3 when the level of the output terminal OUT3 of the multiplexing circuit E1 and the level of the output terminal OUT4 of the latch L3 are different, for example, when one is high and the other is low, and in this case, the comparison circuit D1 applies the precharge control signal STB to the precharge configuration circuit D2.

[0163] In the channel processing unit E3, when any pre-charge configuration circuit D2 loads the pre-charge control signal STB, the pre-charge configuration circuit D2 can load a reference potential to the operational amplifier OP so that the operational amplifier OP pre-charges the pin and the data line DL connected thereto, thereby improving the accuracy of the analog data voltage VD on the data line DL when the next data group is driven.

[0164] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A driver chip, characterized in that: It includes a latch module and a source module; the latch module includes a receiving submodule, a buffer submodule and an output submodule; The receiving submodule includes a plurality of primary latch groups, and the receiving submodule is used to latch a data row; each of the primary latch groups is configured to latch a data group, and the data row includes at least one of the data groups; The cache submodule includes a plurality of secondary latch groups corresponding one-to-one to each of the primary latch groups; The secondary latch group is configured to latch the data latched by the corresponding primary latch group in response to a second enable signal; The output submodule is used to latch each of the data groups in the secondary latch group one by one; The source module is configured to output analog data voltages of respective sub-pixels corresponding to the data group according to the data group output by the output sub-module.

2. The driver chip according to claim 1, wherein: The receiving submodule includes a plurality of latch units, and any one of the latch units includes a plurality of latch subunits corresponding one-to-one to each of the first-level latch groups; wherein any one of the first-level latch groups has a corresponding latch subunit in any one of the latch units; and input ends of the latches of the same latch subunit are connected to each other; The driver chip further includes a scanning circuit corresponding to each of the latch sub-units one by one, and the scanning circuit is used to sequentially generate a first enable signal for each of the latches in the corresponding latch sub-units.

3. The driver chip according to claim 2, wherein: The driver chip includes a write control module, and the write control module includes a plurality of receiving control units corresponding to each of the latch units one by one; The receiving control unit includes a plurality of scanning circuits corresponding one-to-one to each of the latch sub-units in the corresponding latch unit, and a scanning control circuit; The scan control circuit is configured to determine the cascade state between the scan circuits in the same receiving control unit and the cascade state between the scan circuits of adjacent receiving control units according to the scan configuration signal.

4. The driver chip according to claim 3, characterized in that: The latch unit includes a first latch subunit, a second latch subunit, a third latch subunit, and a fourth latch subunit; the receiving control unit includes a first scanning circuit corresponding to the first latch subunit, a second scanning circuit corresponding to the second latch subunit, a third scanning circuit corresponding to the third latch subunit, and a fourth scanning circuit corresponding to the fourth latch subunit; the scanning control circuit includes first to seventh transistors; The receiving control unit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; in two adjacent receiving control units, the first output terminal of the previous receiving control unit is electrically connected to the first input terminal of the next receiving control unit, and the second output terminal of the previous receiving control unit is electrically connected to the second input terminal of the next receiving control unit; In which, in the same receiving control unit, the cascade input end of the first scanning circuit is electrically connected to the first input end; the cascade output end of the first scanning circuit, the cascade input end of the third scanning circuit, and the first pole of the first transistor are electrically connected to each other; the cascade output end of the third scanning circuit, the second pole of the first transistor, the first pole of the fourth transistor, and the first pole of the seventh transistor are electrically connected to each other; the second pole of the fourth transistor, the second pole of the sixth transistor are electrically connected to the first output end; the cascade input end of the second scanning circuit, the first pole of the second transistor are electrically connected to the second input end; the cascade output end of the second scanning circuit, the cascade input end of the fourth scanning circuit, the second pole of the second transistor, and the first pole of the third transistor are electrically connected to each other; the cascade output end of the fourth scanning circuit, the second pole of the third transistor, the first pole of the fifth transistor, and the first pole of the sixth transistor are electrically connected to each other; the second pole of the seventh transistor, the second pole of the fifth transistor are electrically connected to the second output end.

5. The driver chip according to claim 4, characterized in that: The scan control circuit is configured to be capable of assuming a first operating mode according to a first scan configuration signal, configured to be capable of assuming a second operating mode according to a second scan configuration signal, configured to be capable of assuming a third operating mode according to a third scan configuration signal, and configured to be capable of assuming a fourth operating mode according to a fourth scan configuration signal; In the first operating mode, the first transistor, the second transistor, the third transistor, the sixth transistor and the seventh transistor are in an on state, and the fourth transistor and the fifth transistor are in an off state; In the second operating mode, the first transistor, the third transistor, the fourth transistor, and the fifth transistor are in an on state, and the second transistor, the sixth transistor, and the seventh transistor are in an off state; In the third operating mode, the third transistor, the sixth transistor, and the seventh transistor are in an on state, and the first transistor, the second transistor, the fourth transistor, and the fifth transistor are in an off state; In the fourth operation mode, the first transistor, the second transistor, the third transistor, the sixth transistor, and the seventh transistor are in an off state, and the fourth transistor and the fifth transistor are in an on state.

6. The driver chip according to claim 3, wherein: The driver chip is provided with one or more data write lines; the latch sub-unit further includes a selection sub-circuit corresponding to each latch sub-unit one by one, and the input end of each latch of the latch sub-unit is electrically connected to each data write line through the corresponding selection sub-circuit; the selection sub-circuit is configured to be able to electrically connect the input end of each latch of the latch sub-unit to at most one data write line according to a selection configuration signal.

7. The driver chip according to any one of claims 1 to 6, characterized in that: The latch module further includes a buffer control module, the buffer control module being configured to generate a second enable signal for each latch of the cache submodule; The buffer control module is configured to simultaneously generate the second enable signal for each latch of the cache submodule, or to generate the second enable signal for a portion of the latches of the cache submodule each time.

8. The driver chip according to any one of claims 1 to 6, characterized in that: The latch module further includes a multiplexing submodule, and the output end of each of the secondary latch groups is electrically connected to the input end of the output submodule through the multiplexing submodule; The multiplexing submodule is configured to connect the input end of the output submodule to one of the output ends of the plurality of secondary latch groups.

9. The driver chip according to claim 8, characterized in that: The driver chip further includes a pre-charging module; the pre-charging module includes a pre-charging configuration unit and a comparison unit; The multiplexing submodule is configured to output a new data group during the pre-charging phase; The comparison unit is configured to compare the new data group output by the multiplexing submodule with the current data group output by the output submodule during the pre-charging phase, and control the pre-charging configuration unit according to the comparison result; The pre-charging configuration unit is configured to perform pre-charging control on each operational amplifier of the source module in the pre-charging phase according to the comparison result; The output submodule is configured to latch a new data group output by the multiplexing submodule after the pre-charging phase.

10. A display device, characterized in that: The device comprises the driver chip and the display panel according to any one of claims 1 to 9.

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