Display device

Abstract

A display device includes a first scan driver, a light emission driver, and a plurality of pixels, the plurality of pixels receiving a plurality of data voltages in response to a plurality of first scan signals at a turn-on level, and being in a non-emission state in response to a plurality of light emission signals applied at a turn-off level. The light emitting driver includes a plurality of light emitting stages. During a plurality of first scan periods, the plurality of light emitting stages sequentially generate a plurality of light emitting signals of an off level in units of one light emitting stage, and during a plurality of second scan periods, the plurality of light emitting stages sequentially generate a plurality of light emitting signals of an off level in units of m light emitting stages, where m is an integer greater than 1.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0029966, filed on February 29, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to display devices, and more particularly, to a display device having low power consumption performance. Background Art

[0004] In recent years, modern display devices such as liquid crystal display (LCD) devices and organic light emitting diode (OLED) display devices have significantly improved in terms of resolution, display quality, and functionality.

[0005] As the configurations of display devices have become more diverse and complex (eg, with higher resolution and circuit complexity to produce clearer and more realistic images), the power consumption required to support advanced display devices has increased. Summary of the Invention

[0006] An aspect of the present disclosure is to provide a display device capable of reducing power consumption.

[0007] A display device according to an embodiment of the present disclosure includes: a first scan driver configured to transmit a plurality of first scan signals at an on-level during a plurality of first scan periods and maintain the plurality of first scan signals at an off-level during a plurality of second scan periods; a light emitting driver configured to transmit a plurality of light emitting signals at an off-level during the plurality of first scan periods to overlap with the plurality of first scan signals at the on-level, and transmit the plurality of light emitting signals at the off-level during the plurality of second scan periods; and a plurality of pixels configured to receive a plurality of data voltages in response to the plurality of first scan signals at the on-level and to be in a non-emitting state in response to the plurality of light emitting signals at the off-level. The light emitting driver includes a plurality of light emitting stages. During the plurality of first scan periods, the plurality of light emitting stages sequentially generate the plurality of light emitting signals at the off-level in units of one light emitting stage, and during the plurality of second scan periods, the plurality of light emitting stages sequentially generate the plurality of light emitting signals at the off-level in units of m light emitting stages, where m is an integer greater than 1.

[0008] In various embodiments:

[0009] The m may be a multiple of 2.

[0010] The light-emitting driver can be connected to multiple light-emitting clock lines, which include a first light-emitting clock line, a second light-emitting clock line, a third light-emitting clock line and a fourth light-emitting clock line. Each of the multiple light-emitting stages may include: a first input terminal, which receives a light-emitting signal at the cut-off level output from another light-emitting stage among the multiple light-emitting stages; a second input terminal, which is connected to one light-emitting clock line among the first light-emitting clock line, the second light-emitting clock line, the third light-emitting clock line and the fourth light-emitting clock line; a third input terminal, which is connected to another light-emitting clock line among the first light-emitting clock line, the second light-emitting clock line, the third light-emitting clock line and the fourth light-emitting clock line; and an output terminal, which outputs the light-emitting signal at the cut-off level during a portion of each of the multiple first scanning cycles and the multiple second scanning cycles, and two light-emitting stages adjacent to each other among the multiple light-emitting stages can be connected to different light-emitting clock lines among the first light-emitting clock line, the second light-emitting clock line, the third light-emitting clock line and the fourth light-emitting clock line.

[0011] The light-emitting driver includes a first light-emitting stage group and a second light-emitting stage group. The first light-emitting stage group may include m light-emitting stages, the second light-emitting stage group adjacent to the first light-emitting stage group may include m different light-emitting stages, and a structure in which the second light-emitting stage group is connected to the plurality of light-emitting clock lines may be mirror-symmetrical to a structure in which the first light-emitting stage group is connected to the plurality of light-emitting clock lines.

[0012] The m-1th light-emitting stage of the first light-emitting stage group may have a second input terminal connected to the first light-emitting clock line and a third input terminal connected to the second light-emitting clock line, the mth light-emitting stage of the first light-emitting stage group may have a second input terminal connected to the third light-emitting clock line and a third input terminal connected to the fourth light-emitting clock line, the first light-emitting stage of the second light-emitting stage group may have a second input terminal connected to the fourth light-emitting clock line and a third input terminal connected to the third light-emitting clock line, and the second light-emitting stage of the second light-emitting stage group may have a second input terminal connected to the second light-emitting clock line and a third input terminal connected to the first light-emitting clock line.

[0013] The frequencies of the plurality of light emitting clock signals applied to the plurality of light emitting clock lines during the plurality of first scan periods may be m times the frequencies of the plurality of light emitting clock signals applied to the plurality of light emitting clock lines during the plurality of second scan periods.

[0014] During the multiple first scanning cycles, the first lighting clock signal applied to the first lighting clock line may be the same as the fourth lighting clock signal applied to the fourth lighting clock line, and the second lighting clock signal applied to the second lighting clock line may be the same as the third lighting clock signal applied to the third lighting clock line, and during the multiple second scanning cycles, the first lighting clock signal may be the same as the third lighting clock signal, and the second lighting clock signal may be the same as the fourth lighting clock signal.

[0015] The light-emitting driver may further include a light-emitting level connection circuit, which receives an enable signal during the multiple first scanning periods and a disable signal during the multiple second scanning periods. When the enable signal is received, the light-emitting level connection circuit can connect each of the multiple first input terminals of the multiple light-emitting levels to the output terminal of the corresponding previous light-emitting level, and when the disable signal is received, the light-emitting level connection circuit can connect each of the multiple first input terminals of the multiple light-emitting levels to the output terminal of the corresponding previous light-emitting level group.

[0016] The light-emitting level connection circuit may include: a plurality of first connection transistors, which are turned on when receiving the enable signal, and each of the plurality of first connection transistors connects a corresponding one of the plurality of first input terminals of the plurality of light-emitting levels to the output terminal of the corresponding previous light-emitting level; and a plurality of second connection transistors, which are turned on when receiving the disable signal, and each of the plurality of second connection transistors connects a corresponding one of the plurality of first input terminals of the plurality of light-emitting levels to the output terminal of the corresponding previous light-emitting level group.

[0017] Each of the plurality of first connection transistors may be one of a P-type transistor and an N-type transistor, each of the plurality of second connection transistors may be the other of a P-type transistor and an N-type transistor, the plurality of gate electrodes of the plurality of first connection transistors and the plurality of gate electrodes of the plurality of second connection transistors may be commonly connected to an enable line, the enable signal and the disable signal may be applied to the enable line, the enable signal may be a signal of a polarity that turns on the plurality of first connection transistors, and the disable signal may be a signal of an opposite polarity that turns on the plurality of second connection transistors.

[0018] According to an embodiment of the present disclosure, a display device includes: a first scan driver that sends a first scan signal at an on-level during a first scan cycle, and the first scan driver maintains the first scan signal at an off-level during a second scan cycle; a second scan driver that sends a second scan signal at an on-level during the first scan cycle, and the second scan driver sends the second scan signal at the on-level during the second scan cycle; and a pixel that receives a data voltage in response to the first scan signal at the on-level, and the pixel initializes the anode voltage of the light-emitting element in response to the second scan signal at the on-level, wherein the second scan driver includes a plurality of scan levels, and during the first scan cycle, the scan level sequentially generates the second scan signal at the on-level in units of one scan level, and during the second scan cycle, the scan level sequentially generates the second scan signal at the on-level in units of m scan levels, wherein m is an integer greater than 1.

[0019] The m may be a multiple of 2.

[0020] The second scan driver can be connected to a first scan clock line, a second scan clock line, a third scan clock line and a fourth scan clock line, and each of the scan levels can include: a first input terminal, receiving a second scan signal at the conduction level output from another scan level; a second input terminal, connected to one of the first scan clock line, the second scan clock line, the third scan clock line and the fourth scan clock line; a third input terminal, connected to another scan clock line of the first scan clock line, the second scan clock line, the third scan clock line and the fourth scan clock line; and an output terminal, outputting the second scan signal at the conduction level, and two scan levels adjacent to each other can be connected to different scan clock lines.

[0021] The m-1th scanning stage of the first scanning stage group may have a second input terminal connected to the first scanning clock line and a third input terminal connected to the second scanning clock line, the mth scanning stage of the first scanning stage group may have a second input terminal connected to the third scanning clock line and a third input terminal connected to the fourth scanning clock line, the first scanning stage of the second scanning stage group may have a second input terminal connected to the fourth scanning clock line and a third input terminal connected to the third scanning clock line, and the second scanning stage of the second scanning stage group may have a second input terminal connected to the second scanning clock line and a third input terminal connected to the first scanning clock line.

[0022] A frequency of a scan clock signal applied to the scan clock line during the first scan period may be m times a frequency of the scan clock signal applied to the scan clock line during the second scan period.

[0023] During the first scan cycle, the first scan clock signal applied to the first scan clock line may be the same as the fourth scan clock signal applied to the fourth scan clock line, and the second scan clock signal applied to the second scan clock line may be the same as the third scan clock signal applied to the third scan clock line, and during the second scan cycle, the first scan clock signal may be the same as the third scan clock signal, and the second scan clock signal may be the same as the fourth scan clock signal.

[0024] The second scan driver can be connected to a first scan clock line, a second scan clock line, a third scan clock line and a fourth scan clock line, and each of the scan stages may include: a first input terminal, receiving a second scan signal at the conduction level output from another scan stage; a second input terminal, connected to one of the first scan clock line, the second scan clock line, the third scan clock line and the fourth scan clock line; and an output terminal, outputting the second scan signal at the conduction level, and two scan stages adjacent to each other can be connected to different scan clock lines.

[0025] The m-1th scanning stage of the first scanning stage group may have a second input terminal connected to the first scanning clock line, the mth scanning stage of the first scanning stage group may have a second input terminal connected to the third scanning clock line, the first scanning stage of the second scanning stage group may have a second input terminal connected to the fourth scanning clock line, and the second scanning stage of the second scanning stage group may have a second input terminal connected to the second scanning clock line.

[0026] The second scan driver may further include a scan level connection circuit, which receives an enable signal during the first scan period and a disable signal during the second scan period. When the enable signal is received, the scan level connection circuit may connect each of the first input terminals of the scan level to the output terminal of the previous scan level, and when the disable signal is received, the scan level connection circuit may connect each of the first input terminals of the scan level to the output terminal of the previous scan level group.

[0027] The scanning stage connection circuit may include: a first connection transistor, which is turned on when receiving the enable signal and connects each of the first input terminals of the scanning stage to the output terminal of the previous scanning stage; and a second connection transistor, which is turned on when receiving the disable signal and connects each of the first input terminals of the scanning stage to the output terminal of the previous scanning stage group.

[0028] In an embodiment, a display device may include: a scan driver configured to transmit a scan signal at an on-level during corresponding portions of a first scan cycle and to provide the scan signal at an off-level during each of a second scan cycle; a light emitting driver configured to transmit a light emitting signal at an off-level during a time period overlapping with a time period during which the scan signal is at the on-level during the first scan cycle and to transmit the light emitting signal at the off-level during the second scan cycle; and a pixel configured to receive a data voltage in response to the scan signal at the on-level and to be in a non-emitting state in response to the light emitting signal at the off-level. The light emitting driver includes a plurality of light emitting stages. During the first scan cycle, the light emitting stages sequentially generate the light emitting signal at the off-level in units of one light emitting stage, and during the second scan cycle, the light emitting stages sequentially generate the light emitting signal at the off-level in units of m light emitting stages, where m is an integer greater than 1.

[0029] The display device according to the present disclosure may operate with reduced power consumption relative to conventional displays. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic diagram illustrating a display device according to an embodiment of the present disclosure.

[0031] Figure 2 is a schematic diagram illustrating a pixel according to an embodiment of the present disclosure.

[0032] Figure 3 is a timing diagram illustrating a method of changing a display frequency according to an embodiment of the present disclosure.

[0033] Figure 4 is a signal / timing diagram illustrating a first scanning period according to an embodiment of the present disclosure.

[0034] Figure 5 is a signal / timing diagram illustrating a second scanning period according to an embodiment of the present disclosure.

[0035] Figure 6 is a signal / timing diagram illustrating a first scanning period and a second scanning period according to another embodiment of the present disclosure.

[0036] Figure 7 is a schematic diagram illustrating a light emitting driver according to an embodiment of the present disclosure.

[0037] Figure 8 is a schematic diagram illustrating light emission levels according to an embodiment of the present disclosure.

[0038] Figure 9 It shows Figure 8 Signal / timing diagram of the driving method of the light-emitting stage.

[0039] Figure 10 It is shown by Figure 8 Signal / timing diagram of a driving method of a light-emitting driver composed of a light-emitting level.

[0040] Figure 11 is a schematic diagram illustrating light emission levels according to another embodiment of the present disclosure.

[0041] Figure 12 It shows Figure 11 Signal / timing diagram of the driving method of the light-emitting stage.

[0042] Figure 13 It is shown by Figure 11 Signal / timing diagram of a driving method of a light-emitting driver composed of a light-emitting level.

[0043] Figure 14 is a schematic diagram illustrating a second scan driver according to an embodiment of the present disclosure.

[0044] Figure 15 is a schematic diagram illustrating a scanning stage according to an embodiment of the present disclosure.

[0045] Figure 16 It shows Figure 15 Signal / timing diagram of the scanning stage driving method.

[0046] Figure 17 It is shown by Figure 15 Signal / timing diagram of a driving method of a second scan driver composed of a scan stage.

[0047] Figure 18 is a schematic diagram illustrating a second scan driver according to another embodiment of the present disclosure.

[0048] Figure 19 is a schematic diagram illustrating a scanning stage according to another embodiment of the present disclosure.

[0049] Figure 20 It shows Figure 19 Signal / timing diagram of the scanning stage driving method. DETAILED DESCRIPTION

[0050] Hereinafter, with reference to the accompanying drawings, various embodiments of the present disclosure will be described in detail so that those skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein.

[0051] In order to clearly illustrate the present disclosure, descriptions of known components that are not related to the novel aspects of the present disclosure may be omitted or briefly discussed. Throughout the specification, the same reference numerals are given to the same or similar constituent elements.

[0052] In addition, for better understanding and ease of description, the size and thickness of each configuration shown in the drawings may be arbitrarily shown, and the present disclosure is not limited to the embodiments shown. In the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration.

[0053] In addition, the expression “same” in the specification may mean “substantially the same.” For example, it may mean the same degree that a person with ordinary knowledge would understand as the same.

[0054] In the following description, various components of the same or similar type (e.g., scan stage GBT) may be distinguished by appending a second label (e.g., n1 for describing scan stage GBTn1) to the reference label (e.g., scan stage GBT). However, if a given description uses only the first reference label (e.g., scan stage GBT), it applies to any of the same / similar components having the same first reference label, regardless of the second label.

[0055] Figure 1 1 is a schematic diagram showing a display device 10 according to an embodiment of the present disclosure. Figure 1 The display device 10 may include a timing controller 11 , a data driver 12 , a scan driver 13 , a pixel unit 14 and a light emitting driver 15 .

[0056] The timing controller 11 may receive grayscales for an input image (or input frame). The grayscales may include a first color grayscale, a second color grayscale, and a third color grayscale. The first color grayscale, the second color grayscale, and the third color grayscale may be grayscales for representing a first color, a second color, and a third color, respectively.

[0057] In addition, the timing controller 11 can receive control signals for the image. These control signals may include a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync) and a data enable signal. The vertical synchronization signal may include multiple pulses and may indicate the end of the previous frame period and the beginning of the current frame period based on the time when each pulse occurs. The interval between adjacent pulses in the vertical synchronization signal may correspond to one frame period. The horizontal synchronization signal may include multiple pulses and may indicate the end of the previous horizontal period and the beginning of a new horizontal period based on the time when each pulse occurs. The interval between adjacent pulses of the horizontal synchronization signal may correspond to one horizontal period. The data enable signal may have an enable level for a specific horizontal period and a disable level for the remaining periods. When the data enable signal is at the enable level, it may indicate that a color grayscale is supplied in the corresponding horizontal period.

[0058] The timing controller 11 may provide the data driver 12 with a grayscale rendered or corrected to meet the specifications of the display device 10. In addition, the timing controller 11 may provide a clock signal, a scan start signal, etc. to the scan driver 13. The timing controller 11 may provide a clock signal, a light emission stop signal, etc. to the light emission driver 15.

[0059] The data driver 12 may generate data voltages to be supplied to the data lines DL1, ..., DLj, ..., and DLq using the grayscale levels and control signals received from the timing controller 11. For example, the data driver 12 may sample the grayscale levels using a clock signal and apply data voltages corresponding to the grayscale levels to the data lines DL1, ..., DLj, ..., and DLq in units of pixel rows. q may be an integer greater than or equal to 1, and j may be an integer greater than 0 and less than or equal to q.

[0060] The scan driver 13 may include a first scan driver 13GW, a second scan driver 13GB, a third scan driver 13GI, and a fourth scan driver 13GC. The first scan driver 13GW may provide a first scan signal to the first scan lines GW1, ..., GWi, ..., and GWp. p may be an integer greater than or equal to 1, and i may be an integer greater than 0 and less than or equal to p. The second scan driver 13GB may provide a second scan signal to the second scan lines GB1, ..., GBi, ..., and GBp. The third scan driver 13GI may provide a third scan signal to the third scan lines GI1, ..., GIi, ..., and GIp. The fourth scan driver 13GC may provide a fourth scan signal to the fourth scan lines GC1, ..., GCi, ..., and GCp.

[0061] For example, the first scan driver 13GW may receive at least one scan clock signal and a scan start signal from the timing controller 11, and based on these signals, may generate a first scan signal to be provided to the first scan lines GW1 to GWp. The first scan driver 13GW may sequentially provide a first scan signal having an on-level pulse to the first scan lines GW1 to GWp. For example, the first scan driver 13GW may be configured in the form of a shift register, and may generate the first scan signal in such a manner that a scan start signal is sequentially transmitted to the next scan stage under the control of the scan clock signal, and the scan start signal may be a pulse having an on-level ("on-level pulse").

[0062] Each of the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC may be configured similarly to the first scan driver 13GW, and thus repeated descriptions will be omitted. According to an embodiment, at least some of the first scan driver 13GW, the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC may be integrated. For example, when the polarity and width of the pulses are the same, two or more scan drivers may be integrated. For example, referring temporarily to FIG. Figure 4 , because the polarity and width of the on-level pulse applied to the third scan line GIi at time (time point) t2a are the same as the polarity and width of the on-level pulse applied to the fourth scan line GCi at time t3a, the third scan driver 13GI and the fourth scan driver 13GC can be integrated.

[0063] The light-emitting driver 15 can receive at least one light-emitting clock signal and a light-emitting stop signal from the timing controller 11, and can generate light-emitting signals to be provided to the light-emitting lines EM1, ..., EMi, ..., and EMp. The light-emitting driver 15 can sequentially provide light-emitting signals having "off-level pulses" to the light-emitting lines EM1 to EMp. For example, the light-emitting driver 15 can be configured in the form of a shift register, and can generate light-emitting signals in a manner such that the light-emitting stop signal including the off-level pulse is sequentially transmitted to the next light-emitting stage according to the control of the light-emitting clock signal.

[0064] exist Figure 1, the number of each of the first scan lines GW1 to GWp, the second scan lines GB1 to GBp, the third scan lines GI1 to GIp, the fourth scan lines GC1 to GCp, and the emission lines EM1 to EMp is shown as p. In another embodiment, the number of at least one of the second scan lines GB1 to GBp, the third scan lines GI1 to GIp, the fourth scan lines GC1 to GCp, and the emission lines EM1 to EMp is p / 2 or less. For example, two adjacent pixel rows may share one second scan line. Similarly, two adjacent pixel rows may share one third scan line, fourth scan line, or emission line. The same pixel row refers to pixels connected to the same first scan line. Hereinafter, for ease of description, as an example, each of the first scan lines GW1 to GWp, the second scan lines GB1 to GBp, the third scan lines GI1 to GIp, the fourth scan lines GC1 to GCp, and the emission lines EM1 to EMp will be described as consisting of p lines.

[0065] Pixel unit 14 includes a plurality of pixels. Pixel PXij, located in the i-th pixel row and j-th pixel column, can be connected to corresponding data line DLj, scan lines GWi, GBi, GIi, and GCi, and emission line EMi. Pixel unit 14 can include a first pixel that emits light of a first color, a second pixel that emits light of a second color, and a third pixel that emits light of a third color. Examples of the first to third colors may be red, green, and blue; or magenta, cyan, and yellow.

[0066] The pixel unit 14 may have a pattern such as diamond RGB-Striped, S-Striped, Real RGB, and Regular Pixels arranged in any of various shapes, etc.

[0067] Figure 2 is a schematic diagram illustrating a pixel PXij according to an embodiment of the present disclosure. In various schematic diagrams herein including field effect transistors (FETs), a FET with a circle at its gate may be a P-type FET, and a FET without a circle at its gate may be an N-type FET.

[0068] refer to Figure 2 , the pixel PXij may include a pixel circuit PXC and a light-emitting element LD. The pixel circuit PXC may include a storage capacitor Cst, a holding capacitor Chold, and transistors T1-T8, wherein transistors T3 and T4 are N-type transistors, and transistors T1, T2, and T5-T8 are P-type transistors. In other embodiments, the holding capacitor Chold is omitted.

[0069] The pixel PXij may be disposed in an i-th pixel row and a j-th pixel column. The pixel PXij may be an example of any of first to third pixels for expressing first to third colors, respectively.

[0070] In this embodiment, the P-type transistor may be a polycrystalline silicon semiconductor transistor. In a polycrystalline silicon semiconductor transistor, the channel of the active layer may include a polycrystalline silicon semiconductor. For example, the polycrystalline silicon semiconductor transistor may be a low-temperature polycrystalline silicon (LTPS) thin film transistor. The polycrystalline silicon semiconductor transistor has high electron mobility and therefore has fast driving characteristics.

[0071] In this embodiment, the N-type transistor may be an oxide semiconductor transistor. In the oxide semiconductor transistor, the channel of the active layer may include an oxide semiconductor. For example, the oxide semiconductor transistor may be a low-temperature polycrystalline oxide (LTPO) thin film transistor. The oxide semiconductor transistor has a lower charge mobility than the polycrystalline silicon semiconductor transistor. Therefore, the amount of leakage current generated in the off state of the oxide semiconductor transistor may be less than the amount of leakage current generated in the off state of the polycrystalline silicon semiconductor transistor.

[0072] The first transistor T1 may include a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The first transistor T1 may be a driving transistor.

[0073] The second transistor T2 may have a gate electrode connected to the first scan line GWi, a first electrode connected to the data line DLj, and a second electrode connected to the second node N2. The second transistor T2 may be a scan transistor.

[0074] The third transistor T3 may have a gate electrode connected to the fourth scan line GCi, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The third transistor T3 may be a "diode-connected" transistor. This is because when the third transistor T3 is turned on, the transistor T1 becomes a transistor connected in a diode manner.

[0075] The fourth transistor T4 has a gate electrode connected to the third scan line GIi, a first electrode connected to the first node N1, and a second electrode receiving the first initialization voltage VINT. The fourth transistor T4 may be a gate initialization transistor. The fourth transistor T4 may be an N-type transistor.

[0076] The fifth transistor T5 may have a gate electrode connected to the emission line EMi, a first electrode receiving the first power voltage ELVDD, and a second electrode connected to the second node N2. The fifth transistor T5 may be a first emission control transistor. The fifth transistor T5 may be a P-type transistor.

[0077] The sixth transistor T6 may have a gate electrode connected to the emission line EMi, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The sixth transistor T6 may be a second emission control transistor. The sixth transistor T6 may be a P-type transistor.

[0078] The seventh transistor T7 may have a gate electrode connected to the second scan line GBi, a first electrode receiving the second initialization voltage VAINT, and a second electrode connected to the fourth node N4. The seventh transistor T7 may be an anode initialization transistor. The seventh transistor T7 may be a P-type transistor.

[0079] The eighth transistor T8 may have a gate electrode connected to the second scan line GBi, a first electrode receiving the bias voltage VOBS, and a second electrode connected to the second node N2. The eighth transistor T8 may be a P-type transistor.

[0080] The storage capacitor Cst may have a first electrode receiving the first power voltage ELVDD and a second electrode connected to the first node N1.

[0081] A first electrode of the holding capacitor Chold may receive the first power supply voltage ELVDD, and a second electrode of the holding capacitor Chold may be connected to the second node N2 .

[0082] The anode of the light-emitting element LD can be connected to the fourth node N4, and the cathode of the light-emitting element LD can receive the second power supply voltage ELVSS. The light-emitting element LD can emit light in one of the first color, the second color, and the third color. The light-emitting element LD can be a light-emitting diode. The light-emitting element LD can include an organic light-emitting diode, an inorganic light-emitting diode, or a quantum dot / well light-emitting diode, etc. In this embodiment, each pixel can include only one light-emitting element LD, but in other embodiments, each pixel can include multiple light-emitting elements. In this case, the multiple light-emitting elements can be connected in series, in parallel, or in series and parallel.

[0083] Figure 3 is a timing diagram illustrating a method of changing a display frequency according to an embodiment of the present disclosure.

[0084] refer to Figure 3 , also refer to Figure 1 , the display device 10 can use the first scanning period DISPLAY SCAN and the second scanning period SELF SCAN to change the display frequency.

[0085] The first scanning period DISPLAY SCAN may be a period during which the pixels of the pixel unit 14 receive data voltages. Therefore, when a new first scanning period DISPLAY SCAN begins, the image frame displayed by the pixel unit 14 may change. Therefore, the cycle period of the first scanning period DISPLAY SCAN may be the same as the display frequency. For example, during the first scanning period DISPLAY SCAN, the first scan driver 13GW, the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC may send a scanning signal at an on-level. In addition, during the first scanning period DISPLAY SCAN, the light emitting driver 15 may send a light emitting signal at an off-level to overlap with the first scanning signal at an on-level (see Figure 4 ).

[0086] The second scanning period SELF SCAN may be a period in which the pixels of the pixel unit 14 do not receive the data voltage. For example, during the second scanning period SELF SCAN, the first scanning driver 13GW, the third scanning driver 13GI, and the fourth scanning driver 13GC may maintain the scanning signal at the off level. At the same time, during the second scanning period SELF SCAN, the second scanning driver 13GB may transmit the second scanning signal at the on level, and the light emitting driver 15 may transmit the light emitting signal at the off level (see FIG. Figure 5 ).

[0087] exist Figure 3 , a case where one first scanning period DISPLAY SCAN is approximately 1 / 120 second is shown. In this case, when the first scanning period DISPLAY SCAN is repeated without the second scanning period SELF SCAN, the display device 10 can display an image at a display frequency of 120 Hz. As the number of second scanning periods SELF SCAN provided between adjacent first scanning periods DISPLAY SCAN increases, the display frequency can be reduced.

[0088] Figure 4 1 is a signal / timing diagram illustrating the first scanning cycle DISPLAY SCAN 1 according to an embodiment of the present disclosure. Figure 4 When, refer to Figure 2 Pixel PXij.

[0089] refer to Figure 4 , also refer to Figure 2 At time t1a, a light emitting signal at a turn-off level (high level) may be applied to the light emitting line EMi, so that the fifth transistor T5 and the sixth transistor T6 may be turned off, and the pixel PXij may be in a non-emission state.

[0090] At time t2a, a third scan signal at an on-level (high level) is applied to the third scan line GIi, so that the fourth transistor T4 is turned on. Thus, a first initialization voltage VINT is applied to the first node N1. The first initialization voltage VINT may be a sufficiently low voltage, and thus the first transistor T1 may be biased to an on-state (hereinafter, "on-bias state").

[0091] At time t3a, a fourth scan signal at a turn-on level (high level) may be applied to the fourth scan line GCi, so that the third transistor T3 may be turned on. Therefore, the first transistor T1 may be in a diode-connected state in which the drain electrode and the gate electrode are connected.

[0092] At time t4a, a scan signal at a turn-on level (low level) may be applied to the first scan line GWi, so that the second transistor T2 may be turned on. Therefore, the data voltage of the data line DLj may be applied to the first node N1 through the turned-on second transistor T2, the first transistor T1, and the third transistor T3. (Note that as Figure 4 As shown in FIG, the time period during which the first scan line GWi is at the on level starting at time t4a may be a small portion of the entire first scan period DISPLAY SCAN 1. At this time, the voltage of the first node N1 may be a compensation voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage. The storage capacitor Cst may maintain a voltage difference between the first power voltage ELVDD and the compensation voltage.

[0093] At time t5a, a scan signal at an on-level (low level) may be applied to the second scan line GBi, turning on the seventh transistor T7 and the eighth transistor T8. Since the seventh transistor T7 is turned on, the second initialization voltage VAINT may be applied to the anode of the light-emitting element LD, and the voltage of the light-emitting element LD may be initialized to a charge amount corresponding to the voltage difference between the second initialization voltage VAINT and the second power supply voltage ELVSS. Therefore, low grayscale expression of the light-emitting element LD may be facilitated.

[0094] In addition, since the eighth transistor T8 is turned on, the voltage of the second node N2 can be set to the bias voltage VOBS. Therefore, since the bias voltage VOBS is applied to the source electrode of the first transistor T1 instead of the data voltage of the previous frame period, hysteresis can be prevented and the on-bias state can be ensured.

[0095] At time t6a, a light emission signal at a turn-on level (low level) may be applied to the light emission line EMi, so that the fifth transistor T5 and the sixth transistor T6 may be turned on. Thus, a path of a driving current flowing from the line supplied with the first power supply voltage ELVDD to the line supplied with the second power supply voltage ELVSS via the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light emitting element LD may be formed.

[0096] The amount of the driving current can be adjusted according to the voltage maintained in the storage capacitor Cst. The light emitting element LD can emit light with a brightness corresponding to the amount of the driving current. The light emitting element LD can emit light until a light emission signal at an off level is applied to the light emission line EMi.

[0097] Figure 5 1 is a signal / timing diagram illustrating the second scanning cycle SELF SCAN 1 according to an embodiment of the present disclosure. Figure 5 When, refer to Figure 2 Pixel PXij.

[0098] refer to Figure 5 , also refer to Figure 1 and Figure 2 At time t7a, a light emitting signal at a turn-off level (high level) may be applied to the light emitting line EMi, so that the fifth transistor T5 and the sixth transistor T6 may be turned off, and the pixel PXij may be in a non-emission state.

[0099] During the period t7a to t8a, the scan signal at the off level may be maintained in the first scan line GWi, the third scan line GIi, and the fourth scan line GCi. Therefore, the voltage of the first node N1 does not change.

[0100] At time t8a, a scan signal at an on-level (low level) may be applied to the second scan line GBi, turning on the seventh transistor T7 and the eighth transistor T8. Since the seventh transistor T7 is turned on, the second initialization voltage VAINT may be applied to the anode of the light-emitting element LD, and the voltage of the light-emitting element LD may be initialized to a charge amount corresponding to the voltage difference between the second initialization voltage VAINT and the second power supply voltage ELVSS. Therefore, low grayscale expression of the light-emitting element LD may be facilitated.

[0101] In addition, since the eighth transistor T8 is turned on, the voltage of the second node N2 can be set to the bias voltage VOBS. Therefore, since the bias voltage VOBS is applied to the source electrode of the first transistor T1 instead of the data voltage of the previous frame period, hysteresis can be prevented and the on-bias state can be ensured.

[0102] At time t9a, a light emitting signal at a turn-on level (low level) may be applied to the light emitting line EMi, so that the fifth transistor T5 and the sixth transistor T6 may be turned on. Thus, a path of a driving current flowing from the line supplied with the first power supply voltage ELVDD to the line supplied with the second power supply voltage ELVSS via the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light emitting element LD may be formed.

[0103] The amount of driving current can be adjusted according to the voltage maintained in the storage capacitor Cst. Because the voltage of the first node N1 recorded during the first scanning period DISPLAY SCAN 1 is maintained during the second scanning period SELF SCAN 1, the image frame displayed by the pixel unit 14 during the second scanning period SELF SCAN 1 can be the same as the image frame displayed by the pixel unit 14 during the first scanning period DISPLAY SCAN 1.

[0104] Figure 6 1 is a signal / timing diagram illustrating a first scanning cycle DISPLAY SCAN 2 and a second scanning cycle SELF SCAN 2 according to another embodiment of the present disclosure. Figure 6 When, refer to Figure 2 Pixel PXij.

[0105] refer to Figure 6 , also refer to Figure 1 and Figure 2 , first, the first scanning cycle DISPLAY SCAN 2 will be described.

[0106] At time t1b, a light emission signal at a turn-off level (high level) is applied to the light emission line EMi, so that the fifth transistor T5 and the sixth transistor T6 may be turned off, and the pixel PXij may be in a non-emission state.

[0107] At time t2b, a scan signal at an on-level (low level) is applied to the second scan line GBi, turning on the seventh transistor T7 and the eighth transistor T8. Since the seventh transistor T7 is turned on, the second initialization voltage VAINT can be applied to the anode of the light-emitting element LD, and the voltage of the light-emitting element LD can be initialized to a charge amount corresponding to the voltage difference between the second initialization voltage VAINT and the second power supply voltage ELVSS. Therefore, low grayscale expression of the light-emitting element LD can be facilitated.

[0108] At time t3b, a fourth scan signal at a turn-on level (high level) is applied to the fourth scan line GCi, so that the third transistor T3 may be turned on. Therefore, the first transistor T1 may be in a diode-connected state in which the drain electrode and the gate electrode are connected.

[0109] At time t4b, a third scan signal at a turn-on level (high level) is applied to the third scan line GIi, so that the fourth transistor T4 can be turned on. Therefore, the first initialization voltage VINT can be applied to the first node N1. The first initialization voltage VINT can be a sufficiently low voltage and can bias the first transistor T1 to turn on.

[0110] At time t5b, a scan signal at a turn-on level (low level) is applied to the first scan line GWi, turning on the second transistor T2. Thus, the data voltage of the data line DLj is applied to the first node N1 through the turned-on second transistor T2, the first transistor T1, and the third transistor T3. At this time, the voltage of the first node N1 may be a compensation voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage. The storage capacitor Cst may maintain the voltage difference between the first power supply voltage ELVDD and the compensation voltage.

[0111] At time t6b, a scan signal at an on-level (low level) is applied to the second scan line GBi, turning on the seventh transistor T7 and the eighth transistor T8. Since the seventh transistor T7 is turned on, the second initialization voltage VAINT can be applied to the anode of the light-emitting element LD, and the voltage of the light-emitting element LD can be initialized to a charge amount corresponding to the voltage difference between the second initialization voltage VAINT and the second power supply voltage ELVSS. Therefore, low grayscale expression of the light-emitting element LD can be facilitated.

[0112] In addition, since the eighth transistor T8 is turned on, the voltage of the second node N2 can be set to the bias voltage VOBS. Therefore, since the bias voltage VOBS is applied to the source electrode of the first transistor T1 instead of the data voltage of the previous frame period, hysteresis can be prevented and the on-bias state can be ensured.

[0113] At time t7b, a light emission signal at a turn-on level (low level) is applied to the light emission line EMi, so that the fifth transistor T5 and the sixth transistor T6 can be turned on. Therefore, a path of a driving current flowing from the line supplied with the first power supply voltage ELVDD to the line supplied with the second power supply voltage ELVSS via the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light emitting element LD can be formed.

[0114] The amount of the driving current can be adjusted according to the voltage maintained in the storage capacitor Cst. The light emitting element LD can emit light with a brightness corresponding to the amount of the driving current. The light emitting element LD can emit light until a light emission signal at an off level is applied to the light emission line EMi.

[0115] Next, the second scanning period SELF SCAN 2 will be described.

[0116] According to an embodiment of the present disclosure, before the first scan period DISPLAY SCAN 2 is changed to the second scan period SELF SCAN 2, at least one of the second initialization voltage VAINT and the bias voltage VOBS may be changed. For example, the second initialization voltage VAINT and the bias voltage VOBS may be reduced. This may be to set the voltage stress applied to the first transistor T1 to the same level in the first scan period DISPLAY SCAN 2 and the second scan period SELF SCAN 2.

[0117] At time t8b, a light emission signal at a turn-off level (high level) is applied to the light emission line EMi, so that the fifth transistor T5 and the sixth transistor T6 may be turned off, and the pixel PXij may be in a non-emission state.

[0118] At time t9b, a scan signal at an on-level (low level) is applied to the second scan line GBi, turning on the seventh transistor T7 and the eighth transistor T8. Since the seventh transistor T7 is turned on, the second initialization voltage VAINT can be applied to the anode of the light-emitting element LD, and the voltage of the light-emitting element LD can be initialized to a charge amount corresponding to the voltage difference between the second initialization voltage VAINT and the second power supply voltage ELVSS. Therefore, low grayscale expression of the light-emitting element LD can be facilitated.

[0119] In addition, since the eighth transistor T8 is turned on, the voltage of the second node N2 can be set to the bias voltage VOBS. Therefore, since the bias voltage VOBS is applied to the source electrode of the first transistor T1 instead of the data voltage of the previous frame period, hysteresis can be prevented and the on-bias state can be ensured.

[0120] During the period t8b to t10b, the scan signal at the off level may be maintained in the first scan line GWi, the third scan line GIi, and the fourth scan line GCi. Therefore, the voltage of the first node N1 does not change.

[0121] At time t10b, a scan signal at an on-level (low level) is applied to the second scan line GBi, turning on the seventh transistor T7 and the eighth transistor T8. Since the seventh transistor T7 is turned on, the second initialization voltage VAINT can be applied to the anode of the light-emitting element LD, and the voltage of the light-emitting element LD can be initialized to a charge amount corresponding to the voltage difference between the second initialization voltage VAINT and the second power supply voltage ELVSS. Therefore, low grayscale expression of the light-emitting element LD can be facilitated.

[0122] In addition, since the eighth transistor T8 is turned on, the voltage of the second node N2 can be set to the bias voltage VOBS. Therefore, since the bias voltage VOBS is applied to the source electrode of the first transistor T1 instead of the data voltage of the previous frame period, hysteresis can be prevented and the on-bias state can be ensured.

[0123] At time t11b, a light emission signal at a turn-on level (low level) is applied to the light emission line EMi, so that the fifth transistor T5 and the sixth transistor T6 can be turned on. Therefore, a path of a driving current flowing from the line supplied with the first power supply voltage ELVDD to the line supplied with the second power supply voltage ELVSS via the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light emitting element LD can be formed.

[0124] The amount of driving current can be adjusted according to the voltage maintained in the storage capacitor Cst. Because the voltage of the first node N1 recorded during the first scanning period DISPLAY SCAN 2 is maintained during the second scanning period SELF SCAN 2, the image frame displayed by the pixel unit 14 during the second scanning period SELF SCAN 2 can be the same as the image frame displayed by the pixel unit 14 during the first scanning period DISPLAY SCAN 2.

[0125] Figure 7 is a schematic diagram illustrating a light emitting driver 15 according to an embodiment of the present disclosure.

[0126] refer to Figure 7 , also refer to Figure 1 The light emitting driver 15 according to an embodiment of the present disclosure may include a plurality of light emitting stages (..., ESTn1, ESTn2, ESTn3, ESTn4, EST(n+1)1, EST(n+1)2, EST(n+1)3, EST(n+1)4, ...) and a light emitting stage connecting circuit 151. The light emitting driver 15 may be connected to a first light emitting clock line ECK1, a second light emitting clock line ECK2, a third light emitting clock line ECK3, and a fourth light emitting clock line ECK4.

[0127] Each of the light-emitting stages ESTn1 to EST(n+1)4 may include a first input terminal I1, a second input terminal I2, a third input terminal I3, and an output terminal O1. The first input terminal I1 may receive a light-emitting signal at a cut-off level output from another light-emitting stage. However, the first light-emitting stage (not shown) of the light-emitting driver 15 may receive a light-emitting stop signal as a cut-off level pulse type from the timing controller 11 through the first input terminal I1. The second input terminal I2 may be connected to one of the first light-emitting clock lines ECK1 to the fourth light-emitting clock lines ECK4. The third input terminal I3 may be connected to another of the first light-emitting clock lines ECK1 to the fourth light-emitting clock lines ECK4. The output terminal O1 may output a light-emitting signal at a cut-off level. The output terminal O1 may be connected to a corresponding light-emitting line. For example, Figure 7 The output terminal O1 of the lighting stage ESTn1 is shown connected to the corresponding lighting line EMn1. Other output terminals O1 of the lighting stages ESTn2, ESTn3, ESTn4, EST(n+1)1, EST(n+1)2, EST(n+1)3, EST(n+1)4, ... can also be connected to the corresponding lighting lines EMn2, EMn3, EMn4, EM(n+1)1, EM(n+1)2, EM(n+1)3, EM(n+1)4, ...

[0128] According to an embodiment, two adjacent lighting stages may be connected to different lighting clock lines. For example, the lighting stage ESTn2 may be connected to the third lighting clock line ECK3 and the fourth lighting clock line ECK4, and the lighting stage ESTn1 or ESTn3 adjacent to the lighting stage ESTn2 may be connected to the first lighting clock line ECK1 and the second lighting clock line ECK2.

[0129] m light-emitting levels can belong to one light-emitting level group. m can be an integer greater than 1. m can be a multiple of 2. For example, when m is 2, the nth light-emitting level group ESTGn can include two light-emitting levels ESTn1 and ESTn2. When m is 4, the nth light-emitting level group ESTGn can also include two light-emitting levels ESTn3 and ESTn4. In this case, the connection relationship between the light-emitting clock lines ECK1 to ECK4 and the light-emitting levels ESTn3 and ESTn4 can be the same as the connection relationship between the light-emitting clock lines ECK1 to ECK4 and the light-emitting levels ESTn1 and ESTn2, respectively. In this way, those skilled in the art can add reference to m in this embodiment. The following description will assume that m is 4.

[0130] The nth lighting level group ESTGn may include four lighting levels ESTn1, ESTn2, ESTn3, and ESTn4. In addition, the n+1th lighting level group ESTG(n+1) adjacent to the nth lighting level group ESTGn may include four other lighting levels EST(n+1)1, EST(n+1)2, EST(n+1)3, and EST(n+1)4.

[0131] The structure in which the n+1th light emitting stage group ESTG(n+1) is connected to the light emitting clock lines ECK1 to ECK4 may be mirror-symmetrical to the structure in which the nth light emitting stage group ESTGn is connected to the light emitting clock lines ECK1 to ECK4.

[0132] For example, the m-1th light-emitting stage ESTn3 of the nth light-emitting stage group ESTGn may have a second input terminal I2 connected to the first light-emitting clock line ECK1 and a third input terminal I3 connected to the second light-emitting clock line ECK2. The m-1th light-emitting stage ESTn4 of the nth light-emitting stage group ESTGn may have a second input terminal I2 connected to the third light-emitting clock line ECK3 and a third input terminal I3 connected to the fourth light-emitting clock line ECK4.

[0133] At this time, the first light-emitting stage EST(n+1)1 of the n+1th light-emitting stage group ESTG(n+1) may have a second input terminal I2 connected to the fourth light-emitting clock line ECK4 and a third input terminal I3 connected to the third light-emitting clock line ECK3. The second light-emitting stage EST(n+1)2 of the n+1th light-emitting stage group ESTG(n+1) may have a second input terminal I2 connected to the second light-emitting clock line ECK2 and a third input terminal I3 connected to the first light-emitting clock line ECK1.

[0134] The light-emitting level connection circuit 151 may include a first connection transistor (..., NTn1, NTn2, NTn3, NTn4, NT(n+1)1, NT(n+1)2, NT(n+1)3, NT(n+1)4, ...) and a second connection transistor (..., PTno, PTn1, PTn2, PTn3, PTn4, PT(n+1)o, PT(n+1)1, PT(n+1)2, PT(n+1)3, PT(n+1)4, ...).

[0135] The gate electrodes of the first connection transistors NTn1 to NT(n+1)4 and the gate electrodes of the second connection transistors PTno to PT(n+1)4 can be commonly connected to an enable line EN. For example, the timing controller 11 can provide an enable signal and a disable signal through the enable line EN. For example, the enable signal can be a polarity signal (high level) that turns on the first connection transistors NTn1 to NT(n+1)4, which are first conductivity type transistors (e.g., n-type transistors). For example, the disable signal can be a signal of the opposite polarity (low level) that turns on the second connection transistors PTno to PT(n+1)4, which are second conductivity type transistors (e.g., p-type transistors).

[0136] In another embodiment, the first connection transistors NTn1 to NT(n+1)4 and the second connection transistors PTno to PT(n+1)4 may be formed of transistors of the same conductivity type. In this case, the gate electrodes of the first connection transistors NTn1 to NT(n+1)4 and the second connection transistors PTno to PT(n+1)4 are connected to different enable lines.

[0137] Since the first connection transistors NTn1 to NT(n+1)4 are turned on when receiving the enable signal, the first connection transistors NTn1 to NT(n+1)4 can connect each of the first input terminals I1 of the light-emitting stages ESTn1 to EST(n+1)4 to the output terminal of the previous light-emitting stage. For example, when receiving the enable signal, the first connection transistor NTn2 is turned on, and therefore, the first input terminal I1 of the light-emitting stage ESTn2 can be connected to the output terminal O1 of the light-emitting stage ESTn1.

[0138] Because the second connecting transistors PTno to PT(n+1)4 are turned on when receiving the disable signal, the second connecting transistors PTno to PT(n+1)4 can connect each of the first input terminals I1 of the light-emitting levels ESTn1 to EST(n+1)4 to the output terminal of the previous light-emitting level group.

[0139] For example, when a disable signal is received, the second connection transistors PTno, PT(n+1)1, PT(n+1)2, PT(n+1)3, and PT(n+1)4 are turned on, and thus, the first input terminals I1 of the light-emitting stages EST(n+1)1 to EST(n+1)4 may be connected to the output terminal O1 of the previous light-emitting stage group ESTGn. Here, the output terminal O1 of the previous light-emitting stage group ESTGn may be set to the output terminal O1 of the first light-emitting stage ESTn1. In another embodiment, the output terminal O1 of the previous light-emitting stage group ESTGn may be set to the output terminal O1 of at least one of the light-emitting stages ESTn1, ESTn2, ESTn3, and ESTn4.

[0140] Similarly, when a disable signal is received, the second connection transistors PTn1, PTn2, PTn3, and PTn4 are turned on, so that the first input terminal I1 of the light-emitting stage ESTn1 to ESTn4 can be connected to the output terminal of the previous light-emitting stage group (i.e., the n-1th light-emitting stage group (not shown)).

[0141] Figure 8 Schematic diagram showing the light emitting stage ESTn1a according to an embodiment of the present disclosure. Figure 8 , the luminescence level ESTn1a can be Figure 7 The present invention is an example of any light emitting stage in the light emitting stage EST, and may include first to thirteenth transistors ET1 to ET13 and capacitors EC1 to EC3.

[0142] The first transistor ET1 may have a first electrode connected to the first input terminal I1 , a second electrode connected to the first electrode of the twelfth transistor ET12 , and a gate electrode connected to the second input terminal I2 .

[0143] The second transistor ET2 may have a first electrode receiving the first voltage VGH, a second electrode connected to the first electrode of the third transistor ET3 , and a gate electrode connected to the node SR_QBN.

[0144] The third transistor ET3 may have a first electrode connected to the second electrode of the second transistor ET2 , a second electrode connected to the third input terminal I3 , and a gate electrode connected to the node QN.

[0145] The first capacitor EC1 may have a first electrode connected to the first electrode of the third transistor ET3 and a second electrode connected to the gate electrode of the third transistor ET3 .

[0146] The fourth transistor may have a first electrode connected to the node SR_QBN, a second electrode connected to the second input terminal I2, and a gate electrode connected to the second electrode of the first transistor ET1. The fourth transistor may include sub-transistors ET4-1 and ET4-2.

[0147] The fifth transistor ET5 may have a first electrode connected to the node SR_QBN, a second electrode receiving the second voltage VGL, and a gate electrode connected to the second input terminal 12. The second voltage VGL may have a voltage level lower than that of the first voltage VGH.

[0148] The sixth transistor ET6 may have a first electrode connected to the node QBN, a second electrode connected to the first electrode of the seventh transistor ET7 , and a gate electrode connected to the third input terminal I3 .

[0149] The second capacitor EC2 may have a first electrode receiving the first voltage VGH and a second electrode connected to the node QBN.

[0150] The seventh transistor ET7 may have a first electrode connected to the second electrode of the sixth transistor ET6 , a second electrode connected to the third input terminal I3 , and a gate electrode connected to the second electrode of the eleventh transistor ET11 .

[0151] The third capacitor EC3 may have a first electrode connected to the gate electrode of the seventh transistor ET7 and a second electrode connected to the first electrode of the seventh transistor ET7 .

[0152] The eighth transistor ET8 may have a first electrode receiving the first voltage VGH, a second electrode connected to the node QBN, and a gate electrode connected to the second electrode of the first transistor ET1 .

[0153] The ninth transistor ET9 may have a first electrode receiving the first voltage VGH, a second electrode connected to the output terminal O1 , and a gate electrode connected to the node QBN.

[0154] The tenth transistor ET10 may have a first electrode connected to the output terminal O1 , a second electrode receiving the second voltage VGL, and a gate electrode connected to the node QN.

[0155] The eleventh transistor ET11 may have a first electrode connected to the node SR_QBN, a second electrode connected to the gate electrode of the seventh transistor ET7 , and a gate electrode receiving the second voltage VGL.

[0156] The twelfth transistor ET12 may have a first electrode connected to the second electrode of the first transistor ET1 , a second electrode connected to the node QN, and a gate electrode receiving the second voltage VGL.

[0157] The thirteenth transistor ET13 may have a first electrode receiving the first voltage VGH, a second electrode connected to the second electrode of the first transistor ET1, and a gate electrode connected to the reset terminal SESR. In an alternative embodiment, the thirteenth transistor ET13 may be omitted.

[0158] Figure 9 It shows Figure 8 Signal / timing diagram of the driving method of the light-emitting stage ESTn1a.

[0159] exist Figure 9 Also refer to Figure 8"I3(ECK2)" indicates the second emission clock line ECK2 connected to the third input terminal I3. At time t1c, the second emission clock signal on this line may have transitioned from a high level to a low level. Node QN may be coupled to the third input terminal I3 via the conductive third transistor ET3 and the first capacitor EC1. Therefore, the voltage level of node QN may decrease.

[0160] "I2(ECK1)" indicates the first emission clock line ECK1 connected to the second input terminal I2. At time t2c, the first emission clock signal at this line may have transitioned to a low level. Therefore, the first transistor ET1 may be turned on, and the emission signal at the previous emission stage at the cutoff level (high level) input through the first input terminal I1 may be applied to the node QN. The twelfth transistor ET12 may be turned on. At the same time, the second voltage VGL may be applied to the node SR_QBN through the turned-on fifth transistor ET5. Therefore, the second transistor ET2 and the seventh transistor ET7 may be turned on.

[0161] At time t3c, the second light emitting clock signal of the third input terminal I3 can be changed to a low level again. The node SR_QBN can be coupled to the third input terminal I3 via the eleventh transistor ET11 in the on state, the third capacitor EC3, and the seventh transistor ET7 in the on state. Therefore, the voltage level of the node SR_QBN can be reduced. In addition, the voltage level of the node QBN can be reduced by the sixth transistor ET6 being turned on. Therefore, the ninth transistor ET9 can be turned on, and the first voltage VGH can be output as a light emitting signal at a cut-off level (high level) to the output terminal O1.

[0162] At time t4c, the second light emitting clock signal of the third input terminal I3 may have already turned high. Therefore, the sixth transistor ET6 may be turned off. At this time, because the node QBN is maintained at a low voltage through the second capacitor EC2, the ninth transistor ET9 may remain on.

[0163] At time t5c, the light emission level ESTn1a may operate in the same manner as at time t3c.At time t6c, the light emission level ESTn1a may operate in the same manner as at time t4c.

[0164] At time t7c, the first light-emitting clock signal of the second input terminal I2 may have transitioned to a low level. Therefore, the first transistor ET1 may be turned on, and the light-emitting signal of the previous light-emitting stage at the on-level (low level) input through the first input terminal I1 may be applied to the node QN. Therefore, the tenth transistor ET10 may be turned on, and the second voltage VGL may be output to the output terminal O1 as a light-emitting signal at the on-level (low level). At this time, the node QBN may receive the first voltage VGH via the turned-on eighth transistor ET8. Therefore, the ninth transistor ET9 may be turned off.

[0165] At time t8c, the light emission level ESTn1a may operate in the same manner as at time t1c.At time t9c, the light emission level ESTn1a may operate in the same manner as at time t7c.

[0166] Figure 10 It is shown by Figure 8 The signal / timing diagram of the driving method of the light-emitting driver composed of the light-emitting level ESTn1a. Figure 10 Also refer to Figure 7 , the levels associated with stages EST(n-1)1 to EST(n+1)4 may be the voltages at the output terminals O1 of the corresponding stages.

[0167] According to the embodiments of the present disclosure, Figure 10 As shown in FIG, during the first scanning period DISPLAY SCAN, the first lighting clock signal applied to the first lighting clock line ECK1 may be the same as the fourth lighting clock signal applied to the fourth lighting clock line ECK4. Therefore, during the first scanning period DISPLAY SCAN, the frequency and phase of the first lighting clock signal may be the same as the frequency and phase of the fourth lighting clock signal.

[0168] In addition, during the first scanning period DISPLAY SCAN, the second lighting clock signal applied to the second lighting clock line ECK2 may be the same as the third lighting clock signal applied to the third lighting clock line ECK3. Therefore, during the first scanning period DISPLAY SCAN, the frequency and phase of the second lighting clock signal may be the same as the frequency and phase of the third lighting clock signal.

[0169] However, during the second scanning period SELF SCAN, the first emission clock signal may be the same as the third emission clock signal, and the second emission clock signal may be the same as the fourth emission clock signal. Therefore, during the second scanning period SELFSCAN, the frequency and phase of the first emission clock signal may be the same as the frequency and phase of the third emission clock signal, and the frequency and phase of the second emission clock signal may be the same as the frequency and phase of the fourth emission clock signal.

[0170] The light-emitting stage connection circuit 151 may receive an enable signal during the first scanning period DISPLAY SCAN and receive a disable signal during the second scanning period SELF SCAN. As described above, a high-level signal applied to the enable line EN (and applied to the gate of the N-type transistor) may be an enable signal, and a low-level signal applied to the enable line EN may be a disable signal.

[0171] When the enable signal is received, the light-emitting stage connection circuit 151 can connect each of the first input terminals I1 of the light-emitting stages (..., EST(n-1)1, EST(n-1)2, EST(n-1)3, EST(n-1)4, ESTn1, ESTn2, ESTn3, ESTn4, EST(n+1)1, EST(n+1)2, EST(n+1)3, EST(n+1)4, ...) to the output terminal of the previous light-emitting stage. Therefore, during the first scanning period DISPLAY SCAN, the light-emitting stages (..., EST(n-1)1 to EST(n+1)4, ...) can sequentially generate light-emitting signals at the off level in units of one light-emitting stage.

[0172] At the same time, when a disable signal is received, the light-emitting stage connection circuit 151 can connect each of the first input terminals I1 of the light-emitting stages (..., EST(n-1)1 to EST(n+1)4, ...) to the output terminal of the previous light-emitting stage group. Therefore, during the second scanning period SELF SCAN, the light-emitting stages (..., EST(n-1)1 to EST(n+1)4, ...) can sequentially generate light-emitting signals at the cut-off level in units of m light-emitting stages. Figure 10 In the embodiment, m is 4, and four light-emitting levels can constitute each light-emitting level group (..., ESTG(n-1), ESTGn, ESTG(n+1), ...). Therefore, during the second scanning period SELFSCAN, the light-emitting level group (..., ESTG(n-1), ESTGn, ESTG(n+1), ...) can sequentially generate light-emitting signals at the cut-off level in units of four light-emitting levels.

[0173] The frequency of the light emitting clock signal applied to the light emitting clock lines ECK1, ECK2, ECK3, and ECK4 during the first scanning period DISPLAY SCAN may be m times the frequency of the light emitting clock signal applied to the light emitting clock lines ECK1, ECK2, ECK3, and ECK4 during the second scanning period SELF SCAN. Therefore, the length of the light emitting signal at the off level during the first scanning period DISPLAY SCAN may be the same as the length of the light emitting signal at the off level during the second scanning period SELF SCAN.

[0174] Still refer to Figure 10 , it can be seen that the cycle period of the emission clock signal during the second scanning cycle SELF SCAN is longer than the cycle period of the emission clock signal during the first scanning cycle DISPLAY SCAN. For example, when m is 4, the cycle period of the emission clock signal during the second scanning cycle SELF SCAN can be 4 times the cycle period of the emission clock signal during the first scanning cycle DISPLAY SCAN. Therefore, according to this embodiment, the power consumption when generating the emission clock signal can be reduced during the second scanning cycle SELF SCAN.

[0175] Figure 11 FIG is a schematic diagram showing a light emitting stage ESTn1b according to another embodiment of the present disclosure. Figure 11 , the light emitting stage ESTn1b may include transistors ET1, ET2, ET3, ET4, ET5, and ET6. Transistors ET1, ET3, and ET5 may be P-type transistors. Transistors ET2, ET4, and ET6 may be N-type transistors having sub-gate (or back-gate) electrodes. The light emitting stage ESTn1b is Figure 7 Another example of any one of the luminous levels EST.

[0176] The first transistor ET1 may have a first electrode connected to the first input terminal I1 , a second electrode connected to the node AN, and a gate electrode connected to the second input terminal I2 .

[0177] The second transistor ET2 may have a first electrode connected to the first input terminal I1, a second electrode connected to the node AN, and a gate electrode connected to the third input terminal 13. A sub-gate electrode of the second transistor ET2 may be connected to the third input terminal I3.

[0178] The third transistor ET3 may have a first electrode receiving the first voltage VGH, a second electrode connected to the node BN, and a gate electrode connected to the node AN.

[0179] The fourth transistor ET4 may have a first electrode connected to the node BN, a second electrode receiving the second voltage VGL, and a gate electrode connected to the node AN. A sub-gate electrode of the fourth transistor ET4 may be connected to the node AN.

[0180] The fifth transistor ET5 may have a first electrode receiving the first voltage VGH, a second electrode connected to the output terminal O1 , and a gate electrode connected to the node BN.

[0181] The sixth transistor ET6 may have a first electrode connected to the output terminal O1, a second electrode receiving the second voltage VGL, and a gate electrode connected to the node BN. A sub-gate electrode of the sixth transistor ET6 may be connected to the node BN.

[0182] Figure 12 It shows Figure 11 Signal / timing diagram of the driving method of the light-emitting stage ESTn1b.

[0183] refer to Figure 12 , also refer to Figure 11 At time t1d, the first emission clock signal applied to the first emission clock line ECK1 connected to the second input terminal I2 may have transitioned from a low level to a high level. Therefore, the first transistor ET1 may be turned off. Furthermore, the second emission clock signal applied to the second emission clock line ECK2 connected to the third input terminal I3 may have transitioned from a high level to a low level. Therefore, the second transistor ET2 may be turned off.

[0184] At this time, the light emitting signal at the off level (high level) output from the previous light emitting stage may be applied to the first input terminal I1 , but the voltage of the node AN may be maintained by the first and second transistors ET1 and ET2 in the off state.

[0185] At time t2d, the first emission clock signal of the second input terminal I2 may have transitioned to a low level. Therefore, the first transistor ET1 may be turned on. In addition, the second emission clock signal of the third input terminal I3 may have transitioned to a high level. Therefore, the second transistor ET2 may be turned on.

[0186] At this time, the voltage of the node AN may have been raised to a high level by the turned-on first and second transistors ET1 and ET2. Therefore, the fourth transistor ET4 may be turned on, and the node BN may receive the second voltage VGL and the voltage level may be lowered.

[0187] When the voltage level of the node BN becomes low, the fifth transistor ET5 can be turned on. Therefore, the first voltage VGH can be applied to the output terminal O1 as the output signal of the light emitting stage ESTn1b. Therefore, the light emitting stage ESTn1b can output a light emitting signal at a cut-off level.

[0188] At time t3d, the first light-emission clock signal of the second input terminal I2 may have transitioned to a high level. Therefore, the first transistor ET1 may be turned off. In addition, the second light-emission clock signal of the third input terminal I3 may have transitioned to a low level. Therefore, the second transistor ET2 may be turned off.

[0189] At this time, the light emitting signal at the on level (low level) output from the previous light emitting stage may be applied to the first input terminal I1 , but the voltage of the node AN may be maintained by the first and second transistors ET1 and ET2 in the off state.

[0190] At time t4d, the first light-emission clock signal of the second input terminal I2 may have transitioned to a low level. Thus, the first transistor ET1 may be turned on. In addition, the second light-emission clock signal of the third input terminal I3 may transition to a high level. Thus, the second transistor ET2 may be turned on.

[0191] At this time, the voltage of the node AN may be turned into a low level by the turned-on first and second transistors ET1 and ET2. Therefore, the third transistor ET3 may be turned on, and the node BN may receive the first voltage VGH and the voltage level may be increased.

[0192] When the voltage level of the node BN becomes high, the sixth transistor ET6 can be turned on. Therefore, the second voltage VGL can be applied to the output terminal O1 as the output signal of the light emitting stage ESTn1b. Therefore, the light emitting stage ESTn1b can output a light emitting signal at a turn-on level.

[0193] Figure 13 It is shown by Figure 11 The signal / timing diagram of the driving method of the light-emitting driver composed of the light-emitting level ESTn1b. Figure 13 Also refer to Figure 7 , the levels associated with stages EST(n-1)1 to EST(n+1)4 may be the voltages at the output terminals O1 of the corresponding stages.

[0194] exist Figure 13As can be seen from FIG, the waveform is similar to FIG, except that a greater number of emission clock line ECK pulses are illustrated for each corresponding emission level EST pulse during each of the first scanning period DISPLAY SCAN and the second scanning period SELF SCAN and the on / off cycle period of the emission clock line ECK pulses during the second scanning period SELF SCAN is more uniform. Figure 10 In addition, Figure 10 The description can also be applied to Figure 13 , and therefore repeated descriptions are omitted.

[0195] Figure 14 is a schematic diagram illustrating a second scan driver 13GB according to an embodiment of the present disclosure.

[0196] refer to Figure 14 , also refer to Figure 1 , Figure 14 The second scan drive 13GB is Figure 1 1, and a second scan driver 13GB is a portion of the scan driver 13 that supplies scan signals to the scan lines GB1 to GBp. The second scan driver 13GB may include a plurality of scan stages (..., GBTn1, GBTn2, GBTn3, GBTn4, GBT(n+1)1, GBT(n+1)2, GBT(n+1)3, GBT(n+1)4, ...) and a scan stage connection circuit 131. The second scan driver 13GB may be connected to a first scan clock line GCK1, a second scan clock line GCK2, a third scan clock line GCK3, and a fourth scan clock line GCK4.

[0197] Each of the scanning stages GBTn1 to GBT(n+1)4 may include a first input terminal I1, a second input terminal I2, a third input terminal I3, and an output terminal O1. The first input terminal I1 may receive a second scanning signal at an on-level output from another scanning stage. However, the first scanning stage (not shown) of the second scanning driver 13GB may receive a scanning start signal as a pulse having an on-level from the timing controller 11 through the first input terminal I1. The second input terminal I2 may be connected to one of the first to fourth scanning clock lines GCK1 to GCK4. The third input terminal I3 may be connected to another of the first to fourth scanning clock lines GCK1 to GCK4. The output terminal O1 may output a second scanning signal at an on-level. The output terminal O1 may be connected to the corresponding second scanning line GB. For example, Figure 14The output terminal O1 of the scanning stage GBTn1 is shown connected to the corresponding second scanning line GBn1. Other output terminals O1 of the scanning stages GBTn2, GBTn3, GBTn4, GBT(n+1)1, GBT(n+1)2, GBT(n+1)3, GBT(n+1)4, ... can also be connected to the corresponding second scanning lines GBn2, GBn3, GBn4, GB(n+1)1, GB(n+1)2, GB(n+1)3, GB(n+1)4, ...

[0198] According to an embodiment, two adjacent scan stages may be connected to different scan clock lines. For example, the scan stage GBTn2 may be connected to the third scan clock line GCK3 and the fourth scan clock line GCK4, and the scan stage GBTn1 or GBTn3 adjacent to the scan stage GBTn2 may be connected to the first scan clock line GCK1 and the second scan clock line GCK2.

[0199] m scanning stages may belong to one scanning stage group. m may be an integer greater than 1. m may be a multiple of 2. For example, when m is 2, the n-th scanning stage group GBTGn may include two scanning stages GBTn1 and GBTn2. When m is 4, as in Figure 14 In the example shown in FIG, the nth scanning stage group GBTGn may further include two scanning stages GBTn3 and GBTn4. In this case, the connection relationship between the scanning clock lines GCK1 to GCK4 and the scanning stages GBTn3 and GBTn4 may be the same as the connection relationship between the scanning clock lines GCK1 to GCK4 and the scanning stages GBTn1 and GBTn2, respectively. If the number of scanning stage GBTs in each scanning stage group GBTG is further increased by 2 (i.e., m is further increased by 2), the same connection relationship as that of the scan clock lines can be adopted for the additional scanning stages. In the following description, it will be assumed that m is 4.

[0200] The nth scanning stage group GBTGn may include four scanning stages GBTn1, GBTn2, GBTn3, and GBTn4. In addition, the n+1th scanning stage group GBTG(n+1) adjacent to the nth scanning stage group GBTGn may have four other scanning stages GBT(n+1)1, GBT(n+1)2, GBT(n+1)3, and GBT(n+1)4.

[0201] The structure in which the n+1th scanning stage group GBTG(n+1) is connected to the scanning clock lines GCK1 to GCK4 may be mirror-symmetrical to the structure in which the nth scanning stage group GBTGn is connected to the scanning clock lines GCK1 to GCK4.

[0202] For example, the m-1th scanning stage GBTn3 of the nth scanning stage group GBTGn may have a second input terminal I2 connected to the first scan clock line GCK1 and a third input terminal I3 connected to the second scan clock line GCK2. The m-1th scanning stage GBTn4 of the nth scanning stage group GBTGn may have a second input terminal I2 connected to the third scan clock line GCK3 and a third input terminal I3 connected to the fourth scan clock line GCK4.

[0203] Now, the first scanning stage GBT(n+1)1 of the n+1th scanning stage group GBTG(n+1) may have a second input terminal I2 connected to the fourth scanning clock line GCK4 and a third input terminal I3 connected to the third scanning clock line GCK3. The second scanning stage GBT(n+1)2 of the n+1th scanning stage group GBTG(n+1) may have a second input terminal I2 connected to the second scanning clock line GCK2 and a third input terminal I3 connected to the first scanning clock line GCK1.

[0204] The scan level connection circuit 131 may include a first connection transistor (…, NTn1, NTn2, NTn3, NTn4, NT(n+1)1, NT(n+1)2, NT(n+1)3, NT(n+1)4, …) and a second connection transistor (…, PTno, PTn1, PTn2, PTn3, PTn4, PT(n+1)o, PT(n+1)1, PT(n+1)2, PT(n+1)3, PT(n+1)4, …).

[0205] The gate electrodes of the first connection transistors NTn1 to NT(n+1)4 and the gate electrodes of the second connection transistors PTno to PT(n+1)4 can be commonly connected to an enable line EN. For example, the timing controller 11 can provide an enable signal and a disable signal through the enable line EN. For example, the enable signal can be a gate bias signal (high level) that turns on the first connection transistors NTn1 to NT(n+1)4, which are first conductivity type transistors (e.g., N-type transistors). For example, the disable signal can be a gate bias signal (low level) of opposite polarity that turns on the second connection transistors PTno to PT(n+1)4, which are second conductivity type transistors (e.g., P-type transistors).

[0206] In another embodiment, the first connection transistors NTn1 to NT(n+1)4 and the second connection transistors PTno to PT(n+1)4 may be formed of transistors of the same conductivity type. In this case, the gate electrodes of the first connection transistors NTn1 to NT(n+1)4 and the second connection transistors PTno to PT(n+1)4 are connected to different enable lines.

[0207] The first connection transistors NTn1 to NT(n+1)4 may be turned on when receiving an enable signal, and the first connection transistors NTn1 to NT(n+1)4 may connect each of the first input terminals I1 of the scanning stages GBTn1 to GBT(n+1)4 to the output terminal of the previous scanning stage. For example, when receiving an enable signal, the first connection transistor NTn2 may be turned on, and thus, the first input terminal I1 of the scanning stage GBTn2 may be connected to the output terminal O1 of the scanning stage GBTn1.

[0208] The second connecting transistors PTno to PT(n+1)4 can be turned on when receiving a disable signal, and the second connecting transistors PTno to PT(n+1)4 can connect each of the first input terminals I1 of the scanning stages GBTn1 to GBT(n+1)4 to the output terminal of the previous scanning stage group.

[0209] For example, when receiving a disable signal, the second connection transistors PTno, PT(n+1)1, PT(n+1)2, PT(n+1)3, and PT(n+1)4 may be turned on, and thus the first input terminals I1 of the scanning stages GBT(n+1)1 to GBT(n+1)4 may be connected to the output terminal O1 of the previous scanning stage group GBTGn. Here, the output terminal O1 of the previous scanning stage group GBTGn may be set to the output terminal O1 of the first scanning stage GBTn1. In another embodiment, the output terminal O1 of the previous scanning stage group GBTGn may be set to the output terminal O1 of at least one of the scanning stages GBTn1, GBTn2, GBTn3, and GBTn4.

[0210] Similarly, when a disable signal is received, the second connection transistors PTn1, PTn2, PTn3 and PTn4 can be turned on, and thus the first input terminal I1 of the scanning stage GBTn1 to GBTn4 can be connected to the output terminal of the previous scanning stage group (i.e., the n-1th scanning stage group (not shown)).

[0211] Figure 15 is a schematic diagram illustrating a scanning stage GBTn1 according to an embodiment of the present disclosure.

[0212] refer to Figure 15 The scanning stage GBTn1 according to an embodiment of the present disclosure may include transistors GT1, GT2, GT3, GT4, GT5, and GT6. The transistors GT1, GT3, and GT5 may be P-type transistors. The transistors GT2, GT4, and GT6 may be N-type transistors.

[0213] The first transistor GT1 may have a first electrode connected to the first input terminal I1 , a second electrode connected to the node AN, and a gate electrode connected to the second input terminal I2 .

[0214] The second transistor GT2 may have a first electrode connected to the first input terminal I1, a second electrode connected to the node AN, and a gate electrode connected to the third input terminal I3. According to an embodiment, a sub-gate electrode (or back gate electrode) of the second transistor GT2 may be connected to the third input terminal I3.

[0215] The third transistor GT3 may have a first electrode receiving the first voltage VGH, a second electrode connected to the node BN, and a gate electrode connected to the node AN.

[0216] The fourth transistor GT4 may have a first electrode connected to the node BN, a second electrode receiving the second voltage VGL, and a gate electrode connected to the node AN. According to an embodiment, a sub-gate electrode (or back gate electrode) of the fourth transistor GT4 may be connected to the node AN.

[0217] The fifth transistor GT5 may have a first electrode receiving the first voltage VGH, a second electrode connected to the output terminal O1, and a gate electrode connected to the node BN.

[0218] The sixth transistor GT6 may have a first electrode connected to the output terminal O1, a second electrode receiving the second voltage VGL, and a gate electrode connected to the node BN. A sub-gate electrode (or back gate electrode) of the sixth transistor GT6 may be connected to the node BN.

[0219] Figure 16 It shows Figure 15 Signal / timing diagram of the driving method of the scanning stage GBTn1.

[0220] refer to Figure 16 , also refer to Figure 15 At time t1e, the first scan clock signal applied to the first scan clock line GCK1 connected to the second input terminal I2 may have already transitioned to a high level. Therefore, the first transistor GT1 may be turned off. In addition, the second scan clock signal applied to the second scan clock line GCK2 connected to the third input terminal I3 may have already transitioned to a low level. Therefore, the second transistor GT2 may be turned off.

[0221] At this time, the second scan signal at the on level (low level) output from the previous scan stage may be applied to the first input terminal I1 , but the voltage of the node AN may be maintained by the first and second transistors GT1 and GT2 .

[0222] At time t2e, the first scan clock signal of the second input terminal I2 may have been reduced to a low level. Therefore, the first transistor GT1 may be turned on. In addition, the second scan clock signal of the third input terminal I3 may have been increased to a high level. Therefore, the second transistor GT2 may be turned on.

[0223] At this time, the voltage of the node AN may be lowered to a low level by the turned-on first and second transistors GT1 and GT2. Therefore, the third transistor GT3 may be turned on, and the node BN may receive the first voltage VGH and the voltage level may be increased.

[0224] When the voltage level of the node BN becomes high, the sixth transistor GT6 can be turned on. Therefore, the second voltage VGL can be applied to the output terminal O1 as the output signal of the scanning stage GBTn1. Therefore, the scanning stage GBTn1 can output the second scanning signal at the on level (low level).

[0225] At time t3e, the first scan clock signal of the second input terminal I2 may have been turned high. Therefore, the first transistor GT1 may be turned off. In addition, the second scan clock signal of the third input terminal I3 may be reduced to a low level. Therefore, the second transistor GT2 may be turned off.

[0226] At this time, the second scan signal of the off level (high level) output from the previous scan stage may be applied to the first input terminal I1 , but the voltage of the node AN may be maintained by the first and second transistors GT1 and GT2 .

[0227] At time t4e, the first scan clock signal of the second input terminal I2 may have been turned to a low level. Therefore, the first transistor GT1 may be turned on. In addition, the second scan clock signal of the third input terminal I3 may be raised to a high level. Therefore, the second transistor GT2 may be turned on.

[0228] At this time, the voltage of the node AN can be increased to a high level by the turned-on first and second transistors GT1 and GT2. Therefore, the fourth transistor GT4 can be turned on, and the node BN can receive the second voltage VGL and the voltage level can be reduced.

[0229] When the voltage level of the node BN becomes low, the fifth transistor GT5 can be turned on. Therefore, the first voltage VGH can be applied to the output terminal O1 as the output signal of the scanning stage GBTn1. Therefore, the scanning stage GBTn1 can output the second scanning signal at the off level (high level).

[0230] Figure 17 It is shown by Figure 15The signal / timing diagram of the driving method of the second scan driver composed of the scan stage GBTn1. Figure 17 Also refer to Figure 14 , the levels associated with stages GBT(n-1)1 to GBT(n+1)4 may be the voltages at the output terminals O1 of the corresponding stages.

[0231] According to an embodiment of the present disclosure, during the first scanning period DISPLAY SCAN, the first scanning clock signal applied to the first scanning clock line GCK1 may be the same as the fourth scanning clock signal applied to the fourth scanning clock line GCK4. Therefore, during the first scanning period DISPLAY SCAN, the frequency and phase of the first scanning clock signal may be the same as the frequency and phase of the fourth scanning clock signal.

[0232] In addition, during the first scanning period DISPLAY SCAN, the second scanning clock signal applied to the second scanning clock line GCK2 may be the same as the third scanning clock signal applied to the third scanning clock line GCK3. Therefore, during the first scanning period DISPLAY SCAN, the frequency and phase of the second scanning clock signal may be the same as the frequency and phase of the third scanning clock signal.

[0233] However, during the second scanning period SELF SCAN, the first scanning clock signal may be the same as the third scanning clock signal, and the second scanning clock signal may be the same as the fourth scanning clock signal. Therefore, during the second scanning period SELFSCAN, the frequency and phase of the first scanning clock signal may be the same as the frequency and phase of the third scanning clock signal, and the frequency and phase of the second scanning clock signal may be the same as the frequency and phase of the fourth scanning clock signal.

[0234] The scan stage connection circuit 131 may receive an enable signal during the first scan period DISPLAY SCAN and receive a disable signal during the second scan period SELF SCAN. As described above, a high level signal applied to the enable line EN may be an enable signal, and a low level signal applied to the enable line EN may be a disable signal.

[0235] When the enable signal is received, the scanning stage connection circuit 131 can connect each of the first input terminals I1 of the scanning stages (..., GBT(n-1)1, GBT(n-1)2, GBT(n-1)3, GBT(n-1)4, GBTn1, GBTn2, GBTn3, GBTn4, GBT(n+1)1, GBT(n+1)2, GBT(n+1)3, GBT(n+1)4, ...) to the output terminal of the previous scanning stage. Therefore, during the first scanning period DISPLAY SCAN, the scanning stages (..., GBT(n-1)1 to GBT(n+1)4, ...) can sequentially generate the second scanning signal at the on level (low level) in units of one scanning stage.

[0236] At the same time, when receiving the disable signal, the scanning stage connection circuit 131 can connect each of the first input terminals I1 of the scanning stages (..., GBT(n-1)1 to GBT(n+1)4, ...) to the output terminal of the previous scanning stage group. Therefore, during the second scanning period SELF SCAN, the scanning stages (..., GBT(n-1)1 to GBT(n+1)4, ...) can sequentially generate the second scanning signal at the on level (low level) in units of m scanning stages. Figure 17 In the embodiment, m is 4, and four scanning stages may constitute each light-emitting stage group (..., GBTG (n-1), GBTGn, GBTG (n+1), ...). Therefore, during the second scanning period SELF SCAN, the scanning stage group (..., GBTG (n-1), GBTGn, GBTG (n+1), ...) may sequentially generate the second scanning signal at the on-level in units of four scanning stages.

[0237] The frequency of the scan clock signal applied to the scan clock lines GCK1, GCK2, GCK3, and GCK4 during the first scan period DISPLAY SCAN may be m times the frequency of the scan clock signal applied to the scan clock lines GCK1, GCK2, GCK3, and GCK4 during the second scan period SELF SCAN. Therefore, the length of the second scan signal at the on-level during the first scan period DISPLAY SCAN (the cumulative length of the individual pulses at the on-level) may be the same as the length of the second scan signal at the on-level during the second scan period SELF SCAN.

[0238] Still refer to Figure 17, it can be seen that the cycle period of the scan clock signal during the second scanning cycle SELF SCAN is longer than the cycle period of the scan clock signal during the first scanning cycle DISPLAY SCAN. For example, when m is 4, the cycle period of the scan clock signal during the second scanning cycle SELF SCAN can be 4 times the cycle period of the scan clock signal during the first scanning cycle DISPLAY SCAN. Therefore, according to this embodiment, the power consumption when generating the scan clock signal can be reduced during the second scanning cycle SELF SCAN.

[0239] Figure 18 FIG. 1 is a schematic diagram illustrating a second scan driver 13GB′ according to another embodiment of the present disclosure.

[0240] Figure 18 The second scan drive 13GB' can be Figure 14 The second scan driver 13GB is different in that each of the scan stages (..., GBTn1', GBTn2', GBTn3', GBTn4', GBT(n+1)1', GBT(n+1)2', GBT(n+1)3', GBT(n+1)4', ...) does not include the third input terminal I3.

[0241] refer to Figure 18 The second scan driver 13GB′ according to an embodiment of the present disclosure may include a plurality of scan stages (..., GBTn1′ to GBT(n+1)4′, ...) and a scan stage connection circuit 131. The second scan driver 13GB′ may be connected to the first scan clock line GCK1, the second scan clock line GCK2, the third scan clock line GCK3, and the fourth scan clock line GCK4.

[0242] Each of the scanning stages GBTn1' to GBT(n+1)4' may include a first input terminal I1, a second input terminal I2, and an output terminal O1. The first input terminal I1 may receive a second scanning signal at an on-level output from another scanning stage. However, the first scanning stage (not shown) of the second scanning driver 13GB' may receive a scanning start signal as an on-level pulse type from the timing controller 11 through the first input terminal I1. The second input terminal I2 may be connected to one of the first to fourth scanning clock lines GCK1 to GCK4. The output terminal O1 may output a second scanning signal at an on-level. The output terminal O1 may be connected to the corresponding second scanning line GB. For example, Figure 18The output terminal O1 of the scanning stage GBTn1' connected to the corresponding second scanning line GBn1 is shown. Other output terminals O1 of the scanning stages GBTn2', GBTn3', . . . may also be connected to the corresponding second scanning lines GBn2, GBn3, . . .

[0243] According to an embodiment, two adjacent scan stages may be connected to different scan clock lines. For example, the scan stage GBTn2′ may be connected to the third scan clock line GCK3, and the scan stage GBTn1′ or GBTn3′ adjacent to the scan stage GBTn2′ may be connected to the first scan clock line GCK1.

[0244] m scanning stages may belong to one scanning stage group. m may be an integer greater than 1. m may be a multiple of 2. For example, when m is 2, the nth scanning stage group GBTGn' may include two scanning stages GBTn1' and GBTn2'. When m is 4, the nth scanning stage group GBTGn' may also include two scanning stages GBTn3' and GBTn4'. Now, the connection relationship between the scanning clock lines GCK1 to GCK4 and the scanning stages GBTn3' and GBTn4' may be the same as the connection relationship between the scanning clock lines GCK1 to GCK4 and the scanning stages GBTn1' and GBTn2', respectively. If the number of scanning stages GBT' of each scanning stage group GBTG' is further increased by 2 (i.e., m is further increased by 2), the same connection relationship as the scanning clock line may be adopted for the additional scanning stages. In the following, it will be described assuming that m is 4.

[0245] The nth scanning stage group GBTGn' may include four scanning stages GBTn1', GBTn2', GBTn3', and GBTn4'. In addition, the n+1th scanning stage group GBTG(n+1)' adjacent to the nth scanning stage group GBTGn' may include four other scanning stages GBT(n+1)1', GBT(n+1)2', GBT(n+1)3', and GBT(n+1)4'.

[0246] The scanning stage connection circuit 131 can be connected to Figure 14 The scanning stage connection circuit 131 shown in FIG and described above has the same configuration and operates in the same manner (wherein the scanning stage GBTn1′ replaces the scanning stage GBTn1, the scanning stage GBTn2′ replaces the scanning stage GBTn2, and so on). Therefore, a redundant description of the scanning stage connection circuit 131 is omitted.

[0247] Figure 19 FIG. 1 is a schematic diagram illustrating a scanning stage GBTn1′ according to another embodiment of the present disclosure. Figure 19, the scanning stage GBTn1 ′ may include transistors GT1 , GT2 , GT3 , GT4 , GT5 , GT6 , and GT7 and capacitors GC1 ′, GC2 , and GC3 .

[0248] The first transistor GT1 may have a first electrode connected to the output terminal O1 , a second electrode receiving the second voltage VGL, and a gate electrode connected to the second electrode of the seventh transistor GT7 .

[0249] The first capacitor GC1 ′ may have a first electrode connected to the first electrode of the first transistor GT1 and a second electrode connected to the gate electrode of the first transistor GT1 .

[0250] The second transistor GT2 may have a first electrode receiving the first voltage VGH, a second electrode connected to the output terminal O1 , and a gate electrode connected to the node QBN.

[0251] The third transistor GT3 may have a first electrode connected to the first input terminal I1 , a second electrode connected to the node QN, and a gate electrode connected to the second input terminal I2 .

[0252] The fourth transistor GT4 may have a first electrode receiving the first voltage VGH, a second electrode connected to the node SR_QBN, and a gate electrode connected to the first input terminal I1.

[0253] The second capacitor GC2 may have a first electrode receiving the first voltage VGH and a second electrode connected to the node QBN.

[0254] The fifth transistor GT5 may have a first electrode connected to the node QBN, a second electrode connected to the second input terminal I2, and a gate electrode connected to the node SR_QBN.

[0255] The third capacitor GC3 may have a first electrode connected to the gate electrode of the fifth transistor GT5 and a second electrode connected to the second electrode of the fifth transistor GT5 .

[0256] The sixth transistor GT6 may have a first electrode receiving the first voltage VGH, a second electrode connected to the node QBN, and a gate electrode connected to the node QN.

[0257] The seventh transistor GT7 may have a first electrode connected to the node QN, a second electrode connected to the gate electrode of the first transistor GT1 , and a gate electrode receiving the second voltage VGL.

[0258] Figure 20 It shows Figure 19 Signal / timing diagram of the driving method of the scanning stage GBTn1'.

[0259] refer to Figure 20 , also refer to Figure 18 and Figure 19 At time t1f, the second scanning signal at the on-level (low level) output from the previous scanning stage can be input to the first input terminal I1. At this time, because the first scanning clock signal of the first scanning clock line GCK1 connected to the second input terminal I2 can be at a high level, the third transistor GT3 can be turned off. Therefore, the voltage of the node QN can be maintained.

[0260] At time t2f, the first scan clock signal can be reduced to a low level. Therefore, the third transistor GT3 can be turned on, and the voltage level of the node QN can be reduced to a low level. At this time, because the sixth transistor GT6 is turned on, the voltage level of the node QBN can be increased according to the first voltage VGH. Therefore, the second transistor GT2 can be turned off. In addition, the first transistor GT1 can be turned on, and the second voltage VGL can be applied to the output terminal O1. Therefore, the scanning stage GBTn1' can output the second scan signal at the on-level (low level).

[0261] At time t3f, the second scanning signal at the cut-off level (high level) output from the previous scanning stage can be input to the first input terminal I1. At this time, because the first scanning clock signal of the second input terminal I2 is at a high level, the third transistor GT3 can be cut off. Therefore, the voltage of the node QN can be maintained.

[0262] At time t4f, the first scan clock signal may be reduced to a low level. Therefore, the third transistor GT3 may be turned on, and the voltage level of the node QN may be increased to a high level. Therefore, the first transistor GT1 may be turned off.

[0263] At this time, the voltage of the node QBN connected to the second input terminal I2 can be reduced to a low level by the turned-on fifth transistor GT5. Therefore, the second transistor GT2 can be turned on, and the first voltage VGH can be applied to the output terminal O1. Therefore, the scanning stage GBTn1' can output the second scanning signal at the cut-off level (high level).

[0264] Because it includes Figure 19 The driving method of the second scanning driver 13GB' of the scanning stage GBTn1' is the same as Figure 17 The driving method is the same, so redundant description will be omitted.

[0265] The drawings and description of the present disclosure are intended to be illustrative; they are not intended to limit the meaning or scope of the inventive concept as set forth in the appended claims, but are provided merely to facilitate understanding. Therefore, those skilled in the art will appreciate that various modifications and equivalent other embodiments are possible. Therefore, the scope of the inventive concept should be determined by the appended claims.

Claims

1. A display device, wherein: The display device includes: a first scan driver configured to transmit a plurality of first scan signals at an on-level during a plurality of first scan periods and maintain the plurality of first scan signals at an off-level during a plurality of second scan periods; a light emitting driver configured to transmit a plurality of light emitting signals at an off-level to overlap with the plurality of first scanning signals at the on-level during the plurality of first scanning periods, and to transmit the plurality of light emitting signals at the off-level during the plurality of second scanning periods; and a plurality of pixels configured to receive a plurality of data voltages in response to the plurality of first scan signals at the on-level and to be in a non-emission state in response to the plurality of light emitting signals at the off-level, in, The light-emitting driver includes a plurality of light-emitting stages, During the plurality of first scanning periods, the plurality of light emitting stages sequentially generate the plurality of light emitting signals of the cut-off level in units of one light emitting stage, and During the plurality of second scanning periods, the plurality of light emitting levels sequentially generate the plurality of light emitting signals of the turn-off level in units of m light emitting levels, where m is an integer greater than 1.

2. The display device according to claim 1, wherein The m is a multiple of 2.

3. The display device according to claim 1, wherein The light-emitting driver is connected to a plurality of light-emitting clock lines, the plurality of light-emitting clock lines including a first light-emitting clock line, a second light-emitting clock line, a third light-emitting clock line and a fourth light-emitting clock line, Each of the plurality of light emitting stages comprises: a first input terminal receiving a light emitting signal at the cut-off level output from another light emitting stage among the plurality of light emitting stages; a second input terminal connected to one of the first light-emitting clock line, the second light-emitting clock line, the third light-emitting clock line, and the fourth light-emitting clock line; a third input terminal connected to another one of the first light-emitting clock line, the second light-emitting clock line, the third light-emitting clock line, and the fourth light-emitting clock line, and an output terminal that outputs the light emitting signal at the off level during a portion of each of the plurality of first scanning periods and the plurality of second scanning periods, and Two light emitting stages adjacent to each other among the plurality of light emitting stages are connected to different light emitting clock lines among the first light emitting clock line, the second light emitting clock line, the third light emitting clock line, and the fourth light emitting clock line.

4. The display device according to claim 3, wherein The light-emitting driver includes a first light-emitting stage group and a second light-emitting stage group, The first light-emitting stage group includes m light-emitting stages, The second light-emitting stage group is adjacent to the first light-emitting stage group, and the second light-emitting stage group includes m different light-emitting stages, and The structure in which the second light-emitting stage group is connected to the plurality of light-emitting clock lines is mirror-symmetrical to the structure in which the first light-emitting stage group is connected to the plurality of light-emitting clock lines.

5. The display device according to claim 4, wherein The (m-1)th light emitting stage of the first light emitting stage group has a second input terminal connected to the first light emitting clock line and a third input terminal connected to the second light emitting clock line. The m-th light emitting stage of the first light emitting stage group has a second input terminal connected to the third light emitting clock line and a third input terminal connected to the fourth light emitting clock line, The first light emitting stage of the second light emitting stage group has a second input terminal connected to the fourth light emitting clock line and a third input terminal connected to the third light emitting clock line, and The second light emitting stage of the second light emitting stage group has a second input terminal connected to the second light emitting clock line and a third input terminal connected to the first light emitting clock line. The display device according to claim 5 , wherein: A frequency of the plurality of light emitting clock signals applied to the plurality of light emitting clock lines during the plurality of first scanning periods is m times a frequency of the plurality of light emitting clock signals applied to the plurality of light emitting clock lines during the plurality of second scanning periods.

7. The display device according to claim 6, wherein: During the plurality of first scan periods, a first emission clock signal applied to the first emission clock line is identical to a fourth emission clock signal applied to the fourth emission clock line, and a second emission clock signal applied to the second emission clock line is identical to a third emission clock signal applied to the third emission clock line, and During the plurality of second scanning periods, the first light emitting clock signal is identical to the third light emitting clock signal, and the second light emitting clock signal is identical to the fourth light emitting clock signal.

8. The display device according to claim 1, wherein The light emitting driver further includes a light emitting stage connection circuit configured to receive an enable signal during the plurality of first scanning periods and receive a disable signal during the plurality of second scanning periods. When receiving the enable signal, the light emitting stage connection circuit connects each of the plurality of first input terminals of the plurality of light emitting stages to an output terminal of a corresponding previous light emitting stage, and When receiving the disable signal, the light emitting stage connection circuit connects each of the plurality of first input terminals of the plurality of light emitting stages to an output terminal of a corresponding previous light emitting stage group.

9. The display device according to claim 8, wherein The light-emitting stage connection circuit includes: a plurality of first connection transistors that are turned on upon receiving the enable signal, and each of the plurality of first connection transistors connects a corresponding one of the plurality of first input terminals of the plurality of light emitting stages to the output terminal of the corresponding previous light emitting stage; and A plurality of second connection transistors are turned on when receiving the disable signal, and each of the plurality of second connection transistors connects a corresponding one of the plurality of first input terminals of the plurality of light emitting stages to the output terminal of the corresponding previous light emitting stage group.

10. The display device according to claim 9, wherein Each of the plurality of first connection transistors is one of a P-type transistor and an N-type transistor, Each of the plurality of second connection transistors is the other of a P-type transistor and an N-type transistor, The plurality of gate electrodes of the plurality of first connection transistors and the plurality of gate electrodes of the plurality of second connection transistors are commonly connected to an enable line, The enable signal and the disable signal are applied to the enable line, The enable signal is a bias signal for turning on the plurality of first connection transistors, and The disable signal is a bias signal that turns on the plurality of second connection transistors.

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