Bus clock line handover system and method

Abstract

Systems and methods for bus clock line handoff are disclosed. In one aspect, a clock line in a bus is continuously driven during a bus handoff without providing a contended or conflicting drive signal. After arbitration, the original bus master drives the clock line to a predetermined value until a state change on the data line is detected. The incoming bus master will begin driving the clock line to the predetermined value and then drive a state change on the data line. This state change is the one that is detected by the original bus master that causes the original bus master to stop driving the clock line.

Description

[0001] Priority Application

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 166,171, entitled “BUS CLOCK LINE HANDOVER SYSTEMS AND METHODS,” filed February 8, 2023, which is incorporated by reference herein in its entirety. BACKGROUND

[0003] I. TECHNICAL FIELD

[0004] The technology of the present disclosure generally relates to communication buses and processes for implementing handover between masters after arbitration.

[0005] II. BACKGROUND

[0006] Computing devices, and more specifically mobile communication devices, are ubiquitous in modern society. The popularity of these mobile communication devices is due in part to the many features now enabled on such devices. The increased processing power in such devices means that mobile communication devices have evolved from pure communication tools to sophisticated mobile entertainment centers, enabling an enhanced user experience. As the plethora of features available for such devices has emerged, the circuitry used to provide such features has become more powerful and requires greater power to operate. This increase in power requirements has led to the use of more power management integrated circuits (PMICs) on a single power management bus to manage and balance power sources. This increase in the number of PMICs increases the overall bus length and results in the need to switch control of the bus between various PMICs. Balancing control of the bus between various PMICs creates opportunities for innovation. SUMMARY

[0007] Aspects disclosed in the detailed description include bus clock line handover systems and methods. Specifically, exemplary aspects of the present disclosure enable a clock line in a bus to be continuously driven during a bus handover without providing a contended or conflicting drive signal. After arbitration, the original bus master drives the clock line to a predetermined value until a state change on the data line is detected. The incoming bus master will begin driving the clock line to the predetermined value and then drive a state change on the data line. This state change is the state change detected by the original bus master that causes the original bus master to stop driving the clock line. By having a window of two masters driving the clock line to the same predetermined value, the opportunity for an improper contention on the clock line is reduced or eliminated, thereby reducing the risk of a bus collapse. Furthermore, because the bus is never floating, the opportunity for a slave on the bus to misinterpret a residual charge on the clock line as a clock pulse is reduced.

[0008] In this regard, in one aspect, a master device is disclosed. The master device includes a bus interface coupled to a two-wire communication bus. The master device also includes a control circuit coupled to the bus interface. The control circuit is configured to detect that a data line of the two-wire communication bus is driven from an initial state to a changed state by a second master device. The control circuit is also configured to drive and hold a clock line of the two-wire communication bus at a known state in response to detecting that the data line is driven to the changed state until detecting that the data line is driven back to the initial state by the second master device. The control circuit is also configured to release the clock line in response to detecting that the data line is driven back to the initial state by the second master device.

[0009] In another aspect, a master device is disclosed. The master device includes a bus interface coupled to a two-wire communication bus. The master device also includes a control circuit coupled to the bus interface. The control circuit is configured to drive a data line of the two-wire communication bus from an initial state to a changed state in response to winning an arbitration process. The control circuit is also configured to drive a clock line of the two-wire communication bus to a known state after a predetermined delay. The control circuit is also configured to drive the data line back to the initial state while driving the clock line to the known state. The control circuit is also configured to subsequently transmit a periodic clock signal on the clock line.

[0010] In another aspect, a power management system is disclosed. The power management system includes a two-wire communication bus including a clock line and a data line. The power management system also includes a first master device. The first master device includes a first bus interface coupled to the two-wire communication bus. The first master device also includes a first control circuit coupled to the first bus interface. The first control circuit is configured to detect that the data line is driven from an initial state to a changed state by a second master device. The first control circuit is also configured to drive and hold the clock line at a known state in response to detecting that the data line is driven to the changed state until detecting that the data line is driven back to the initial state by the second master device. The first control circuit is also configured to release the clock line in response to detecting that the data line is driven back to the initial state by the second master device. The power management system also includes a second master device. The second master device includes a second bus interface coupled to the two-wire communication bus. The second master device also includes a second control circuit coupled to the second bus interface. The second control circuit is configured to drive the data line from the initial state to the changed state in response to winning an arbitration process. The second control circuit is also configured to drive the clock line to the known state after a predetermined delay. The second control circuit is also configured to drive the data line back to the initial state while driving the clock line to the known state. The second control circuit is also configured to subsequently transmit a periodic clock signal on the clock line.

[0011] In another aspect, a power management system is disclosed. The power management system includes a two-wire communication bus including a clock line and a data line. The power management system also includes a first master device. The first master device includes a first bus interface coupled to the two-wire communication bus. The first master device also includes a first control circuit coupled to the first bus interface. The first control circuit is configured to drive the clock line to a known state for a first predetermined time period based on a common slowest frequency associated with the two-wire communication bus after losing an arbitration process. The first control circuit is also configured to release the clock line upon expiration of the first predetermined time period. The power management system also includes a second master device. The second master device includes a second bus interface coupled to the two-wire communication bus. The second master device also includes a second control circuit coupled to the second bus interface. The second control circuit is configured to drive the clock line to the known state for a second predetermined time period after a last clock cycle from the first master device based on the common slowest frequency in response to winning the arbitration process. The second control circuit is also configured to transmit a periodic clock signal on the clock line upon expiration of the second predetermined time period. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a block diagram of an exemplary power management system having multiple masters on a single bus;

[0013] Figure 2A is a timing diagram for a power management bus published by MIPI showing a bus handover with arbitration;

[0014] Figure 2B is a timing diagram of voltage levels on a clock line of the bus of Figure 2A

[0015] Figure 3 is a flow diagram showing an exemplary handover process in accordance with aspects of the present disclosure;

[0016] Figure 4 is a timing diagram of signals on a power management bus for a handover showing a process in accordance with Figure 3

[0017] Figure 5 is a flow diagram showing an exemplary handover process in accordance with alternative aspects of the present disclosure;

[0018] Figure 6 is a timing diagram of signals on a power management bus for a handover showing a process in accordance with Figure 5

[0019] Figure 7 is a block diagram of an exemplary mobile computing device that can include a power management bus operating in accordance with aspects of the present disclosure. DETAILED DESCRIPTION​​​

[0020] Several example aspects of the disclosure are now described with reference to the following drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0021] Aspects disclosed in the detailed description include bus clock line handoff systems and methods. Specifically, example aspects of the disclosure enable a clock line in a bus to be continuously driven during a bus handoff without having to provide a contended or conflicting drive signal. After arbitration, the original bus master will drive the clock line to a predetermined value until a state change on the data line is detected. The incoming bus master will begin driving the clock line to the predetermined value and then drive a state change on the data line. This state change is the one that is detected by the original bus master that causes the original bus master to stop driving the clock line. By having a window of two masters driving the clock line to the same predetermined value, the opportunity for an improper contention on the clock line is reduced or eliminated, thereby reducing the risk of a bus collapse. Furthermore, because the bus is never floating, the opportunity for a slave on the bus to misinterpret a residual charge on the clock line as a clock pulse is reduced.

[0022] Prior to addressing example aspects of the disclosure, reference is made to Figure 1 A brief overview of a power management system is provided. Reference is made to Figure 2A and Figure 2B A discussion of potential sources of failure during handoff of a power management system is provided. Reference is made to Figure 3 Discussion of example aspects of the disclosure begins.

[0023] In this regard, Figure 1 is a block diagram of a power management system 100, and more specifically, a system power management interface (SPMI) system. While example aspects of the disclosure are well suited for use with an SPMI system, and the discussion herein is focused on an SPMI system, it should be understood that other communication buses can benefit from the teachings contained herein, and the disclosure is not specifically limited to SPMI.

[0024] The power management system 100 can include a first system on a chip (SoC) 102, a second SoC 104, and a third SoC 106, and a first peripheral device 108 and a second peripheral device 110 coupled to each other by a two-wire communication bus 112 (e.g., an SPMI communication bus). The two-wire communication bus 112 can include a data line (e.g., SDATA) 114 and a clock line (e.g., SCLK) 116. SPMI generally allows up to four masters and up to sixteen slaves as part of an SPMI system. The multiple masters and slaves can reside on a single integrated circuit (IC), on several ICs, or any combination of the two.

[0025] Accordingly, the first SoC 102 can include a clock 118, a first master 120, and a second master 122. The first master 120 can include a bus interface 124 configured to couple to the communication bus 112. The first master 120 can also include a control circuit 126. The second master 122 can also include a bus interface 128 configured to couple to the communication bus 112. The second master 122 can also include a control circuit 130. Note that first and second are used herein as convenient terms to distinguish between different devices. The present disclosure also refers to the devices as original and upcoming devices to distinguish between the devices by temporal action.

[0026] Similarly, the second SoC 104 can include a clock 132 and a master 134. The master 134 can include a bus interface 136 configured to couple to the communication bus 112. The master 134 can also include a control circuit 138. Likewise, the third SoC 106 can include a clock 140 and a master 142. The master 142 can include a bus interface 144 configured to couple to the communication bus 112. The master 142 can also include a control circuit 146. While not central to the present disclosure, the slaves 108, 110 can also include a bus interface, a control circuit, and an optional clock (not shown).

[0027] At different times, different ones of the masters 120, 122, 134, and 142 can need to control the communication bus 112. The SPMI standard published by MIPI defines an arbitration process by which the masters can negotiate a transfer of bus ownership. Figure 2Afrom the MIPI SPMI v.1.0 specification and shows the signals on the data line 114 and clock line 116 arbitrated by a new bus owner controlling the communication bus 112. Specifically, during an idle state, one or more masters (or slaves) can initiate arbitration at point 200. The original master drives the clock line 116 through arbitration (typically at 202) until at the end of arbitration, when a new master has been selected, the original master stops driving the clock line 116 with a final falling edge 204. After the final falling edge 204, the clock line 116 is floating (typically at region 206) until the new master begins driving the data line 114 and clock line 116 at point 208.

[0028] It should be appreciated that the clock line 116 has a natural capacitance as a function of its geometry. After operating with a periodic signal on the clock line 116, this natural capacitance can create a stored voltage on the clock line 116. When the clock line 116 is actively driven, this stored voltage is irrelevant, but when the clock line 116 is floating as in region 206, this stored voltage can manifest as an intermediate level voltage 210 as better shown in FIG. 2B. More specifically, Figure 2B The clock line 116 is shown as a function of time. Region 202 shows the voltage moving between a logical high 212 and a logical low 214, but resting at some intermediate level voltage 210 in region 206 until the clock line 116 is actively driven to a logical low at point 208. Figure 2B The clock line 116 is shown as a function of time. Region 202 shows the voltage moving between a logical high 212 and a logical low 214, but resting at some intermediate level voltage 210 in region 206 until the clock line 116 is actively driven to a logical low at point 208.

[0029] While Figure 2B While there is a relatively flat and stable region 206, there can be instances where the amplitude varies more. In either case, this intermediate level voltage 210 can be misinterpreted as a clock pulse by one or more devices in the system 100. This can cause synchronization to be lost and in extreme cases, cause the communication bus 112 to collapse.

[0030] Exemplary aspects of the present disclosure provide a bus clock line handoff procedure that causes the clock line to be driven throughout the handoff procedure without any adverse contention between the masters driving the clock line. More specifically, exemplary aspects of the present disclosure cause the original master that has bus ownership and that did not win arbitration to continue driving the clock line to a known value for some period of time after the end of arbitration. At a signal from the upcoming master (i.e., the master that won arbitration) on the data line, the original master releases the clock line. The upcoming master starts driving the clock line to the known value concurrently with sending a signal on the data line that causes the original master to release the clock line. The propagation delay of the signal means that for some small window, both the original and upcoming masters are driving the clock line to the known value. Because both masters are driving the clock line to the known value, there is no adverse contention and no window of clock line floating. As noted above, original and upcoming are convenience terms to distinguish the masters based on their timing actions. It should be understood that the original master can be any master that initially has bus ownership, and the upcoming master can be any master that assumes bus ownership such as after winning arbitration.

[0031] Figure 3 is a flowchart of a procedure 300 associated with this handoff procedure. Specifically, the procedure 300 begins when arbitration ends (block 302). Note that the procedure 300 can be triggered by other events (e.g., power-up or reset), but most likely will occur after arbitration. The upcoming master drives the data line from an initial state to a changed state (block 304). This change can occur, for example, at the last rising edge of a clock signal on the clock line, and can involve driving the data line to a logic high. It should be understood that the specific rising and falling edges and logic states are for the purpose of example (and are indicated within dashed boxes in Figure 3 ). The present disclosure is not specifically limited to this example (e.g., the clock signal can end on a falling edge, and the data line can be driven to a logic low). Likewise, while a single transition is envisioned, a sequence of transitions can be used to signal the change in state of the data line.

[0032] After the last falling edge of the clock signal on the clock line and in response to detecting the change in state on the data line, the original master drives the clock line and holds the clock line in a known state (block 306). In exemplary aspects, the known state is a logic low. Note also that the original master can not actually detect the change in state of the data line, but can drive and hold the clock line at the end of arbitration even if the data line does not change state.

[0033] After a predetermined delay, the upcoming master drives the clock line to a known state and changes the data line back to the initial state (block 308). By driving the clock line to the same known state by both the original master and the upcoming master, there is no bad contention on the clock line. Again, the delay of the upcoming master is provided to help ensure that the original master has the clock line in the known state without transient or settling issues. In an example aspect, the predetermined delay is two clock cycles of the internal clock of the upcoming master.

[0034] In response to detecting that the data line returns to its initial state, the original master now releases the clock line (block 310). However, the clock line remains in the known state because the upcoming master has driven the clock line to the known state.

[0035] The upcoming master then begins to transmit a periodic clock signal on the clock line (block 312), and operation continues according to the specification associated with the communication bus (e.g., the SPMI specification).

[0036] It should be appreciated that the processes of the present disclosure apply to systems in which the master is in a single integrated circuit (IC) or distributed across multiple ICs. Thus, as Figure 1 shown, the first and second masters are in a first SoC and thus in a first IC, and the third master is in a second SoC or second IC. Other variations of placement of the master are also contemplated within the present disclosure.

[0037] Figure 4 It is exemplified by Figure 3the clock line 400 at the last rising edge 408, the incoming master changes the data line 402 from an initial state 410 to a changed state 412 (e.g., logic low to logic high). At the last falling edge 414, the original master drives the clock line 400 and holds it at logic low. The incoming master waits for two internal clock cycles (shown at 416) and then drives the clock line 400 to a known state and restores 418 the data line 402 back to its initial logic state (e.g., logic low, shown at 410A). The change on the data line 402 is delayed by some small propagation delay before reaching the original master. During this time 420, both the original master and the incoming master drive the clock line 400 to a known state. When the original master receives the state change on the data line 402, the original master releases the clock line 400. After some additional delay (e.g., one internal clock cycle), the incoming master begins to transmit periodic signals on the clock line 400 as well as commands and / or data on the data line 402.

[0038] The process 300 has the advantage of being indifferent to the frequency difference of the clock signals generated by the original master and the incoming master. That is, the original master drives the clock line 400 until a state change in the data line is detected that indicates that the incoming master is also driving the clock line 400. If the incoming master has a faster or slower internal clock, the behavior of the original master does not change.

[0039] While the process 300 has advantages, the present disclosure is not limited thereto. Figure 5 Another example process 500 is illustrated in FIG. 5 that takes into account the frequencies of the devices on the bus. In this regard, the process 500 begins with the respective frequencies of all devices on the shared communication bus (block 502). This information can be programmed into memory associated with the control circuit at manufacture; read from configuration registers as part of an enumeration or other initialization process; or provided by any device joining the communication bus in a system broadcast. From the set of frequencies, a common slowest frequency can be determined. This is the slowest frequency to be used by any device that will drive the clock line. For example, if three masters are at 20 megahertz (MHz) but one is at 10 MHz, the common slowest frequency is 10 MHz.

[0040] The operation continues and at some point there is an arbitration phase, which ends (block 504). The original master, using the clock signal from the clock or clock source, drives the clock line to a known state for a first time period equal to a predetermined number of cycles of the common slowest frequency (block 506). In an example aspect, this is two cycles.

[0041] The upcoming master detects the last falling edge of the clock signal from the original master and drives the clock line to a known state for a second time period equal to a second predetermined number of cycles of the common slowest frequency (block 508). In an example aspect, the second predetermined number of cycles is two or more. The upcoming master will not begin driving the clock signal until after the last falling edge is detected, which arrives at the upcoming master after some propagation delay, and thus the upcoming master will not begin driving until after the original master has driven the clock line to a known state, ensuring no bad contention. The upcoming master will then continue to hold the clock line in the known state while the original master releases the clock line before the second predetermined time period expires (block 510). This release by the original master before the second predetermined time period expires also helps to ensure no bad contention. The upcoming master then begins transmitting a periodic clock signal on the clock line (block 512).

[0042] Figure 6 A timing diagram of the signals of the internal clocks of the process 500 relative to Figure 5 is provided. Specifically, the original master has a first internal clock 600 and the upcoming master has a second internal clock 602. At the end of the arbitration, the original master has a final falling edge 604, then drives the clock line and holds it at logic low for a time period X corresponding to two cycles of the slowest common frequency. Upon detecting the final falling edge 604 (i.e., after time Y), the upcoming master begins driving the clock line to a known state for a time period Z. There will be an overlap period 608 in which both masters drive the clock line to a known state.

[0043] Because the process 500 relies on the slowest common frequency, the process 500 can introduce additional latency when the handoff is between two fast masters. In contrast, the process 300 does not have this latency.

[0044] Bus clock line handoff systems and methods in accordance with aspects disclosed herein can be provided in or integrated into any processor-based device. Non-limiting examples include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a transportation component, avionics systems, a drone, and a multicopter.

[0045] As further context, Figure 7 An illustration of an SPMI bus in a mobile computing device is provided. In this regard, Figure 7 is a system-level block diagram of an example mobile terminal 700 such as a smart phone, a mobile computing device tablet, etc. While a mobile terminal having an SPMI bus is specifically contemplated as an example mobile terminal that can benefit from example aspects of the present disclosure, it should be understood that the present disclosure is not so limited and can be used in any system having a two-wire communication bus with multiple masters.

[0046] With continued reference to Figure 7 , the mobile terminal 700 includes an application processor 704 (sometimes referred to as a host) that communicates with a mass storage element 706 over a universal flash storage (UFS) bus 708. The application processor 704 can further be connected to a display 710 over a display serial interface (DSI) bus 712 and to a camera 714 over a camera serial interface (CSI) bus 716. Various audio elements such as a microphone 718, a speaker 720, and an audio codec 722 can be coupled to the application processor 704 over a serial low-power inter-chip multimedia bus (SLIMbus) 724. Additionally, the audio elements can communicate with one another over a SOUNDWIRE bus 726. A modem 728 can also be coupled to the SLIMbus 724 and / or the SOUNDWIRE bus 726. The modem 728 can further be connected to the application processor 704 over a peripheral component interconnect (PCI) or peripheral component interconnect express (PCIe) bus 730 and / or a system power management interface (SPMI) bus 732.

[0047] With continued reference to Figure 7The SPMI bus 732 can also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) 734, one or more power management integrated circuits (PMICs, only one shown) 736, a companion IC (sometimes referred to as a bridge chip) 738, and a radio frequency IC (RFIC) 740. It should be understood that separate PCI buses 742 and 744 can also couple the application processor 704 to the companion IC 738 and the WLAN IC 734, respectively. The application processor 704 can further be connected to sensors 746 through a sensor bus 748. The modem 728 and the RFIC 740 can communicate using a bus 750.

[0048] With continued reference to Figure 7 The RFIC 740 can be coupled to one or more radio frequency front end (RFFE) elements, such as an antenna tuner 752, a switch 754, and a power amplifier 756, through an RFFE bus 758. Additionally, the RFIC 740 can be coupled to an envelope tracking power supply (ETPS) 760 through a bus 762, and the ETPS 760 can be in communication with the power amplifier 756. Together, these RFFE elements (including the RFIC 740) can be considered an RFFE system 764. It should be understood that the RFFE bus 758 can be formed of a clock line and a data line (not illustrated).

[0049] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium, and / or combinations of both. To clearly illustrate this interchangeability of hardware and instructions, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented, including the particular

[0050] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field- Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0051] The aspects disclosed herein can be embodied in hardware and in instructions stored in hardware, and can reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a remote station. In the alternative, the processor and the storage medium can reside as discrete components in a remote station, a base station, or a server.

[0052] Note also that the operations described in any of the example aspects presented herein are described for illustrative purposes and are not meant to be limiting. The operations described can be performed in many different sequences than illustrated. Further, an operation described in a single operation step can be performed in multiple different steps. Additionally, one or more operation steps discussed in an example aspect can be combined. It will be understood by those skilled in the art that numerous modifications can be made to the procedures illustrated in the flowcharts. It will also be understood by those skilled in the art that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0053] The foregoing description of the present disclosure has been provided in order to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations. Thus, the present disclosure is not intended to be limited to the example and design described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0054] Various implementation examples are described in the following numbered clauses:

[0055] 1. A master device, the master device comprising:

[0056] a bus interface coupled to a two-wire communication bus; and a control circuit coupled to the bus interface and configured to:

[0057] detect that a data line of the two-wire communication bus is driven from an initial state to a changed state by a second master device;

[0058] in response to detecting that the data line is driven to the changed state, drive and hold a clock line of the two-wire communication bus in a known state until detecting that the data line is driven back to the initial state by the second master device; and in response to detecting that the data line is driven back to the initial state by the second master device, release the clock line.

[0059] 2. The master device of clause 1, wherein the control circuit is configured to detect that the data line is driven to the changed state after an arbitration process, wherein a power management device did not win the arbitration process.

[0060] 3. The master device of clause 1 or 2, wherein the bus interface comprises a power management bus interface.

[0061] 4. The master device of any of clauses 1-3, wherein the control circuit is configured to have ownership of the two-wire communication bus until the clock line is released.

[0062] 5. The master device of any of clauses 1-4, integrated into a system on a chip (SoC).

[0063] 6. The master device of any of clauses 1-5, wherein the initial state is a logical low and the changed state is a logical high.

[0064] 7. The master device of any of clauses 1-6, wherein the known state is a logical low.

[0065] 8. A master device, the master device comprising:

[0066] a bus interface coupled to a two-wire communication bus; and

[0067] a control circuit coupled to the bus interface and configured to:

[0068] in response to winning an arbitration process, drive a data line of the two-wire communication bus from an initial

[0069] state to a changed state;

[0070] after a predetermined delay, drive a clock line of the two-wire communication bus to a known

[0071] state;

[0072] while driving the clock line to the known state, drive the data line

[0073] back to the initial state; and

[0074] subsequently transmit a periodic clock signal on the clock line.

[0075] 9. The master device of clause 8, wherein the control circuit is configured to drive the data line to a logic high on a last rising edge of a clock signal from a second master device.

[0076] 10. The master device of clause 8 or 9, further comprising a clock source, and wherein the predetermined delay comprises two clock periods from the clock source.

[0077] 11. The master device of any of clauses 8-10, wherein the known state comprises a logic low.

[0078] 12. The master device of any of clauses 8-11, wherein the bus interface comprises a power management bus interface.

[0079] 13. The master device of any of clauses 8-12, wherein the control circuit is configured to assume ownership of the two-wire communication bus by driving the clock line to the known state.

[0080] 14. The master device of any of clauses 8-13, integrated into a system on a chip (SoC).

[0081] 15. A power management system, the power management system comprising:

[0082] a two-wire communication bus comprising a clock line and a data line;

[0083] a first master device comprising:

[0084] a first bus interface coupled to the two-wire communication bus; and

[0085] a first control circuit coupled to the first bus interface and configured to:

[0086] detect the data line being driven from an initial state to a changed state by a second master device;

[0087] in response to detecting the data line being driven to the changed state, drive and hold the clock line in a known state until detecting the data line being driven back to the initial state by the second master device, and in response to detecting the data line being driven back to the initial state by the second master device, release the clock line; and

[0088] the second master device, the second master device comprising:

[0089] a second bus interface coupled to the two-wire communication bus; and

[0090] a second control circuit coupled to the second bus interface and configured to:

[0091] in response to winning an arbitration process, drive the data line from the initial state to the changed state;

[0092] after a predetermined delay, drive the clock line to the known state;

[0093] while driving the clock line to the known state, drive the data line back to the initial state; and

[0094] subsequently transmit a periodic clock signal on the clock line.

[0095] 16. The power management system of clause 15, wherein the two-wire communication bus, the first master device, and the second master device are integrated into a single system on a chip (SoC).

[0096] 17. The power management system of clause 15, wherein the first master device comprises a first integrated circuit (IC) and the second master device comprises a second IC, the second IC being different from the first IC and coupled to the first IC through the two-wire communication bus.

[0097] 18. The power management system of any one of clauses 15 to 17, wherein the two-wire communication bus comprises a power management communication bus.

[0098] 19. A power management system, the power management system comprising:

[0099] a two-wire communication bus including a clock line and a data line;

[0100] a first master device, the first master device comprising:

[0101] a first bus interface coupled to the two-wire communication bus

[0102] and a first control circuit coupled to the first bus interface

[0103] and configured to:

[0104] after losing an arbitration process, drive the clock line to a known state for a first predetermined time period based on a common slowest frequency associated with the two-wire communication bus; and

[0105] upon expiration of the first predetermined time period, release the clock line; and

[0106] after winning the arbitration process, drive the clock line to the known state for a second predetermined time period based on the common slowest frequency after a last clock cycle from the first master device; and upon expiration of the second predetermined time period, transmit a periodic clock signal on the clock line.

[0107] a second master device, the second master device comprising:

[0108] a second bus interface coupled to the two-wire communication bus

[0109] and a second control circuit coupled to the second bus interface

[0110] and configured to:

[0111] after winning the arbitration process, drive the clock line to the known state for a second predetermined time period based on the common slowest frequency after a last clock cycle from the first master device; and upon expiration of the second predetermined time period, transmit a periodic clock signal on the clock line.

[0112]

[0113] 20. The power management system of clause 19, wherein the first predetermined time period comprises two clock cycles of the common slowest frequency.

[0114] 21. The power management system of clause 19 or 20, wherein the second predetermined time period comprises two clock cycles of the common slowest frequency.

[0115] 22. The power management system of any one of clauses 19 to 21, wherein the first master device and the second master device are both configured to drive the clock line to the known state during an overlapping time period that ends prior to expiration of the second predetermined time period.

[0116] ​23. The power management system of any of Clauses 19-22, further comprising a first memory in the first master device, wherein the first memory is configured to store the common slowest frequency.

[0117] 24. The power management system of Clause 23, wherein the first memory is configured to store the common slowest frequency in response to a system broadcast when a master device joins the two-wire communication bus.

[0118] 25. The power management system of any of Clauses 19-24, wherein the two-wire communication bus comprises a power management communication bus.

[0119] 26. The power management system of any of Clauses 19-25, wherein the first master device, the second master device, and the two-wire communication bus are integrated into a single system on a chip (SoC).

[0120] 27. The power management system of any of Clauses 19-25, wherein the first master device comprises a first integrated circuit (IC) and the second master device comprises a second IC, the second IC being different from the first IC and coupled to the first IC through the two-wire communication bus.

Claims

1. A main device, the main device comprising: A bus interface coupled to a two-wire communication bus; and Control circuitry, coupled to the bus interface and configured to: The data line of the two-wire communication bus is detected by the second master device from its initial state to a changed state. In response to detecting that the data line is driven to the changed state, the clock line of the two-wire communication bus is driven and held in a known state until the data line is detected to be driven back to the initial state by the second master device; as well as In response to detecting that the data line has been driven back to the initial state by the second master device, the clock line is released.

2. The main device of claim 1, wherein the control circuitry is configured to detect, after the arbitration process, that the data line is driven to the changed state, wherein the power management device did not win the arbitration process.

3. The main device according to claim 1, wherein the bus interface includes a power management bus interface.

4. The master device of claim 1, wherein the control circuitry is configured to have ownership of the two-wire communication bus until the clock line is released.

5. The main device according to claim 1, wherein the main device is integrated into a system-on-a-chip (SoC).

6. The master device according to claim 1, wherein the initial state is logic low and the changed state is logic high.

7. The master device according to claim 1, wherein the known state is logic low.

8. A main device, the main device comprising: A bus interface coupled to a two-wire communication bus; and Control circuitry, coupled to the bus interface and configured to: In response to winning the arbitration process, the data lines of the two-wire communication bus are driven from the initial state to the changed state; After a predetermined delay, the clock line of the two-wire communication bus is driven to a known state; While driving the clock line to the known state, the data line is driven back to the initial state; as well as A periodic clock signal is then transmitted on the clock line.

9. The master device of claim 8, wherein the control circuitry is configured to drive the data line to logic high on the last rising edge of a clock signal from the second master device.

10. The master device of claim 8, further comprising a clock source, wherein the predetermined delay comprises two clock cycles from the clock source.

11. The master device of claim 8, wherein the known state includes logic low.

12. The master device according to claim 8, wherein the bus interface includes a power management bus interface.

13. The master device of claim 8, wherein the control circuitry is configured to assume ownership of the two-wire communication bus by driving the clock line to the known state.

14. The main device according to claim 8, wherein the main device is integrated into a system-on-a-chip (SoC).

15. A power management system, the power management system comprising: A two-wire communication bus, the two-wire communication bus including a clock line and a data line; The first master device includes: A first bus interface, the first bus interface being coupled to the two-wire communication bus; and A first control circuit, coupled to the first bus interface and configured to: The data line is detected to be driven from an initial state to a changed state by the second master device; In response to detecting that the data line is driven to the changed state, the clock line is driven and held in a known state until the data line is detected to be driven back to the initial state by the second master device; and In response to detecting that the data line has been driven back to the initial state by the second master device, the clock line is released; and The second master device includes: A second bus interface, coupled to the two-wire communication bus; and A second control circuit, coupled to the second bus interface and configured to: In response to winning the arbitration process, the data line is driven from the initial state to the changed state; After a predetermined delay, the clock line is driven to the known state; While driving the clock line to the known state, the data line is driven back to the initial state; and A periodic clock signal is then transmitted on the clock line.

16. The power management system of claim 15, wherein the two-wire communication bus, the first master device, and the second master device are integrated into a single system-on-chip (SoC).

17. The power management system of claim 15, wherein the first master device includes a first integrated circuit (IC), and the second master device includes a second IC, the second IC being different from the first IC and coupled to the first IC via the two-wire communication bus.

18. The power management system of claim 15, wherein the two-wire communication bus includes a power management communication bus.

19. A power management system, the power management system comprising: A two-wire communication bus, the two-wire communication bus including a clock line and a data line; The first master device includes: A first bus interface, the first bus interface being coupled to the two-wire communication bus; and A first control circuit, coupled to the first bus interface and configured to: After losing the arbitration process, the clock line is driven to a known state for a first predetermined time period based on the slowest common frequency associated with the two-wire communication bus; and Release the clock line when the first predetermined time period expires; and The second master device includes: A second bus interface, coupled to the two-wire communication bus; and A second control circuit, coupled to the second bus interface and configured to: In response to winning the arbitration process, the clock line is driven to the known state for a second predetermined time period based on the common slowest frequency after the last clock cycle from the first master device; and When the second predetermined time period expires, a periodic clock signal is transmitted on the clock line.

20. The power management system of claim 19, wherein the first predetermined time period comprises two clock cycles of the common slowest frequency.

21. The power management system of claim 19, wherein the second predetermined time period comprises two clock cycles of the common slowest frequency.

22. The power management system of claim 19, wherein both the first master device and the second master device are configured to drive the clock line to the known state during an overlapping period that ends before the second predetermined time period expires.

23. The power management system of claim 19, further comprising a first memory in the first master device, wherein the first memory is configured to store the common slowest frequency.

24. The power management system of claim 23, wherein the first memory is configured to store the common slowest frequency in response to a system broadcast when a master device joins the two-wire communication bus.

25. The power management system of claim 19, wherein the two-wire communication bus includes a power management communication bus.

26. The power management system of claim 19, wherein the first master device, the second master device and the two-wire communication bus are integrated into a single system-on-chip (SoC).

27. The power management system of claim 19, wherein the first master device includes a first integrated circuit (IC), and the second master device includes a second IC, the second IC being different from the first IC and coupled to the first IC via the two-wire communication bus.

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