Generating text using one or more neural networks

Abstract

The present disclosure relates to generating text using one or more neural networks. Apparatuses, systems, and techniques for summarizing text with one or more neural networks are disclosed. In at least one embodiment, a processor is configured to cause one or more neural networks to generate one or more digests of a first portion of text based at least in part on one or more second portions of the text.

Description

Technical Field

[0001] At least one embodiment involves using a neural network to summarize text. For example, at least one embodiment involves using a neural network to generate a text summary that summarizes an audio transcript. Background Art

[0002] Speech-to-text transcription services use audio transcripts to generate text summaries, but these services can sometimes be inaccurate due to the complexity of these meeting transcripts, such as contextual nuances. For example, information from the audio transcript may not clearly indicate which speaker is speaking. Therefore, improvements can be made to better generate text summaries. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A system for summarizing an audio transcript of a multi-party conference is shown in accordance with at least one embodiment;

[0004] Figure 2 is a block diagram illustrating an audio file preprocessor according to at least one embodiment;

[0005] Figure 3 is a sequence diagram illustrating the interaction between a prompt generator and a neural network according to at least one embodiment;

[0006] Figure 4 is a block diagram illustrating the use of a neural network to generate a text summary according to at least one embodiment;

[0007] Figure 5A is a flow chart illustrating an example process for priming a neural network to generate a summary of a portion of an audio transcript in accordance with at least one embodiment;

[0008] Figure 5B is a flowchart illustrating an example process for initiating a neural network to generate a summary of text in accordance with at least one embodiment;

[0009] Figure 6 is a flowchart illustrating a process for generating a text summary using a neural network according to at least one embodiment;

[0010] Figure 7 is a block diagram illustrating a system for generating a text summary from an audio file according to at least one embodiment;

[0011] Figure 8 is a flow chart illustrating a process for generating a text summary from an audio file according to at least one embodiment;

[0012] Figure 9is an example illustrating a processor and modules according to at least one embodiment;

[0013] Figure 10 is a block diagram illustrating a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment;

[0014] Figure 11A illustrates logic according to at least one embodiment;

[0015] Figure 11B illustrates logic according to at least one embodiment;

[0016] Figure 12 illustrates the training and deployment of a neural network according to at least one embodiment;

[0017] Figure 13 An example data center system is shown in accordance with at least one embodiment;

[0018] Figure 14A An example of an autonomous vehicle according to at least one embodiment is shown;

[0019] Figure 14B According to at least one embodiment, Figure 14A Examples of camera positions and fields of view for autonomous vehicles;

[0020] Figure 14C is a diagram showing a method according to at least one embodiment Figure 14A A block diagram of an example system architecture for an autonomous vehicle;

[0021] Figure 14D is a diagram illustrating a method for one or more cloud-based servers and Figure 14A A diagram of a system for communicating between autonomous vehicles;

[0022] Figure 15 is a block diagram illustrating a computer system according to at least one embodiment;

[0023] Figure 16 is a block diagram illustrating a computer system according to at least one embodiment;

[0024] Figure 17 A computer system according to at least one embodiment is shown;

[0025] Figure 18 A computer system according to at least one embodiment is shown;

[0026] Figure 19A A computer system according to at least one embodiment is shown;

[0027] Figure 19B A computer system according to at least one embodiment is shown;

[0028] Figure 19C A computer system according to at least one embodiment is shown;

[0029] Figure 19D A computer system according to at least one embodiment is shown;

[0030] Figure 19E and Figure 19F illustrates a shared programming model according to at least one embodiment;

[0031] Figure 20 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0032] Figure 21A and Figure 21B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0033] Figure 22A and Figure 22B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0034] Figure 23 A computer system according to at least one embodiment is shown;

[0035] Figure 24A A parallel processor according to at least one embodiment is shown;

[0036] Figure 24B shows a partition unit according to at least one embodiment;

[0037] Figure 24C illustrates a processing cluster according to at least one embodiment;

[0038] Figure 24D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0039] Figure 25 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0040] Figure 26 A graphics processor according to at least one embodiment is shown;

[0041] Figure 27 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0042] Figure 28 A deep learning application processor according to at least one embodiment is shown;

[0043] Figure 29 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0044] Figure 30 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0045] Figure 31 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0046] Figure 32 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0047] Figure 33 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0048] Figure 34 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0049] Figure 35A and Figure 35B Thread execution logic including an array of processing elements of a graphics processor core is shown in accordance with at least one embodiment;

[0050] Figure 36 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0051] Figure 37 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0052] Figure 38 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0053] Figure 39 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0054] Figure 40 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0055] Figure 41 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment;

[0056] Figure 42 includes an example illustration of a high-level computational pipeline for processing imaging data in accordance with at least one embodiment;

[0057] Figure 43A including an example data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0058] Figure 43B An example data flow diagram including a virtual instrument supporting a CT scanner according to at least one embodiment;

[0059] Figure 44A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment;

[0060] Figure 44B is an example illustration of a client-server architecture for enhancing an annotation tool using a pre-trained annotation model in accordance with at least one embodiment; and

[0061] Figure 45 Components of a system for accessing large language models in accordance with at least one embodiment are shown. DETAILED DESCRIPTION

[0062] This document describes a processor, system, method, and / or computer program product for generating a summary of text using one or more neural networks. In at least one embodiment, the text is an audio transcript of a meeting. In at least one embodiment, at least one of the one or more neural networks is a large language model (LLM).

[0063] In at least one embodiment, one or more software components divide an audio track of an audio or video recording of a meeting into multiple segments and transcribe the audio segments into different transcripts. In at least one embodiment, each of the different transcripts is a portion of text generated from the meeting. In at least one embodiment, the one or more software components generate a prompt to instruct one or more neural networks to use one portion of the text to summarize another portion of the text. In at least one embodiment, the one or more neural networks generate a summary of each portion of the text, where each portion is summarized using one or more previous portions as context. In at least one embodiment, the context is provided by one or more previous portions or one or more summaries of the portion.

[0064] In at least one embodiment, once all portions of the text have been summarized, the one or more software components combine the individual summaries of the different portions of the text into a combined summary and provide the combined summary to the one or more neural networks. In at least one embodiment, the one or more software components provide the combined summary to the neural network via one or more prompts. In at least one embodiment, the one or more neural networks generate outputs in various desired formats. In at least one embodiment, each output is generated in response to one or more prompts that include the combined summary and one or more instructions specifying a desired output format. In at least one embodiment, the desired output format is specified in a separate startup prompt for each output.

[0065] Figure 1 A system 100 for summarizing audio transcripts of a multi-party conference is shown in accordance with at least one embodiment. In at least one embodiment, a conference summary generator 104 is executed by one or more processors 106 in the system 100. In at least one embodiment, each of the one or more processors 106 is a central processing unit (CPU), a graphics processing unit (GPU), a parallel processing unit (PPU), a general purpose graphics processing unit (GPGPU), a computing cluster, and / or a combination of these and / or other such processors. In at least one embodiment, the computer system 101 is a processor such as a processor incorporating a processor. Figure 11A and Figure 11B or Figure 13 Describe the computer system.

[0066] In at least one embodiment, the meeting summary generator 104 is a software module that encapsulates several software components 105, 107, and 109, which combine to generate a text summary 111 of the meeting text recorded in the audio file 103. In at least one embodiment, each of these software components 105, 107, and 109 includes a plurality of program instructions for performing one or more functions. In at least one embodiment, the software component 109 is a neural network, such as a large language model, a recurrent neural network (RNN), a long short-term memory network (LSTM), and a sequence-to-sequence (Seq2Seq) model.

[0067] In at least one embodiment, audio file 103 is an audio recording of a conference in which one or more speakers speak. In at least one embodiment, the audio recording can be in a variety of formats, such as MP3 (MPEG audio layer) and WAV (Waveform Audio File Format). In at least one embodiment, audio file 103 can also be the audio track of a video recording of one or more participants.

[0068] In at least one embodiment, a text summary 111 is generated by the neural network 109 to summarize the text of the meeting. In at least one embodiment, the one or more prompts include instructions to generate a text summary 111 that uses one of a variety of formats, including a summary of a predetermined length, a topic summary, a speaker-by-speaker summary, or a summary of the top N topics. In at least one embodiment, the summary of the predetermined length includes a fixed number of words or pages, such as a 300-word summary. In at least one embodiment, the topic summary is organized around the main topics or themes of the discussion. In at least one embodiment, the speaker-by-speaker summary provides a brief overview of the main points or contributions of each speaker. In at least one embodiment, the summary of the top N topics is a summary that covers the N (e.g., 5) most important topics in the meeting transcript. In at least one embodiment, these formats are provided for illustration purposes only, and other formats may also be used.

[0069] In at least one embodiment, the audio file preprocessor 105 includes a plurality of computer-executable program instructions that, when executed by one or more processors 106, perform the function of preprocessing the audio file 103. In at least one embodiment, the preprocessing includes segmenting the audio track in the audio file into track segments at a time instance or a point where a pause is detected, transcribing each of the track segments into an audio transcript, and modifying each transcript. In at least one embodiment, modifying the transcript includes punctuating and capitalizing the transcripts, and adding timestamps to the transcripts of the track segments. In at least one embodiment, each audio transcript is a portion of the text of the audio track in the audio file 103. In at least one embodiment, the preprocessing includes transcribing the audio track into a transcript, adjusting punctuation, capitalizing the transcript, adding timestamps to the transcript, and then segmenting the transcript into different portions.

[0070] In at least one embodiment, these portions of the transcript are stored in storage 112. In at least one embodiment, storage 112 is one of a variety of storage types, such as cache, RAM, and a database.

[0071] In at least one embodiment, prompt generator 107 includes a plurality of computer-executable program instructions that, when executed by one or more processors 106, perform the function of generating one or more prompts for neural network 109. In at least one embodiment, each of the one or more prompts includes at least a portion of the text to be summarized and one or more instructions for initiating neural network 109 to generate an output in a desired format. In at least one embodiment, the one or more instructions are used to customize the output of neural network 109 to a specific format. In at least one embodiment, an example of such an instruction is "generate a 100-word summary."

[0072] In at least one embodiment, the prompt generator 107 sends these prompts to the neural network 109 one by one and receives a summary of each text portion.

[0073] In at least one embodiment, at least one of the one or more prompts includes, in addition to the portion of text to be summarized and one or more formatting instructions, one or more summaries of previous portions. In at least one embodiment, at least one of the one or more prompts includes, in addition to the portion of text to be summarized and one or more formatting instructions, one or more previous portions. In at least one embodiment, these previous summaries or previous text portions in the prompt provide context for the neural network 109 when summarizing the current portion of text in the prompt.

[0074] In one embodiment, prompt generator 107 checks whether any word in the generated prompt exists as a key in dictionary 108. If the word is a key in dictionary 108, prompt generator 107 replaces it with the corresponding definition in the dictionary within prompt generator 107. In at least one embodiment, dictionary 108 contains key-value pairs, where the key is the word (e.g., abbreviations, acronyms, and jargon) and the value is its definition, for example, in the format of JavaScript Object Notation (JSON), Extensible Markup Language (XML), or text. In at least one embodiment, dictionary 108 may include one or more words that the organization does not want to use in the meeting summary. In at least one embodiment, such words may be considered immoral or biased towards certain ethnic groups. In at least one embodiment, the dictionary is used as an example of a data structure for storing such mappings. In at least one embodiment, other data structure examples include hash tables, hash maps, and arrays. In at least one embodiment, dictionary 108 can be replaced by a relational database.

[0075] In at least one embodiment, the neural network 109 is a large language model (LLM), such as a generative pre-trained transformer.

[0076] Figure 2 is a block diagram 200 illustrating an audio file preprocessor 205 according to at least one embodiment. In at least one embodiment, the audio file preprocessor 205 corresponds to a Figure 1 In at least one embodiment, the audio file preprocessor 205 includes a plurality of software components 207, 210, and 211 for preprocessing the audio file (e.g., in conjunction with Figure 1 Audio transcripts of the different track segments of the audio file 103) described.

[0077] In at least one embodiment, the track splitter 207 comprises a set of computer executable program instructions that, when executed by one or more processors (e.g., in conjunction with Figure 1 When executed by the processor 106 described above, the audio track segmenter 207 can detect pause points in the audio track and segment the audio track into multiple segments at these detected pauses. In at least one embodiment, the audio track segmenter 207 calls an audio processing API or a signal processing library (e.g., SciPy, a mathematical library from Python, and the signal processing toolbox of MATLAB) or one or more machine learning models to perform audio analysis to detect pause points in the audio track.

[0078] In at least one embodiment, pause points are identified when a new speaker begins speaking or at the end of a sentence. In at least one embodiment, the audio track segmenter 207 scans the audio waveform within the audio track, searching for intervals without speech or substantial sound to determine moments of silence. In at least one embodiment, each identified period of silence is characterized by two criteria. In at least one embodiment, the first criterion is that the duration of silence exceeds a predetermined threshold, such as 2 seconds. In at least one embodiment, the second criterion is that the energy level of the signal (which indicates the loudness or intensity of the sound) drops below a specified threshold, such as 0.05%. In at least one embodiment, for this second criterion, the audio file segmenter 207 establishes a low energy threshold, such as 0.05%, which means that any sound with an energy level below this percentage is considered silence, rather than speech or background noise.

[0079] In at least one embodiment, transcriber 210 comprises a set of computer-executable program instructions that, when executed by one or more processors (e.g., in conjunction with Figure 1 When executed by the processor 106 described above, each audio track segment is transcribed into an audio transcript. In at least one embodiment, the transcriber 210 includes one or more program instructions that call an application programming interface (API) of an automatic speech recognition (ASR) model to perform the transcription of the audio track segment. In at least one embodiment, the ASR model is a large language model (LLM).

[0080] In at least one embodiment, text normalizer 211 comprises a set of computer-executable program instructions that, when executed by one or more processors (e.g., in conjunction with Figure 1 When executed by the processor 106 described above, the transcript of each audio track segment can be normalized by punctuating and capitalizing the first letter of the transcript. In at least one embodiment, the text normalizer 211 also adds the speaker to its corresponding utterance and adds timestamps to these utterances. In at least one embodiment, these timestamps are relative times that indicate the position of the audio content relative to the beginning of the audio track.

[0081] Figure 3 is a sequence diagram illustrating the interaction between the prompt generator 307 and the neural network 309 according to at least one embodiment. In at least one embodiment, the prompt generator 307 corresponds to Figure 1 The prompt generator 107 described in the above, the neural network 309 corresponds to Figure 1 The neural network described in 109. Figure 3 Also shown is an audio file pre-processor 305, which corresponds to Figure 1 The audio file preprocessor 105 described in .

[0082] In at least one embodiment, the cue generator 307 prepares (primes) 310 the neural network 309 with a startup cue, which will Figure 5A and Figure 5B In at least one embodiment, the prompt generator 307 receives the portion A 311 from the audio file preprocessor 305. In at least one embodiment, the portion A 311 is as described in conjunction with Figure 2 In at least one embodiment, the prompt generator 307 constructs 312 a prompt 313 using the portion A 311 and provides the prompt 313 to the neural network 309 as input. In at least one embodiment, the prompt 313 includes the portion A 311 and one or more instructions that instruct the neural network 400 to generate a summary 315 of the portion A 311 in a desired format. In at least one embodiment, the desired format is, for example, a combination of Figure 1 A format similar to the format used by the text summary 111 described above.

[0083] In at least one embodiment, prompt generator 307 stores summary 315 in a storage device, such as in conjunction with Figure 1The storage device 112 is described. In at least one embodiment, the prompt generator 307 then receives part B 317, which is a transcript of another audio track segment. In at least one embodiment, the prompt generator 307 retrieves the summary 315 from the storage device and uses the retrieved summary 315 and part B 317 to construct 318 a prompt 319. In at least one embodiment, the prompt 319 includes the summary 315, part B 317, and one or more instructions instructing the neural network 309 to generate the summary 321 in a desired format. In at least one embodiment, the summary 315 in the prompt 319 provides contextual information for the neural network 309 to use when summarizing part B 317. In at least one embodiment, the prompt generator 307 uses part A 311 and part B 317 and one or more instructions to construct 318 the prompt 319, wherein part A 311 (rather than the summary 315 of part A 311) is used to provide contextual information to the neural network 309.

[0084] In at least one embodiment, prompt generator 307 saves summary 321 to the storage device. In at least one embodiment, after receiving subsequent portion N 323, prompt generator 307 retrieves summary 321 from the storage device and constructs 325 prompt 327. In at least one embodiment, portion N 323 is a transcript of the last track segment of an audio track extracted from an audio file (e.g., audio file 103). In at least one embodiment, prompt generator 307 retrieves both summary 315 and summary 321 and embeds these summaries along with portion N 323 to be summarized into prompt 327. In at least one embodiment, prompt generator 307 constructs prompt 327 to include portion N 323 and portions 311 and 317 (rather than summaries 315 and 321 of portions 311 and 317), as well as one or more formatting instructions. In at least one embodiment, in response to prompt 327, neural network 309 generates summary 329. In at least one embodiment, the prompt generator 309 then combines all of the individual summaries of the different portions 315, 321, and 329 to produce a combined summary. In at least one embodiment, the prompt generator 307 then constructs 331 a startup prompt to start 332 the neural network 309 and constructs 331 another prompt 333 to cause the neural network 309 to generate a summary 335 of the combined summary.

[0085] In at least one embodiment, contextual information is any information from one portion of text that enables neural network 309 to more accurately interpret another portion of the text. In at least one embodiment, for example, if a portion of text mentions a person's name, title, and role in an organization, then the person's title and role are contextual information for subsequent portions of the text in which only the person's name is mentioned. As another example, if a portion of text, or a summary thereof, includes an argument or viewpoint, then the argument or viewpoint is contextual information for subsequent portions in which only the conclusion is mentioned.

[0086] In at least one embodiment, contextual information refers to any data derived from one portion of text that helps neural network 309 more accurately interpret another portion of the text. In at least one embodiment, for example, consider a portion of text, or a summary thereof, that includes a person's name, title, and role in an organization. Here, the person's title and role serve as contextual information for another portion of text that only references the person's name. In at least one embodiment, if a portion of text, or a summary thereof, presents an argument or main point, that argument or main point becomes contextual information for subsequent portions of text that only reference the conclusion drawn from it.

[0087] In at least one embodiment, after each portion of text received from audio file pre-processor 105 is summarized by neural network 309, prompt generator 307 combines these individual summaries into a combined summary.

[0088] In at least one embodiment, prior to sending the combined digest to the neural network 309, the hint generator 307 prepares (primes) 332 the neural network 309 with a priming hint, which Figure 5A and Figure 5B In at least one embodiment, the prompt generator 307 then constructs a new prompt 333 containing the combined summary. In at least one embodiment, the prompt 333 instructs the neural network 309 to generate a summary 355 of the combined summary that follows the format specified in the starting prompt, such as Figure 5A and Figure 5B In at least one embodiment, prompt 333 includes the combined summary and the initiation instructions.

[0089] Figure 4 is a block diagram illustrating a neural network 400 according to at least one embodiment. In at least one embodiment, the neural network 400 corresponds to a combination of Figure 1 and Figure 3Neural network 109 and neural network 309 are described in detail. In at least one embodiment, neural network 400 is a large language model, such as a generative pre-trained transformer (GPT). In at least one embodiment, during pre-training, neural network 400 learns from a dataset before undergoing any specialized training for a specific task. During this phase, the neural network is not fine-tuned for any specific application, but is instead exposed to a variety of topics, writing styles, and structures. In at least one embodiment, the goal of this phase is to build a broad understanding of language and its nuances.

[0090] In at least one embodiment, the neural network 400 is trained on a dataset consisting of billions of words from the internet, including books, articles, and websites. In at least one embodiment, a typical learning goal during pre-training is to predict the next word in a sentence based on the words that precede it. In at least one embodiment, this pre-training is unsupervised, meaning that the neural network 400 learns patterns from the text without explicit instructions or labeled data, and the neural network 400 discovers these patterns through the large amount and variety of texts it is exposed to. In at least one embodiment, the neural network 400 has millions or billions of parameters (weights) that are adjusted during this pre-training phase to minimize the prediction error of the next word in the sequence.

[0091] In at least one embodiment, during pre-training, the training platform uses a loss function to guide the training of the neural network 400. In at least one embodiment, the loss function provides a measure of how well the neural network 400 performs at each step of the training process by calculating an error or loss. In at least one embodiment, the training framework uses an algorithm such as gradient descent to adjust the parameters of the neural network 400 to minimize the loss function. In at least one embodiment, a variety of loss functions can be used during the training of the neural network 400. In at least one embodiment, examples of loss functions include mean squared error (MSE), mean absolute error (MAE), and cross entropy loss.

[0092] In at least one embodiment, neural network 400 includes: an encoder 405 having an embedding layer 402 and a position embedding layer 403; a decoder 413 having an embedding layer 409 and a position encoding layer 411; a linear layer 415; and a softmax layer 417.

[0093] In at least one embodiment, the encoder 405 transforms the prompt 401 into a compressed representation. In at least one embodiment, the prompt 401 corresponds to Figure 3 Any of the above prompts 313, 319 and 327. In at least one embodiment, the encoder 405 has three main layers ( Figure 4 401 ), which are multi-head attention, layer normalization, and multi-layer perception (MLP). In at least one embodiment, the multi-head attention and MLP are referred to as sublayers. In at least one embodiment, between these sublayers, there is layer normalization and dropout and residual connections therebetween. In at least one embodiment, the encoder 405 has a large number of layers, which enables the neural network 400 to capture the global context of the prompt 401, which can lead to better task generalization.

[0094] In at least one embodiment, decoder 413 is similar in structure to encoder 405, except for the addition of multi-head attention that operates on the output of encoder 405. In at least one embodiment, the goal of decoder 413 is to generate summary 408. In at least one embodiment, summary 408 corresponds to Figure 1 The text summary 111.

[0095] In at least one embodiment, the embedding layer 402 of the encoder 405 is used to process the prompt 401, and the embedding layer 409 of the decoder 413 is used to process the summary 408. In at least one embodiment, these embedding layers convert the tokens in the prompt 401 or summary 408 into fixed-size dense vectors, essentially mapping each token in the prompt 401 or summary 408 to a specific dense vector. Using these embedded token vectors, tokens with similar semantic meanings tend to align in the same direction.

[0096] In at least one embodiment, position embedding layers 403 and 411 are used as components in the initial stages of encoder 405 and decoder 413. In at least one embodiment, these position embedding layers 403 and 411 are used to preserve the order of tokens in a sequence, such as the order of tokens in prompt 401 or summary 408.

[0097] In at least one embodiment, a linear layer 415 takes the decoded activations and projects them to the size of the vocabulary. In at least one embodiment, the linear layer produces logits, and a softmax layer 417 takes the logits and converts them into output probabilities 419. In at least one embodiment, the next token predicted is the token with the highest probability in the output probabilities 419.

[0098] In at least one embodiment, decoder 414 generates summary 408 one token at a time using output probabilities 419. In at least one embodiment, decoder 413 first receives a start-of-sequence token, indicating that it should begin generating summary 408. In at least one embodiment, the first sublayer in decoder 413 is a masked multi-headed attention layer, which ensures that the prediction of a particular token depends only on previously generated tokens and not on future tokens. In at least one embodiment, after processing through the masked multi-headed attention layer, the next sublayer is a multi-headed attention layer, which attends to the output of encoder 405, allowing decoder 413 to focus on different parts of the input sequence (e.g., the paragraph being summarized in prompt 401) for each token it generates. In at least one embodiment, after attending to the encoder output and previous tokens in decoder 413, the output of decoder 413 passes through a linear layer 415, which transforms it into a larger vector—a vector whose length corresponds to the size of the vocabulary. In at least one embodiment, a softmax layer 417 applies a softmax function to this vector to obtain a probability distribution 419 over all possible tokens in the vocabulary.

[0099] In at least one embodiment, neural network 400 selects the token with the highest probability as the next token in digest 408. In at least one embodiment, this selected token is then fed back into decoder 413 as part of the input for generating the next token. In at least one embodiment, this process is iteratively repeated until an end-of-sequence token is generated or the maximum length of digest 408 is reached.

[0100] In at least one embodiment, throughout the process, encoder 405 will provide contextual understanding of prompt 401 , and decoder 413 uses that contextual understanding and its own partially generated output to select the next best token for summary 408 .

[0101] Figure 5A is a flow chart illustrating an example process 500 for initiating a neural network to generate a summary of a portion of an audio transcript according to at least one embodiment. In at least one embodiment, the neural network corresponds to Figure 4Neural network 400 described herein. In at least one embodiment, one or more steps in process 500 are combined in other ways, performed sequentially, and / or performed in parallel. In at least one embodiment, some or all of process 500 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that is collectively executed by hardware, software, or a combination thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform process 500 are not stored solely using transitory signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of transitory signals. In at least one embodiment, process 500 is performed at least in part on a computer system (e.g., a computer system described elsewhere in this disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs process 500. In at least one embodiment, each step in process 500 is performed by one or more processors 106.

[0102] In at least one embodiment, when feeding a neural network (e.g., in conjunction with Figure 4 Process 500 is performed before the neural network 400 described above provides prompts for individual portions of an audio transcript. In at least one embodiment, the audio transcript is a transcript of an audio track extracted from an audio file (e.g., audio file 103). In at least one embodiment, process 508 is performed to implement the corresponding Figure 3 The operation of the startup operation 310 is described.

[0103] In at least one embodiment, in operation 502, one or more processors 106 construct a startup prompt that specifies a desired format for a summary of a portion of the audio transcript. In at least one embodiment, the desired format is a combination of Figure 1The format used by the described text summary 111 is similar to that used in the text summary 111. In at least one embodiment, the example startup prompt is as follows: "You are a meeting summarizer, and you are providing a summary of a portion of a long meeting transcript. Your summary should not contain any harmful, unethical, racist, sexist, toxic, dangerous, or illegal content. Use only information from the portion of the meeting transcript provided to you as input, and do not use any information from any other source."

[0104] In at least one embodiment, one or more processors 106 provide the priming hint to the neural network to be primed (prepared) in operation 504. In at least one embodiment, priming is a technique for influencing a pre-trained neural network to generate output in a particular manner for a particular instance.

[0105] In at least one embodiment, in operation 506 , one or more processors 106 analyze the summary generated by the neural network in response to the launch prompt to identify one or more differences between the expected format and an actual format of the summary.

[0106] In at least one embodiment, operations 502, 504, and 506 are repeated as necessary until a summary conforming to the desired format is generated from a portion of the audio transcript. In at least one embodiment, for each iteration after the first, operation 502 is modified to include additional instructions. These instructions direct the neural network to correct any identified differences between the desired format and the actual format of the generated summary.

[0107] Figure 5B is a flow chart illustrating an example process 508 for initiating a neural network to generate a summary of text according to at least one embodiment. In at least one embodiment, the neural network corresponds to a process for initiating a neural network to generate a summary of text according to at least one embodiment. Figure 4Neural network 400 described herein. In at least one embodiment, one or more steps in process 508 are combined in other ways, performed sequentially, and / or performed in parallel. In at least one embodiment, part or all of process 508 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that is collectively executed by hardware, software, or a combination thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions for performing process 508 are not stored solely using transient signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of transient signals. In at least one embodiment, process 508 is performed at least in part on a computer system (e.g., a computer system described elsewhere in this disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs process 508. In at least one embodiment, each step in process 508 is performed by one or more processors 106.

[0108] In at least one embodiment, when feeding a neural network (e.g., in conjunction with Figure 4 Process 508 is performed before the neural network 400 described above provides a prompt for text. In at least one embodiment, the text is a combined summary of all portions of the audio transcript of the audio track extracted from the audio file (e.g., audio file 103). In at least one embodiment, process 508 is performed to implement a method corresponding to the combined Figure 3 The operation of the startup operation 332 is described.

[0109] In at least one embodiment, in operation 510, one or more processors 106 construct a startup prompt that specifies a desired format for the summary of the text. In at least one embodiment, the desired format is such as a combination of Figure 1In at least one embodiment, the startup prompt includes one or more examples of summaries in the desired format. In at least one embodiment, these example summaries closely match the style and structure of the desired format. Furthermore, in at least one embodiment, the startup prompt includes explicit instructions to rescale the desired format. In at least one embodiment, for example, the instructions may explicitly state that a bullet point format is to be used for the summary to be generated by the neural network. In at least one embodiment, an example startup example is as follows: "You are a meeting summarizer and you are providing a summary of a long meeting transcript. Your summary should not contain any harmful, unethical, racist, sexist, toxic, dangerous, or illegal content. Use only information from the meeting transcript provided to you as input and do not use any information from any other source."

[0110] In at least one embodiment, one or more processors 106 provide the priming hint to the neural network to be primed (ready) in operation 512. In at least one embodiment, priming is a technique for influencing a pre-trained neural network to generate outputs in a particular manner for a particular instance.

[0111] In at least one embodiment, in operation 514 , one or more processors 106 analyze the digest generated by the neural network in response to the launch prompt to identify one or more differences between the expected format and an actual format of the digest.

[0112] In at least one embodiment, operations 510, 512, and 514 are repeated as necessary until a summary conforming to the desired format is generated from the text. In at least one embodiment, for each iteration after the first, operation 510 is modified to include additional instructions. These instructions direct the neural network to correct any identified differences between the desired format and the actual format of the generated summary. For example, if the desired format requires a summary to be less than 300 words, but the generated summary exceeds this limit, correction instructions (e.g., "Notice the discrepancy. Please limit the summary to 300 words.") can be incorporated into the startup prompt.

[0113] Figure 6 is a flow chart illustrating a process 600 of inferring a neural network according to at least one embodiment. In at least one embodiment, the neural network corresponds to Figure 4The neural network 400 described herein is described. In at least one embodiment, one or more steps in process 600 are combined in other ways, performed sequentially, and / or performed in parallel. In at least one embodiment, part or all of process 600 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that is collectively executed by hardware, software, or a combination thereof on one or more processors.

[0114] In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes a plurality of computer-readable instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform process 600 are not stored using only transient signals (e.g., propagating transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuits (e.g., buffers, caches, and queues) within a transceiver of transient signals. In at least one embodiment, process 600 is at least partially executed on a computer system (e.g., a computer system described elsewhere in this disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) executes process 600. In at least one embodiment, each step in process 600 is performed by one or more processors 106.

[0115] In at least one embodiment, in operation 601, one or more processors 106 execute one or more computer-executable program instructions to cause the neural network to receive a prompt for each portion of a transcript of an audio track extracted from an audio file (e.g., audio file 103). In at least one embodiment, each subsequent prompt, except for the first prompt, includes one or more summaries of previous portions of the transcript or such previous portions as context for the neural network to generate a summary of the current portion. In at least one embodiment, each prompt also includes one or more instructions that instruct the neural network to generate a summary in a desired format, such as incorporating Figure 1 The format used for the text summary 111 is described. In at least one embodiment, an example prompt for generating a summary of a section is as follows: "Write a summary of the section in 100 words. Try to identify contextual transitions within the meeting and also give their starting timestamps. The summary of the meeting so far is - <summary passed to the LLM so far>. The transcript of the current section is - <transcript of the current section>."

[0116] In at least one embodiment, in operation 603, one or more processors 106 execute one or more computer-executable program instructions to cause the neural network to generate a summary for each portion of the transcript in a sequence defined by the order in which the corresponding prompts were received.

[0117] In at least one embodiment, in operation 605, one or more processors 106 execute one or more computer executable program instructions to cause the neural network to receive a start prompt. In at least one embodiment, the start prompt corresponds to a combination of Figure 5A The start prompt described in operation 502. In at least one embodiment, the start prompt can be performed multiple times by the neural network, such as in combination with Figure 5A and Figure 5B described.

[0118] In at least one embodiment, after priming the neural network using the priming prompt, one or more processors 106 execute one or more computer-executable program instructions to cause the neural network to receive a prompt comprising a combined summary in operation 607. In at least one embodiment, the combined summary is created by merging individual summaries of different portions of the audio transcript of the audio track of the meeting recording. In at least one embodiment, the combined summary is generated by a prompt generator, for example, in combination with Figure 3 Prompt generator 307 is described.

[0119] In at least one embodiment, in operation 609 , one or more processors 106 execute one or more computer-executable program instructions to cause the neural network to generate a summary of the combined summary in response to the prompt.

[0120] Figure 7 is a block diagram illustrating a system 700 for generating text summaries from audio files according to at least one embodiment. In at least one embodiment, the system 700 uses a natural language processing (NLP) solution to process and transcribe multi-party conversations and generate concise and coherent summaries that are contextually accurate and free of jargon. In at least one embodiment, the system 700 corresponds to the system 100. In at least one embodiment, the CPU 702 and the GPU 709 are processors, such as Figure 1 The processor 106 described in .

[0121] In at least one embodiment, the CPU 702 executes one or more computer-executable instructions to download an audio file 704 (e.g., from a cloud server) and split 706 the audio file 704 into smaller audio files. In at least one embodiment, the audio file 704 represents a meeting transcript or any other audio / video file. In at least one embodiment, the CPU 702 extracts the audio track from the audio file 704 after downloading the file.

[0122] In at least one embodiment, the CPU 702 segments 706 the audio file 704 into track segments at points where a pause is detected (e.g., a sentence or speaker change occurs). In at least one embodiment, pause detection relies on digital signal processing to identify moments of silence that last for more than a predetermined duration (e.g., 2 seconds), while also considering signal energy levels falling below a predetermined threshold (e.g., 0.05%).

[0123] In at least one embodiment, the GPU 708 uses an automatic speech recognition (ASR) model to transcribe 710 each audio track segment. In at least one embodiment, the GPU 708 then uses a punctuation model (e.g., the Nemo punctuation_en_distilbert model) to punctuate and capitalize 712 each audio segment transcript so that a neural network can process the transcripts to identify nuanced context from the transcripts. In at least one embodiment, the GPU 708 adds timestamps to the transcripts. In at least one embodiment, the GPU 708 can use one or more neural networks to summarize each transcript and combine the summaries into a combined summary.

[0124] In at least one embodiment, the GPU 708 executes one or more computer-executable instructions to send 714 the combined transcript to the LLM, which generates a summary in a desired format. In at least one embodiment, the summary is presented to a user for review. In at least one embodiment, the summary can be in a format that includes only a predetermined number of topics (e.g., the first five topics) or another predefined format as specified by a prompt to the LLM. In at least one embodiment, the system 700 reduces the time required to understand the content of a meeting to a few minutes. For example, in at least one embodiment, the system 700 reduces the time required for a one-hour meeting from 20 minutes to 4 minutes.

[0125] Figure 8 is a flow chart illustrating a process 800 for generating a text summary from an audio file using a neural network according to at least one embodiment. In at least one embodiment, the neural network corresponds to Figure 4Neural network 400 described herein. In at least one embodiment, one or more steps in process 800 are combined in other ways, performed sequentially, and / or performed in parallel. In at least one embodiment, part or all of process 800 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that is collectively executed by hardware, software, or a combination thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform process 800 are not stored solely using transient signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of transient signals. In at least one embodiment, process 800 is performed at least in part on a computer system (e.g., a computer system described elsewhere in this disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs process 800. In at least one embodiment, each step in process 800 is performed by one or more processors 106.

[0126] In at least one embodiment, one or more processors ingest, download, or otherwise obtain a meeting recording file in operation 802. In at least one embodiment, the meeting recording file is in one of a variety of formats, such as WAV and MP3.

[0127] In at least one embodiment, in operation 804, one or more processors 106 segment the audio file based on pauses. In at least one embodiment, for example, if the energy of the audio is less than 0.05% for at least 2 seconds, the audio is segmented at that point. In at least one embodiment, start and stop timestamps of the segmented audio are calculated.

[0128] In at least one embodiment, in operation 806, one or more processors 106 transcribe the segmented audio files. In at least one embodiment, each segmented audio file is a segment of an audio track extracted from the conference record file.

[0129] In at least one embodiment, the one or more processors 106 modify the transcripts by adding one or more punctuation marks and one or more capital letters to each transcript in operation 808. In at least one embodiment, the punctuation marks and capital letters are added using a punctuation model.

[0130] In at least one embodiment, in operation 810, one or more processors 106 pass these modified transcripts to a neural network, e.g. Figure 4 In at least one embodiment, the neural network generates a summary of each modified transcript. In at least one embodiment, one or more processors 106 then combine these individual summaries into a combined summary.

[0131] In at least one embodiment, in operation 812, one or more processors 106 input optimized instruction hints to the neural network to extract relevant information. In at least one embodiment, the extracted information is a summary of the combined summary in a desired format. In at least one embodiment, the optimized instruction hints include the combined summary and one or more instructions for instructing the neural network to generate the summary in the desired format.

[0132] In at least one embodiment, in operation 814 , one or more processors 106 communicate the summary generated by the neural network to a user for review.

[0133] Figure 9 An environment 900 including a processor 902 and modules is shown according to at least one embodiment. In at least one embodiment, the processor 902 executes one or more processes (e.g., the processes described herein) to generate a summary of a meeting transcript (e.g., Figures 1 to 8 In at least one embodiment, processor 902 includes one or more processors (e.g., in conjunction with Figure 1In at least one embodiment, the processor 902 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof. In at least one embodiment, the processor 902 includes a neural network training module 904, a data collection module 906, a trained neural network reasoning module 908, and / or an audio file pre-processing module 910. In at least one embodiment, the neural network training module 904, the data collection module 906, the trained neural network reasoning module 908, and / or the audio file pre-processing module 910 are part of the processor 902 and / or one or more other processors. In at least one embodiment, the neural network training module 904, the data collection module 906, the trained neural network reasoning module, and / or the audio file pre-processing module 910 are distributed among multiple processors, which communicate via a bus, a network, by writing to a shared memory, and / or any suitable communication process (e.g., the communication process described herein).

[0134] In at least one embodiment, as used in any implementation described herein, unless the context clearly dictates otherwise or clearly to the contrary, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein may, for example, include, individually or in any combination, hardwired circuits, programmable circuits, state machine circuits, fixed function circuits, execution unit circuits, and / or firmware that stores instructions executed by programmable circuits. In at least one embodiment, modules may be collectively or individually embodied as circuits that constitute part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), and the like. In at least one embodiment, a module performs one or more processes together with any suitable processing unit and / or combination of processing units (e.g., one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof).

[0135] In at least one embodiment, the neural network training module 904 is a module that trains one or more neural networks. In at least one embodiment, the neural network training module 904 performs one or more processes (e.g., the processes described herein) by at least including or otherwise encoding instructions that cause the execution or otherwise be used to perform the one or more processes (e.g., by the processor 902). In at least one embodiment, the neural network training module 604 obtains or is otherwise provided with one or more neural networks (e.g., by one or more systems, such as in conjunction with Figure 1In at least one embodiment, the neural network training module 904 uses the training data set through one or more processes (e.g., combining Figures 1 to 8 In at least one embodiment, the neural network training module 904 uses any suitable training process (including, in combination with Figure 4 The one or more neural networks are trained using the process described herein.

[0136] In at least one embodiment, the data collection module 906 receives input audio (e.g., Figure 1 In at least one embodiment, the data collection module 906 performs one or more processes (e.g., the processes described herein) by at least including or otherwise encoding instructions that cause execution or are otherwise usable to perform the one or more processes (e.g., by the processor 902).

[0137] In at least one embodiment, the trained neural network reasoning module 908 is a module that represents one or more trained neural networks that can be used to reason about patterns. In at least one embodiment, the trained neural network reasoning module 908 performs one or more processes (e.g., the processes described herein) by at least including or otherwise encoding instructions that cause the execution or are otherwise operable to execute the one or more processes (e.g., by the processor 902). In at least one embodiment, the trained neural network reasoning module 908 generates a summary from a transcript of a meeting recording.

[0138] In at least one embodiment, the audio file processing module 910 corresponds to Figure 2 In at least one embodiment, the audio file processing module 910 is executed Figure 2 Modules for the operations, processes and / or techniques described in.

[0139] Figure 10 1 is a block diagram illustrating a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, software program 1002 is a software module. In at least one embodiment, software program 1002 can be a computer readable medium (CRM). In at least one embodiment, software program 1002 includes one or more software modules. In at least one embodiment, one or more software modules such as Figures 1 to 81002 . In at least one embodiment, one or more APIs 1010 are software instruction sets that, if executed, cause one or more processors to perform one or more computing operations. In at least one embodiment, one or more APIs 1010 are distributed or otherwise provided as part of a grouping of one or more libraries 1006, runtimes 1004, drivers 1004, and / or any other software and / or executable code further described herein. In at least one embodiment, one or more APIs 1010 perform one or more computing operations in response to invocation of software program 1002. In at least one embodiment, software program 1002 is a collection of software code, commands, instructions, or other text sequences that instruct a computing device to perform one or more computing operations and / or invoke one or more other instruction sets (e.g., APIs 1010 or API functions 1012) for execution. In at least one embodiment, the functionality provided by one or more APIs 1010 includes software functions 1012, such as software functions that can be used to accelerate one or more portions of software program 1002 using one or more parallel processing units (PPUs), such as graphics processing units (GPUs). In at least one embodiment, the software program is a compiler.

[0140] In at least one embodiment, the API 1010 is a hardware interface to one or more circuits for performing one or more computing operations. In at least one embodiment, the one or more software APIs 1010 described herein are implemented to perform operations in conjunction with Figures 1 to 8 In at least one embodiment, one or more software programs 1002 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform operations in conjunction with one or more of the techniques described herein. Figures 1 to 8 One or more techniques further described.

[0141] In at least one embodiment, a software program 1002 (e.g., a user-implemented software program) utilizes one or more application programming interfaces (APIs) 1010 to perform various computational operations, such as memory reservations, matrix multiplications, arithmetic operations, or any computational operations performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, the one or more APIs 1010 provide a set of callable functions 1012 (referred to herein as APIs, API functions, and / or functions) that each perform one or more computational operations, such as computational operations associated with parallel computing. In at least one embodiment, the one or more APIs 1010 provide functions 1012 to cause 1016 one or more neural networks to generate a text summary in a desired format from an audio transcript.

[0142] In at least one embodiment, one or more software programs 1002 interact with or otherwise communicate with one or more APIs 1010 to perform one or more computing operations using one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more computing operations using the one or more PPUs include at least one or more groups of computing operations that are accelerated by being executed at least in part by the one or more PPUs. In at least one embodiment, the one or more software programs 1002 interact with the one or more APIs 1010 to facilitate parallel computing using remote or local interfaces.

[0143] In at least one embodiment, the interface is software instructions that, if executed, provide access to one or more functions 1012 provided by one or more APIs 1010. In at least one embodiment, the software programs 1002 use native interfaces when a software developer compiles one or more software programs 1002 in conjunction with one or more libraries 1006 that include or otherwise provide access to one or more APIs 1010. In at least one embodiment, the one or more software programs 1002 are statically compiled in conjunction with precompiled libraries 1006 or uncompiled source code that includes instructions for executing the one or more APIs 1010. In at least one embodiment, the one or more software programs 1002 are dynamically compiled and linked to the one or more precompiled libraries 1006 that include the one or more APIs 1010 using a linker.

[0144] In at least one embodiment, the software program 1002 uses a remote interface when a software developer executes a software program that utilizes a library 1006 including one or more APIs 1010 or otherwise communicates with a library 1006 including one or more APIs 1010 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 1006 including one or more APIs 1010 are executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, the one or more libraries 1006 including one or more APIs 1010 are executed by any other computing host that provides the one or more APIs 1010 to the one or more software programs 1002.

[0145] In at least one embodiment, a processor executing or using one or more software programs 1002 calls, uses, executes, or otherwise implements one or more APIs 1010 to allocate and otherwise manage memory for use by the software programs 1002. In at least one embodiment, one or more software programs 1002 utilize one or more APIs 1010 to allocate and otherwise manage memory for use by one or more portions of the software programs 1002 for acceleration using one or more PPUs (e.g., GPUs or any other accelerators or processors further described herein). In at least one embodiment, the software program 1002 requests a neural network to generate a text summary in a desired format from an audio transcript.

[0146] In at least one embodiment, API 1010 is an API for facilitating parallel computing. In at least one embodiment, API 1010 is any other API described further herein. In at least one embodiment, API 1010 is provided by a driver and / or runtime 1004. In at least one embodiment, API 1010 is provided by a CUDA user-mode driver. In at least one embodiment, API 1010 is provided by a CUDA runtime. In at least one embodiment, driver 1004 is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 1012 of API 1010 during the loading and execution of one or more portions of software program 1002. In at least one embodiment, runtime 1004 is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 1012 of API 1010 during the execution of software program 1002. In at least one embodiment, one or more software programs 1002 utilize one or more APIs 1010 implemented or otherwise provided by a driver and / or runtime 1004 to perform combined arithmetic operations by the one or more software programs 1002 during execution by one or more PPUs (e.g., GPUs).

[0147] In at least one embodiment, one or more software programs 1002 utilize one or more APIs 1010 provided by a driver and / or runtime 1004 to perform combined arithmetic operations for one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more APIs 1010 provide combined arithmetic operations through the driver and / or runtime 1004, as described above. In at least one embodiment, one or more software programs 1002 utilize one or more APIs 1010 provided by the driver and / or runtime 1004 to allocate or otherwise reserve one or more blocks of memory 1014 for one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 1002 utilize one or more APIs 1010 provided by the driver and / or runtime 1004 to allocate or otherwise reserve blocks of memory. In at least one embodiment, the one or more APIs 1010 are used to perform combined arithmetic operations, as described below in conjunction with Figures 1 to 12 Any of those described in .

[0148] To improve the usability of the software program 1002 and / or optimize one or more portions of the software program 1002 for acceleration by one or more PPUs (e.g., GPUs), in one embodiment, the one or more APIs 1010 provide one or more API functions 1012 to implement a scheduling system that can be used or utilized by one or more computing devices, as described above and in conjunction with Figures 1 to 12 In at least one embodiment, block diagram 1000 depicts a processor comprising one or more circuits for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, block diagram 1000 depicts a system comprising one or more processors for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, the API is used to cause a neural network to generate a text summary in a desired format from an audio transcript.

[0149] In at least one embodiment, a system for generating a text summary in a desired format is used to 14A to 14D In at least one embodiment, the system can be installed in an autonomous vehicle such as 14A to 14D In the autonomous vehicle shown, a driver or passenger in the vehicle can upload a meeting record to the vehicle and receive a text summary generated by the system. In at least one embodiment, the system for generating a text summary in a desired format is used in and by other neural networks, such as Figure 12 In at least one embodiment, the system for generating a text summary in a desired format is used as follows Figure 13 In at least one embodiment, the system for generating a text summary in a desired format is incorporated into other logic, such as Figure 11A and / or Figure 11B In at least one embodiment, the system for generating a text summary in a desired format is composed of a system such as Figure 15 The computer system shown in is used.

[0150] In at least one embodiment, the module includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuits configured to perform the functions. In at least one embodiment, the module includes one or more circuits (e.g., integrated circuit (IC), system on chip (SoC), central processing unit (CPU), graphics processing unit (GPU), data processing unit (DPU), etc.) that form part of a larger system. In at least one embodiment, the controller includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuits configured to perform the functions. In at least one embodiment, the software includes a software package, code, programming language, driver, instructions, instruction set, or some combination thereof. In at least one embodiment, the hardware includes hard-wired circuits, programmable circuits, state machine circuits, fixed function circuits, execution unit circuits, firmware storing instructions executed by programmable circuits, or some combination thereof.

[0151] logic

[0152] Figure 11A 11 is a diagram illustrating logic 1115 according to at least one embodiment, which may be used in one or more devices to perform operations such as those discussed herein, as described elsewhere herein. In at least one embodiment, logic 1115 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic 1115 is reasoning and / or training logic. Figure 11A and / or Figure 11B Details are provided regarding logic 1115. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic used to provide the functionality or operations described herein, where the logic may collectively or individually be embodied as circuitry forming part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., CPU, GPU)).

[0153] In at least one embodiment, logic 1115 may include, but is not limited to, code and / or data storage 1101 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 1115 may include or be coupled to code and / or data storage 1101 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information are loaded to configure logic including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 1101 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 1101 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0154] In at least one embodiment, any portion of code and / or data storage 1101 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1101 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 1101 is internal or external to a processor, e.g., or includes DRAM, SRAM, flash memory, or some other type of storage, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0155] In at least one embodiment, logic 1115 may include, but is not limited to, code and / or data storage 1105 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 1105 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, logic 1115 may include or be coupled to code and / or data storage 1105 for storing graph code or other software to control the timing and / or sequence in which weight and / or other parameter information is loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0156] In at least one embodiment, code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 1105 can be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 1105 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1105 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 1105 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other type of storage, can depend on the available on-chip or off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0157] In at least one embodiment, code and / or data storage 1101 and code and / or data storage 1105 may be separate storage structures. In at least one embodiment, code and / or data storage 1101 and code and / or data storage 1105 may be the same storage structure. In at least one embodiment, code and / or data storage 1101 and code and / or data storage 1105 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 1101 and code and / or data storage 1105 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0158] In at least one embodiment, logic 1115 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 1110 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or as directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 1120, which are functions of input / output and / or weight parameter data stored in code and / or data storage 1101 and / or code and / or data storage 1105. In at least one embodiment, activations stored in activation storage 1120 are generated based on linear algebra and / or matrix-based math performed by ALU 1110 in response to executing instructions or other code, with weight values ​​stored in code and / or data storage 1105 and / or in code and / or data storage 1101 used as operands, as well as other values ​​such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 1105 or code and / or data storage 1101 or other on-chip or off-chip storage.

[0159] In at least one embodiment, one or more ALUs 1110 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 1110 may be external to the processor or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, ALUs 1110 may be included within the execution units of a processor or otherwise included in an ALU bank accessible by the execution units of the processor, which may be within the same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 1101, code and / or data storage 1105, and activation storage 1120 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 1120 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0160] In at least one embodiment, activation storage 1120 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 1120 can be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 1120 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, can depend on the available storage on-chip versus off-chip, the latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training neural networks, or some combination of these factors.

[0161] In at least one embodiment, Figure 11A The logic 1115 shown in FIG. 1 may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 11AThe illustrated logic 1115 may be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware such as a field programmable gate array ("FPGA").

[0162] In at least one embodiment, Figure 11A At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 11A The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 11A The components can be used to train one or more neural networks (such as, Figure 4 400 ) and performing inference using the one or more neural networks.

[0163] Figure 11B Logic 1115 is shown in accordance with at least one embodiment. In at least one embodiment, logic 1115 is inference and / or training logic. In at least one embodiment, logic 1115 may include, but is not limited to, hardware logic where computing resources are dedicated or otherwise used exclusively with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 11B The logic 1115 shown in FIG can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 11B The logic 1115 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, logic 1115 includes, but is not limited to, code and / or data storage 1101 and code and / or data storage 1105, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 11BIn at least one embodiment shown in FIG, code and / or data storage 1101 and code and / or data storage 1105 are each associated with dedicated computing resources, such as computing hardware 1102 and computing hardware 1106, respectively. In at least one embodiment, computing hardware 1102 and computing hardware 1106 each include one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 1101 and code and / or data storage 1105, respectively, with the results being stored in activation storage 1120.

[0164] In at least one embodiment, each of the code and / or data stores 1101 and 1105 and the corresponding computing hardware 1102 and 1106 corresponds to a different layer of a neural network, such that activations from one storage / computation pair 1101 / 1102 of the code and / or data store 1101 and computing hardware 1102 are provided as inputs to the next storage / computation pair 1105 / 1106 of the code and / or data store 1105 and computing hardware 1106, reflecting the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 1101 / 1102 and 1105 / 1106 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) can be included in logic 1115 after or in parallel with storage / computation pairs 1101 / 1102 and 1105 / 1106.

[0165] In at least one embodiment, Figure 11B At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 11B The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 11B The components can be used to train one or more neural networks (such as, in combination with Figure 4 400 ) and performing inference using the one or more neural networks.

[0166] Neural network training and deployment

[0167] Figure 12The training and deployment of a deep neural network according to at least one embodiment is shown. In at least one embodiment, an untrained neural network 1206 is trained using a training dataset 1202. In at least one embodiment, the training framework 1204 is the PyTorch framework, while in other embodiments, the training framework 1204 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1204 trains the untrained neural network 1206 and enables it to be trained using the processing resources described herein to generate a trained neural network 1208. In at least one embodiment, the weights can be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, the training can be performed in a supervised, partially supervised, or unsupervised manner.

[0168] In at least one embodiment, untrained neural network 1206 is trained using supervised learning, where training dataset 1202 includes inputs paired with expected outputs for the inputs, or where training dataset 1202 includes inputs with known outputs and the outputs of neural network 1206 are manually graded. In at least one embodiment, untrained neural network 1206 is trained in a supervised manner, processing inputs from training dataset 1202 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through untrained neural network 1206. In at least one embodiment, training framework 1204 adjusts the weights that control untrained neural network 1206. In at least one embodiment, training framework 1204 includes tools for monitoring the degree to which untrained neural network 1206 converges toward a model (such as trained neural network 1208) suitable for generating correct answers (such as results 1214) based on input data (such as new dataset 1212). In at least one embodiment, the training framework 1204 iteratively trains the untrained neural network 1206 while adjusting the weights to refine the output of the untrained neural network 1206 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 1204 trains the untrained neural network 1206 until the untrained neural network 1206 reaches a desired accuracy. In at least one embodiment, the trained neural network 1208 can then be deployed to implement any number of machine learning operations.

[0169] In at least one embodiment, untrained neural network 1206 is trained using unsupervised learning, wherein untrained neural network 1206 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 1202 will include input data without any associated output data or "ground truth" data. In at least one embodiment, untrained neural network 1206 can learn groupings within training dataset 1202 and can determine how individual inputs relate to untrained dataset 1202. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 1208, which can perform operations useful for reducing the dimensionality of new dataset 1212. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in new dataset 1212 that deviate from the normal pattern of new dataset 1212.

[0170] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1202. In at least one embodiment, the training framework 1204 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1208 to adapt to new datasets 1212 without forgetting the knowledge that was infused into the trained neural network 1208 during initial training.

[0171] In at least one embodiment, the training framework 1204 is a framework that is processed in conjunction with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes logic 1115 or uses logic 1115 to perform the operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0172] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations (such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variants thereof). In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variants thereof.

[0173] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image restoration, style transfer, action recognition, colorization, and / or their variants.

[0174] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes a neural network model for execution on various devices and / or processing units, such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers from the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the model's inputs (e.g., resizing the model's inputs), modifying the size of the model's inputs (e.g., modifying the model's batch size), modifying the model's structure (e.g., modifying the model's layers), normalization, standardization, quantization (e.g., converting the model's weights from a first representation, such as floating point, to a second representation, such as integers), and / or variants thereof.

[0175] In at least one embodiment, OpenVINO includes one or more software libraries for reasoning, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is used to reason about input data. In at least one embodiment, the inference engine implements various classes to reason about input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0176] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (for example, executing a first set of layers on a first device (e.g., a GPU) and executing a second set of layers on a second device (e.g., a CPU)).

[0177] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0178] In at least one embodiment, Figure 12 At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 12 The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 12 The components can be used to train one or more neural networks (such as, Figure 4 400 ) and performing inference using the one or more neural networks.

[0179] Data Center

[0180] Figure 13 An example data center 1300 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 1300 includes a data center infrastructure layer 1310, a framework layer 1320, a software layer 1330, and an application layer 1340.

[0181] In at least one embodiment, Figure 13 As shown, the data center infrastructure layer 1310 may include a resource coordinator 1312, grouped computing resources 1314, and node computing resources ("node CRs") 1316(1)-1316(N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, the node CRs 1316(1)-1316(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1318(1)-1318(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1316(1)-1316(N) may be a server having one or more of the above-mentioned computing resources.

[0182] In at least one embodiment, the grouped computing resources 1314 may include separate groups of node CRs housed in one or more racks (not shown), or may be housed in many racks in data centers (also not shown) at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 1314 may include computing, networking, memory, or storage resources that may be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0183] In at least one embodiment, resource coordinator 1312 may configure or otherwise control one or more nodes CR 1316(1)-1316(N) and / or grouped computing resources 1314. In at least one embodiment, resource coordinator 1312 may comprise a software design infrastructure ("SDI") management entity for data center 1300. In at least one embodiment, resource coordinator 1312 may comprise hardware, software, or some combination thereof.

[0184] In at least one embodiment, Figure 13As shown, framework layer 1320 includes a job scheduler 1322, a configuration manager 1324, a resource manager 1326, and a distributed file system 1328. In at least one embodiment, framework layer 1320 may include a framework that supports software 1332 of software layer 1330 and / or one or more applications 1342 of application layer 1340. In at least one embodiment, software 1332 or applications 1342 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1320 may include, but is not limited to, a type of free and open source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which can utilize distributed file system 1328 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 1322 may include a Spark driver to facilitate scheduling workloads supported by the various layers of data center 1300. In at least one embodiment, a configuration manager 1324 may be capable of configuring different layers, such as a software layer 1330 and a framework layer 1320 including Spark and a distributed file system 1328 for supporting large-scale data processing. In at least one embodiment, a resource manager 1326 may be capable of managing clustered or grouped computing resources mapped to or allocated to support the distributed file system 1328 and the job scheduler 1322. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1314 at the data center infrastructure layer 1310. In at least one embodiment, the resource manager 1326 may coordinate with a resource coordinator 1312 to manage these mapped or allocated computing resources.

[0185] In at least one embodiment, the software 1332 included in the software layer 1330 may include software used by at least portions of the node CRs 1316(1)-1316(N), the grouped computing resources 1314, and / or the distributed file system 1328 of the framework layer 1320. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0186] In at least one embodiment, the one or more applications 1342 included in the application layer 1340 may include one or more types of applications used by at least portions of the node CRs 1316(1)-1316(N), the grouped computing resources 1314, and / or the distributed file system 1328 of the framework layer 1320. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0187] In at least one embodiment, any of configuration manager 1324, resource manager 1326, and resource coordinator 1312 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 1300 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0188] In at least one embodiment, data center 1300 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by computing weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1300. In at least one embodiment, the resources described above with respect to data center 1300 may be used to infer or predict information using a trained machine learning model corresponding to one or more neural networks using weight parameters computed using one or more training techniques described herein.

[0189] In at least one embodiment, the data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0190] Logic 1115 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 11A and / or Figure 11BDetails are provided regarding logic 1115. In at least one embodiment, logic 1115 can be used in data center 1300 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0191] In at least one embodiment, Figure 13 At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 13 The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 13 The components can be used to train one or more neural networks (such as, in combination with Figure 4 400 ) and performing inference using the one or more neural networks.

[0192] autonomous vehicles

[0193] Figure 14A An example of an autonomous vehicle 1400 is shown, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1400 (alternatively referred to herein as "vehicle 1400") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1400 can be a semi-tractor-trailer truck for hauling cargo. In at least one embodiment, vehicle 1400 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0194] Autonomous vehicles may be described according to the automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation, “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of such standards). In at least one embodiment, the vehicle 1400 may be capable of one or more of Levels 1 to 5 according to the autonomous driving levels. For example, in at least one embodiment, the vehicle 1400 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0195] In at least one embodiment, vehicle 1400 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, vehicle 1400 may include, but is not limited to, a propulsion system 1450, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 1450 may be connected to a drive train of vehicle 1400, which may include, but is not limited to, a transmission, for enabling propulsion of vehicle 1400. In at least one embodiment, propulsion system 1450 may be controlled in response to receiving a signal from throttle / accelerator 1452.

[0196] In at least one embodiment, when propulsion system 1450 is operating (e.g., when vehicle 1400 is in motion), a steering system 1454 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1400 (e.g., along a desired path or route). In at least one embodiment, steering system 1454 may receive signals from steering actuator 1456. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1446 may be used to operate vehicle brakes in response to signals received from brake actuator 1448 and / or brake sensors.

[0197] In at least one embodiment, one or more controllers 1436, which may include, but are not limited to, one or more system-on-chips ("SoCs") ( Figure 14A) and / or a graphics processing unit (“GPU”) to provide signals (e.g., representing commands) to one or more components and / or systems of vehicle 1400. For example, in at least one embodiment, one or more controllers 1436 can send signals to operate vehicle brakes via brake actuator 1448, operate steering system 1454 via one or more steering actuators 1456, and operate propulsion system 1450 via one or more throttle / accelerator 1452. In at least one embodiment, one or more controllers 1436 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1400. In at least one embodiment, one or more controllers 1436 may include a first controller for autonomous driving functionality, a second controller for functional safety functionality, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0198] In at least one embodiment, the one or more controllers 1436 provide signals for controlling one or more components and / or systems of the vehicle 1400 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1458 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1460, one or more ultrasonic sensors 1462, one or more LIDAR sensors 1464, one or more inertial measurement unit (IMU) sensors 1466 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1496, one or more stereo cameras 1468, one or more wide-angle cameras 1470 (e.g., fisheye cameras), one or more infrared cameras 1472, one or more surround cameras 1474 (e.g., 360-degree cameras), telemetry cameras (e.g., gyroscopes), and the like. Figure 14A Not shown), mid-range camera ( Figure 14A), one or more speed sensors 1444 (e.g., for measuring the speed of the vehicle 1400), one or more vibration sensors 1442, one or more steering sensors 1440, one or more brake sensors (e.g., as part of a brake sensor system 1446), and / or other sensor types.

[0199] In at least one embodiment, one or more controllers 1436 may receive input (e.g., represented by input data) from a dashboard 1432 of the vehicle 1400 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface (“HMI”) display 1434, an audible annunciator, a speaker, and / or via other components of the vehicle 1400. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 14A ), location data (e.g., the location of the vehicle 1400, such as on a map), directions, the locations of other vehicles (e.g., an occupancy grid), information about objects and the states of objects sensed by the one or more controllers 1436, etc. For example, in at least one embodiment, the HMI display 1434 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers the vehicle has, is, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0200] In at least one embodiment, the vehicle 1400 further includes a network interface 1424 that can communicate over one or more networks using one or more wireless antennas 1426 and / or one or more modems. For example, in at least one embodiment, the network interface 1424 can be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2300") networks, and the like. In at least one embodiment, the one or more wireless antennas 1426 can also enable communication between objects in the environment (e.g., vehicles, mobile devices, and the like) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, and the like) and / or one or more low power wide area networks ("LPWAN") (such as LoRaWAN, SigFox, and the like protocols).

[0201] Logic 1115 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 11A and / or Figure 11BDetails are provided regarding logic 1115. In at least one embodiment, logic 1115 can be used in vehicle 1400 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0202] In at least one embodiment, Figure 14A At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 14A The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 14A The components can be used to train one or more neural networks (such as, in combination with Figure 4 400 ) and performing inference using the one or more neural networks.

[0203] Figure 14B According to at least one embodiment, Figure 14A 1400. In at least one embodiment, the cameras and corresponding fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on vehicle 1400.

[0204] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1400. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red-clear-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a clear pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity.

[0205] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0206] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to remove stray light and reflected light from within the vehicle 1400 (e.g., reflected light from the dashboard reflecting in the windshield mirror), which may interfere with the camera's image data capture capabilities. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated into the four pillars at each corner of the cabin.

[0207] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes portions of the environment in front of the vehicle 1400 can be used for surround vision to help identify the path ahead and obstacles, as well as to assist in providing information critical to generating an occupancy grid and / or determining a preferred vehicle path with the assistance of one or more controllers 1436 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (such as traffic sign recognition).

[0208] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 1470 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 14BOnly one wide-angle camera 1470 is shown, but in other embodiments, there can be any number (including zero) of wide-angle cameras on the vehicle 1400. In at least one embodiment, any number of remote cameras 1498 (e.g., a pair of telescopic stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, one or more remote cameras 1498 can also be used for object detection and classification and basic object tracking.

[0209] In at least one embodiment, any number of stereo cameras 1468 may also be included in the forward configuration. In at least one embodiment, one or more stereo cameras 1468 may include an integrated control unit including an extensible processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle 1400's environment, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1468 may include, but are not limited to, a compact stereo vision sensor that may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 1400 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1468 may be used in addition to or in place of those described herein.

[0210] In at least one embodiment, cameras having a field of view of portions of the environment including the sides of the vehicle 1400 (e.g., side view cameras) can be used for surround view, which provides information for creating and updating occupancy grids and generating side impact collision warnings. For example, in at least one embodiment, surround cameras 1474 (e.g., Figure 14B Four surround cameras (shown as four surround cameras) can be positioned on the vehicle 1400. In at least one embodiment, the one or more surround cameras 1474 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, the four fisheye cameras can be located on the front, rear, and sides of the vehicle 1400. In at least one embodiment, the vehicle 1400 can use three surround cameras 1474 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0211] In at least one embodiment, a camera having a field of view that includes portions of the environment behind the vehicle 1400 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1498 and / or one or more mid-range cameras 1476, one or more stereo cameras 1468, one or more infrared cameras 1472, etc.), as described herein.

[0212] In at least one embodiment, Figure 14B At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 14B The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 14B The components can be used to train one or more neural networks (such as, in combination with Figure 4 400 ) and performing inference using the one or more neural networks.

[0213] Figure 14C is a diagram illustrating a method according to at least one embodiment Figure 14A A block diagram of an example system architecture for an autonomous vehicle 1400 is provided. In at least one embodiment, Figure 14C Each of the components, features, and systems of the vehicle 1400 is shown as being connected via a bus 1402. In at least one embodiment, the bus 1402 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, the CAN may be a network internal to the vehicle 1400 that assists in controlling various features and functions of the vehicle 1400, such as brake actuation, acceleration, braking, steering, wipers, etc. In at least one embodiment, the bus 1402 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 1402 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, the bus 1402 may be an ASIL B compliant CAN bus.

[0214] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, there may be any number of buses forming bus 1402, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions, and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 1402 may communicate with any component of vehicle 1400, and two or more buses in bus 1402 may communicate with corresponding components. In at least one embodiment, each of any number of systems on a chip (“SoCs”) 1404 (e.g., SoC 1404(A) and SoC 1404(B)), each of one or more controllers 1436, and / or each computer within the vehicle can access the same input data (e.g., inputs from sensors of the vehicle 1400) and can be connected to a common bus, such as a CAN bus.

[0215] In at least one embodiment, the vehicle 1400 may include one or more controllers 1436, such as those described herein with respect to Figure 14A In at least one embodiment, the controller 1436 can be used for a variety of functions. In at least one embodiment, the controller 1436 can be coupled to any of the various other components and systems of the vehicle 1400 and can be used to control the vehicle 1400, the artificial intelligence of the vehicle 1400, the infotainment and / or other functions of the vehicle 1400.

[0216] In at least one embodiment, the vehicle 1400 may include any number of SoCs 1404. In at least one embodiment, each of the SoCs 1404 may include, but is not limited to, a central processing unit ("CPU(s)") 1406, a graphics processing unit ("GPU(s")) 1408, one or more processors 1410, one or more caches 1412, one or more accelerators 1414, one or more data stores 1416, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1404 may be used to control the vehicle 1400 in a variety of platforms and systems. For example, in at least one embodiment, the one or more SoCs 1404 may be combined in a system (e.g., a system of the vehicle 1400) along with a high-definition ("HD") map 1422 that may be downloaded from one or more servers (e.g., a system of the vehicle 1400) via a network interface 1424. Figure 14C ) to obtain map refreshes and / or updates.

[0217] In at least one embodiment, one or more CPUs 1406 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 1406 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 1406 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 1406 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, one or more CPUs 1406 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, such that any combination of clusters of one or more CPUs 1406 may be active at any given time.

[0218] In at least one embodiment, one or more CPUs 1406 may implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware blocks when idle to save dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1406 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state to enter for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein work is offloaded to the microcode.

[0219] In at least one embodiment, one or more GPUs 1408 may include an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 1408 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1408 may utilize an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1408 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 1408 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1408 may utilize one or more computing application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1408 may utilize one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0220] In at least one embodiment, one or more GPUs 1408 may be power optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1408 may be fabricated on fin field-effect transistor (“FinFET”) circuits. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., a warp scheduler) or serializer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for providing efficient execution of workloads using a mix of compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor can include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0221] In at least one embodiment, one or more GPUs 1408 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem, configured to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as fifth generation graphics double data rate type synchronous random access memory ("GDDR5"), may be used in addition to or in place of HBM memory.

[0222] In at least one embodiment, one or more GPUs 1408 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow one or more GPUs 1408 to directly access one or more CPU 1406 page tables. In at least one embodiment, when a memory management unit ("MMU") of a GPU in one or more GPUs 1408 experiences a miss, an address translation request may be sent to one or more CPUs 1406. In response, in at least one embodiment, two of the one or more CPUs 1406 may look up the virtual-to-physical mapping of the address in their page tables and send the translation back to the one or more GPUs 1408. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both the one or more CPUs 1406 and the one or more GPUs 1408, thereby simplifying programming the one or more GPUs 1408 and porting applications to the one or more GPUs 1408.

[0223] In at least one embodiment, one or more GPUs 1408 may include any number of access counters that can track the frequency with which one or more GPUs 1408 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of sharing memory ranges between processors.

[0224] In at least one embodiment, one or more SoCs 1404 may include any number of caches 1412, including those described herein. For example, in at least one embodiment, one or more caches 1412 may include a level 3 ("L3") cache that may be used for both (e.g., connected to) one or more CPUs 1406 and one or more GPUs 1408. In at least one embodiment, one or more caches 1412 may include a write-back cache that may track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0225] In at least one embodiment, one or more SoCs 1404 may include one or more accelerators 1414 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1404 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1408 and offload some tasks of one or more GPUs 1408 (e.g., to free up more cycles of one or more GPUs 1408 to perform other tasks). In at least one embodiment, one or more accelerators 1414 may be used for target workloads that are sufficiently stable to withstand acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based or region-based convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

[0226] In at least one embodiment, one or more accelerators 1414 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and often significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and recognition and detection using data from a microphone; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for protection and / or safety related events.

[0227] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 1408, and by using an inference accelerator, for example, a designer can target any function to either one or more DLAs or one or more GPUs 1408. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 1408 and / or one or more accelerators 1414.

[0228] In at least one embodiment, one or more accelerators 1414 may include a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1438, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0229] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0230] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of the one or more CPUs 1406. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0231] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can operate as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as, for example, a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0232] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even different algorithms on a sequence of images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0233] In at least one embodiment, one or more accelerators 1414 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 1414. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0234] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may conform to the International Organization for Standardization ("ISO") 26262 or the International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0235] In at least one embodiment, one or more SoCs 1404 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0236] In at least one embodiment, one or more accelerators 1414 may have a wide range of uses for autonomous driving. In at least one embodiment, the PVA may be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency are well matched to the domain of algorithms that require predictable processing. In other words, the PVA excels at semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, such as in vehicle 1400, the PVA may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math operations.

[0237] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0238] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used to perform time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0239] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence measurement for each object detection. In at least one embodiment, the confidence can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a high confidence detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1466 associated with vehicle 1400 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1464 or one or more RADAR sensors 1460).

[0240] In at least one embodiment, one or more SoCs 1404 may include one or more data stores 1416 (e.g., memory). In at least one embodiment, one or more data stores 1416 may be on-chip memory of one or more SoCs 1404 that may store neural networks to be executed on one or more GPUs 1408 and / or DLAs. In at least one embodiment, one or more data stores 1416 may have a capacity large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, one or more data stores 1416 may include one or more L2 or L3 caches.

[0241] In at least one embodiment, one or more SoCs 1404 may include any number of processors 1410 (e.g., embedded processors). In at least one embodiment, one or more processors 1410 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and associated secure execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1404 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, manage one or more SoCs 1404 thermal and temperature sensors, and / or manage one or more SoCs 1404 power states. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1404 may use the ring oscillator to detect the temperature of one or more CPUs 1406, one or more GPUs 1408, and / or one or more accelerators 1414. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor can enter a temperature fault routine and place one or more SoCs 1404 into a lower power state and / or place the vehicle 1400 into a driver's safe parking mode (e.g., bringing the vehicle 1400 to a safe stop).

[0242] In at least one embodiment, one or more processors 1410 may further include a set of embedded processors that can serve as an audio processing engine, which can be an audio subsystem that implements full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0243] In at least one embodiment, one or more processors 1410 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0244] In at least one embodiment, one or more processors 1410 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to produce a final image for use in a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1470, one or more surround cameras 1474, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC 1404, the neural network being configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain features are available to the driver when the vehicle is operating in autonomous mode that would otherwise be disabled.

[0245] In at least one embodiment, the video image compositor can include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, in the presence of motion in the video, the noise reduction appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, in the presence of motion in the image or portion of an image, the temporal noise reduction performed by the video image compositor can use information from previous images to reduce noise in the current image.

[0246] In at least one embodiment, the video image compositor can also be configured to perform stereo rectification on the input stereo footage frames. In at least one embodiment, the video image compositor can also be used for user interface composition when the operating system desktop is being used, and does not require the one or more GPUs 1408 to continuously render new surfaces. In at least one embodiment, when the one or more GPUs 1408 are powered and active for 3D rendering, the video image compositor can be used to offload the one or more GPUs 1408 to improve performance and responsiveness.

[0247] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic rectification on the input stereoscopic lens frames. In at least one embodiment, the video image compositor can further be used for user interface composition when the operating system desktop is in use and the one or more GPUs 1408 do not need to continuously render new surfaces. In at least one embodiment, when the one or more GPUs 1408 are powered on and actively performing 3D rendering, the video image compositor can be used to offload the one or more GPUs 1408 to improve performance and responsiveness.

[0248] In at least one embodiment, one or more of the SoCs 1404 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1404 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0249] In at least one embodiment, one or more of the SoCs 1404 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1404 may be configured to process data from cameras (e.g., connected via a Gigabit multimedia serial link and an Ethernet channel), sensors (e.g., one or more LIDAR sensors 1464, one or more RADAR sensors 1460, etc., which may be connected via an Ethernet channel), data from the bus 1402 (e.g., vehicle 1400 speed, steering wheel position, etc.), data from one or more GNSS sensors 1458 (e.g., connected via an Ethernet bus or a CAN bus), and the like. In at least one embodiment, one or more of the SoCs 1404 may further include dedicated high-performance large-scale storage controllers, which may include their own DMA engines and may be used to offload one or more of the CPUs 1406 from routine data management tasks.

[0250] In at least one embodiment, one or more SoCs 1404 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for flexible, reliable driving software stacks and deep learning tools. In at least one embodiment, one or more SoCs 1404 can be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1414, when combined with one or more CPUs 1406, one or more GPUs 1408, and one or more data stores 1416, can provide a fast, efficient platform for Level 3-5 autonomous vehicles.

[0251] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute various processing algorithms on various visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous vehicles.

[0252] The embodiments described herein allow for the execution of multiple neural networks simultaneously and / or sequentially, and for the results to be combined to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1420) may include text and word recognition, thereby allowing for the reading and understanding of traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of signs, and passing this semantic understanding to a path planning module running on the CPU complex.

[0253] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign stating "Caution: Flashing lights indicate icy conditions," along with electric lights, can be interpreted independently or collectively by several neural networks. In at least one embodiment, the warning sign itself can be identified as a traffic sign by a first deployed neural network (e.g., an already trained neural network), and the text "Flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1408.

[0254] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1400. In at least one embodiment, an always-on sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1404 provide protection against theft and / or carjacking.

[0255] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 1496 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1404 use a CNN to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, a CNN running on a DLA is trained to identify the relative approaching speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, a CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1458. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1462 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0256] In at least one embodiment, the vehicle 1400 may include one or more CPUs 1418 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to the one or more SoCs 1404 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1418 may include, for example, an X86 processor. The one or more CPUs 1418 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and the one or more SoCs 1404, and / or monitoring the status and health of the one or more controllers 1436 and / or an infotainment system on a chip ("infotainment SoC") 1430. In at least one embodiment, the one or more SoCs 1404 include one or more interconnects, and the interconnects may include a high-speed peripheral component interconnect (PCIe).

[0257] In at least one embodiment, the vehicle 1400 may include one or more GPUs 1420 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 1404 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the one or more GPUs 1420 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural network based at least in part on input from sensors of the vehicle 1400 (e.g., sensor data).

[0258] In at least one embodiment, vehicle 1400 may further include a network interface 1424, which may include, but is not limited to, one or more wireless antennas 1426 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1424 may be used to enable wireless connectivity to internet cloud services (e.g., to servers and / or other network devices), to other vehicles, and / or to computing devices (e.g., a passenger's client device). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1400 and the other vehicle, and / or an indirect link may be established (e.g., via a network and the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1400 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1400). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of vehicle 1400.

[0259] In at least one embodiment, the network interface 1424 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1436 to communicate over a wireless network. In at least one embodiment, the network interface 1424 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by a well-known process and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2300, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0260] In at least one embodiment, the vehicle 1400 may further include one or more data stores 1428, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoCs 1404) storage. In at least one embodiment, the one or more data stores 1428 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0261] In at least one embodiment, the vehicle 1400 may further include one or more GNSS sensors 1458 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1458 may be used, including, for example, but not limited to, GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0262] In at least one embodiment, the vehicle 1400 may further include one or more RADAR sensors 1460. In at least one embodiment, the one or more RADAR sensors 1460 may be used by the vehicle 1400 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASILB. In at least one embodiment, the one or more RADAR sensors 1460 may use a CAN bus and / or bus 1402 (e.g., for transmitting data generated by the one or more RADAR sensors 1460) for control and access to object tracking data, and in some examples, an Ethernet channel may be accessed to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, the one or more RADAR sensors 1460 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1460 are pulse Doppler RADAR sensors.

[0263] In at least one embodiment, one or more RADAR sensors 1460 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved by two or more independent scans (e.g., within a range of 250m). In at least one embodiment, one or more RADAR sensors 1460 can help distinguish between static objects and moving objects and can be used by the ADAS system 1438 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 1460 included in the long-range RADAR system may include, but are not limited to, a monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, using six antennas, the central four antennas can create a focused beam pattern designed to record the surrounding environment of the vehicle 1400 at a higher speed with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas may extend the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 1400 .

[0264] In at least one embodiment, as an example, a medium-range RADAR system may include a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1460 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1438 for blind spot detection and / or lane change assistance.

[0265] In at least one embodiment, the vehicle 1400 may further include one or more ultrasonic sensors 1462. In at least one embodiment, one or more ultrasonic sensors 1462, which may be positioned at the front, rear, and / or side of the vehicle 1400, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1462 may be used, and different ultrasonic sensors 1462 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1462 may operate at an ASIL B functional safety level.

[0266] In at least one embodiment, the vehicle 1400 can include one or more LIDAR sensors 1464. In at least one embodiment, the one or more LIDAR sensors 1464 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1464 can operate at a functional safety level of ASIL B. In at least one embodiment, the vehicle 1400 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1464 that can use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0267] In at least one embodiment, one or more LIDAR sensors 1464 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1464 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-obtrusive LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1464 may comprise a small device that can be embedded in the front, rear, side, and / or corner locations of the vehicle 1400. In at least one embodiment, one or more LIDAR sensors 1464 may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for low-reflectivity objects, and have a range of 200 meters. In at least one embodiment, the forward-mounted one or more LIDAR sensors 1464 may be configured for a horizontal field of view between 45 and 135 degrees.

[0268] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate up to approximately 200 meters around vehicle 1400. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 1400 to the object. In at least one embodiment, flash LIDAR can allow for the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 1400. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0269] In at least one embodiment, the vehicle 1400 may also include one or more IMU sensors 1466. In at least one embodiment, the one or more IMU sensors 1466 may be located at the center of the rear axle of the vehicle 1400. In at least one embodiment, the one or more IMU sensors 1466 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 1466 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 1466 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0270] In at least one embodiment, one or more IMU sensors 1466 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical system ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filter algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 1466 can enable the vehicle 1400 to estimate its heading by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1466, without the need for input from a magnetic sensor. In at least one embodiment, one or more IMU sensors 1466 and one or more GNSS sensors 1458 can be combined in a single integrated unit.

[0271] In at least one embodiment, vehicle 1400 can include one or more microphones 1496 positioned within and / or around vehicle 1400. In at least one embodiment, one or more microphones 1496 can be used for emergency vehicle detection and identification.

[0272] In at least one embodiment, the vehicle 1400 may further include any number of camera types, including one or more stereo cameras 1468, one or more wide angle cameras 1470, one or more infrared cameras 1472, one or more surround cameras 1474, one or more long range cameras 1498, one or more mid range cameras 1476, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1400. In at least one embodiment, the type of camera used depends on the vehicle 1400. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1400. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1400 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example but not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, the present disclosure previously referred to herein may provide a description of the camera types and the camera types used. Figure 14A and Figure 14B Each camera is described in more detail.

[0273] In at least one embodiment, vehicle 1400 may further include one or more vibration sensors 1442. In at least one embodiment, one or more vibration sensors 1442 may measure vibration of a component (e.g., an axle) of vehicle 1400. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1442 are used, the difference between the vibrations may be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0274] In at least one embodiment, the vehicle 1400 may include an ADAS system 1438. In at least one embodiment, the ADAS system 1438 may include, in some examples, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1438 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0275] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 1460, one or more LIDAR sensors 1464, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1400 and automatically adjusts the speed of the vehicle 1400 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 1400 change lanes when needed. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0276] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles indirectly via a wireless link or through a network connection (e.g., through the Internet) via a network interface 1424 and / or one or more wireless antennas 1426. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 1400 and in the same lane as it), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicle ahead of vehicle 1400, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0277] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1460, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses.

[0278] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can utilize one or more forward-facing cameras and / or one or more RADAR sensors 1460 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or collision approach braking.

[0279] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1400 crosses a lane marking. In at least one embodiment, the LDW system does not activate when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a forward-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration assembly. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 1400 begins to leave its lane, the LKA system provides steering input or braking to correct the vehicle 1400.

[0280] In at least one embodiment, the BSW system detects and warns the driver that a vehicle is in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1460 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0281] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when the vehicle 1400 detects an object outside the range of the rear camera while in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure that the vehicle's brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1460 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0282] In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take action accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1400 independently decides whether to follow the results of the primary computer or the secondary computer (e.g., the first or second controller in controller 1436). For example, in at least one embodiment, the ADAS system 1438 can be a backup and / or secondary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1438 can be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0283] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU that indicates the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0284] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the secondary computer provides a false alarm based, at least in part, on output from the primary computer and output from the secondary computer. In at least one embodiment, the one or more neural networks in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the one or more neural networks in the supervisory MCU can learn when the FCW system is identifying a metal object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override LDW when a cyclist or pedestrian is present and lane departure is actually the safest action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 1404.

[0285] In at least one embodiment, the ADAS system 1438 may include an auxiliary computer that uses traditional computer vision rules to perform ADAS functions. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or bug in the software running on the main computer, and the non-identical software code running on the auxiliary computer provides a consistent overall result, the supervisory MCU can have greater confidence that the overall result is correct and that the vulnerability in the software or hardware on the main computer did not cause a significant error.

[0286] In at least one embodiment, the output of the ADAS system 1438 can be fed into the primary computer's perception block and / or the primary computer's dynamic driving task block. For example, in at least one embodiment, if the ADAS system 1438 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when the object is identified. In at least one embodiment, the secondary computer can have its own neural network that has been trained, as described herein, to reduce the risk of false positives.

[0287] In at least one embodiment, the vehicle 1400 may further include an infotainment SoC 1430 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1430 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1430 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1400. For example, the infotainment SoC 1430 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, an onboard computer, an onboard entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a head-up display ("HUD"), an HMI display 1434, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1430 may be further configured to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 1400, such as information from an ADAS system 1438, autonomous driving information (e.g., planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0288] In at least one embodiment, the infotainment SoC 1430 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1430 can communicate with other devices, systems, and / or components of the vehicle 1400 via the bus 1402. In at least one embodiment, the infotainment SoC 1430 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event that one or more of the main controllers 1436 (e.g., the vehicle's 1400 main computer and / or backup computer) fails. In at least one embodiment, the infotainment SoC 1430 can place the vehicle 1400 in a driver-to-safety parking mode, as described herein.

[0289] In at least one embodiment, the vehicle 1400 may further include an instrument panel 1432 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 1432 may include, but is not limited to, a controller and / or a supercomputer (e.g., a separate controller or a supercomputer). In at least one embodiment, the instrument panel 1432 may include, but is not limited to, a set of instruments in any number and combination, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a gear position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1430 and the instrument panel 1432. In at least one embodiment, the instrument panel 1432 may be included as part of the infotainment SoC 1430, or vice versa.

[0290] In at least one embodiment, Figure 14C At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 14C The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 14C The components can be used to train one or more neural networks (such as, Figure 4 400 ) and performing inference using the one or more neural networks.

[0291] Figure 14D In accordance with at least one embodiment, one or more cloud-based servers and Figure 14A14. A diagram of a system for communicating between autonomous vehicles 1400. In at least one embodiment, the system may include, but is not limited to, one or more servers 1478, one or more networks 1490, and any number and type of vehicles, including vehicle 1400. In at least one embodiment, one or more servers 1478 may include, but are not limited to, multiple GPUs 1484(A)-1484(H) (collectively referred to herein as GPUs 1484), PCIe switches 1482(A)-1482(D) (collectively referred to herein as PCIe switches 1482), and / or CPUs 1480(A)-1480(B) (collectively referred to herein as CPUs 1480). In at least one embodiment, GPUs 1484, CPUs 1480, and PCIe switches 1482 may be interconnected with a high-speed interconnect, such as, for example, but not limited to, NVLink interface 1488 and / or PCIe connection 1486 developed by NVIDIA. In at least one embodiment, the GPUs 1484 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1484 and PCIe switches 1482 are connected via PCIe interconnects. Although eight GPUs 1484, two CPUs 1480, and four PCIe switches 1482 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1478 may include, but is not limited to, any number of GPUs 1484, CPUs 1480, and / or PCIe switches 1482 in any combination. For example, in at least one embodiment, one or more servers 1478 may each include eight, sixteen, thirty-two, and / or more GPUs 1484.

[0292] In at least one embodiment, one or more servers 1478 may receive image data representing an image from a vehicle via one or more networks 1490 that depicts an unexpected or altered road condition, such as a recently begun road project. In at least one embodiment, one or more servers 1478 may transmit an updated neural network 1492 and / or map information 1494 to the vehicle via one or more networks 1490, including, but not limited to, information regarding traffic and road conditions. In at least one embodiment, updates to the map information 1494 may include, but not limited to, updates to the HD map 1422, such as information regarding construction sites, potholes, service roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1492 and / or map information 1494 may have been generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or may be based at least on training performed at a data center (e.g., using one or more servers 1478 and / or other servers).

[0293] In at least one embodiment, one or more servers 1478 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., sent to the vehicle via one or more networks 1490, and / or the machine learning model can be used by one or more servers 1478 to remotely monitor the vehicle.

[0294] In at least one embodiment, one or more servers 1478 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 1478 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1484, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1478 can include the deep learning infrastructure of a data center using CPU power.

[0295] In at least one embodiment, the deep learning infrastructure of one or more servers 1478 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or associated hardware in the vehicle 1400. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1400, such as an image sequence and / or objects that the vehicle 1400 has located in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1400, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1400 is malfunctioning, the one or more servers 1478 may send a signal to the vehicle 1400 instructing the vehicle's 1400 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0296] In at least one embodiment, one or more servers 1478 may include one or more GPUs 1484 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time responses. In at least one embodiment, such as in situations where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 1115 are used to execute one or more embodiments. Figure 11A and / or Figure 11B Provides details about the hardware structure 1115.

[0297] In at least one embodiment, Figure 14D At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 14D The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 14D The components can be used to train one or more neural networks (such as, in combination with Figure 4 400 ) and performing inference using the one or more neural networks.

[0298] Computer system

[0299] Figure 15 15 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include an execution unit for executing instructions. In at least one embodiment, in accordance with the present disclosure, such as in the embodiments described herein, computer system 1500 may include, but is not limited to, components such as processor 1502 for executing algorithms for processing data using execution units (including logic). In at least one embodiment, computer system 1500 may include a processor such as the Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, CoreTM or In at least one embodiment, computer system 1500 may be configured to run a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0300] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0301] In at least one embodiment, computer system 1500 may include, but is not limited to, a processor 1502, which may include, but is not limited to, one or more execution units 1508 for performing machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, computer system 1500 is a single-processor desktop or server system, but in another embodiment, computer system 1500 may be a multi-processor system. In at least one embodiment, processor 1502 may include, but is not limited to, for example, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1502 may be coupled to a processor bus 1510, which may transmit data signals between processor 1502 and other components in computer system 1500.

[0302] In at least one embodiment, processor 1502 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1504. In at least one embodiment, processor 1502 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1502. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1506 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0303] In at least one embodiment, an execution unit 1508, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1502. In at least one embodiment, the processor 1502 may also include a microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, the execution unit 1508 may include logic for processing a packed instruction set 1509. In at least one embodiment, by including the packed instruction set 1509 in the instruction set of a general-purpose processor and associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the processor 1502. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0304] In at least one embodiment, execution unit 1508 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 1500 may include, but is not limited to, memory 1520. In at least one embodiment, memory 1520 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1520 may store one or more instructions 1519 and / or data 1521 represented by data signals that may be executed by processor 1502.

[0305] In at least one embodiment, the system logic chip can be coupled to the processor bus 1510 and the memory 1520. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1516, and the processor 1502 can communicate with the MCH 1516 via the processor bus 1510. In at least one embodiment, the MCH 1516 can provide a high-bandwidth memory path 1518 to the memory 1520 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1516 can direct data signals between the processor 1502, the memory 1520, and other components in the computer system 1500, and bridge data signals between the processor bus 1510, the memory 1520, and the system I / O interface 1522. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1516 may be coupled to the memory 1520 via a high-bandwidth memory path 1518 , and the graphics / video card 1512 may be coupled to the MCH 1516 via an accelerated graphics port (“AGP”) interconnect 1514 .

[0306] In at least one embodiment, computer system 1500 may use system I / O interface 1522 as a proprietary hub interface bus to couple MCH 1516 to I / O controller hub ("ICH") 1530. In at least one embodiment, ICH 1530 may provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to memory 1520, chipset, and processor 1502. Examples may include, but are not limited to, an audio controller 1529, a firmware hub ("flash BIOS") 1528, a wireless transceiver 1526, a data store 1524, a legacy I / O controller 1523 including a user input and keyboard interface 1525, a serial expansion port 1527 (such as a universal serial bus ("USB") port), and a network controller 1534. In at least one embodiment, data store 1524 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0307] In at least one embodiment, Figure 15 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 15 An exemplary SoC may be shown. In at least one embodiment, Figure 15The devices shown in FIG1500 can be interconnected using a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1500 are interconnected using a Compute Express Link (CXL) interconnect.

[0308] Logic 1115 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 11A and / or Figure 11B Details are provided regarding logic 1115. In at least one embodiment, logic 1115 can be used in computer system 1500 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0309] In at least one embodiment, Figure 15 At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 15 The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 15 The components can be used to train one or more neural networks (such as, in combination with Figure 4 As another example, in at least one embodiment, Figure 15 The components of can be used to transcribe one or more audio files and pre-process the text before sending it to one or more neural networks for summarization.

[0310] Figure 16 1 is a block diagram illustrating an electronic device 1600 for utilizing a processor 1610 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1600 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0311] In at least one embodiment, the electronic device 1600 may include, but is not limited to, a processor 1610 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, the processor 1610 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Figure 16 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 16 An exemplary SoC may be shown. In at least one embodiment, Figure 16 The devices shown in can be interconnected using a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 16 One or more components of the system are interconnected using a Compute Express Link (CXL) interconnect.

[0312] In at least one embodiment, Figure 16 It may include a display 1624, a touch screen 1625, a touchpad 1630, a near field communication unit (“NFC”) 1645, a sensor hub 1640, a thermal sensor 1646, an express chipset (“EC”) 1635, a trusted platform module (“TPM”) 1638, BIOS / firmware / flash memory (“BIOS, FW Flash”) 1622, a DSP 1660, a drive 1620 (such as a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1650, a Bluetooth unit 1652, a wireless wide area network unit (“WWAN”) 1656, a global positioning system (GPS) unit 1655, a camera (“USB 3.0 camera”) 1654 (such as a USB 3.0 camera), and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1615 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0313] In at least one embodiment, other components may be communicatively coupled to processor 1610 via the components described herein. In at least one embodiment, accelerometer 1641, ambient light sensor (“ALS”) 1642, compass 1643, and gyroscope 1644 may be communicatively coupled to sensor hub 1640. In at least one embodiment, thermal sensor 1639, fan 1637, keyboard 1636, and touchpad 1630 may be communicatively coupled to EC 1635. In at least one embodiment, speaker 1663, earphone 1664, and microphone (“mic”) 1665 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1662, which in turn may be communicatively coupled to DSP 1660. In at least one embodiment, audio unit 1662 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1657 may be communicatively coupled to WWAN unit 1656. In at least one embodiment, components such as the WLAN unit 1650 and the Bluetooth unit 1652 and the WWAN unit 1656 may be implemented as a next generation form factor ("NGFF").

[0314] Logic 1115 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 11A and / or Figure 11B Details are provided regarding logic 1115. In at least one embodiment, logic 1115 may be used in electronic device 1600 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0315] In at least one embodiment, Figure 16 At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 16 The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 16 The processor 1610 corresponds to the combination of Figure 1 At least one processor of the described one or more processors.

[0316] Figure 17 Illustrated is a computer system 1700 in accordance with at least one embodiment. In at least one embodiment, the computer system 1700 is configured to implement the various processes and methods described throughout this disclosure.

[0317] In at least one embodiment, computer system 1700 includes, but is not limited to, at least one central processing unit ("CPU") 1702 connected to a communication bus 1710 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1700 includes, but is not limited to, main memory 1704 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1704, which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1722 provides an interface to other computing devices and networks for receiving data from and sending data to other systems using computer system 1700.

[0318] In at least one embodiment, computer system 1700 includes, but is not limited to, input device 1708, parallel processing system 1712, and display device 1706, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diode ("LED") displays, plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1708 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein can be located on a single semiconductor platform to form a processing system.

[0319] Logic 1115 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 11A and / or Figure 11B Details are provided regarding inference and / or training logic 1115. In at least one embodiment, logic 1115 can be used in computer system 1700 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0320] In at least one embodiment, Figure 17 At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 17 The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 17 The computer system 1700 corresponds to the combination Figure 1Computer system 101 is described.

[0321] Figure 18 A computer system 1800 is shown according to at least one embodiment. In at least one embodiment, computer system 1800 includes, but is not limited to, a computer 1810 and a USB drive 1820. In at least one embodiment, computer 1810 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1810 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0322] In at least one embodiment, the USB disk 1820 includes, but is not limited to, a processing unit 1830, a USB interface 1840, and USB interface logic 1850. In at least one embodiment, the processing unit 1830 may be any instruction execution system, device, or apparatus capable of executing instructions. In at least one embodiment, the processing unit 1830 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1830 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1830 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing unit 1830 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0323] In at least one embodiment, USB interface 1840 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1840 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1840 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1850 can include any number and type of logic that enables processing unit 1830 to interface with a device (e.g., computer 1810) via USB connector 1840.

[0324] Logic 1115 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 11A and / or Figure 11B Details are provided regarding logic 1115. In at least one embodiment, logic 1115 can be used in computer system 1800 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0325] In at least one embodiment, Figure 18 At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 18 The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 18 The computer system 1800 corresponds to the combination Figure 1 Computer system 101 is described.

[0326] Figure 19A An exemplary architecture is shown in which a plurality of GPUs 1910(1)-1910(N) are communicatively coupled to a plurality of multi-core processors 1905(1)-1905(M) via high-speed links 1940(1)-1940(N) (e.g., a bus, a point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1940(1)-1940(N) support a communication throughput of 4GB / s, 30GB / s, 80GB / s, or more. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure. In at least one embodiment, one or more of the plurality of GPUs 1910(1)-1910(N) include, for example, Figure 22A and Figure 22B 2. In at least one embodiment, one or more graphics cores 2200 may be referred to as streaming multiprocessors ("SMs"), streaming processors ("SPs"), streaming processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where, in this context, a slice may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or a scheduler).

[0327] Furthermore, in at least one embodiment, two or more GPUs 1910 are interconnected via high-speed links 1929(1)-1929(2), which may be implemented using protocols / links similar to or different from those used for high-speed links 1940(1)-1940(N). Similarly, two or more multi-core processors 1905 may be connected via high-speed link 1928, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links may be used (e.g., via a common interconnect fabric) to accomplish this. Figure 19A All communications between the various system components shown in .

[0328] In at least one embodiment, each multi-core processor 1905 is communicatively coupled to processor memory 1901(1)-1901(M) via memory interconnects 1926(1)-1926(M), respectively, and each GPU 1910(1)-1910(N) is communicatively coupled to GPU memory 1920(1)-1920(N) via GPU memory interconnects 1950(1)-1950(N), respectively. In at least one embodiment, memory interconnects 1926 and 1950 can utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1901(1)-1901(M) and GPU memory 1920 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 1901 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0329] As described herein, although each multi-core processor 1905 and GPU 1910 can be physically coupled to a specific memory 1901, 1920, respectively, and / or a unified memory architecture can be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, processor memories 1901(1)-1901(M) can each include 64GB of system memory address space, and GPU memories 1920(1)-1920(N) can each include 32GB of system memory address space, resulting in a total of 256GB of addressable memory when M=2 and N=4. Other values ​​of N and M are possible.

[0330] In at least one embodiment, Figure 19A At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 19A The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 19A At least one of the GPUs 1910(1-N) corresponds to a combination of Figure 1 One of the one or more processors 106 depicted.

[0331] Figure 19B Additional details are shown for the interconnection between multi-core processor 1907 and graphics acceleration module 1946 according to an exemplary embodiment. In at least one embodiment, graphics acceleration module 1946 may include one or more GPU chips integrated on a line card that is coupled to processor 1907 via a high-speed link 1940 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 1946 may alternatively be integrated on a package or chip with processor 1907.

[0332] In at least one embodiment, processor 1907 includes multiple cores 1960A-1960D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1961A-1961D and one or more caches 1962A-1962D. In at least one embodiment, cores 1960A-1960D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, caches 1962A-1962D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1956 may be included in caches 1962A-1962D and shared by groups of cores 1960A-1960D. For example, one embodiment of processor 1907 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1907 and the graphics acceleration module 1946 are connected to the system memory 1914, which may include Figure 19A Processor memory 1901(1)-1901(M) in.

[0333] In at least one embodiment, coherence of data and instructions stored in the various caches 1962A-1962D, 1956, and system memory 1914 is maintained through inter-core communication over coherent bus 1964. For example, in at least one embodiment, each cache may have cache coherence logic / circuitry associated therewith to communicate over coherent bus 1964 in response to a detected read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over coherence bus 1964 to snoop cache accesses.

[0334] In at least one embodiment, proxy circuitry 1925 communicatively couples graphics acceleration module 1946 to coherence bus 1964, thereby allowing graphics acceleration module 1946 to participate in a cache coherence protocol as a peer of cores 1960A-1960D. In particular, in at least one embodiment, interface 1935 provides connectivity to proxy circuitry 1925 via high-speed link 1940, and interface 1937 connects graphics acceleration module 1946 to high-speed link 1940.

[0335] In at least one embodiment, the accelerator integrated circuit 1936 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1931(1)-1931(N) of the graphics acceleration module 1946. In at least one embodiment, the graphics processing engines 1931(1)-1931(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the multiple graphics processing engines 1931(1)-1931(N) of the graphics acceleration module 1946 include, for example, a combination of Figure 22A and Figure 22B The one or more graphics cores 2200 discussed. In at least one embodiment, the graphics processing engines 1931(1)-1931(N) may alternatively include different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1946 may be a GPU having multiple graphics processing engines 1931(1)-1931(N), or the graphics processing engines 1931(1)-1931(N) may be individual GPUs integrated on a common package, circuit card, or chip.

[0336] In at least one embodiment, the accelerator integrated circuit 1936 includes a memory management unit (MMU) 1939 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and a memory access protocol for accessing system memory 1914. In at least one embodiment, the MMU 1939 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 1938 may store commands and data for efficient access by the graphics processing engines 1931(1)-1931(N). In at least one embodiment, a fetch unit 1944 may be used to keep data stored in the cache 1938 and graphics memory 1933(1)-1933(M) consistent with the core caches 1962A-1962D, 1956, and system memory 1914. As previously described, this can be implemented on behalf of cache 1938 and memory 1933(1)-1933(M) via proxy circuit 1925 (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1962A-1962D, 1956 to cache 1938 and receiving updates from cache 1938).

[0337] In at least one embodiment, a set of registers 1945 stores context data for threads executed by graphics processing engines 1931(1)-1931(N), and context management circuitry 1948 manages thread contexts. For example, context management circuitry 1948 can perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1948 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​can then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 1947 receives and processes interrupts received from system devices.

[0338] In at least one embodiment, the MMU 1939 translates virtual / effective addresses from the graphics processing engine 1931 into real / physical addresses in the system memory 1914. In at least one embodiment, the accelerator integrated circuit 1936 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1946 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1946 can be dedicated to a single application executing on the processor 1907, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1931 (1)-1931 (N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0339] In at least one embodiment, the accelerator integrated circuit 1936 acts as a bridge to the system for the graphics acceleration module 1946 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1936 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1931(1)-1931(N).

[0340] In at least one embodiment, because the hardware resources of graphics processing engines 1931(1)-1931(N) are explicitly mapped into the real address space seen by host processor 1907, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1936 is the physical separation of graphics processing engines 1931(1)-1931(N) so that they appear to the system as independent units.

[0341] In at least one embodiment, one or more graphics memories 1933(1)-1933(M) are coupled to each graphics processing engine 1931(1)-1931(N), respectively, with N=M. In at least one embodiment, graphics memories 1933(1)-1933(M) store instructions and data being processed by each graphics processing engine 1931(1)-1931(N). In at least one embodiment, graphics memories 1933(1)-1933(M) can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0342] In at least one embodiment, to reduce data traffic on high-speed link 1940, a biasing technique may be used to ensure that the data stored in graphics memory 1933(1)-1933(M) is the data most frequently used by graphics processing engines 1931(1)-1931(N), and preferably is not used (at least not frequently) by cores 1960A-1960D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not needed by graphics processing engines 1931(1)-1931(N)) in caches 1962A-1962D, 1956, and system memory 1914.

[0343] In at least one embodiment, Figure 19B At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 19B The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 19B The processor 1907 corresponds to the combination of Figure 1 One of the one or more processors 106 depicted.

[0344] Figure 19C Another exemplary embodiment is shown in which an accelerator integrated circuit 1936 is integrated within the processor 1907. In this embodiment, the graphics processing engines 1931(1)-1931(N) communicate directly with the accelerator integrated circuit 1936 via interface 1937 and interface 1935 (again, which can be any form of bus or interface protocol) over a high-speed link 1940. In at least one embodiment, the accelerator integrated circuit 1936 can perform operations related to Figure 19B The operations described above are similar to those described above, but may have higher throughput due to its close proximity to the coherence bus 1964 and caches 1962A-1962D, 1956. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1936 and a programming model controlled by the graphics acceleration module 1946.

[0345] In at least one embodiment, graphics processing engines 1931(1)-1931(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1931(1)-1931(N), thereby providing virtualization within a VM / partition.

[0346] In at least one embodiment, graphics processing engines 1931(1)-1931(N) can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1931(1)-1931(N) to allow each operating system to access them. In at least one embodiment, for a single partition system without a hypervisor, the operating system owns graphics processing engines 1931(1)-1931(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1931(1)-1931(N) to provide access to each process or application.

[0347] In at least one embodiment, the graphics acceleration module 1946 or individual graphics processing engines 1931(1)-1931(N) use a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1914 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1931(1)-1931(N) (i.e., calling system software to add the process element to a linked list of process elements). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the linked list of process elements.

[0348] In at least one embodiment, Figure 19C At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 19C The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 19C The processor 1907 corresponds to the combination of Figure 1 One of the one or more processors 106 depicted.

[0349] Figure 19DAn exemplary accelerator integrated slice 1990 is shown. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of the accelerator integrated circuit 1936. In at least one embodiment, the application is an effective address space 1982 in system memory 1914, which stores a process element 1983. In at least one embodiment, the process element 1983 is stored in response to a GPU call 1981 from an application 1980 executing on the processor 1907. In at least one embodiment, the process element 1983 contains the process state of the corresponding application 1980. In at least one embodiment, the work descriptor (WD) 1984 contained in the process element 1983 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1984 is a pointer to a job request queue in the effective address space 1982 of the application.

[0350] In at least one embodiment, the graphics acceleration module 1946 and / or the individual graphics processing engines 1931(1)-1931(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure can be included for setting process state and sending WD 1984 to the graphics acceleration module 1946 to start a job in a virtualized environment.

[0351] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns a graphics acceleration module 1946 or an individual graphics processing engine 1931. In at least one embodiment, when a graphics acceleration module 1946 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when a graphics acceleration module 1946 is assigned, the operating system initializes the accelerator integrated circuit 1936 for the owned process.

[0352] In operation, in at least one embodiment, a WD fetch unit 1991 in the accelerator integrated slice 1990 fetches a next WD 1984, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1946. In at least one embodiment, data from the WD 1984 may be stored in registers 1945 and used by the MMU 1939, interrupt management circuitry 1947, and / or context management circuitry 1948, as shown. For example, one embodiment of the MMU 1939 includes segment / page walk circuitry for accessing segment / page tables 1986 within the OS virtual address space 1985. In at least one embodiment, the interrupt management circuitry 1947 may process interrupt events 1992 received from the graphics acceleration module 1946. In at least one embodiment, when performing graphics operations, effective addresses 1993 generated by the graphics processing engines 1931(1)-1931(N) are converted to real addresses by the MMU 1939.

[0353] In at least one embodiment, registers 1945 are replicated for each graphics processing engine 1931(1)-1931(N) and / or graphics acceleration module 1946, and these registers 1945 can be initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers can be included in an accelerator integration slice 1990. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0354] Table 1 - Registers initialized by the hypervisor

[0355]

[0356]

[0357] Example registers that may be initialized by the operating system are shown in Table 2.

[0358] Table 2 - Registers initialized by the operating system

[0359]

[0360] In at least one embodiment, each WD 1984 is specific to a particular graphics acceleration module 1946 and / or graphics processing engine 1931(1)-1931(N). In at least one embodiment, it contains all the information needed by the graphics processing engine 1931(1)-1931(N) to complete its work, or it may be a pointer to a memory location where an application has set up a command queue for work to be done.

[0361] In at least one embodiment, Figure 19DAt least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 19D The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 19D The processor 1907 corresponds to the combination of Figure 1 One of the one or more processors 106 depicted.

[0362] Figure 19E Additional details of an exemplary embodiment of a sharing model are shown. This embodiment includes a hypervisor real address space 1998 in which a process element list 1999 is stored. In at least one embodiment, the hypervisor real address space 1998 is accessible via a hypervisor 1996 that virtualizes a graphics acceleration module engine for an operating system 1995.

[0363] In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 1946. In at least one embodiment, there are two programming models where the graphics acceleration module 1946 is shared by multiple processes and partitions, namely, time-sliced ​​sharing and graphics-directed sharing.

[0364] In at least one embodiment, in this model, the hypervisor 1996 owns the graphics acceleration module 1946 and makes its functionality available to all operating systems 1995. In at least one embodiment, for the graphics acceleration module 1946 to support virtualization through the hypervisor 1996, the graphics acceleration module 1946 may adhere to certain requirements, such as (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1946 must provide a context save and restore mechanism, (2) the graphics acceleration module 1946 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1946 provides the ability to preempt job processing, and (3) the graphics acceleration module 1946 must ensure fairness between processes when operating in a directed shared programming model.

[0365] In at least one embodiment, the application 1980 is required to make an operating system 1995 system call using a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1946 and can take the form of a graphics acceleration module 1946 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure that describes the work to be performed by the graphics acceleration module 1946.

[0366] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that set the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1936 (not shown) and the graphics acceleration module 1946 does not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1996 may selectively apply the current AMR value before placing the AMR into the process element 1983. In at least one embodiment, the CSRP is one of the registers 1945 that contains the effective address of an area in the application's effective address space 1982 for the graphics acceleration module 1946 to save and restore context state. In at least one embodiment, this pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0367] Upon receiving the system call, the operating system 1995 can verify that the application 1980 has been registered and granted permission to use the graphics acceleration module 1946. Then, in at least one embodiment, the operating system 1995 calls the hypervisor 1996 using the information shown in Table 3.

[0368]

[0369] In at least one embodiment, upon receiving the hypervisor call, hypervisor 1996 verifies that operating system 1995 has registered and been granted permission to use graphics acceleration module 1946. Then, in at least one embodiment, hypervisor 1996 places process element 1983 into a linked list of process elements of the corresponding type of graphics acceleration module 1946. In at least one embodiment, the process element may include the information shown in Table 4.

[0370] Table 4 - Process element information

[0371]

[0372]

[0373] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1990 registers 1945 .

[0374] like Figure 19F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memory 1901(1)-1901(N) and GPU memory 1920(1)-1920(N). In this implementation, operations executed on GPUs 1910(1)-1910(N) utilize the same virtual / effective memory address space to access processor memory 1901(1)-1901(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1901(1), a second portion is allocated to second processor memory 1901(N), a third portion is allocated to GPU memory 1920(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1901 and GPU memory 1920, thereby allowing any processor or GPU to access any physical memory using a virtual address mapped to that memory.

[0375] In at least one embodiment, bias / coherency management circuitry 1994A-1994E within one or more MMUs 1939A-1939E ensures cache coherency between the caches of one or more host processors (e.g., 1905) and GPU 1910 and implements biasing techniques that indicate physical memory where certain types of data should be stored. Figure 19FMultiple instances of bias / coherence management circuits 1994A- 1994E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1905 and / or within an accelerator integrated circuit 1936 .

[0376] One embodiment allows GPU memory 1920 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability to access GPU memory 1920 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows host processor 1905 software to set operands and access computation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1920 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in situations with heavy streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1910. In at least one embodiment, the efficiency of operand setup, result access, and GPU computation can play a role in determining the effectiveness of GPU offloading.

[0377] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU additional memory page. In at least one embodiment, the bias table can be implemented in a stolen memory range of one or more GPU memories 1920, with or without a bias cache in GPU 1910 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0378] In at least one embodiment, a bias table entry associated with each access to GPU-attached memory 1920 is accessed before the GPU memory is actually accessed, resulting in the following operations. In at least one embodiment, local requests from GPU 1910 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1920. In at least one embodiment, local requests from the GPU whose pages are found in the host bias are forwarded to processor 1905 (e.g., via a high-speed link as described herein). In at least one embodiment, requests from processor 1905 that find the requested page in the host processor bias complete similarly to normal memory reads. Alternatively, requests directed to GPU-biased pages can be forwarded to GPU 1910. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in a limited set of cases, a purely hardware-based mechanism.

[0379] In at least one embodiment, a mechanism for changing bias states employs an API call (e.g., OpenCL), which in turn calls a device driver for the GPU, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1905 bias to GPU bias, but not for the reverse migration.

[0380] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1905. In at least one embodiment, to access these pages, processor 1905 may request access from GPU 1910, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between processor 1905 and GPU 1910, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1905, and vice versa.

[0381] One or more hardware structures 1115 are used to implement one or more embodiments. Figure 11A and / or Figure 11B Details regarding one or more hardware structures 1115 are provided.

[0382] In at least one embodiment, Figure 19E At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 19E The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 19E The processor 1907 corresponds to the combination of Figure 1 One of the one or more processors 106 depicted.

[0383] Figure 20 An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to those shown, other logic and circuits may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0384] Figure 20 is a block diagram illustrating an exemplary system on a chip integrated circuit 2000 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 2000 includes one or more application processors 2005 (e.g., CPUs), at least one graphics processor 2010, and may additionally include an image processor 2015 and / or a video processor 2020, any of which can be modular IP cores. In at least one embodiment, integrated circuit 2000 includes peripheral or bus logic, including a USB controller 2025, a UART controller 2030, an SPI / SDIO controller 2035, and an I2S / I2C controller 2040. In at least one embodiment, integrated circuit 2000 may include a display device 2045 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 2050 and a Mobile Industry Processor Interface (MIPI) display interface 2055. In at least one embodiment, storage may be provided by a flash memory subsystem 2060, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 2065 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 2070 .

[0385] Logic 1115 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 11A and / or Figure 11BDetails are provided regarding logic 1115. In at least one embodiment, logic 1115 may be used in integrated circuit 2000 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0386] In at least one embodiment, Figure 20 At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 20 The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 20 The application processor 2005 and / or the graphics processor 2010 correspond to the combination Figure 1 One of the one or more processors 106 depicted.

[0387] Figure 21A and Figure 21B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to those shown, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0388] Figure 21A and Figure 21B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 21A An exemplary graphics processor 2110 of a system-on-chip integrated circuit is shown, which may be fabricated using one or more IP cores, in accordance with at least one embodiment. Figure 21B An additional exemplary graphics processor 2140 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 21A The graphics processor 2110 is a low-power graphics processor core. In at least one embodiment, Figure 21B The graphics processor 2140 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 2110, 2140 can be Figure 20 A variant of the GPU 2010.

[0389] In at least one embodiment, the graphics processor 2110 includes a vertex processor 2105 and one or more fragment processors 2115A-2115N (e.g., 2115A, 2115B, 2115C, 2115D through 2115N-1 and 2115N). In at least one embodiment, the graphics processor 2110 can execute different shader programs via separate logic, such that the vertex processor 2105 is optimized to perform operations for vertex shader programs, while one or more fragment processors 2115A-2115N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 2105 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 2115A-2115N use the primitives and vertex data generated by the vertex processor 2105 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 2115A-2115N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0390] In at least one embodiment, the graphics processor 2110 additionally includes one or more memory management units (MMUs) 2120A-2120B, one or more caches 2125A-2125B, and one or more circuit interconnects 2130A-2130B. In at least one embodiment, the one or more MMUs 2120A-2120B provide virtual to physical address mapping for the graphics processor 2110 (including for the vertex processor 2105 and / or the fragment processors 2115A-2115N), which can reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 2125A-2125B. In at least one embodiment, the one or more MMUs 2120A-2120B can synchronize with other MMUs within the system, including with other MMUs. Figure 20 One or more MMUs associated with one or more application processors 2005, graphics processor 2015, and / or video processor 2020 enable each processor 2005-2020 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2130A-2130B enable the graphics processor 2110 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0391] In at least one embodiment, graphics processor 2140 includes the following: Figure 21B One or more shader cores 2155A-2155N (e.g., 2155A, 2155B, 2155C, 2155D, 2155E, 2155F through 2155N-1 and 2155N) are shown, which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 2140 includes an inter-core task manager 2145 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2155A-2155N and a tiling unit 2158 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0392] Logic 1115 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 11A and / or Figure 11B Details are provided regarding logic 1115. In at least one embodiment, logic 1115 may be used in graphics processors 2110 and / or 2140 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0393] In at least one embodiment, Figure 21A and Figure 21B At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 21A and Figure 21B The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used or combined together to generate a summary of an audio transcript of an audio file.

[0394] Figure 22A and Figure 22B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figure 22A and Figure 22B Shown and combined Figures 22A-22B The components described are integrated into a single system, such as a graphics processing unit (GPU), SoC, or another type of processor. In at least one embodiment, Figure 22A Shows that can be included in Figure 20The graphics core 2200 within the graphics processor 2010 of FIG. 10 and, in at least one embodiment, may be as follows Figure 21B Unified shader cores 2155A-2155N are shown. Figure 22B A highly parallel general-purpose graphics processing unit ("GPGPU," which may also be referred to as a "graphics processing unit") 2230 suitable for deployment on a multi-chip module in at least one embodiment is shown. In at least one embodiment, graphics processing unit 2230 is a GPGPU that includes a graphics processor. In at least one embodiment, integrated circuit 2000 includes graphics core 2200, e.g., to form an integrated circuit and / or to form a SoC, wherein such integrated circuit and / or such SoC performs the operations described herein.

[0395] In at least one embodiment, graphics core 2200 includes a shared instruction cache 2202, texture units 2218, and cache / shared memory 2220 (e.g., including L1, L2, L3, last level cache, or other caches), which are common to execution resources within graphics core 2200. In at least one embodiment, graphics core 2200 may include multiple slices 2201A-2201N, or partitions of each core, and the graphics processor may include multiple instances of graphics core 2200. In at least one embodiment, each slice 2201A-2201N refers to graphics core 2200. In at least one embodiment, a slice 2201A-2201N has multiple sub-slices, which are portions of a slice 2201A-2201N. In at least one embodiment, slices 2201A-2201N may be independent of or dependent on other slices. In at least one embodiment, the slices 2201A-2201N may include support logic including a local instruction cache 2204A-2204N, a thread scheduler (serializer) 2206A-2206N, a thread dispatcher 2208A-2208N, and a set of registers 2210A-2210N. In at least one embodiment, the slices 2201A-2201N may include a set of additional function units (AFUs 2212A-2212N), floating point units (FPUs 2214A-2214N), integer arithmetic logic units (ALUs 2216A-2216N), address calculation units (ACUs 2213A-2213N), double precision floating point units (DPFPUs 2215A-2215N), and matrix processing units (MPUs 2217A-2217N). In at least one embodiment, the MPUs 2217A-2217N are referred to as a matrix engine.

[0396] In at least one embodiment, each slice 2201A-2201N includes one or more engines for floating-point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large data set workloads. In at least one embodiment, one or more slices 2201A-2201N include one or more vector engines for computing vectors (e.g., computing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16-bit floating point (also known as "FP16"), 32-bit floating point (also known as "FP32"), or 64-bit floating point (also known as "FP64"). In at least one embodiment, one or more slices 2201A-2201N include 16 vector engines paired with 16 matrix math units to compute matrix / tensor operations, where the vector engines and math units are illustrated by matrix expansion. In at least one embodiment, a slice can be a designated portion of the processing resources of a processing unit, for example, 16 cores and a ray tracing unit, or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of the processor. In at least one embodiment, graphics core 2200 includes one or more matrix engines for computing matrix operations, such as when computing tensor operations.

[0397] In at least one embodiment, one or more slices 2201A-2201N include one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice for slices 2201A-2201N). In at least one embodiment, the ray tracing units compute ray traversals, triangle intersections, bounding box intersections, or other ray tracing operations.

[0398] In at least one embodiment, one or more slices 2201A-2201N comprise a media slice that encodes, decodes, and / or transcodes data; scales and / or format converts data; and / or performs video quality operations on video data.

[0399] In at least one embodiment, one or more slices 2201A-2201N are linked to an L2 cache and memory structure, a link connector, a high bandwidth memory (HBM) (e.g., HBM2e, HDM3) stack, and a media engine. In at least one embodiment, one or more slices 2201A-2201N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 2201A-2201N have one or more L1 caches. In at least one embodiment, one or more slices 2201A-2201N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing, for example, data corresponding to instructions; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometry for performing operations in the geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., a shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by the shape); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, slices 2201A-2201N include memory structures, such as, for example, an L2 cache.

[0400] In at least one embodiment, the FPU 2214A-2214N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2215A-2215N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2216A-2216N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2217A-2217N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2217A-2217N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 2212A-2212N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0401] Logic 1115 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 11A and / or Figure 11B Details are provided regarding logic 1115. In at least one embodiment, logic 1115 may be used in graphics core 2200 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0402] In at least one embodiment, the graphics core 2200 includes an interconnect and a link fabric sublayer attached to switches and GPU-GPU bridges that enable multiple graphics processors 2200 (e.g., eight) to interconnect with each other without glue via load / store units (LSUs), data transfer units, and synchronization semantics across the multiple graphics processors 2200. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0403] In at least one embodiment, the graphics core 2200 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where each die can be connected with an interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, the graphics core 2200 includes compute tiles, memory tiles (e.g., where a memory tile is exclusively accessible by different tiles or different chipsets (such as a Rambo tile)), base tiles, base tiles, HMB tiles, link tiles, and EMIB tiles, where all tiles are packaged together in the graphics core 2200 as part of the GPU. In at least one embodiment, the graphics core 2200 can include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a compute tile can have eight graphics cores 2200, an L1 cache, and a base tile can have host interfaces with PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with eight links, and eight ports with an embedded switch. In at least one embodiment, the tiles are connected via fine-pitch 36 micron microbumps (e.g., copper pillars) with face-to-face (F2F) chip-to-chip bonding. In at least one embodiment, the graphics core 2200 includes a memory structure that includes memory and is accessible to multiple tiles.

[0404] In at least one embodiment, graphics core 2200 stores, accesses, or loads its own hardware context in memory, where the hardware context is a set of data loaded from registers before a process resumes, and where the hardware context may indicate the state of the hardware (e.g., the state of the GPU).

[0405] In at least one embodiment, graphics core 2200 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream into a parallel data stream, or vice versa.

[0406] In at least one embodiment, graphics core 2200 includes a high-speed coherent unified fabric (GPU to GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected via an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0407] In at least one embodiment, the graphics core 2200 executes an API that abstracts the graphics core 2200 hardware and uses instructions to access libraries to perform mathematical operations (e.g., math kernel libraries), deep neural network operations (e.g., deep neural network libraries), vector operations, aggregate communications, thread building blocks, video processing, data analytics libraries, and / or ray tracing operations.

[0408] In at least one embodiment, Figure 22A At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 22A The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used or combined together to generate a summary of an audio transcript of an audio file.

[0409] Figure 22BA GPGPU 2230 is shown in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by an array of graphics processing units. In at least one embodiment, GPGPU 2230 can be directly linked to other instances of GPGPU 2230 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 2230 includes a host interface 2232 for connecting to a host processor. In at least one embodiment, host interface 2232 is a PCI Express interface. In at least one embodiment, host interface 2232 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 2230 receives commands from the host processor and uses a global scheduler 2234 (which can be referred to as a thread serializer and / or asynchronous compute engine) to assign execution threads associated with those commands to a set of compute clusters 2236A-2236H. In at least one embodiment, compute clusters 2236A-2236H share a cache memory 2238. In at least one embodiment, cache memory 2238 may be used as a higher level cache for cache memory within compute clusters 2236A-2236H. In at least one embodiment, compute clusters 2236A-2236H include slices or "slices." In at least one embodiment, GPGPU 2230 is part of a SoC, such as integrated circuit 2000 ( Figure 20 ) part.

[0410] In at least one embodiment, the GPGPU 2230 includes memory 2244A-2244B coupled to the compute cluster 2236A-2236H via a set of memory controllers 2242A-2242B (e.g., one or more controllers of HBM2e). In at least one embodiment, the memory 2244A-2244B may include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0411] In at least one embodiment, the computing clusters 2236A-2236H each include a set of graphics cores, such as Figure 22AThe graphics core 2200 may include multiple types of integer and floating-point logic units that can perform computational operations across a range of precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each compute cluster 2236A-2236H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0412] In at least one embodiment, multiple instances of GPGPU 2230 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 2236A-2236H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 2230 communicate via host interface 2232. In at least one embodiment, GPGPU 2230 includes an I / O hub 2239 that couples GPGPU 2230 to a GPU link 2240, which enables direct connections to other instances of GPGPU 2230. In at least one embodiment, GPU link 2240 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2230. In at least one embodiment, GPU link 2240 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2230 are located in separate data processing systems and communicate via a network device accessible via host interface 2232. In at least one embodiment, GPU link 2240 may be configured to enable connection to a host processor in addition to or in lieu of host interface 2232 .

[0413] In at least one embodiment, the GPGPU 2230 can be configured to train a neural network. In at least one embodiment, the GPGPU 2230 can be used within an inference platform. In at least one embodiment, when using the GPGPU 2230 for inference, the GPGPU 2230 can include fewer compute clusters 2236A-2236H than when using the GPGPU 2230 for training a neural network. In at least one embodiment, the memory technology associated with the memories 2244A-2244B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2230 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0414] Logic 1115 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 11A and / or Figure 11B Details are provided regarding logic 1115. In at least one embodiment, logic 1115 may be used in GPGPU 2230 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0415] In at least one embodiment, Figure 22B At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 22B The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used or combined together to generate a summary of an audio transcript of an audio file.

[0416] Figure 23 23 is a block diagram illustrating a computing system 2300 according to at least one embodiment. In at least one embodiment, computing system 2300 includes a processing subsystem 2301 having one or more processors 2302 and system memory 2304 communicating via an interconnect path that may include a memory hub 2305. In at least one embodiment, memory hub 2305 may be a separate component within a chipset assembly or may be integrated within one or more processors 2302. In at least one embodiment, memory hub 2305 is coupled to an I / O subsystem 2311 via a communication link 2006. In at least one embodiment, I / O subsystem 2311 includes an I / O hub 2307, which enables computing system 2300 to receive input from one or more input devices 2308. In at least one embodiment, I / O hub 2307 may enable a display controller, which may be included in one or more processors 2302, to provide output to one or more display devices 2310A. In at least one embodiment, the one or more display devices 2310A coupled to the I / O hub 2307 may include local, internal, or embedded display devices.

[0417] In at least one embodiment, the processing subsystem 2301 includes one or more parallel processors 2312 coupled to the memory hub 2305 via a bus or other communication link 2313. In at least one embodiment, the communication link 2313 can use one of any number of standard based communication link technologies or protocols (such as, but not limited to, PCI Express), or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 2312 form a parallel or vector processing system in a computational cluster, which can include a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In at least one embodiment, some or all of the one or more parallel processors 2312 form a graphics processing subsystem that can output pixels to one of one or more display devices 2310A coupled via the I / O hub 2307. In at least one embodiment, the one or more parallel processors 2312 can also include a display controller and display interface (not shown) for enabling direct connection to one or more display devices 2310B. In at least one embodiment, the one or more parallel processors 2312 include one or more cores, such as the graphics core 2200 discussed herein.

[0418] In at least one embodiment, a system storage unit 2314 can be connected to the I / O hub 2307 to provide a storage mechanism for the computing system 2300. In at least one embodiment, an I / O switch 2316 can be used to provide an interface mechanism for enabling connections between the I / O hub 2307 and other components, such as a network adapter 2318 and / or a wireless network adapter 2319 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 2320. In at least one embodiment, the network adapter 2318 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2319 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0419] In at least one embodiment, the computing system 2300 may include other components not explicitly shown that may also be connected to the I / O hub 2307, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (such as NV-Link high-speed interconnect or interconnect protocol). Figure 23 The communication paths between the various components in the system.

[0420] In at least one embodiment, one or more parallel processors 2312 include circuits optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU), e.g., one or more parallel processors 2312 include graphics core 2200. In at least one embodiment, one or more parallel processors 2312 include circuits optimized for general-purpose processing. In at least one embodiment, the components of computing system 2300 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2312, memory hub 2305, one or more processors 2302, and I / O hub 2307 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 2300 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2300 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0421] Logic 1115 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 11A and / or Figure 11B Provides details about logic 1115. In at least one embodiment, logic 1115 may be Figure 23 for use in system 2300 for performing inference or prediction operations based at least in part on weight parameters computed using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0422] In at least one embodiment, Figure 23 At least one component shown or described is used to implement the combination Figure 1-8 In at least one embodiment, Figure 23 The components can be used with Figure 1-8 The components, processes, and / or combinations thereof are used together or in combination to generate a summary of an audio transcript of an audio file. In at least one embodiment, for example, Figure 23 The computer system 2300 corresponds to the combination Figure 1 Computer system 101 is described.

[0423] processor

[0424] Figure 24A2400 in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 2400 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 2400 is shown as a processor according to an exemplary embodiment. Figure 23 A variation of the one or more parallel processors 2312 is shown. In at least one embodiment, parallel processors 2400 include one or more graphics cores 2200.

[0425] In at least one embodiment, parallel processor 2400 includes parallel processing unit 2402. In at least one embodiment, parallel processing unit 2402 includes an I / O unit 2404 that enables communication with other devices, including other instances of parallel processing unit 2402. In at least one embodiment, I / O unit 2404 can be directly connected to other devices. In at least one embodiment, I / O unit 2404 connects to other devices using a hub or switch interface (e.g., memory hub 2405). In at least one embodiment, the connection between memory hub 2405 and I / O unit 2404 forms a communication link 2413. In at least one embodiment, I / O unit 2404 is connected to a host interface 2406 and a memory crossbar switch 2416, where host interface 2406 receives commands for performing processing operations and memory crossbar switch 2416 receives commands for performing memory operations.

[0426] In at least one embodiment, when host interface 2406 receives command buffers via I / O unit 2404, host interface 2406 can direct work operations for executing those commands to front end 2408. In at least one embodiment, front end 2408 is coupled with scheduler 2410 (which can be referred to as a serializer), which is configured to distribute commands or other work items to processing cluster array 2412. In at least one embodiment, scheduler 2410 ensures that processing cluster array 2412 is properly configured and in a valid state before assigning tasks to clusters within processing cluster array 2412. In at least one embodiment, scheduler 2410 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, a microcontroller-implemented scheduler 2410 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing cluster array 2412. In at least one embodiment, host software can validate workloads for scheduling on processing cluster array 2412 via one of multiple graphics processing paths. In at least one embodiment, the workload may then be automatically distributed across the processing cluster array 2412 by scheduler 2410 logic within a microcontroller that includes scheduler 2410 .

[0427] In at least one embodiment, processing cluster array 2412 may include up to "N" processing clusters (e.g., cluster 2414A, cluster 2414B, through cluster 2414N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, each cluster 2414A-2414N in processing cluster array 2412 may execute a large number of concurrent threads. In at least one embodiment, scheduler 2410 may use various scheduling and / or work distribution algorithms to distribute work to clusters 2414A-2414N in processing cluster array 2412, which may vary depending on the workload generated for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 2410 or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by processing cluster array 2412. In at least one embodiment, different clusters 2414A-2414N in processing cluster array 2412 may be assigned to process different types of programs or to perform different types of computations.

[0428] In at least one embodiment, processing cluster array 2412 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2412 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2412 can include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0429] In at least one embodiment, processing cluster array 2412 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2412 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2412 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 2402 may transfer data from system memory via I / O units 2404 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2422) during processing and then written back to system memory.

[0430] In at least one embodiment, when parallel processing unit 2402 is used to perform graphics processing, scheduler 2410 can be configured to divide the processing workload into tasks of approximately equal size to better enable distribution of graphics processing operations to multiple clusters 2414A-2414N in processing cluster array 2412. In at least one embodiment, portions of processing cluster array 2412 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2414A-2414N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2414A-2414N for further processing.

[0431] In at least one embodiment, the processing cluster array 2412 can receive processing tasks to be executed via the scheduler 2410, which receives commands defining the processing tasks from the front end 2408. In at least one embodiment, the processing tasks can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2410 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 2408. In at least one embodiment, the front end 2408 can be configured to ensure that the processing cluster array 2412 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0432] In at least one embodiment, each of the one or more instances of parallel processing unit 2402 can be coupled to parallel processor memory 2422. In at least one embodiment, parallel processor memory 2422 can be accessed via memory crossbar 2416, which can receive memory requests from processing cluster array 2412 and I / O unit 2404. In at least one embodiment, memory crossbar 2416 can access parallel processor memory 2422 via memory interface 2418. In at least one embodiment, memory interface 2418 can include multiple partition units (e.g., partition unit 2420A, partition unit 2420B, through partition unit 2420N), which can each be coupled to a portion of parallel processor memory 2422 (e.g., a memory unit). In at least one embodiment, the number of partition units 2420A-2420N is configured to be equal to the number of memory cells, such that the first partition unit 2420A has a corresponding first memory cell 2424A, the second partition unit 2420B has a corresponding second memory cell 2424B, and the Nth partition unit 2420N has a corresponding Nth memory cell 2424N. In at least one embodiment, the number of partition units 2420A-2420N may not be equal to the number of memory cells.

[0433] In at least one embodiment, memory units 2424A-2424N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2424A-2424N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM), HBM2e, or HDM3. In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 2424A-2424N, allowing partition units 2420A-2420N to write to portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2422. In at least one embodiment, local instances of parallel processor memory 2422 may be eliminated in favor of a unified memory design that utilizes system memory as well as local cache memory.

[0434] In at least one embodiment, any of the clusters 2414A-2414N in the processing cluster array 2412 can process data to be written to any memory unit 2424A-2424N within the parallel processor memory 2422. In at least one embodiment, the memory crossbar 2416 can be configured to transmit the output of each cluster 2414A-2414N to any partition unit 2420A-2420N or to another cluster 2414A-2414N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 2414A-2414N can communicate with a memory interface 2418 via the memory crossbar 2416 to read from or write to various external memory devices. In at least one embodiment, memory crossbar switch 2416 has connections to memory interface 2418 for communicating with I / O unit 2104, and connections to local instances of parallel processor memory 2422, which enables processing units within different processing clusters 2414A-2414N to communicate with system memory or other memory that is not local to parallel processing unit 2402. In at least one embodiment, memory crossbar switch 2416 can use virtual channels to separate traffic flows between clusters 2414A-2414N and partition units 2420A-2420N.

[0435] In at least one embodiment, multiple instances of parallel processing unit 2402 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2402 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2402 can include higher precision floating point units relative to other instances. In at least one embodiment, a system including one or more instances of parallel processing unit 2402 or parallel processor 2400 can be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0436] Figure 24B is a block diagram of a partition unit 2420 according to at least one embodiment. In at least one embodiment, the partition unit 2420 is Figure 24A 2420N。In at least one embodiment, the partition unit 2420 includes an L2 cache 2421, a frame buffer interface 2425, and an ROP 2426 (raster operation unit). In at least one embodiment, the L2 cache 2421 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 2416 and the ROP 2426. In at least one embodiment, the L2 cache 2421 outputs read misses and urgent write-back requests to the frame buffer interface 2425 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 2425 for processing. In at least one embodiment, the frame buffer interface 2425 communicates with memory units in the parallel processor memory (such as Figure 24A is coupled to one of the memory units 2424A-2424N (e.g., within parallel processor memory 2422).

[0437] In at least one embodiment, ROP 2426 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2426 then outputs the processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2426 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2426 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data on a per-tile basis.

[0438] In at least one embodiment, ROP 2426 is included within each processing cluster (e.g., Figure 24A In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are routed through memory crossbar 2416. In at least one embodiment, the processed graphics data may be displayed on a display device such as a Figure 23 2302 for further processing, or by Figure 24A One of the processing entities within parallel processor 2400 is routed for further processing.

[0439] Figure 24C is a block diagram of a processing cluster 2414 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Figure 24A In at least one embodiment, processing cluster 2414 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster.

[0440] In at least one embodiment, the operation of the processing cluster 2414 can be controlled via a pipeline manager 2432 that allocates processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2432 Figure 24AThe scheduler 2410 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2434 and / or the texture unit 2436. In at least one embodiment, the graphics multiprocessor 2434 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 2414. In at least one embodiment, one or more instances of the graphics multiprocessor 2434 may be included within the processing cluster 2414. In at least one embodiment, the graphics multiprocessor 2434 may process data, and the data crossbar 2440 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2432 may facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 2440.

[0441] In at least one embodiment, each graphics multiprocessor 2434 within a processing cluster 2414 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0442] In at least one embodiment, instructions transmitted to the processing cluster 2414 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 2434. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 2434. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines can be idle during the cycle in which the thread group is being processed. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 2434. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2434, processing can be performed within consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on the graphics multiprocessor 2434.

[0443] In at least one embodiment, the graphics multiprocessor 2434 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2434 can abandon the internal cache and use cache memory within the processing cluster 2414 (e.g., L1 cache 2448). In at least one embodiment, each graphics multiprocessor 2434 can also access a partition unit (e.g., Figure 24A L2 cache within partition units 2420A-2420N) of the graphics multiprocessor 2434 is shared across all processing clusters 2414 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2434 can also access off-chip global memory, which can include one or more of local para...

Claims

1. A processor, comprising: One or more circuits for causing one or more neural networks to generate one or more summaries of the first portion of text based at least in part on one or more second portions of text.

2. The processor of claim 1 , wherein the one or more neural networks are configured to generate the text based at least in part on audio information.

3. The processor of claim 1 , wherein the one or more circuits are configured to generate one or more prompts to cause the one or more neural networks to store information generated from the one or more second portions of the text and to generate the one or more summaries of the first portion of the text using the stored information.

4. The processor of claim 1 , wherein the one or more circuits are to combine two or more summaries of two or more portions of the text and cause the one or more neural networks to generate a summary of the combined two or more summaries.

5. The processor of claim 1, wherein the one or more circuits are configured to modify a transcript of audio to generate the text.

6. The processor of claim 1, wherein the first portion and each of the one or more portions of the text are transcripts of portions of an audio track.

7. The processor of claim 1 , wherein the one or more circuits are configured to cause the one or more neural networks to generate one or more summaries in a specified format.

8. A method comprising: One or more circuits cause one or more neural networks to generate one or more summaries of the first portion of the text based at least in part on one or more second portions of the text.

9. The method of claim 8, wherein the one or more neural networks are used to generate the text based at least in part on an audio track recording a multi-speaker conference.

10. The method of claim 8, wherein the one or more circuits are configured to generate one or more prompts comprising the one or more second portions of the text to cause the one or more neural networks to generate the one or more summaries of the first portion of the text.

11. The method of claim 8, wherein the one or more circuits are configured to combine two or more summaries of two or more portions of the text and cause the one or more neural networks to generate a summary of the combined two or more summaries in a format specified by a prompt.

12. The method of claim 8, wherein the one or more circuits are configured to: Split an audio track into one or more track segments; transcribing each of the one or more track segments; and The transcripts of the transcribed audio track segments are combined to generate the text.

13. The method of claim 8, wherein the one or more circuits are configured to: generating one or more transcripts from the audio track; modifying each of the one or more transcripts; and Each of the one or more modified transcripts is combined to generate the text.

14. The method of claim 8, wherein the one or more circuits are configured to cause the one or more neural networks to generate a summary of the text in a format specified by a prompt.

15. A system comprising: one or more processors; as well as A memory for storing instructions that, when executed by the one or more processors, cause one or more neural networks to generate one or more summaries of a first portion of text based at least in part on one or more second portions of text.

16. The system of claim 15, wherein the one or more neural networks are used to generate the text based at least in part on an audio file.

17. The system of claim 15, wherein the one or more circuits are configured to generate one or more prompts comprising one or more summaries of the one or more second portions of the text to cause the one or more neural networks to generate the one or more summaries of the first portion of the text.

18. The system of claim 15, wherein the one or more circuits are configured to transcribe an audio track into one or more segments and combine transcripts of different audio track segments to generate the text.

19. The system of claim 15, wherein the text includes a timestamp, punctuation marks, and capital letters.

20. The system of claim 15, wherein the one or more circuits are configured to generate an audio transcript from a meeting recording and generate a summary of the audio transcript using the one or more neural networks.

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