An on-chip image recognition method based on ultra-high switching ratio memristor drive

Abstract

This invention discloses an on-chip image recognition method based on ultra-high switching ratio memristor drive, belonging to the field of image recognition. This invention aims to solve the crosstalk problem faced by existing passive memristor arrays in on-chip neuromorphic computing. The invention includes the following steps: inputting an image; preprocessing the input image to obtain a relative intensity ranking matrix of the input image pixels; obtaining sample vectors; converting the distribution of the relative intensity ranking matrix into spatiotemporal pulse sequence coding topological features, constructing a sequence pulse topological mapping relationship that matches the arrangement of the spatiotemporal pulse sequence coding topological features; extracting an initial feature vector for each sample vector based on the sample vectors and the sequence pulse topological mapping; constructing a topological neural network; training the topological neural network; inputting the sample vectors into the trained topological neural network, and selecting the digit category that best matches the sample vectors as the output result.

Description

Technical Field

[0001] This invention relates to the field of image recognition technology, and more specifically to an on-chip image recognition method based on ultra-high switching ratio memristor driving. Background Technology

[0002] Traditional von Neumann computing architectures suffer from inherent bottlenecks due to the physical separation of memory and processing units, severely limiting the computational efficiency and energy sustainability of data-intensive applications. To address this issue, neuromorphic computing systems based on memristor arrays have emerged. These systems enable in-memory computation and parallelized vector-matrix multiplication, fundamental operations for accelerating neural networks. Memristors, with their programmable conductance states, can intrinsically simulate synaptic plasticity, making them an ideal platform for hardware-based neural networks.

[0003] However, traditional methods that directly map neural weights to memristor conductance face persistent challenges, such as array crosstalk, limited scalability, and device-level variability, which hinder reliable large-scale implementation. Existing neuromorphic computing systems suffer from severe crosstalk, poor scalability, insufficient device consistency, and limited recognition accuracy, failing to meet the demands of large-scale, high-precision pattern recognition applications.

[0004] Specifically, existing passive memristor arrays face crosstalk challenges in on-chip neuromorphic computing; while the 1T1R (1 Transistor 1 Resistor) / 1S1R (1 Selector 1 Resistor) architecture suffers from scalability limitations and area overhead. Traditional intensity-to-conductance mapping methods, when processing large-scale neural networks, suffer from decreased recognition accuracy and increased power consumption due to conductance differences between devices and leakage current issues within the array.

[0005] Furthermore, existing memristors have a relatively low on / off ratio, typically in the range of... This range makes it difficult to effectively suppress leakage current in high-density arrays, thus affecting the overall system performance. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention proposes an on-chip image recognition method based on ultra-high switching ratio memristor driving, comprising the following steps:

[0007] Step 1: Input image;

[0008] Step 2: Preprocess the input image to obtain the relative intensity sorting matrix of the input image pixels;

[0009] Step 3: Obtain the sample vector based on the relative strength ranking matrix;

[0010] Step 4: Convert the relative intensity sorting matrix distribution into spatiotemporal pulse sequence coding topological features, and map the spatiotemporal pulse sequence coding topological features onto a 32×32 integrated passive array to construct a sequence pulse topological mapping relationship that matches the arrangement of the spatiotemporal pulse sequence coding topological features; the 32×32 integrated passive array integrates ultra-high switching ratio memristors; Step 5: Extract the initial feature vector of each sample vector based on the sample vector and the topological mapping of the sequence pulses;

[0011] Step 6: Construct a topological neural network;

[0012] Step 7: Train a topological neural network based on the initial feature vector and sample vector;

[0013] Step 8: Input the sample vector into the trained topological neural network to obtain the output result.

[0014] As a further improvement of the present invention, by calculating the relative intensity sorting matrix distribution, the pulse sequence applied to the 32×32 integrated passive array is sorted according to time. Only one set of voltage pulses is applied to the 32×32 integrated passive array within each time step. When voltage pulses are applied at different positions, the position of the voltage pulse in the entire pulse sequence corresponds to the sorting number of the image pixel intensity. Thus, the topological features are mapped to the 32×32 integrated passive array, constructing a sequence pulse topological mapping relationship that matches the arrangement of the spatiotemporal pulse sequence coding topological features.

[0015] As a further improvement of the present invention, step 5 extracts the initial feature vector of each sample vector, specifically by using a cold start algorithm to extract the initial feature vector corresponding to each sample vector based on the sample vector and the topological mapping of the sequence pulse.

[0016] As a further improvement of the present invention, the construction of the topological neural network in step 6 is specifically: constructing the topological neural network based on the PCB peripheral control circuit and the 32×32 integrated passive array.

[0017] As a further improvement of the present invention, the training of the topological neural network in step 7 specifically involves: using the ridge regression algorithm to train the topological neural network based on the count of the activation ultra-high switching ratio memristor points corresponding to the initial feature vector and sample vector at the diagonal positions of the 32×32 integrated passive array.

[0018] As a further improvement of the present invention, the 32×32 integrated passive array integrates an ultra-high switching ratio memristor.

[0019] As a further improvement of the present invention, the specific steps for obtaining the output result in step 8 are as follows: inputting the sample vector into the trained topological neural network, comparing the sample vector with the number of diagonal activations of the 32×32 integrated passive array corresponding to each digit category, and selecting the digit category that best matches the sample vector as the output result.

[0020] As a further improvement of the present invention, in step 3, the relative strength ranking matrix is ​​linearly transformed to obtain a one-dimensional vector with a dimension of 1×625, which is the sample vector.

[0021] As a further improvement of the present invention, in step 2, the input image is converted into a grayscale image and then its size is standardized to 25×25 pixels, thereby obtaining the relative intensity sorting matrix of the input image pixels.

[0022] As a further improvement of the present invention, the ultra-high switching ratio memristor is fabricated using magnetron sputtering technology. structure.

[0023] As a further improvement of the present invention, the initial state of the ultra-high switching ratio memristor is a high resistance state.

[0024] The beneficial effects of this invention are:

[0025] By replacing the traditional intensity-conductance mapping with topological feature encoding, the crosstalk problem of traditional memristor arrays can be solved. Specifically, a crosstalk-free array activation mode is proposed to ensure that only one memristor cell is activated in each row and column. In this way, when reading the activated point, the crosstalk path will be blocked by the inactive point, thus successfully eliminating the influence of crosstalk.

[0026] On-chip image recognition is achieved through topological combination based on pulse timing, that is, converting image pixel intensity into spatiotemporal pulse sequence encoding that preserves topological features. When the temporal arrangement of the feature vector and the sample vector is the same, the spatiotemporal ordering points of the applied pulses are also consistent. On a 32×32 integrated passive array, the activated ultra-high on / off ratio memristor points will be distributed around the diagonal of the 32×32 integrated passive array. Combining the pattern recognition method based on counting the diagonal activated memristors of the 32×32 integrated passive array with the high on / off ratio 32×32 integrated passive array can improve the scalability of the array.

[0027] The ultra-high switching ratio of memristors ( This gives it powerful discriminative capabilities, achieving a 99.8% recognition accuracy on the MNIST dataset. Based on the scalability analysis of the unit online pull OBPU method, the architecture demonstrates a storage potential of 6.59PB with a 10% read margin. Attached Figure Description

[0028] Figure 1 This is a structural diagram of the 32×32 integrated passive array and high switching ratio memristor in this embodiment;

[0029] Figure 2 This is the IV curve of the ultra-high switching ratio memristor in this embodiment;

[0030] Figure 3 This is a cycle endurance test of the ultra-high switching ratio memristor in this embodiment;

[0031] Figure 4 This embodiment presents a schematic diagram of an on-chip image recognition application topological neural network driven by an ultra-high switching ratio memristor.

[0032] Figure 5 In this embodiment, the activation points of the sample vector and feature vector are distributed in the diagonal region.

[0033] Figure 6 The number of diagonal activations for different combinations of numbers is shown in this embodiment. Detailed Implementation

[0034] To facilitate understanding of this application, a more comprehensive description will be provided below with reference to the accompanying drawings. The drawings illustrate the described embodiments. Rather, these embodiments are provided to enable a more thorough and complete understanding of the disclosure of this application.

[0035] In this implementation:

[0036] The pulse programming protocol is designed as a precise timing control system. It ensures the time synchronization of pulse signals through high-precision timing control, so that the memristor can receive voltage pulses at strictly aligned time points. The voltage pulse width is selected based on the optimization of memristor switching dynamics to ensure sufficient energy transfer while avoiding over-switching.

[0037] The ultra-high switching ratio memristor has a switching threshold voltage of 2.5V and a voltage pulse of 3.0V, ensuring that only at the matching level crossover point does the ultra-high switching ratio memristor accumulate enough voltage (approximately 3.0V) to exceed the switching threshold of 2.5V.

[0038] The auxiliary peripheral control circuit is the PCB (Printed Circuit Board) peripheral control circuit.

[0039] This invention proposes an on-chip image recognition method based on ultra-high switching ratio memristor driving, used for crosstalk-free on-chip memory computing of handwritten digit recognition. Memristors with this structure have an ultra-high on / off ratio. ,Exceed The duration of holding the device for more than a few seconds Durability.

[0040] like Figure 1 As shown, the ultra-high switching ratio memristor is fabricated using magnetron sputtering technology. Memristor structure.

[0041] Wherein, Pt represents platinum. Indium oxide, It is chromium. This indicates that chromium is doped into indium oxide using a co-sputtering thin film preparation method, where W represents tungsten.

[0042] Specifically, the ultra-high switching ratio memristor is fabricated using the following method:

[0043] After standard cleaning, the silicon substrate for the memristor was used to fabricate a patterned Pt bottom electrode with a thickness of 50 nm using thermal evaporation or electron beam evaporation at a DC sputtering power of 200 W. Then, a 20 nm thick Cr-doped electrode was fabricated using co-sputtering technology. Active layer, in which RF sputtering power of 100W was used, and Cr was sputtered using DC power of 50W. The argon gas flow rate in the sputtering chamber was set to 50 sccm. Cr doping was introduced through... The formation of lattice defects in the matrix reduces carrier mobility and increases high-resistivity state resistance, while Cr-induced conductive filaments reduce low-resistivity state resistance, thereby achieving an ultra-high on / off ratio memristor. Finally, a 30 nm thick W-type top electrode is fabricated using a DC sputtering power of 200 W.

[0044] The above preparation process is carried out under a vacuum degree better than The process is completed in Torr's magnetron sputtering system, with the substrate temperature maintained at room temperature.

[0045] Electrical tests were conducted on the ultra-high switching ratio memristor to verify its high switching ratio and cycle durability. The relevant test results are as follows: Figure 2 and Figure 3 As shown, this ultra-high switching ratio memristor has more than Its high switching ratio and good cycle endurance achieve The stable cycle ensures the stability and reliability of the ultra-high switching ratio memristor under long-term operation.

[0046] Statistical analysis verified the consistency among ultra-high switching ratio memristors. The conductance graphs for high and low resistance states showed a uniform and randomly distributed behavior. The cumulative probability distribution of the set and reset voltages for 100 randomly selected ultra-high switching ratio memristors showed the following variation among them. ,in, Standard deviation This is the average value.

[0047] Finally, the ultra-high switching ratio memristor is integrated into a 32×32 integrated passive array to form a complete array of storage and computing units.

[0048] like Figure 4 As shown, the on-chip image recognition method based on the aforementioned memristor with ultra-high switching ratio, driven by an ultra-high switching ratio memristor, includes the following steps:

[0049] Step 1: Input image;

[0050] Step 2: Preprocess the input image to obtain the relative intensity sorting matrix of the input image pixels;

[0051] The input image is converted into a grayscale image, and then its size is normalized to 25×25 pixels to obtain the relative intensity sorting matrix of the input image pixels;

[0052] Step 3: Linearly convert the relative strength ranking matrix into a 1×625 one-dimensional vector, which is the sample vector;

[0053] Step 4: Convert the relative intensity sorting matrix distribution into spatiotemporal pulse sequence coding topological features, and map the spatiotemporal pulse sequence coding topological features onto a 32×32 integrated passive array to construct a sequence pulse topological mapping relationship that matches the arrangement of the spatiotemporal pulse sequence coding topological features;

[0054] By calculating the relative intensity sorting matrix distribution, the pulse sequence applied to the 32×32 integrated passive array is sorted according to time. Only one set of voltage pulses is applied to the 32×32 integrated passive array within each time step. When voltage pulses are applied at different positions, the position of the voltage pulse in the entire pulse sequence corresponds to the sorting number of the image pixel intensity. Then, the topological features are mapped to the 32×32 integrated passive array to construct a sequence pulse topological mapping relationship that matches the arrangement of the spatiotemporal pulse sequence coding topological features.

[0055] Step 5: Extract the initial feature vector for each sample vector based on the sample vector and the topological mapping of the sequence pulses;

[0056] Based on the sample vectors and the topological mapping of the sequence pulses, the initial feature vector corresponding to each sample vector is extracted using the cold start algorithm.

[0057] Key features are obtained by image preprocessing and multiple iterations of topological mapping of the diagonal of a 32×32 integrated passive array with different sample vectors. These features are then converted into pulse signals received at different time positions on the bit lines of the 32×32 integrated passive array. These pulse signals form the initial feature vector for recognition and judgment, reflecting the feature intensity and relative position. They are expressed in binary form, which is the topological feature encoding of the sample, for subsequent image recognition.

[0058] Step 6: Construct a topological neural network;

[0059] A topological neural network is constructed based on PCB peripheral control circuits and a 32×32 integrated passive array.

[0060] Step 7: Train a topological neural network based on the initial feature vector and sample vector;

[0061] The ridge regression algorithm is used to train the topological neural network based on the count of the activation ultra-high switching ratio memristor points corresponding to the initial feature vector and sample vector at the diagonal position of the 32×32 integrated passive array.

[0062] The image pixel intensity is converted into a spatiotemporal pulse sequence coding method that preserves topological features. When the temporal arrangement of the initial feature vector and the temporal arrangement of the sample vector are consistent, that is, when the same topological feature coding is shared, the timing of the voltage pulses applied to the bit lines and word lines is basically consistent. The activation ultra-high switching ratio memristor points in the 32×32 integrated passive array are concentrated on the diagonal of the 32×32 integrated passive array. This diagonal activation mode reflects the consistent positional alignment of pixel intensities of similar levels.

[0063] Specifically, within each time step, the bit line and word line are only applied a voltage pulse once simultaneously. When the sample vector and the initial feature vector have the same topological feature encoding, the corresponding topological encoding process is executed on the 32×32 integrated passive array. At this time, the ultra-high switching ratio memristor points activated by the voltage pulse applied under the same timing are basically concentrated in the diagonal region of the 32×32 integrated passive array.

[0064] Specifically, a sample vector voltage pulse (1.5V, 10μs pulse width) is applied to the word line, while an initial feature vector voltage pulse (-1.5V, 10μs pulse width) is simultaneously transmitted to the bit line. This voltage pulse application method ensures that the applied voltage to the selected active bit is greater than the threshold switching voltage of the ultra-high switching ratio memristor, thereby causing the ultra-high switching ratio memristor to switch from its initial high resistance state to a low resistance state, at which point the output logic "1" is displayed. Meanwhile, the surrounding unselected ultra-high switching ratio memristors have not reached their turn-on voltage and remain in a high resistance state, at which point the output logic "0" is displayed.

[0065] Based on the above process, a matching vector is defined based on the count of activated ultra-high switching ratio memristor points on the diagonal of the 32×32 integrated passive array, and topological neural network training is performed based on this matching vector. When the initial feature vector matches the sample vector, the distribution of activated ultra-high switching ratio memristor points in the 32×32 integrated passive array will be concentrated in the diagonal region, and the number of activated ultra-high switching ratio memristor points is typically in the range of 200-400. However, when the two do not match, the distribution of activated ultra-high switching ratio memristor points is more dispersed, and the number of activated ultra-high switching ratio memristor points on the diagonal of the 32×32 integrated passive array is typically less than 100.

[0066] Based on the above pattern, a threshold can be set. This is used to train a topological neural network, thereby achieving high-precision pattern recognition based on topological feature matching.

[0067] The specific judgment rule is as follows: when the number of activated digital tags corresponding to the highest number of activated ultra-high switching ratio memristor points exceeds a set threshold. When the number is less than the threshold, it is considered a successful identification; when the number is less than the threshold, it is considered a successful identification. If the recognition fails, a new initial feature vector is constructed. This process is repeated until the recognition accuracy reaches 100%, thus completing the recognition process and outputting the final recognition result.

[0068] Furthermore, during training, the accuracy of the recognized label at each successful recognition point is continuously compared with the true label. A ridge regression scheme is also employed to gradually adjust the threshold. The process continues until the recognition accuracy reaches 100%. Ridge regression is used to update feature weights and effectively prevent model overfitting.

[0069] The real label mentioned here is the actual number represented on the image; in this embodiment, the real label is the number "3". The recognition label is the number represented by the image as predicted by the topological neural network.

[0070] Step 8: Input the sample vector into the trained topological neural network, and compare the sample vector with the number of diagonal activations of the 32×32 ensemble passive array corresponding to each digit category. Select the digit category that best matches the sample vector as the output result.

[0071] The sample vector is input into the trained topological neural network, and the sample vector is compared with the number of diagonal activations of the 32×32 integrated passive array corresponding to each number category. The number category that best matches the sample vector is selected as the output result, that is, the number category corresponding to the largest number of diagonal activations of the 32×32 integrated passive array memristor points with the highest switching ratio is selected as the output result.

[0072] like Figure 5 As shown in (a), the similarity map of the 32×32 integrated passive array when the sample vector matches the initial feature vector shows a high concentration of highly activated ultra-high switching ratio memristor points along the diagonal direction of the 32×32 integrated passive array. This spatial density of diagonal activations provides a quantitative measure of similarity, capable of distinguishing matched digits with extremely high specificity. In contrast, Figure 5 (b) shows the scattered activation pattern of the unmatched vectors, with only a few activation points distributed in the diagonal region of the 32×32 integrated passive array.

[0073] For different combinations of numbers, the diagonal activation distribution of the 32×32 integrated passive array is as follows: Figure 6 As shown, it is clear that the number of diagonal activations generated by matching numbers is significantly higher than that of non-matching combinations.

[0074] This invention encodes images as spatiotemporal pulse sequences that preserve topological features, which are relative spatial brightness relationships rather than absolute intensity values. By converting image pixel intensities into spatiotemporal pulse sequences to encode topological features, these features are mapped to a 32×32 integrated passive array. Image recognition is determined by calculating the number of activated ultra-high switching ratio (UHRR) memristors on the diagonal of the 32×32 integrated passive array, ensuring that only a single UHRR memristor is activated per row / column to eliminate crosstalk. A higher match between the sample vector and the initial feature vector results in a greater number of activated diagonal points in the 32×32 integrated passive array. The label with the highest number of diagonal activations is selected, achieving 99.8% accuracy on the MNIST dataset using the UHRR-based recognition method. Based on the OBPU scheme, the array scalability reaches 6.59 PB (with a 10% read margin).

[0075] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An on-chip image recognition method based on ultra-high switching ratio memristor driving, characterized in that, Includes the following steps: Step 1: Input image; Step 2: Preprocess the input image to obtain the relative intensity sorting matrix of the input image pixels; Step 3: Obtain the sample vector based on the relative strength ranking matrix; Step 4: Convert the relative intensity sorting matrix distribution into spatiotemporal pulse sequence coding topological features, and map these features onto a 32×32 integrated passive array to construct a sequence pulse topological mapping relationship that matches the arrangement of the spatiotemporal pulse sequence coding topological features. Specifically, by calculating the relative intensity sorting matrix distribution, the pulse sequence applied to the 32×32 integrated passive array is sorted according to time. Only one set of voltage pulses is applied to the 32×32 integrated passive array within each time step. When a voltage pulse is applied at different positions, its position in the entire pulse sequence corresponds to the sorting number of the image pixel intensity. The topological features are then mapped onto the 32×32 integrated passive array to construct a sequence pulse topological mapping relationship that matches the arrangement of the spatiotemporal pulse sequence coding topological features. The 32×32 integrated passive array integrates ultra-high switching ratio memristors. Step 5: Extract the initial feature vector for each sample vector based on the sample vector and the topological mapping of the sequence pulses; Step 6: Construct a topological neural network; Step 7: Train a topological neural network based on the initial feature vector and sample vector; Step 8: Input the sample vector into the trained topological neural network to obtain the output result.

2. The on-chip image recognition method based on ultra-high switching ratio memristor driving according to claim 1, characterized in that, Step 5 involves extracting the initial feature vector for each sample vector. Specifically, based on the sample vector and the topological mapping of the sequence pulses, the initial feature vector corresponding to each sample vector is extracted using a cold start algorithm.

3. The on-chip image recognition method based on ultra-high switching ratio memristor driving according to claim 1, characterized in that, The construction of the topological neural network in step 6 specifically involves: constructing a topological neural network based on the PCB peripheral control circuit and a 32×32 integrated passive array.

4. The on-chip image recognition method based on ultra-high switching ratio memristor driving according to claim 1, characterized in that, The specific steps in step 7 for training the topological neural network are as follows: using the ridge regression algorithm, the topological neural network is trained based on the count of the activated ultra-high switching ratio memristor points corresponding to the initial feature vector and sample vector at the diagonal positions of the 32×32 integrated passive array.

5. The on-chip image recognition method based on ultra-high switching ratio memristor driving according to claim 1, characterized in that, The specific steps for obtaining the output result in step 8 are as follows: input the sample vector into the trained topological neural network, compare the sample vector with the number of diagonal activations of the 32×32 ensemble passive array corresponding to each digit category, and select the digit category that best matches the sample vector as the output result.

6. The on-chip image recognition method based on ultra-high switching ratio memristor driving according to claim 1, characterized in that, In step 3, the relative strength ranking matrix is ​​linearly transformed to obtain a one-dimensional vector with a dimension of 1×625, which is the sample vector.

7. The on-chip image recognition method based on ultra-high switching ratio memristor driving according to claim 1, characterized in that, In step 2, the input image is converted into a grayscale image and then its size is standardized to 25×25 pixels to obtain the relative intensity sorting matrix of the input image pixels.

8. The on-chip image recognition method based on ultra-high switching ratio memristor driving according to claim 1, characterized in that, The ultra-high switching ratio memristor was fabricated using magnetron sputtering technology. structure.

9. The on-chip image recognition method based on ultra-high switching ratio memristor driving according to claim 1, characterized in that, The initial state of the ultra-high switching ratio memristor is a high resistance state.

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