Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a shift register unit, n gating signal lines and N pixel circuit rows, the output end of the driving module in the ith-level shift register unit is connected with one input end of the driving module in the (i + 1) th-level shift register unit; a gating module in the shift register unit is configured to at least receive a signal output by a driving module and a signal output control signal provided by a gating signal line; the n gating signal lines are alternately connected with the gating modules in the plurality of shift register units; the working mode of the display panel comprises that a pixel circuit row comprises at least two light-emitting stages in first time, the duration of the first time is equal to the duration of one frame time, the time interval between every two adjacent light-emitting stages is t * m, t is row time, and T is one frame time mgt; n. According to the invention, the light-emitting device can emit light relatively uniformly in one frame of time, and the problem of display flicker caused by concentrated light emission in one frame of time is avoided.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The operation of pixel circuits requires a light-emission control signal. The effective pulse width of the light-emission control signal affects the duration of the light-emission phase, and thus the light-emission duration of the sub-pixels. In one prior art technique, a gating module is provided within the shift register unit that provides the light-emission control signal. The gating modules in multiple cascaded shift register units are alternately connected to multiple gating signal lines. In practice, however, the effective pulse width of the light-emission control signal is limited, which in turn limits the light-emission duration of the sub-pixels. Simply increasing the number of times the gating signal triggers the gating module can easily cause display flicker. Summary of the Invention

[0003] Embodiments of the present invention provide a display panel and a display device to solve the technical problem of improving display flicker.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, the display panel comprising a plurality of shift register units, n gate signal lines, and N pixel circuit rows, where n and N are both positive integers;

[0005] The pixel circuit row includes a plurality of pixel circuits arranged in the same direction;

[0006] A plurality of shift register units are cascaded, the shift register units including a driving module and a gating module, a control terminal of the gating module being connected to an output terminal of the driving module; an output terminal of the driving module in the i-th stage shift register unit being connected to an input terminal of the driving module in the i+1-th stage shift register unit, where i is a positive integer; the gating module being configured to receive at least a signal output by the driving module and a signal provided by a gating signal line, and output a control signal; an output terminal of the gating module being connected to a plurality of pixel circuits in at least one pixel circuit row;

[0007] The n strobe signal lines include a first strobe signal line, a second strobe signal line, and an nth strobe signal line arranged in sequence, and the n strobe signal lines are alternately connected to strobe modules in the plurality of shift register units;

[0008] The display panel's operating modes include:

[0009] The pixel circuit row includes at least two light-emitting stages in the first time, wherein the duration of the first time is equal to the duration of a frame time, and the time interval between two adjacent light-emitting stages is t*m, where t is the row time, m is a coefficient, t=T / N, T is a frame time, m is a positive integer, and m>n.

[0010] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising the display panel provided by any embodiment of the present invention.

[0011] The display panel and display device provided by the embodiments of the present invention have the following beneficial effects: the embodiments of the present invention configure the pixel circuit row to include at least two light-emitting phases within a time period equal to one frame time, and the time interval between two adjacent light-emitting phases is t*m, where m is greater than the number of selection signal lines n, and the time interval between two adjacent light-emitting phases is greater than t*n. With such a configuration, it is possible to ensure that the duration of the light-emitting phase is sufficiently long when the number of selection signal lines is determined, and that the time interval between two adjacent light-emitting phases of the pixel circuit row within the first time period is a constant value. The light-emitting device driven by the pixel circuit row can then emit light at least twice within the first time period, and the time interval between the start moments of the two adjacent light-emitting phases is equal, so that the light-emitting device emits light relatively evenly within the first time period, avoiding the problem of display flicker caused by concentrated light emission within one frame time period. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0013] Figure 1 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0014] Figure 2 A schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0015] Figure 3 A signal timing diagram provided by an embodiment of the present invention;

[0016] Figure 4 Another signal timing diagram provided by an embodiment of the present invention;

[0017] Figure 5 It is a signal timing diagram in the related art;

[0018] Figure 6 A schematic diagram of a display panel operating mode provided by an embodiment of the present invention;

[0019] Figure 7 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0020] Figure 8 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0021] Figure 9 Another signal timing diagram provided by an embodiment of the present invention;

[0022] Figure 10 A schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0023] Figure 11 Another signal timing diagram provided by an embodiment of the present invention;

[0024] Figure 12 A schematic diagram of another display panel operating mode provided by an embodiment of the present invention;

[0025] Figure 13 A schematic diagram of another display panel operating mode provided by an embodiment of the present invention;

[0026] Figure 14 A schematic diagram of another display panel operating mode provided by an embodiment of the present invention;

[0027] Figure 15 A schematic diagram of another display panel operating mode provided by an embodiment of the present invention;

[0028] Figure 16 Other signal timing diagrams provided for embodiments of the present invention;

[0029] Figure 17 Other signal timing diagrams provided for embodiments of the present invention;

[0030] Figure 18 A schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0031] Figure 19 Another signal timing diagram provided by an embodiment of the present invention;

[0032] Figure 20 Another signal timing diagram provided by an embodiment of the present invention;

[0033] Figure 21 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0035] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "an", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0036] Figure 1 Schematic diagram of a display panel provided by an embodiment of the present invention. Figure 1 As shown, the display panel includes a plurality of shift register units 10, n gate signal lines 20 and N pixel circuit rows 30H, where n and N are both positive integers; the pixel circuit row 30H includes a plurality of pixel circuits 30 arranged in the same direction.

[0037] Multiple shift register units 10 are cascaded, each comprising a driver module 11 and a gating module 12. A control terminal of the gating module 12 is connected to an output terminal of the driver module 11. The output terminal of the driver module 11 in the i-th shift register unit 10 is connected to an input terminal of the driver module 11 in the i+1-th shift register unit 10, where i is a positive integer. The gating module 12 is configured to receive at least a signal output by the driver module 11 and a signal provided by a gating signal line 20, and output a control signal. The output terminal of the gating module 12 is connected to a plurality of pixel circuits 30 in at least one pixel circuit row 30H. That is, the output terminal of the gating module 12 provides the control signal to the pixel circuits 30. The embodiments of the present invention do not limit the specific structures of the driver module 11 and the gating module 12. The driver module 11 is a structure capable of implementing a signal shifting function, and the gating module 12 is a structure capable of implementing a signal gating function. The structures of the driver module 11 and the gating module 12 are further illustrated in the following relevant embodiments.

[0038] The n selection signal lines 20 include a first selection signal line 20-1, a second selection signal line 20-2, and an nth selection signal line 20-n arranged in sequence. The n selection signal lines 20 are alternately connected to the selection modules 12 in the cascaded plurality of shift register units 10. That is, the cascaded plurality of shift register units 10 are arranged in a cycle of n, and the n shift register units in one cycle are sequentially connected to the n selection signal lines 20. Figure 1 As shown in FIG. 6 , n=6 is used for illustration. It can be understood that the shift register unit 10 driving the first pixel circuit row 30H and the shift register unit 10 driving the seventh pixel circuit row 30H (i.e., the 1+nth pixel circuit row 30H) in the display panel are connected to the first selection signal line 20-1, the shift register unit 10 driving the second pixel circuit row 30H and the shift register unit 10 driving the eighth pixel circuit row 30H (i.e., the 2+nth pixel circuit row 30H) are connected to the first selection signal line 20-1, and so on.

[0039] Figure 2 A schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 3 A signal timing diagram provided by an embodiment of the present invention, Figure 2 The pixel circuit provided can be used Figure 3 Provided signal timing for driving.

[0040] like Figure 2 As shown, the pixel circuit 30 includes a first drive circuit 31 and a second drive circuit 32. The first drive circuit 31 is configured to control the amplitude of the drive current provided to the light-emitting device PD based on the first data voltage PAM-data, and the second drive circuit 32 is configured to control the duration of the drive current provided to the light-emitting device PD based on the second data voltage PWM-data and the sweep signal sweep. The first drive circuit 31 is a pulse amplitude modulation circuit, and the second drive circuit 32 is a pulse width modulation circuit. The light-emitting device PD is a light-emitting diode (LED), such as a Micro LED or a Mini LED.

[0041] The first driving circuit 31 includes a first driving transistor T1, a first gate reset transistor T2, a first data write transistor T3, a first compensation transistor T4, a first control transistor T5, a second control transistor T6, an electrode reset transistor T7, and a first capacitor C1. The first control transistor T5 is connected between a first power supply voltage PAM-vdd and the first electrode of the first driving transistor T1, and the second control transistor T6 is connected between the second electrode of the first driving transistor T1 and the light-emitting device PD. The first driving transistor T1 is configured to generate a driving current under the control of its gate voltage, and the gate of the first driving transistor T1 is connected to a first node N1. The first data write transistor T3 is connected to the first electrode of the first driving transistor T1, the first compensation transistor T4 is connected to the second electrode and the gate of the first driving transistor T1, the first gate reset transistor T2 is connected to the gate of the first driving transistor T1, the electrode reset transistor T7 is connected to the first electrode of the light-emitting device PD, and the second control transistor T6 is also connected to the first electrode of the light-emitting device PD. The second electrode of the light-emitting device PD is connected to the second power supply voltage VEE. The gate of the first gate reset transistor T2 is connected to the scan signal PAM-S1; the gates of the first data write transistor T3, the first compensation transistor T4, and the electrode reset transistor T7 are connected to the scan signal PAM-S2. The gates of the first control transistor T5 and the second control transistor T6 are connected to the light emission control signal PAM-EM. The first gate reset transistor T2 and the electrode reset transistor T7 each receive a reset signal PAM-REF. In other embodiments, the electrode reset transistor T7 may also receive a constant voltage signal having a different voltage value than the reset signal PAM-REF.

[0042] The second drive circuit 32 includes a second drive transistor T8, a second gate reset transistor T9, a second data write transistor T10, a second compensation transistor T11, a third control transistor T12, a fourth control transistor T13, and a second capacitor C2. The second capacitor C2 serves as a storage capacitor in the second drive circuit 32. The third control transistor T12 is connected between the third power supply voltage PWM-vdd and the first electrode of the second drive transistor T8, and the fourth control transistor T13 is connected between the second electrode of the second drive transistor T8 and the first node N1. The second data write transistor T10 is connected to the first electrode of the second drive transistor T8, the second compensation transistor T11 is connected to the second electrode and the gate of the second drive transistor T8, and the second gate reset transistor T9 is connected to the gate of the second drive transistor T8. The first plate of the second capacitor C2 is connected to the gate of the second drive transistor T8, and the second plate of the second capacitor C2 is connected to the sweep signal Sweep. The gate of the second gate reset transistor T9 is connected to the sweep signal PWM-S1, and the gates of the second data write transistor T10 and the second compensation transistor T11 are connected to the sweep signal PWM-S2. The gates of the third control transistor T12 and the fourth control transistor T13 are connected to the light emitting control signal PWM-EM. The second gate reset transistor T9 receives the reset signal PWM-REF.

[0043] Combine Figure 3Let's look at the operation of pixel circuit 30. During period t1, scan signal PAM-S1 provides an enable signal, and the first gate reset transistor T2 turns on to reset the first node N1. During period t2, scan signal PAM-S1 provides an enable signal, and the first data write transistor T3 and the first compensation transistor T4 turn on, writing the first data voltage PAM-data to the first node N1. During period t3, scan signal PWM-S1 provides an enable signal, and the second gate reset transistor T9 turns on to reset the gate of the second drive transistor T8. During period t4, scan signal PWM-S2 provides an enable signal, and the second data write transistor T10 and the second compensation transistor T11 turn on, writing the second data voltage PWM-data to the gate of the second drive transistor T8. During the t5 period, the light-emitting control signal PAM-EM provides an enable signal to control the first control transistor T5 and the second control transistor T6 to turn on, and the first driving transistor T1 generates a driving current under the control of its gate voltage; the light-emitting control signal PWM-EM provides an enable signal to control the third control transistor T12 and the fourth control transistor T13 to turn on. Due to the coupling effect of the second capacitor C2, the gate potential of the second driving transistor T8 changes with the voltage change of the sweep signal sweep. When the gate potential of the second driving transistor T8 reaches a certain level, the second driving transistor T8 is controlled to turn on. After the second driving transistor T8 is turned on, the potential of the first node N1 changes. When the potential of the first node N1 reaches a certain value, the first driving transistor T1 is controlled to turn off, and the driving current is stopped from being provided to the light-emitting device PD. The t5 period is the light-emitting stage of the pixel circuit 30. Figure 3 The figure shows that the falling edge of the light-emitting control signal PAM-EM is earlier than the falling edge of the light-emitting control signal PWM-EM. The falling edge of the light-emitting control signal PAM-EM can be regarded as the starting time of the light-emitting stage. The effective level pulse width of the light-emitting control signal PAM-EM affects the duration of the light-emitting stage, which also affects the actual adjustable light-emitting time of the light-emitting device PD.

[0044] In the embodiments of the present invention, it is necessary to distinguish between the light-emitting phase of the pixel circuit 30 and the actual light-emitting duration of the light-emitting device PD. The light-emitting device PD emits light during the light-emitting phase. The actual light-emitting duration of the light-emitting device PD during the light-emitting phase varies depending on the grayscale displayed by the light-emitting device PD. The start time of the light-emitting phase is the actual start time of light emission by the light-emitting device PD. The duration of the light-emitting phase determines the maximum time that the light-emitting device PD actually emits light.

[0045] In some embodiments of the present invention, the output end of the shift register unit 10 is electrically connected to the gate (i.e., the control end) of the first control transistor T5 and the gate (i.e., the control end) of the second control transistor T6 in the first driving circuit 31, that is, the shift register unit 10 provides the light emission control signal PAM-EM to the pixel circuit 30. In other embodiments, the output end of the shift register unit 10 is electrically connected to the second plate of the second capacitor C2 in the second driving circuit 32, that is, the shift register unit 10 provides the light emission control signal sweep signal to the pixel circuit 30.

[0046] Take the example where the output terminal of the shift register unit 10 is electrically connected to the gate of the first control transistor T5 and the gate of the second control transistor T6 in the first driving circuit 31 . Figure 4 Another signal timing diagram provided by an embodiment of the present invention. Figure 4 The figure shows the signal waveforms of the first selection signal line 20-1, the second selection signal line 20-2, to the sixth selection signal line 20-6 when n=6, and the waveforms of the light emitting control signals PAM-EM1, PAM-EM2 to PAM-EM12 sequentially output by the cascaded 12 shift register units 10. Figure 4 It can be seen that the light emitting control signals PAM-EM1 and PAM-EM12 are outputted by controlling the first selection signal line 20 - 1 . Figure 4 The t in the figure is the row time, which refers to the total time required to complete the scan of a pixel circuit row. The row time is related to the refresh rate of the panel. The shorter the row time, the higher the refresh rate. If the display panel includes N pixel circuit rows 30H, then N*t is the time required for the display panel to scan from top to bottom once, that is, the time required for the panel to refresh one frame, that is, one frame time. Figure 4 When the display panel is driven by the signal timing, the pixel circuits 30 in the pixel circuit row 30H include one light-emitting phase within one frame time. Figure 4 The signal provided by the selection signal line is shown in the figure with a period of 6t. The cascaded multiple shift register units 10 are alternately connected to the six selection signal lines in sequence. Then, the effective level pulse width (that is, the width of the effective pulse) of the light-emitting control signal PAM-EM output by the shift register unit 10 is limited by the signal period on the selection signal line 20.

[0047] To increase the light-emitting duration of the light-emitting devices PD, it is desirable to set multiple light-emitting phases for the pixel circuits 30 in the pixel circuit row 30H. However, simply increasing the number of times the start signal in the shift register is triggered, so that the light-emitting devices PD driven by each pixel circuit row 30H all emit light in one frame, can easily cause display flickering.

[0048] In addition, if the pixel circuits 30 in a pixel circuit row 30H include two or more light-emitting phases within one frame time, and the light-emitting phases are relatively concentrated, it is easy to cause load differences on the selection signal line 20, resulting in different signal delays and affecting display uniformity. Figure 5 This is a signal timing diagram in the related art. For example, a display panel includes six selection signal lines, and a shift register unit that outputs the light-emission control signal PAM-EM is connected to the selection signal line 20. Assume there are a total of 12 pixel circuit rows, corresponding to light-emission control signals PAM-EM1 to PAM-EM12, respectively. It can be understood that the shift register unit that generates the light-emission control signal PAM-EM1 and the shift register unit that generates the light-emission control signal PAM-EM7 are connected to the same selection signal line 20, the shift register unit that generates the light-emission control signal PAM-EM2 and the shift register unit that generates the light-emission control signal PAM-EM8 are connected to the same selection signal line 20, and so on. The low-level period of the light-emission control signal PAM-EM corresponds to the light-emission phase of the pixel circuit operation.

[0049] Depend on Figure 5 It can be seen that during the first time period T0, the light-emission control signal PAM-EM has two low-level periods, and these periods are relatively concentrated. For the select signal line 20 connected to the shift register unit generating the light-emission control signal PAM-EM6 and the shift register unit generating the light-emission control signal PAM-EM12, during period t″, the select signal line 20 controls the generation of the second low-level signal of the light-emission control signal PAM-EM6 and the first low-level period of the light-emission control signal PAM-EM12. In contrast, during period t′, the select signal line 20 controls only the generation of the second low-level period of the light-emission control signal PAM-EM12. In other words, the number of pixel circuit rows 30H driven by the select signal line 20 during period t″ and period t′ is different. Although a single select signal line 20 connects to multiple shift register units, it cannot control all of them to output active levels simultaneously. In other words, a single select signal line 20 generally cannot drive multiple pixel circuit rows 30H into the light-emission phase simultaneously. When the pixel circuit row 30H has two or more light-emitting phases within the first time period T0, the selection signal line 20 drives different numbers of pixel circuit rows 30H into the light-emitting phase at different time periods, resulting in different loads between the different selection signal lines 20. This results in different signal delays for each selection signal line 20, and also causes differences in the delays of the light-emitting control signals PAM-EM generated by them. The light-emitting control signals PAM-EM control the start time of the light-emitting phase (also the time when the light-emitting device PD starts to emit light). This will cause the light-emitting time of the light-emitting device PD to be affected by different delays, thereby affecting display uniformity.

[0050] Based on this, an embodiment of the present invention sets the working mode of the display panel, and sets the pixel circuit row to include at least two light-emitting stages within a time equal to the length of one frame time, and the time interval t*m between two adjacent light-emitting stages is a constant value, so that the light-emitting device can emit light relatively evenly, avoiding the problem of display flicker. Then, in a further embodiment, the relationship between m and the total number of pixel circuit rows N is set, so that when each selection signal line drives the pixel circuit row in the light-emitting stage, the number of pixel circuit rows driven by each selection signal line at the same time is equal, thereby improving the delay difference on the selection signal line and improving the display uniformity. The above is the main technical idea of ​​the present invention, and the technical concept of the present invention is explained in specific embodiments below.

[0051] Figure 6 A schematic diagram of a display panel operating mode provided by an embodiment of the present invention. Figure 6 The light emitting phase of the pixel circuit row 30H in the first time is shown. Figure 6 As shown, the working modes of the display panel in the embodiment of the present invention include:

[0052] The pixel circuit row 30H includes at least two light emitting phases t5 (eg, Figure 3 The first time period T0 is equal to the length of one frame time, and the time interval between two adjacent light-emitting stages t5 is t*m, where t is the row time, m is a coefficient, t=T / N, T is one frame time, m is a positive integer, and m>n. The time interval between two adjacent light-emitting stages t5 is calculated as the time interval between the start times of the two light-emitting stages t5. When the display panel is displaying, multiple pixel circuits 30 in a pixel circuit row 30H are driven simultaneously. Therefore, if the pixel circuit row 30H includes the light-emitting stage t5, it means that the pixel circuits 30 in the pixel circuit row 30H include the light-emitting stage t5.

[0053] In the embodiment of the present invention, the number n of the selection signal lines 20 affects the duration of the light-emitting phase t5. Figure 4To understand the timing diagram, the number n of strobe signal lines 20 affects the effective level width of the light-emitting control signal PAM-EM, thereby affecting the duration of the light-emitting phase t5. In this embodiment of the present invention, pixel circuit row 30H includes at least two light-emitting phases t5 within a time period equal to one frame time (first time period T0), and the time interval between two adjacent light-emitting phases t5 is t*m, where m is greater than the number n of strobe signal lines 20. Therefore, the time interval between two adjacent light-emitting phases t5 is greater than t*n. This configuration ensures that the duration of light-emitting phase t5 is sufficiently long, while the number n of strobe signal lines 20 is fixed. Furthermore, the time interval between two adjacent light-emitting phases t5 in pixel circuit row 30H within the first time period T0 is constant. The light-emitting devices PD driven by pixel circuit row 30H can emit light at least twice within the first time period T0, with the start times of the two adjacent light-emitting phases being equal in time. This ensures that the light-emitting devices PD emit light relatively evenly within the first time period T0, avoiding the problem of display flicker caused by concentrated light emission within a frame time.

[0054] In some embodiments, Figure 7 A schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 7 As shown, the shift register unit 10 includes a first shift register unit 10a, which includes a driving module 11 and a gating module 12. The gating signal line 20 includes a first gating signal line 21, which is connected to the first shift register unit 10a. Taking n=6 as an example, the display panel includes six first gating signal lines 21, namely first gating signal lines 21-1, 21-2, 21-3, 21-4, 21-5, and 21-6. The six first gating signal lines 21 are sequentially connected to the cascaded plurality of first shift register units 10a. Figure 6 The pixel circuit 30 is only simplified for illustration. The complete structure of the pixel circuit 30 can be found in the above description. Figure 2 The pixel circuit 30 includes a first driving circuit 31, which includes a first driving transistor T1, a first control transistor T5, and a second control transistor T6. The first driving transistor T1 is connected in series between the first control transistor T5 and the second control transistor T6. The output end of the gating module 12 in the first shift register unit 10a is connected to the control end of the first control transistor T5 and the control end of the second control transistor T6. In this embodiment, the first shift register unit 10a provides the light emission control signal PAM-EM to the first driving circuit 31 in the pixel circuit 30.

[0055] In other embodiments, Figure 8 A schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 8As shown, the shift register unit 10 includes a second shift register unit 10b, and the selection signal line 20 includes a second selection signal line 22. The second selection signal line 22 is connected to the second shift register unit 10b. Taking n=6 as an example, the display panel includes six second selection signal lines 22, namely second selection signal lines 22-1, 22-2, 22-3, 22-4, 22-5, and 22-6. The six second selection signal lines 22 are sequentially connected to the plurality of cascaded second shift register units 10b. Figure 8 The pixel circuit 30 is only simplified for illustration. The complete structure of the pixel circuit 30 can be found in the above description. Figure 2 The pixel circuit 30 includes a second driving circuit 32, which includes a second driving transistor T8 and a second capacitor C2. The output end of the gating module 12 in the second shift register unit 10b is connected to the second driving circuit 32. Specifically, the output end of the gating module 12 in the second shift register unit 10b is connected to the second capacitor C2, that is, the control signal output by the output end of the second shift register unit 10b is the sweep signal sweep.

[0056] Figure 9 Another signal timing diagram provided by an embodiment of the present invention. Figure 9 The signal timing provided by the embodiment can be Figure 2 The pixel circuit 30 provided in the embodiment is driven. Figure 9 The signal timing provided in this embodiment enables the pixel circuits 30 in the pixel circuit row 30H to include at least two light-emitting phases t5 during the first time T0, and the time interval between two adjacent light-emitting phases t5 is t*m. The time interval between two adjacent light-emitting phases t5 is calculated as the time interval between the start times of the two light-emitting phases t5, specifically, the time interval between the falling edges of the light-emitting control signals PAM-EM in two adjacent light-emitting phases t5.

[0057] Figure 9 The signal timing within the first time T0 is just the signal timing within one frame time for illustration. Figure 9As shown, during a single frame of image display, the pixel circuit 30 completes the writing of the first data voltage PAM-data and the second data voltage PWM-data over time periods t1, t2, t3, and t4, and then proceeds to the first light-emitting phase t5. After the first light-emitting phase t5, the first driving transistor T1 in the first driving circuit 31 is turned off. To achieve the next light-emitting phase t5, the first driving transistor T1 needs to be turned on. Therefore, the light-emitting phase t5 may include at least time period t2, or may also include both time periods t2 and t1. During time period t2, the first data voltage PAM-data is written to the gate of the first driving transistor T1. Because all light-emitting devices PD of the same color across the entire display panel use the same first data voltage PAM-data, multiple writes of the first data voltage PAM-data during the driving of a pixel circuit row 30H during a single frame of display do not adversely affect the driving of other pixel circuit rows 30H.

[0058] Figure 7 The first shift register unit 10a in the embodiment can provide the first driving circuit 31 in the pixel circuit 30 with the following information: Figure 9 The light-emission control signal PAM-EM in the timing diagram is Figure 8 The second shift register unit 10b in the embodiment can provide the second driving circuit 32 in the pixel circuit 30 with the following information: Figure 9 The first shift register unit 10a and the second shift register unit 10b cooperate to realize that the pixel circuit 30 in the pixel circuit row 30H includes at least two light-emitting phases t5 in the first time T0, and the time interval between two adjacent light-emitting phases t5 is t*m.

[0059] In other embodiments, Figure 10 FIG. 1 is another schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 10As shown, the pixel circuit 30 includes a first drive circuit 31 and a second drive circuit 32. The first drive circuit 31 includes a first drive transistor T1, a first gate reset transistor T2, a first data write transistor T3, a first compensation transistor T4, a first control transistor T5, a second control transistor T6, an electrode reset transistor T7, a first capacitor C1, and a light emission duration control transistor T14. The light emission duration control transistor T14 is connected in series between the first drive transistor T1 and the light-emitting device PD. The second drive circuit 32 includes a second drive transistor T8, a second gate reset transistor T9, a second data write transistor T10, a second compensation transistor T11, a third control transistor T12, a fourth control transistor T13, and a second capacitor C2. The fourth control transistor T13 in the second drive circuit 32 is electrically connected to the gate of the light emission duration control transistor T14. The pixel circuit 30 also includes a reset circuit 33, which is electrically connected to the gate of the light emission duration control transistor T14 and is used to reset the gate potential of the light emission duration control transistor T14. Optionally, the reset circuit 33 includes a reset transistor T15 and a third capacitor C3. The gate of the reset transistor T15 receives a reset control signal SET. The first electrode of the reset transistor T15 receives the reset signal Vset, and the second electrode is connected to the gate of the light-emission duration control transistor T14. The first plate of the third capacitor C3 receives the reset signal Vset, and the second plate is connected to the gate of the light-emission duration control transistor T14. The reset signal Vset is a constant voltage signal, such as a low-level constant voltage signal. The reset signal Vset can control the light-emission duration control transistor T14 to turn on.

[0060] In some embodiments, Figure 7 and Figure 8 In the embodiment, the pixel circuit 30 may also be Figure 10 Schematic structure.

[0061] Figure 11 Another signal timing diagram provided by an embodiment of the present invention is: Figure 10 The pixel circuit provided can be used Figure 11 The signal timing provided is driven. Figure 11 As shown, the operation of the pixel circuit 30 includes not only the t1 period, the t2 period, the t3 period, the t4 period, and the t5 period, but also the t6 period. The operation of the pixel circuit in the t1 period, the t2 period, the t3 period, and the t4 period can refer to the above Figure 3The description in the embodiment will not be repeated here. Among them, the period t6 is the reset stage. During the period t6, the reset control signal SET provides an enable level to control the reset transistor T15 to turn on and write the reset signal Vset to the gate of the light-emitting duration control transistor T14, so that the light-emitting duration control transistor T14 is turned on. During period t5, the light-emission control signal PAM-EM provides an enable signal to control the turning on of the first control transistor T5 and the second control transistor T6. The first drive transistor T1 generates a drive current under the control of its gate voltage. The light-emission duration control transistor T14 is turned on, and the drive current is supplied to the light-emitting device PD, causing it to emit light. The light-emission control signal PWM-EM provides an enable signal to control the turning on of the third control transistor T12 and the fourth control transistor T13. As the voltage of the sweep signal sweep changes, the gate potential of the second drive transistor T8 changes due to the coupling effect of the second capacitor C2. When the gate potential of the second drive transistor T8 reaches a certain level, the second drive transistor T8 is controlled to turn on. After the second drive transistor T8 turns on, the gate potential of the light-emission duration control transistor T14 changes. When the gate potential of the light-emission duration control transistor T14 reaches a certain value, the gate of the light-emission duration control transistor T14 is controlled to turn off, stopping the supply of drive current to the light-emitting device PD. Period t5 is the light-emission phase of the pixel circuit 30.

[0062] use Figure 11 The signal timing provided by the embodiment can enable the pixel circuits 30 in the pixel circuit row 30H to include at least two light-emitting phases t5 in the first time T0, and the time interval between two adjacent light-emitting phases t5 is t*m. Figure 10 For illustration, the signal timing within the first time period T0 is used to illustrate that it corresponds to the signal timing within a frame. During a single frame, the pixel circuit 30 completes the writing of the first data voltage PAM-data and the second data voltage PWM-data over time periods t1, t2, t3, and t4, then proceeds to time period t6 and the first light-emitting phase t5. After the first light-emitting phase t5, the light-emitting duration control transistor T14 is turned off. To achieve the next light-emitting phase t5, the light-emitting duration control transistor T14 must be turned on. Therefore, time period t6 is included between two adjacent light-emitting phases t5. During time t6, the gate potential of the light-emitting duration control transistor T14 is reset, turning the light-emitting duration control transistor T14 on. This allows the pixel circuits 30 in pixel circuit row 30H to perform two or more light-emitting phases t5 after writing the first data voltage PAM-data and the second data voltage PWM-data once.

[0063] In some embodiments of the present invention, N is an integer multiple of m. That is, the number N of pixel circuit rows 30H in the display panel is an integer multiple of m. During a first time period T0, the number of light-emitting stages t5 included in a pixel circuit row 30H is T / (t*m). Since t=T / N, T / (t*m)=N / m, and T / (t*m) is an integer. That is, during a first time period T0, the number of light-emitting stages t5 included in a pixel circuit row 30H is an integer, and the number of light-emitting stages t5 included in each pixel circuit row 30H during the corresponding first time period T0 is equal. The pixel circuit row 30H includes w light-emitting stages during the first time period, where w=N / m and w is an integer.

[0064] Figure 12 A schematic diagram of another display panel operating mode provided by an embodiment of the present invention. Figure 12 Taking n=6, w=N / m=4 as an example, that is, there are 6 selection signal lines 20 arranged in the display panel, each pixel circuit row 30H has 4 light-emitting stages t5 in the first time T0, and the time interval between two adjacent light-emitting stages t5 is t*m. Figure 12 The gray filling in the middle indicates the lighting stage t5. Figure 12 The light emitting phase t5 corresponding to the pixel circuit rows 30H1 to 30H24 arranged in succession is shown. Figure 7 The first shift register unit 10a is shown in FIG. The first shift register unit 10a provides a light-emission control signal PAM-EM to the pixel circuit row 30H. The first shift register units 10a connected to the pixel circuit rows 30H1, 30H7, 30H13, and 30H19, respectively, are connected to the same first selection signal line 21. It can be seen that the light-emission phases t5 of the pixel circuit rows 30H1, 30H7, 30H13, and 30H19 occur simultaneously, meaning that the pixel circuit row 30H is driven in a six-row cycle.

[0065] Figure 12 Two consecutive first times T0 are shown, and the starting moment of the first time T0 is the starting light-emitting moment of a light-emitting phase t5 of the pixel circuit row 30H1. Figure 12 It can be seen that in the first time T0, the pixel circuit row 30H includes 4 light-emitting stages, and the time intervals between two adjacent light-emitting stages are equal and are both t*m. The duration of the first time T0 is equal to the duration of a frame time, so it can be understood that Figure 12 The marked first time T0 is not the period for actually displaying a frame of image. Any pixel circuit row 30H in the display panel includes four light-emitting stages in its corresponding first time T0, and the time intervals between two adjacent light-emitting stages are equal.

[0066] Figure 12 The diagram shows 24 pixel circuit rows 30H. One selection signal line 20 drives four of the 24 pixel circuit rows 30H via a shift register unit, and the six selection signal lines 20 alternately drive the 24 pixel circuit rows arranged in sequence. The △1 period corresponds to a light-emitting phase of the pixel circuit row 30H1. It can be seen that during the △1 period, the selection signal line 20 driving the pixel circuit row 30H1 simultaneously drives four pixel circuit rows into the light-emitting phase. The △2 period corresponds to a light-emitting phase of the pixel circuit row 30H3. It can be seen that during the △3 period, the selection signal line 20 driving the pixel circuit row 30H3 simultaneously drives four pixel circuit rows into the light-emitting phase. In this way, when each selection signal line 20 drives the pixel circuit row 30H into the light-emitting phase, the number of pixel circuit rows 30H that are simultaneously driven by each selection signal line 20 is equal.

[0067] In an embodiment of the present invention, a pixel circuit row 30H is configured to include at least two light-emitting phases t5 during a first time period T0, with the time interval between two adjacent light-emitting phases t5 being t*m, where m>n, and N being an integer multiple of m. The time interval between two adjacent light-emitting phases t5 during a first time period T0 of a pixel circuit row 30H is constant, so that the light-emitting devices PD driven by the pixel circuit row 30H can emit light relatively evenly at least twice during the first time period T0, thereby avoiding the problem of display flicker caused by concentrated light emission within a frame time. Furthermore, the number of pixel circuit rows 30H in the light-emitting phase driven by each selection signal line 20 is equal, thereby reducing the load differences between the selection signal lines 20 at different time periods, reducing the delay differences in the output signals of the shift register unit, and improving display uniformity.

[0068] In other embodiments, the number of pixel circuit rows 30H actually included in the display panel is not an integer multiple of m. However, N+r is an integer multiple of m, and r is an integer. The pixel circuit row 30H includes w light-emitting stages t5 in the first time, where w=(N+r) / m. When the pixel circuit row 30H is set to include at least two light-emitting stages t5 in the first time T0, the time interval between two adjacent light-emitting stages t5 is t*m, and m>n, and N+r is an integer multiple of m, it is also possible to achieve that the light-emitting device PD driven by the pixel circuit row 30H can emit light relatively uniformly at least twice in the first time T0, and each pixel circuit row 30H includes an equal number of light-emitting stages in the first time T0, thereby avoiding the problem of display flickering caused by concentrated light emission within a frame time.

[0069] Optionally, 1 ≤ r < m. Since N + r is an integer multiple of m and 1 ≤ r < m, when N is an integer multiple of n, the number of pixel circuit rows 30H that are simultaneously in the light-emitting stage t5 driven by different gate signal lines 20 is equal. When N is not divisible by n, the gate signal lines 20 are divided into two categories. The number of pixel circuit rows 30H in the light-emitting stage driven by these two categories of gate signal lines 20 may differ by 1. However, overall, compared with before the improvement, the load difference of each gate signal line 20 at different time periods can be reduced, the delay difference of the output signals of the shift register unit can be reduced, and the display uniformity can be improved.

[0070] In some embodiments, the output end of the gate module 12 in the shift register unit 10 is connected to k pixel circuit rows 30H, where k is an integer and k ≥ 1; the duration of the light-emitting stage t5 is Z, and Z ≤ k * t * n. For example, when k = 1, Z ≤ t * n; when k = 2, Z ≤ 2 * t * n. When k = 1, one shift register unit 10 drives one pixel circuit row 30H; when k = 2, one shift register unit 10 drives two pixel circuit rows 30H. The larger the number of pixel circuit rows 30H connected to the output end of the shift register unit 10 and the longer the duration of a single light-emitting stage of the pixel circuit, the more gate signal lines 20 are provided in the display panel and the longer the duration of a single light-emitting stage of the pixel circuit. In the embodiments of the present invention, the duration of a single light-emitting stage of the pixel circuit is related to k and n, so that the duration of a single light-emitting stage is long enough to meet the requirement of the light-emitting duration for the gray-scale display of the light-emitting device PD.

[0071] In some embodiments, the duration of each light-emitting stage t5 in the pixel circuit row 30H is equal in the first time T0. Thus, the light-emitting control signal for driving the pixel circuit row 30H to work can be set regularly. By setting the effective level width of the light-emitting control signal to a fixed value, the duration of each light-emitting stage t5 is equal, and the generation method of the control signal is relatively simple. Figure 3 Understood in combination with the schematic timing diagram, the falling edge of the light-emitting control signal PWM-EM is earlier than the falling edge of the light-emitting control signal PAM-EM, and the rising edge of the light-emitting control signal PWM-EM is later than the rising edge of the light-emitting control signal PAM-EM. That is, the low level of the light-emitting control signal PWM-EM covers the low level of the light-emitting control signal PAM-EM. Then, the light-emitting control signal PAM-EM required by the pixel circuit 30 affects the duration of the light-emitting stage t5. In applications, at least the low-level pulse widths of the light-emitting control signal PAM-EM are set to be equal, so that the duration of each light-emitting stage t5 in the pixel circuit row 30H is equal.

[0072] In some embodiments, the output of the strobe module 12 in the shift register unit 10 is connected to k pixel circuit rows 30H, where k is an integer, k ≥ 1, and m is an integer multiple of k*n. This configuration can reduce the load differences between the strobe signal lines 20 at different time periods, reduce the delay differences in the output signals of the shift register unit, and improve display uniformity.

[0073] Figure 1 Taking k=1 as an example, that is, one shift register unit 10 drives one pixel circuit row 30H, then m is an integer multiple of n. Since m>n, m is at least twice n, and the duration of the light-emitting phase is Z≤t*n. When k=2, m is an integer multiple of 2*n, and the duration of the light-emitting phase is Z≤k*t*n=2*t*n. At this time, it is also necessary to satisfy that the time interval between two adjacent light-emitting phases is greater than the duration of a single light-emitting phase, that is, it is necessary to simultaneously satisfy t*m>Z, then t*m>2*t*n, and m is at least twice 2*n.

[0074] Taking k=1 as an example, m is at least twice of n. n is the number of strobe signal lines 20 arranged in the display panel, and n strobe signal lines 20 are alternately connected to the cascaded multiple shift register units 10, that is, the cascaded multiple shift register units 10 are connected to the corresponding strobe signal lines 20 with n as a period. Figure 4 In this embodiment, the periodic signal on the selection signal line 20 controls the shift register unit 10 to output the light-emitting control signal PAM-EM, thereby controlling the pixel circuit row 30H to operate in the light-emitting phase t5. When the time interval between two adjacent light-emitting phases t5 of the pixel circuit row 30H in the first time period T0 is t*m, and m is an integer multiple of n, it is possible to achieve that a single selection signal line 20 drives multiple pixel circuit rows 30H to operate in the light-emitting phase simultaneously. The specific number of pixel circuit rows 30H driven by a single selection signal line 20 to operate in the light-emitting phase simultaneously is related to the specific value of m.

[0075] When N / n is an integer, one strobe signal line 20 connects to N / n shift register units 10, and one strobe signal line 20 drives a maximum of N / n pixel circuit rows 30H. It can be understood that one strobe signal line 20 drives multiple pixel circuit rows 30H to operate simultaneously in the light-emitting phase, and the number of pixel circuit rows 30H operating simultaneously in the light-emitting phase is less than N / n. Furthermore, since m is an integer multiple of k*n, the larger the value of m, the smaller the number of pixel circuit rows 30H operating simultaneously in the light-emitting phase driven by one strobe signal line 20.

[0076] Take k=1, and one shift register unit 10 is connected to one pixel circuit row 30H as an example. Figure 13 A schematic diagram of another display panel operating mode provided by an embodiment of the present invention. Figure 13Schematically shows a schematic diagram of the light-emitting stage t5 of pixel circuit rows 30H1 to 30H19 arranged in sequence within a certain period of time. In the figure, the time position of the light-emitting stage t5 is schematically shown by gray filling. Figure 13 Still taking n = 6 as an example, the shift register units 10 respectively connected to the pixel circuit rows 30H1, 30H7, 30H13, and 30H19 are connected to the same strobe signal line 20. Figure 13 The light-emitting stage t5 driven by the same strobe signal line 20 is schematically shown by a darker filling. Figure 13 It can be seen that the light-emitting stage t5 of the pixel circuit row 30H1 and the light-emitting stage t5 of the pixel circuit row 30H13 are driven simultaneously, and the light-emitting stage t5 of the pixel circuit row 30H7 and the light-emitting stage t5 of the pixel circuit row 30H19 are driven simultaneously. That is, the number of pixel circuit rows 30H that are simultaneously working in the light-emitting stage t5 driven by the strobe signal line 20 is less than the number of pixel circuit rows 30H electrically connected to the strobe signal line 20 through the shift register unit 10. And the larger m is, the smaller the number of pixel circuit rows 30H that are simultaneously driven by one strobe signal line 20 in the light-emitting stage.

[0077] In addition, when N / n is an integer and m is an integer multiple of k*n, the relationship between N and m can be that N is an integer multiple of m, or N + r is an integer multiple of m.

[0078] When N is an integer multiple of m, at the starting moment of the light-emitting stage t of the pixel circuit row 30H, the number of pixel circuit rows 30H in the light-emitting stage t5 driven by n strobe signal lines 20 through the strobe module 12 is equal. The embodiment of the present invention can reduce the load difference of each strobe signal line 20 at different time periods, reduce the delay difference of the output signals of the shift register unit, and improve the display uniformity. Among them, the duration of the first time T0 is equal to the duration of one frame time T. Within the first time T0, N pixel circuit rows 30H are driven row by row. Then, the number of light-emitting stages t5 included in the pixel circuit row 30H in the first time T0 is equal to the number of pixel circuit rows 30H that are simultaneously driven by one strobe signal line 20 in the light-emitting stage t5 in one frame time T. Therefore, when N is an integer multiple of m, the number of pixel circuit rows 30H that are simultaneously in the light-emitting stage t5 driven by n strobe signal lines 20 through the strobe module is N / m.

[0079] When N + r is an integer multiple of m, the number of pixel circuit rows 30H that are simultaneously in the light-emitting stage t5 driven by different strobe signal lines 20 through the strobe module 12 differs by at most 1. Optionally, 1 ≤ r < m. The embodiment of the present invention can reduce the load difference of each strobe signal line 20 at different time periods, reduce the delay difference of the output signals of the shift register unit, and improve the display uniformity.

[0080] When N is an integer multiple of m, the number of the light-emitting phases t5 included in the pixel circuit row 30H in the first time T0 is equal to the number of the pixel circuit rows 30H in the light-emitting phase t5 driven simultaneously by one gate signal line 20 in one frame time T. Then when N + r is an integer multiple of m, it is equivalent to arranging r virtual pixel circuit rows in the display panel, so that the total number of pixel circuit rows can be divided evenly by m. Then the number of the light-emitting phases t5 included in the pixel circuit row 30H in the first time T0 is (N + r) / m. Since r virtual pixel circuit rows are provided, when N is an integer multiple of n, the number of the pixel circuit rows 30H in the light-emitting phase t5 driven simultaneously by different gate signal lines 20 through the gating module 12 is equal. When N cannot be divided evenly by n, at least one of the n gate signal lines 20 is preset to drive a virtual pixel circuit row, that is, the number of pixel circuit rows actually driven by at least one of the n gate signal lines 20 is less. When 1 ≤ r < m, among the n gate signal lines 20, the number of the pixel circuit rows 30H in the light-emitting phase t5 driven simultaneously by some gate signal lines 20 through the gating module 12 is (N + r) / m, and the number of the pixel circuit rows 30H in the light-emitting phase t5 driven simultaneously by the remaining gate signal lines 20 through the gating module 12 is N / m, and (N + r) / m = N / m + 1.

[0081] In some embodiments, Figure 14 is another schematic diagram of the working mode of the display panel provided by the embodiment of the present invention. As Figure 14 shown, the working mode of the display panel includes a first mode mode1 and a second mode mode2, and the brightness of the display panel in the first mode mode1 is less than its brightness in the second mode mode2. For example, the first mode mode1 can be a display mode applied in an indoor scene, and the second mode mode2 can be a display mode applied in an outdoor scene.

[0082] Among them, the coefficient m includes a first coefficient m1 and a second coefficient m2.

[0083] In the first mode mode1, the pixel circuit row 30H includes at least two light-emitting phases t5 in the first time T0, and the time interval between two adjacent light-emitting phases t5 is t*m1.

[0084] In the second mode mode2, the pixel circuit row 30H includes at least two light-emitting phases t5 in the first time T0, and the time interval between two adjacent light-emitting phases t5 is t*m2; where m1 > m2.

[0085] In combination with the above description of the relevant embodiments, the pixel circuit row 30H includes w light-emitting stages t5 in the first time T0, w = N / m; or w = (N+r) / m. That is, the larger the coefficient m is, the smaller w is. So it can be understood that in Figure 14 In the two illustrated modes, the number of light-emitting phases t5 included in the pixel circuit row 30H during the first time T0 is different, and the duration of a single light-emitting phase t5 is Z = k*t*n. In the first mode mode1, the number of light-emitting phases t5 included in the pixel circuit row 30H during the first time T0 is smaller than the number of light-emitting phases t5 included in the pixel circuit row 30H during the first time T0 in the second mode mode2.

[0086] The embodiment of the present invention differentially sets the coefficient m for the display panel operating in different brightness modes, thereby meeting the brightness requirements of the display panel in different application scenarios. In a relatively high brightness mode, the coefficient m is relatively small, so the pixel circuit row 30H includes a greater number of light-emitting stages t5 during the first time T0. This also results in a longer total duration of the light-emitting stages of the pixel circuit row 30H during the first time T0. This allows the light-emitting device PD to actually emit light for a longer duration and at a higher brightness, thus meeting the brightness requirements of the high brightness mode.

[0087] In some embodiments, Figure 15 A schematic diagram of another display panel operating mode provided by an embodiment of the present invention. Figure 15 Taking k=1 and one shift register unit 10 connected to one pixel circuit row 30H as an example, a schematic diagram of the light-emitting phase t5 of pixel circuit rows 30H1 to 30H19 arranged sequentially when displaying two consecutive frames is shown. Gray fill in the figure indicates the time position of the light-emitting phase t5. Figure 15 Still taking n=6 as an example, the shift register units 10 connected to the pixel circuit rows 30H1, 30H7, 30H13, and 30H19 are connected to the same selection signal line 20. The darker color fill indicates the light-emitting phase t5 of the pixel circuit rows 30H1, 30H7, 30H13, and 30H19. Figure 15As shown, the working mode of the display panel includes: in the display of one frame, N pixel circuit rows 30H are sequentially driven; in the display of two consecutive frames, the time interval between the starting moments of driving the first pixel circuit row 30H1 twice is T. T is the display time of one frame, i.e., one frame time. It can be understood that the time interval between the starting moments of driving the second pixel circuit row 30H2 twice in the display of two consecutive frames is also T. The display panel provided in the embodiment of the present invention has no front and back corridors when continuously displaying multiple frames. Combined with the design of the time interval of two adjacent light-emitting stages t5 of the pixel circuit row 30H in the first time T0 as t*m in the embodiment of the present invention, the light-emitting stages t5 of the pixel circuit 30 in the pixel circuit row 30H during display can be evenly distributed in time, and the light-emitting device PD can also emit light relatively evenly in time, avoiding the problem of display flickering caused by concentrated light emission.

[0088] Combine Figure 1 In this embodiment of the present invention, the gating module 12 outputs a control signal to the pixel circuit row 30H connected to the shift register unit 10 based on at least the received signal output by the driving module 11 and the signal provided by the gating signal line 20. The operating mode of the display panel includes: the control signal includes at least two cycles in the first time period T0, and the period of the control signal is t*m. This configuration enables the pixel circuit 30 to be driven by the control signal, ensuring that the time interval between two adjacent light-emitting phases t5 of the pixel circuit row 30H is t*m.

[0089] The shift register unit 10 includes Figure 7 The first shift register unit 10a shown in FIG. 1 includes a gate signal line 20. Figure 7 The first selection signal line 21 is shown as an example. Figure 16 Other signal timing diagrams provided for embodiments of the present invention. Figure 16 Schematic diagram of the signal timing of the light emitting control signal PAM-EM required for the pixel circuit 30 to work. Figure 16 As shown, the light emitting control signal PAM-EM includes 4 cycles in the first time T0, one low level and one high level of the light emitting control signal PAM-EM constitute a signal cycle, and the cycle of the light emitting control signal PAM-EM is t*m. Figure 16 The length of one cycle is defined as the width between two adjacent falling edges of the light emitting control signal PAM-EM. The light emitting control signal PAM-EM is a control signal required for the operation of the pixel circuit 30. Figure 9 Schematic timing diagram and Figure 2In the schematic structure of pixel circuit 30, the light-emission control signal PAM-EM provides a low level, turning on the first control transistor T5 and the second control transistor T6 in the first driver circuit 31. This enables the first driver transistor T1 to provide a drive current to the light-emitting device PD. The low level of the light-emission control signal PAM-EM controls whether the path between the first driver transistor T1 and the light-emitting device PD is conductive. The duration of the low level of the light-emission control signal PAM-EM affects the duration of the light-emission phase t5. This embodiment of the present invention sets the period of the light-emission control signal PAM-EM to drive the pixel circuit 30, ensuring that the time interval between two adjacent light-emission phases t5 in pixel circuit row 30H is t*m.

[0090] The shift register unit 10 includes Figure 8 The second shift register unit 10b shown in FIG. 1 includes a gate signal line 20. Figure 8 The second selection signal line 22 is shown as an example. Figure 17 Other signal timing diagrams provided for embodiments of the present invention. Figure 17 Schematic diagram of the signal timing of the sweep signal required for the pixel circuit 30 to work. Figure 17 As shown, the sweep signal sweep includes 4 cycles in the first time T0, a constant voltage signal and a ramp signal of the sweep signal sweep constitute a signal cycle, and the cycle of the sweep signal sweep is t*m. Figure 17 The width between the start times of two adjacent ramp signals of the sweep signal is defined as the length of one cycle. The sweep signal is a control signal required for the operation of the pixel circuit 30. Figure 9 Schematic timing diagram and Figure 2 From the schematic structure of the pixel circuit 30, during light-emitting phase t5, the third control transistor T12 and the fourth control transistor T13 in the second drive circuit 32 are turned on under the control of the light-emitting control signal PWM-EM. The ramp signal of the sweep signal causes the gate potential of the second drive transistor T8 to change. When the gate potential of the second drive transistor T8 reaches a certain level, the second drive transistor T8 is controlled to turn on. After the second drive transistor T8 turns on, the potential of the first node N1 changes. When the potential of the first node N1 reaches a certain value, the first drive transistor T1 is controlled to turn off, stopping the supply of drive current to the light-emitting device PD. The sweep signal sweep cooperates with the pixel circuit to complete each light-emitting phase t5. The embodiment of the present invention sets the period of the sweep signal sweep to drive the pixel circuit 30 to operate, ensuring that the time interval between two adjacent light-emitting phases t5 of the pixel circuit row 30H is t*m.

[0091] In some embodiments, Figure 18Schematic diagram of a shift register unit provided by an embodiment of the present invention. Figure 18 As shown, the shift register unit 10 includes a driving module 11 and a gating module 12. The driving module 11 includes a first transistor M1, a second transistor M2, and a twelfth transistor M12. The driving module 11 also includes a first capacitor C1, a second capacitor C2, and a third capacitor C3. The gating module 12 includes a thirteenth transistor M13 and a fourteenth transistor M14. The operation of the shift register unit 10 utilizes a high-level signal VGH, a low-level signal VGL, an input signal IN, a first clock signal CK, a second clock signal CKB, and a gating signal CLK provided by a gating signal line 20. The gating module 12 is configured to receive at least a signal Carry output by the driving module 11 and a signal CLK provided by the gating signal line 20, and output a control signal CT.

[0092] Figure 18 The structures of the driving module 11 and the strobe module 12 are only schematically shown and are only used to illustrate the working principle of the shift register unit 10. In the embodiment of the present invention, the first shift register unit 10a and the second shift register unit 10b can adopt the same structure, such as Figure 18 The structure in the embodiment.

[0093] Figure 19 Another signal timing diagram provided by an embodiment of the present invention is: Figure 18 The shift register unit 10 provided in the embodiment can be used Figure 19 Provided signal timing for driving. Figure 18 Take n=6 as an example, that is, there are 6 gate signal lines 20 arranged in the display panel. Figure 18 It can be seen that when the pulse period of the trigger signal STV received by the driving module 11 in the first-stage shift register unit 10 is set to t*m in the working mode of the display panel, the pulse period of the control signal CT output by the shift register unit 10 is t*m. Figure 18 The control signal CT can be used as the light control signal PAM-EM, using Figure 18 The signal timing provided in the embodiment can drive the pixel circuit 30 to operate so that the time interval between two adjacent light emitting phases t5 of the pixel circuit row 30H is t*m.

[0094] In addition, the strobe signal line 20 provides a strobe signal, and the period of the strobe signal is n*t. Figure 19 Assume that n=6, and show the selection signals outputted by the selection signal lines 20-1 to 20-6 respectively. Figure 19It can be seen that the period of the strobe signal is 6*t, that is, the period of the strobe signal is n*t, and the start time of the strobe signal period provided by two adjacent strobe signal lines 20 arranged in sequence differs by t. This arrangement can use n strobe signal lines 20 to control the multiple strobe modules 12 in the multiple shift register units 10 to sequentially output the control signal CT, thereby realizing row-by-row driving of the multiple pixel circuit rows 30H.

[0095] Combine Figure 7 According to the embodiment, the shift register unit 10 includes a first shift register unit 10 a , and the selection signal line 20 includes a first selection signal line 21 . The first selection signal line 21 is connected to the first shift register unit 10 a . Figure 19 The signal timing provided by the embodiment can be Figure 7 The first shift register unit 10a provided in the embodiment is driven. Figure 19 Schematic diagram of the first selection signal provided by the six first selection signal lines 21, the six first selection signal lines 21 are the first selection signal line 21-1 to the first selection signal line 21-6. Figure 19 It can be seen that the period of the first selection signal provided by the first selection signal line 21 is n*t. The first selection signal includes a first level signal V1 and a second level signal V2, and the first level signal V1 is an enable signal. One of the first level signal V1 and the second level signal V2 is a high level signal and the other is a low level signal. In the embodiment of the present invention, the first level signal V1 is a low level signal and the second level signal V2 is a high level signal as an example. In one period of the first selection signal, the duration of the first level signal V1 is greater than the duration of the second level signal V2. In the embodiment of the present invention, the period of the first selection signal is set to n*t, which can realize the use of n first selection signal lines 21 to control the multiple selection modules 12 in the multiple first shift register units 10a to output control signals in sequence, so as to realize row-by-row driving of the multiple pixel circuit rows 30H. In addition, the duration of the enable signal in the cycle of the first selection signal is set to be longer, which can ensure that the duration of the enable signal of the light-emitting control signal PAM-EM output by the first shift register unit 10a is longer, thereby ensuring that the duration of a single light-emitting phase is longer when the pixel circuit 30 is driven to work.

[0096] In some embodiments, Figure 20 Another signal timing diagram provided by an embodiment of the present invention is: Figure 18 The shift register unit 10 provided in the embodiment may also adopt Figure 20 Provided signal timing for driving. Figure 18 The shift register unit 10 provided in the embodiment can be used as Figure 8 The second shift register unit 10b in the embodiment. Figure 8 、 Figure 18To understand. Figure 20 Taking n=6 as an example, the display panel is provided with six second selection signal lines 22 connected to the second shift register unit 10b. The six second selection signal lines 22 are respectively a second selection signal line 22-1 to a second selection signal line 22-6. The signals provided by the second selection signal lines 22 include periodic ramp signals.

[0097] Depend on Figure 20 It can be seen that when the pulse period of the trigger signal STV received by the driving module 11 in the first-stage second shift register unit 10b is set to t*m in the working mode of the display panel, the pulse period of the control signal CT output by the second shift register unit 10b is t*m. The control signal CT can be used as a sweep signal sweep to drive the pixel circuit 30 to work. Figure 20 The signal timing provided in the embodiment can drive the pixel circuit 30 to operate so that the time interval between two adjacent light emitting phases t5 of the pixel circuit row 30H is t*m.

[0098] in addition, Figure 20 Take n=6 for illustration. Figure 20 It can be seen that the second selection signal lines 22-1 to 22-6 respectively output the selection signals, and the period of the selection signals provided by the second selection signal lines 22 is n*t, and the starting time of the periods of the selection signals provided by two adjacent second selection signal lines 22 arranged in sequence differs by t. This configuration can realize the use of n second selection signal lines 22 to control the multiple selection modules 12 in the multiple second shift register units 10b to sequentially output the sweep signal sweep, thereby realizing row-by-row driving of the multiple pixel circuit rows 30H.

[0099] like Figure 20 As shown, the second selection signal line 22 provides a second selection signal, and the period of the second selection signal is n*t. The second selection signal includes a constant voltage signal V3 and a ramp signal V4. During one period of the second selection signal, the duration of the ramp signal V4 is greater than the duration of the constant voltage signal V3. In the embodiment of the present invention, the period of the second selection signal is set to n*t, which can realize the use of n second selection signal lines 22 to control the multiple selection modules 12 in the multiple second shift register units 10b to sequentially output control signals, thereby realizing row-by-row driving of multiple pixel circuit rows 30H. In addition, the duration of the ramp signal V4 during the period of the second selection signal is set to be longer, which can ensure that the duration of the ramp signal in the sweep signal output by the second shift register unit 10b is longer. Therefore, the sweep signal sweep can adjust the actual light-emitting duration of the light-emitting device PD in accordance with the duration of the light-emitting stage.

[0100] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Figure 21 Schematic diagram of a display device provided by an embodiment of the present invention. Figure 21 As shown, the display device includes a display panel 100 provided by any embodiment of the present invention. The structure of the display panel 100 has been described in the above embodiments and will not be repeated here. The display device provided by the embodiment of the present invention can be, for example, a mobile phone, tablet, computer, television, smart wearable product, or other electronic device with a display function.

[0101] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of shift register units, n gate signal lines and N pixel circuit rows, where n and N are both positive integers; The pixel circuit row includes a plurality of pixel circuits arranged in the same direction; A plurality of shift register units are cascaded, the shift register units comprising a driving module and a gating module, a control terminal of the gating module being connected to an output terminal of the driving module; an output terminal of the driving module in the i-th stage of the shift register unit being connected to an input terminal of the driving module in the i+1-th stage of the shift register unit, where i is a positive integer; the gating module being configured to receive at least a signal output by the driving module and a signal provided by the gating signal line, and output a control signal; an output terminal of the gating module being connected to a plurality of pixel circuits in at least one pixel circuit row; The n strobe signal lines include the first strobe signal line, the second strobe signal line, to the nth strobe signal line arranged in sequence, and the n strobe signal lines are alternately connected to the strobe modules in the plurality of shift register units; The operating modes of the display panel include: The pixel circuit row includes at least two light-emitting stages in the first time, wherein the duration of the first time is equal to the duration of a frame time, and the time interval between two adjacent light-emitting stages is t*m, t is the row time, m is a coefficient, t=T / N, T is a frame time, m is a positive integer, and m>n.

2. The display panel according to claim 1, wherein: N is an integer multiple of m; Alternatively, N+r is an integer multiple of m, and r is an integer.

3. The display panel according to claim 1, wherein: The output end of the gating module is connected to k pixel circuit rows, where k is an integer and k≥1; m is an integer multiple of k*n.

4. The display panel according to claim 1, wherein: The pixel circuit row includes w light emitting phases in the first time, wherein: w = N / m; or, w = (N + r) / m, where r is an integer.

5. The display panel according to claim 1, wherein: The output end of the gating module is connected to k pixel circuit rows, where k is an integer and k≥1; The duration of the light emitting phase is Z, where Z≤k*t*n.

6. The display panel according to claim 1, wherein: The durations of the light emitting phases of the pixel circuit row in the first time are equal.

7. The display panel according to claim 1, wherein: The operating mode of the display panel includes a first mode and a second mode, and the brightness of the display panel in the first mode is lower than the brightness in the second mode; The coefficients include a first coefficient m1 and a second coefficient m2; In the first mode, the pixel circuit row includes at least two light-emitting phases in the first time, and the time interval between two adjacent light-emitting phases is t*m1. In the second mode, the pixel circuit row includes at least two light emitting phases in the first time, and the time interval between two adjacent light emitting phases is t*m2; wherein m1>m2.

8. The display panel according to claim 1, wherein: The operating modes of the display panel include: In displaying one frame of picture, sequentially driving N rows of pixel circuits; The time interval between the start times of driving the first pixel circuit row twice in displaying two consecutive frames is T.

9. The display panel according to claim 1, wherein: N is an integer multiple of m; The working mode of the display panel includes: at the start moment of the light-emitting phase of the pixel circuit row, the number of the pixel circuit rows in the light-emitting phase driven by the n selection signal lines through the selection module is equal.

10. The display panel according to claim 1, wherein N+r is an integer multiple of m, where r is an integer; At the start time of the light emitting phase of the pixel circuit row, the number of the pixel circuit rows in the light emitting phase driven by different selection signal lines through the selection module differs by at most 1.

11. The display panel according to claim 1, wherein The operation mode of the display panel includes: the control signal includes at least two periods in the first time, and the period of the control signal is t*m.

12. The display panel according to claim 1, wherein The working mode of the display panel includes: the pulse period of the trigger signal received by the driving module in the first-stage shift register unit is t*m.

13. The display panel according to claim 1, wherein The operating modes of the display panel include: The strobe signal line provides a strobe signal, the period of the strobe signal is n*t, and the start time of the periods of the strobe signals provided by two adjacent strobe signal lines arranged in sequence differs by t.

14. The display panel according to claim 1, wherein The pixel circuit includes a first driving circuit and a second driving circuit. The first driving circuit is configured to control the amplitude of the driving current provided to the light-emitting device based on the first data voltage, and the second driving circuit is configured to control the duration of the driving current provided to the light-emitting device based on the second data voltage and the sweep signal.

15. The display panel according to claim 14, wherein: The first driving circuit includes a first driving transistor, a first control transistor and a second control transistor, wherein the first driving transistor is connected in series between the first control transistor and the second control transistor; The shift register unit includes a first shift register unit, the strobe signal line includes a first strobe signal line, and the first strobe signal line is connected to the first shift register unit; An output end of the gating module in the first shift register unit is connected to a control end of the first control transistor and a control end of the second control transistor.

16. The display panel according to claim 15, wherein: The first selection signal line provides a first selection signal, and the period of the first selection signal is n*t; The first selection signal includes a first level signal and a second level signal, the first level signal is an enable signal; in one cycle of the first selection signal, the duration of the first level signal is greater than the duration of the second level signal.

17. The display panel according to claim 14, wherein: The shift register unit includes a second shift register unit, the strobe signal line includes a second strobe signal line, and the second strobe signal line is connected to the second shift register unit; The output end of the strobe module in the second shift register unit is connected to the second driving circuit, and the control signal output by the second shift register unit is the frequency sweep signal.

18. The display panel according to claim 17, wherein: The second selection signal line provides a second selection signal, and the period of the second selection signal is n*t; The second selection signal includes a constant voltage signal and a ramp signal; in one cycle of the second selection signal, the duration of the ramp signal is greater than the duration of the constant voltage signal.

19. The display panel according to claim 1, wherein n＝6。 20. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 19.

Images