Method for multipath cooperative communication

Abstract

The application discloses a kind of multi-path cooperative communication methods, belong to wireless communication technical field, for solving the problem of inaccurate path selection, unreasonable power allocation and signal merging misalignment caused by dynamic change of channel state in multi-path communication.The method obtains the channel state information of at least three communication paths in real time by the transmitting end, including signal strength, frequency offset and noise power spectral density;Based on path quality factor, dynamically divide and distribute data stream to each path, adjust the transmitting power in combination with signal strength and noise difference;The receiving end uses sliding window cross-correlation algorithm for time domain alignment, and implements phase compensation based on least mean square error criterion;When continuous bit error rate exceeds threshold value, trigger path redistribution.The method can optimize multi-path resource utilization, improve communication stability and data transmission efficiency.

Description

Technical Field

[0001] This invention relates to the field of communications. More specifically, this invention relates to a multi-channel cooperative communication method. Background Technology

[0002] In multi-path cooperative communication systems, existing technologies face several pressing issues. Traditional methods for path quality assessment typically rely on a single parameter or static threshold, focusing only on signal strength while ignoring the combined effects of frequency offset and noise. Because parameters such as frequency offset and ambient noise power spectral density in channel state information have different dimensions, direct quantification is difficult, leading to biases in path quality assessment results. This bias can cause high-interference paths to fail to be identified in a timely manner, allowing low-quality paths to continue transmitting critical data, ultimately resulting in a decline in communication link performance. Furthermore, the dynamic adjustment strategy for transmit power lacks sufficient correlation with real-time signal-to-noise ratio changes. Fixed-step designs are prone to power oscillations in low signal-to-noise ratio ranges, while significant response delays occur in sudden interference scenarios, further exacerbating link instability.

[0003] In signal combining at the receiver, multipath delay differences make signal alignment difficult. Traditional methods use a fixed-length sliding window for time-domain alignment, but the window length cannot adapt to dynamically changing delay ranges. When multipath interference exists in the channel, the main peak detection of the cross-correlation algorithm is easily affected by secondary peak interference, and existing technologies lack a mechanism to dynamically expand the window based on the number of secondary peaks, leading to a continuous accumulation of alignment errors. Furthermore, in high-speed mobile scenarios, carrier frequency offset changes rapidly over time. Traditional phase correction models only compensate based on the current frequency offset value, without considering the dynamic correction of the frequency offset change rate, making it difficult to completely eliminate residual frequency offset problems and severely affecting the accuracy of signal combining.

[0004] The optimization of correction parameters also has significant limitations. Existing technologies lack a unified evaluation standard for the joint correction of phase and amplitude distortions, typically designing error functions only for a single distortion type, making it difficult to balance the combined impact of the two types of distortions on system performance. Furthermore, the weighting coefficients of predistortion techniques are usually fixed and cannot be dynamically adjusted according to long-term channel changes, leading to a degradation of correction effectiveness with environmental changes. In power adjustment and path allocation strategies, the utilization efficiency of historical data is low, and the prediction model does not effectively integrate time decay factors, making it difficult to accurately capture the gradual trend of channel state changes. When facing high-frequency channel fluctuations, traditional prediction algorithms converge slowly due to high computational complexity, requiring repeated trade-offs between resource consumption and prediction accuracy in practical deployments, further increasing the difficulty of system design.

[0005] The causes of these problems involve inherent contradictions between multidimensional parameter fusion, dynamic adaptation mechanisms, and algorithm complexity. For example, path quality assessment requires the normalization of parameters with different dimensions, but the selection of normalization coefficients lacks theoretical basis and is prone to subjective bias. Dynamic window adjustment needs to strike a balance between delay measurement accuracy, computational real-time performance, and hardware resource consumption, and the quantification standards for extended conditions are difficult to unify. In addition, high-frequency operations in dense correction mode place extremely high demands on the parallel computing capabilities of the processor, while adaptive parameter adjustment under long-term channel changes needs to balance stability and sensitivity. The closed-loop coupling design of bit error rate feedback and correction parameters faces the dual challenges of algorithm convergence and real-time performance. Summary of the Invention

[0006] One object of the present invention is to solve at least the above-mentioned problems and to provide at least the advantages that will be described later.

[0007] To achieve these objectives and other advantages according to the present invention, a multi-path cooperative communication method is provided, comprising:

[0008] By deploying a channel status monitoring module at the transmitter, the channel status information of at least three independent communication paths within the target area can be obtained in real time. The channel status information includes the current signal strength measurement, frequency offset, and ambient noise power spectral density of each communication path.

[0009] In the data stream segmentation module, based on a preset priority allocation algorithm, the data stream to be transmitted is divided into N data sub-blocks and dynamically allocated to each communication path. The priority allocation algorithm generates a path quality factor based on the product of the frequency offset output by the channel state monitoring module and the ambient noise power spectral density. When the path quality factor is lower than a preset switching threshold, the load weight of the communication path is reduced by 40-60%.

[0010] In the power control module, the transmit power of each communication path is dynamically adjusted based on the difference between the real-time measured signal strength and the ambient noise power spectral density.

[0011] The signal combining module at the receiving end performs time-domain alignment and phase compensation on the data sub-blocks from each communication path. The time-domain alignment adopts a cross-correlation algorithm with a sliding window length of 8~32μs, and the phase compensation adopts a pre-distortion correction based on the minimum mean square error criterion, with a correction angle range of -π / 6~π / 6.

[0012] A bit error rate monitoring unit is set up in the feedback link. When the bit error rate of three consecutive data sub-blocks exceeds 1×10, the unit will detect the error rate. -4 At that time, the channel status monitoring module is triggered to rescan the target area and update the communication path allocation table.

[0013] In multipath communication, dynamic changes in channel conditions lead to inaccurate path selection, unreasonable power allocation, and delays and phase mismatches during signal combining at the receiving end, resulting in a decline in overall communication quality. This invention optimizes path selection efficiency through real-time channel monitoring and dynamic load allocation; combined with power adjustment and signal combining techniques, it improves multipath signal alignment accuracy, reduces bit error rate, and enhances communication stability.

[0014] Preferably, the method for calculating the path quality factor includes: normalizing the frequency offset and the ambient noise power spectral density, wherein the normalization coefficient for the frequency offset is 1 / (15kHz), and the normalization coefficient for the ambient noise power spectral density is 1 / (10kHz). -3 W / Hz), generating a dimensionless path quality factor Q=Δf norm ×P noise_norm , where Δf norm P is the normalized frequency offset. noise_norm This represents the normalized environmental noise power spectral density.

[0015] The priority allocation algorithm includes: dynamically calculating the load weight reduction ratio based on the difference between the path quality factor Q and the switching threshold; when Q is lower than the switching threshold, the load weight reduction ratio is increased by 0.5 × 10⁻⁶ for every 0.5 × 10⁻⁶ decrease. -3 Each unit Q value corresponds to a 10% reduction in weight, with a maximum weight reduction of 60% and a minimum of 40%.

[0016] During the data sub-block segmentation process, based on the historical bit error rate statistics of the communication path, the delay-sensitive data sub-blocks in the data stream to be transmitted are preferentially allocated to the communication path with a Q value higher than 1.2 times the switching threshold. The length of the delay-sensitive data sub-block is set to 256 bytes to 512 bytes.

[0017] Add a path assignment identifier field to each data sub-block. This field contains the Q-value verification code of the target communication path and the sequence verification code of the data sub-block. The Q-value verification code is generated by retaining three significant digits of the binary floating-point number of the Q-value.

[0018] When the load weight of a communication path is reduced, a remapping operation of data sub-blocks is triggered, and the data sub-blocks that have not been transmitted in the original path are redistributed in descending order of Q value to communication paths with a current Q value higher than the switching threshold.

[0019] Traditional path quality assessment lacks normalization processing, resulting in inconsistent quantification standards for cross-parameters (such as frequency offset and noise), and data allocation strategies cannot effectively distinguish priorities. This invention achieves standardized assessment of multi-dimensional parameters by normalizing the calculation of the path quality factor Q; combined with a priority allocation strategy, it prioritizes the transmission of critical data along high-Q-value paths, improving resource utilization efficiency.

[0020] Preferably, the power control module dynamically adjusts the transmission power of each communication path based on the difference between the real-time measured signal strength and the ambient noise power spectral density, specifically including:

[0021] A mapping relationship is established between the transmit power adjustment and the signal strength-noise difference ΔS, where ΔS is defined as the difference between the current signal strength measurement and the ambient noise power spectral density. When ΔS is in the range of -90 to -85 dBm, a 2 dB step adjustment is adopted, and when ΔS is in the range of -85 to -70 dBm, a 0.5 dB step adjustment is adopted.

[0022] During power adjustment, the instantaneous interference mutation rate of the target communication path is monitored synchronously. When the change in ΔS after two consecutive power increases is less than 20% of the adjustment step size, the sudden interference suppression mode is activated, shortening the transmit power adjustment period from 100ms to 50ms, while increasing the step size to 150% of the original step size.

[0023] A power adjustment history table is established for each communication path, recording triplet data including timestamp, ΔS value and actual transmit power value. When the fluctuation of ΔS within 300ms exceeds 15dB, the step size correction coefficient for the next adjustment cycle is predicted based on the ΔS gradient values ​​of the last five cycles in the history table.

[0024] After the power boost operation is executed, the effectiveness of the power adjustment is verified by the bit error rate monitoring unit of the feedback link. If the bit error rate of two consecutive data sub-blocks after the adjustment does not decrease by 30% of the bit error rate before the adjustment, the power boost of the current communication path is stopped and the backup frequency band is switched.

[0025] A saturation protection mechanism for transmission power adjustment is set up. When the cumulative power increase of a single communication path reaches 25% of the initial transmission power, a cross-path power rebalancing operation is triggered, and the power value exceeding the threshold is proportionally allocated to other communication paths with a Q value higher than 1.5 times the switching threshold.

[0026] Fixed-step power adjustment strategies cannot adapt to different noise environments, and the power response lags under sudden interference, increasing the risk of link interruption. This invention optimizes power control sensitivity based on dynamic step size adjustment within the ΔS range; it also shortens the response time through a sudden interference suppression mode, reducing the impact of sudden interference on the communication link.

[0027] Preferably, the step size correction coefficient for the next adjustment period is predicted based on the ΔS gradient values ​​of the most recent five periods in the historical record table, specifically including:

[0028] The gradient values ​​of ΔS over the most recent five periods are processed using a cubic polynomial fitting algorithm to generate a prediction model that includes a time decay factor, which is set at 0.8.n The weight of historical data decays exponentially, where n represents the interval between the current period and the historical period;

[0029] Substituting the fitted polynomial coefficients into the gradient change equation ∂G / ∂t=α·G max +β·G min Where α takes values ​​of 0.6 to 0.8, β takes values ​​of 0.2 to 0.4, and G max and G min These represent the absolute values ​​of the maximum and minimum gradients within the five periods, respectively;

[0030] Based on the equation solution, generate the step size correction coefficient K = 1 + 0.15·sign(∂G / ∂t)·|∂G / ∂t| 0.5 When the K value exceeds the range of 0.7-1.3, it is forcibly limited to the interval endpoint value and the prediction model parameters are reset.

[0031] After each power adjustment operation is performed, the residual between the actual ΔS change gradient and the predicted gradient is calculated. When the absolute value of the residual exceeds 30% of the predicted value for three consecutive times, the system automatically switches to the moving weighted average prediction mode, which uses 60%, 30%, and 10% weights of the gradient values ​​of the first three periods.

[0032] Configure the effective duration parameter for the correction coefficient K. When K>1, the effective duration is set to 150~300ms. When K<1, the effective duration is set to 400~600ms. During the effective period, the power rebalancing operation of other communication paths is frozen.

[0033] Traditional power adjustment relies on current state data and lacks historical trend prediction, causing the adjustment strategy to lag behind rapid channel changes. This invention utilizes cubic polynomial fitting and historical gradient prediction to improve the foresight of power adjustment; a residual monitoring mechanism adaptively switches the prediction model, enhancing robustness in nonlinear environments.

[0034] Preferably, the temporal alignment employs a cross-correlation algorithm with a sliding window length of 8~32μs, specifically including:

[0035] Calculate the maximum delay difference Δτ between each communication path at the receiving end, set the basic length of the sliding window to 3 to 5 times Δτ, and constrain it within the range of 8 to 32 μs, where Δτ is calculated by the timestamp difference of data sub-blocks of adjacent paths;

[0036] During the execution of the cross-correlation algorithm, the number and amplitude of the correlation peaks are monitored in real time. When more than two secondary peaks are detected within a 3dB bandwidth on both sides of the main peak, the sliding window length is extended to 1.2 to 1.8 times the current value, and the extended window length does not exceed 32μs.

[0037] The window movement step size is dynamically adjusted according to the length of the data sub-block. When the length of the data sub-block is 256~512 bytes, the step size is set to 1 / 8~1 / 4 of the window length. When the length of the data sub-block is 1024~2048 bytes, the step size is reduced to 1 / 16~1 / 12 of the window length.

[0038] During the window sliding process, Doppler frequency shift pre-correction is performed synchronously. The signal samples within the window are rotated using the carrier frequency offset measurement value. The rotation angle is θ = 2π·Δf·t, where Δf is the frequency offset of the current path and t is the relative time of the sampling points within the window.

[0039] After each window adjustment, the alignment effect is verified by the bit error rate monitoring unit of the feedback link. If the decrease in bit error rate of three consecutive data sub-blocks after adjustment does not reach 15% of the bit error rate before adjustment, the sliding window parameters are reset and the delay difference Δτ measurement is re-executed.

[0040] Multipath delay differences can lead to inaccurate signal alignment at the receiver, especially in dynamic channels where the window parameters are fixed, resulting in deteriorated merging performance. This invention addresses this by dynamically adjusting the sliding window length and step size to match channel delay characteristics; combined with a secondary peak detection extended window, it suppresses multipath interference and improves time-domain alignment accuracy.

[0041] Preferably, Doppler frequency shift pre-correction is performed synchronously during the window sliding process, and the phase of the signal samples within the window is rotated using the carrier frequency offset measurement value, specifically including:

[0042] The rate of change Δf is calculated in real time during the window sliding process. rate =[Δf(t)-Δf(t-Δt)] / Δt, where Δt is the time interval between two consecutive frequency offset measurements, and the phase rotation angle is corrected to θ=2π×(Δf+Δf rate ×t)×t;

[0043] Set phase rotation angle constraint conditions. When the calculated absolute value of θ exceeds π / 3, enable the angle limiter to limit θ to the range of -π / 3 to π / 3, and trigger the calibration signal generator of the frequency offset measurement module to output a test tone signal of 1 to 5 kHz.

[0044] Residual frequency offset compensation is performed after the phase rotation operation. The compensation factor C = 1 - (EVM) is calculated based on the constellation diagram divergence of the rotated signal. measured / EVM threshold ), of which EVM measured EVM represents the measured error vector magnitude. threshold Set to 8~12%, the compensation factor is applied to the Δf measurement value in the subsequent window to form a closed-loop correction;

[0045] A segmented correction strategy is adopted. When the fluctuation amplitude of Δf exceeds ±2kHz for three consecutive measurement cycles, the dense correction mode is activated, which increases the execution interval of phase rotation operation from once per window to once per sampling point, while shortening Δt to 20-30% of the original value.

[0046] After each window slide, the correction effect is verified by comparing the mean change of θ between adjacent windows. If the residual carrier frequency offset after correction is still greater than 10% of Δf, the extended Kalman filter algorithm is automatically switched to re-estimate the Δf value, and the new estimate is written to the frequency calibration field of the path allocation table.

[0047] In high-speed moving scenarios, Doppler frequency shift leads to the accumulation of phase rotation errors, and traditional correction methods cannot track rapid frequency shift changes in real time. This invention introduces a frequency shift change rate Δf. rate The phase rotation angle is corrected to dynamically compensate for the Doppler effect; closed-loop compensation and segmented correction strategies further eliminate residual frequency offset and ensure signal integrity under high-speed movement.

[0048] Preferably, the phase compensation employs pre-distortion correction based on the minimum mean square error criterion, specifically including:

[0049] Construct a joint error function E=γ·(Δε) that includes phase difference and amplitude fluctuation. 2 +δ·(ΔA / A ref ) 2 Where Δε is the measured phase deviation, ΔA is the amplitude fluctuation, and A ref The weighting coefficient γ is set to 80-120% of the average amplitude of the received signal, and the weighting coefficient γ is set to 0.6-0.8 and δ is set to 0.2-0.4.

[0050] The minimum error function is solved using a recursive least squares algorithm to generate a predistortion vector containing both I and Q corrections. During the iterative calculation, the step size parameter μ is constrained to be 0.05–0.15, and the residual convergence threshold is set to 1 × 10⁻⁶. -4 ~5×10 -4 ;

[0051] The pre-distortion correction operation is performed in stages. In the first stage, the full correction vector is applied only to the path with a phase difference Δε exceeding π / 12. In the second stage, 50-70% of the correction vector is used to progressively compensate the remaining path.

[0052] After the calibration operation, the error vector magnitude (EVM) of the pilot symbol is extracted as a verification index. When the measured EVM value is higher than 8%, the calibration vector update module is triggered to recalculate the predistortion parameters with a period of 200~500ms.

[0053] A dynamic adjustment mechanism for correction parameters is established. The weighting coefficients γ and δ are adjusted in reverse according to the bit error rate change trend of three consecutive data sub-blocks. If the bit error rate decrease rate is less than 10% / sub-block, γ is increased by 5% to 10% and δ is reduced by the corresponding ratio.

[0054] A single error function is insufficient to simultaneously address phase and amplitude distortion, and traditional fixed correction parameters cannot adapt to long-term channel variations. This invention combines phase and amplitude error weighting optimization to improve the comprehensiveness of pre-distortion correction; it dynamically adjusts weighting coefficients and a phased compensation strategy to achieve adaptive parameter optimization under long-term channel conditions.

[0055] Other advantages, objectives and features of the present invention will become apparent in part from the following description, and in part from those skilled in the art through study and practice of the invention. Detailed Implementation

[0056] The present invention will be further described in detail below with reference to embodiments, so that those skilled in the art can implement it based on the description.

[0057] This invention provides a multi-path cooperative communication method, comprising:

[0058] By deploying a channel status monitoring module at the transmitter, the channel status information of at least three independent communication paths within the target area can be obtained in real time. The channel status information includes the current signal strength measurement, frequency offset, and ambient noise power spectral density of each communication path.

[0059] In the data stream segmentation module, based on a preset priority allocation algorithm, the data stream to be transmitted is divided into N data sub-blocks and dynamically allocated to each communication path. The priority allocation algorithm generates a path quality factor based on the product of the frequency offset output by the channel state monitoring module and the ambient noise power spectral density. When the path quality factor is lower than a preset switching threshold, the load weight of the communication path is reduced by 40-60%.

[0060] In the power control module, the transmit power of each communication path is dynamically adjusted based on the difference between the real-time measured signal strength and the ambient noise power spectral density.

[0061] The signal combining module at the receiving end performs time-domain alignment and phase compensation on the data sub-blocks from each communication path. The time-domain alignment adopts a cross-correlation algorithm with a sliding window length of 8~32μs, and the phase compensation adopts a pre-distortion correction based on the minimum mean square error criterion, with a correction angle range of -π / 6~π / 6.

[0062] A bit error rate monitoring unit is set up in the feedback link. When the bit error rate of three consecutive data sub-blocks exceeds 1×10, the unit will detect the error rate. -4At that time, the channel status monitoring module is triggered to rescan the target area and update the communication path allocation table.

[0063] Specifically, the channel state monitoring module can be deployed between the antenna array and the baseband processing unit at the transmitting end, connected via RF front-end circuitry. This module can utilize a spectrum analyzer supporting multi-channel synchronous sampling, such as a device with at least three independent receiving channels. Its signal strength measurement range can be set to -100dBm to -50dBm, and the frequency offset measurement accuracy to ±0.1kHz. The ambient noise power spectral density measurement bandwidth can be set to 1MHz, with a resolution bandwidth of 10kHz. The module's circuit board material can be FR-4 epoxy resin laminate, and the RF connector can be an SMA interface.

[0064] Signals are extracted from each communication path using directional couplers, amplified by low-noise amplifiers, and then input to an analog-to-digital converter (ADC) at a sampling rate of 20 MS / s. Signal strength is measured using a logarithmic detector circuit, frequency offset is calculated by comparing the signal with a reference clock using a digital phase detector, and noise power spectral density is extracted using an FFT spectrum analysis module. The channel state monitoring module should be mounted close to the transmit antenna feed point to minimize the impact of transmission line loss on measurement accuracy.

[0065] The channel status monitoring module ensures the accuracy of channel status information through high-precision real-time monitoring, providing reliable input for subsequent path allocation and power control.

[0066] The priority allocation algorithm can run on the FPGA chip or embedded processor at the transmitter, and the number of data stream segments N can be set to 4 to 8 sub-blocks. The switching threshold for the path quality factor Q can be set to 0.6 × 10⁻⁶. -3 The load weight reduction ranges from 40% to 60%, with the specific reduction percentage adjusted linearly based on the difference between the Q value and the threshold. For example, for every 0.5 × 10⁻⁶ decrease in the Q value... -3 The weight reduction rate increases by 10%. The length of the data sub-block can be configured to 256 bytes or 512 bytes, and latency-sensitive sub-blocks are preferentially allocated to blocks with a Q value higher than 0.72×10. -3 The path.

[0067] During algorithm execution, the data stream segmentation module can be implemented based on a circular buffer. The Q-value verification code in the path allocation identifier field adopts the IEEE 754 single-precision floating-point format, retaining three significant digits. After load weight adjustment, data sub-blocks that have not yet completed transmission are reallocated to paths with Q values ​​higher than the threshold in descending order of Q value. Related computing resources can be integrated into the shared memory of the baseband processing unit and communicate with the main control unit via the PCIe interface.

[0068] The data stream segmentation module optimizes data stream allocation efficiency, reduces the transmission load of high-interference paths, and improves overall communication reliability.

[0069] The power control module can be deployed at the front end of the power amplifier circuit at the transmitter. The measurement period for the signal strength and noise difference ΔS is 10ms. When ΔS is between -90 and -85dBm, the power adjustment step size is 2dB; when ΔS is between -85 and -70dBm, the step size is 0.5dB. The monitoring window length for the instantaneous interference mutation rate is 50ms. If the change in ΔS after two consecutive adjustments is less than 20% of the step size, the adjustment period is shortened to 50ms, and the step size is increased to 150% of the original value. The power adjustment history record table is stored in EEPROM, with a recording interval of 100ms.

[0070] The transmit power is adjusted via a digitally controlled attenuator, and the power value is converted into an analog control voltage via a DAC. The saturation protection mechanism has a threshold set at 25% of the initial power; any excess power is allocated to other paths proportionally to the Q value. In burst interference suppression mode, the dynamic range of the power amplifier bias voltage is extended to ±5V to support rapid power switching.

[0071] The power control module enables precise control of transmission power, avoiding power waste and suppressing the impact of sudden interference on communication quality.

[0072] The signal combining module can be integrated into the digital signal processor at the receiver. The sliding window length can be selected as 8μs, 16μs, or 32μs, and the window movement step size is dynamically set to 1 / 8 to 1 / 4 of the window length based on the data sub-block length. The main peak detection threshold of the cross-correlation algorithm is set to -3dB. When the number of sub-peaks exceeds two, the window length is expanded to 1.5 times the current value. The minimum mean square error iteration convergence threshold for phase compensation is 1×10⁻⁶. -4 The pre-distortion correction angle range is limited to -π / 6 to π / 6.

[0073] The received signal is sampled by an ADC and stored in a dual-port RAM. Time-domain alignment is achieved using a parallel correlator array with a sliding window, and the phase compensation coefficient is calculated using the CORDIC algorithm. The bit error rate monitoring unit employs a CRC check circuit; if the bit error rate of three consecutive sub-blocks exceeds 1×10⁻⁶, the error is considered zero. -4 At this time, an interrupt signal is sent to the channel state monitoring module. The module should be installed close to the output of the receiver mixer to reduce phase errors introduced by clock jitter. The signal combining module improves the combining accuracy of multipath signals and reduces the bit error rate degradation caused by delay and phase mismatch.

[0074] Furthermore, the method for calculating the path quality factor includes: normalizing the frequency offset and the ambient noise power spectral density, wherein the normalization coefficient for the frequency offset is 1 / (15kHz), and the normalization coefficient for the ambient noise power spectral density is 1 / (10kHz). -3 W / Hz), generating a dimensionless path quality factor Q=Δf norm ×P noise_norm , where Δf norm P is the normalized frequency offset. noise_norm This represents the normalized environmental noise power spectral density.

[0075] The priority allocation algorithm includes: dynamically calculating the load weight reduction ratio based on the difference between the path quality factor Q and the switching threshold; when Q is lower than the switching threshold, the load weight reduction ratio is increased by 0.5 × 10⁻⁶ for every 0.5 × 10⁻⁶ decrease. -3 Each unit Q value corresponds to a 10% reduction in weight, with a maximum weight reduction of 60% and a minimum of 40%.

[0076] During the data sub-block segmentation process, based on the historical bit error rate statistics of the communication path, the delay-sensitive data sub-blocks in the data stream to be transmitted are preferentially allocated to the communication path with a Q value higher than 1.2 times the switching threshold. The length of the delay-sensitive data sub-block is set to 256 bytes to 512 bytes.

[0077] Add a path assignment identifier field to each data sub-block. This field contains the Q-value verification code of the target communication path and the sequence verification code of the data sub-block. The Q-value verification code is generated by retaining three significant digits of the binary floating-point number of the Q-value.

[0078] When the load weight of a communication path is reduced, a remapping operation of data sub-blocks is triggered, and the data sub-blocks that have not been transmitted in the original path are redistributed in descending order of Q value to communication paths with a current Q value higher than the switching threshold.

[0079] Specifically, the path quality factor Q can be calculated based on the frequency offset Δf and the ambient noise power spectral density P. noise_norm Normalization processing. The normalization coefficient for the frequency offset can be set to 1 / (15kHz), and the normalization coefficient for the ambient noise power spectral density can be set to 1 / (10kHz). -3 W / Hz). Normalized Δf norm With P noise_norm Multiplying the product produces a dimensionless value Q, calculated using the formula Q = Δf. norm ×P noise_normFrequency offset can be measured using a digital frequency meter, with a range covering ±50kHz and a resolution of at least 0.1kHz. Noise power spectral density can be measured using a spectrum analyzer, with a dynamic range of -120 to -20dBm and an RBW (resolution bandwidth) configurable from 1 to 10kHz.

[0080] The normalization module can be integrated into the FPGA of the baseband processing unit, using a 32-bit floating-point arithmetic unit to implement multiplication operations. The frequency offset measurement circuit can be deployed at the output of the transmitter's local oscillator module, and the noise power measurement circuit is located after the receiver's low-noise amplifier. The normalization coefficients are stored in EEPROM and can be dynamically configured via the SPI interface. The module's substrate material can be FR-4 epoxy resin, and the RF path uses gold-plated microstrip lines to reduce losses. The normalization module eliminates dimensional differences through normalization, providing a unified standard for path quality assessment and improving algorithm robustness.

[0081] In the priority allocation algorithm, the load weight reduction ratio can be dynamically calculated as follows: when the Q value is lower than the switching threshold of 0.6 × 10⁻⁶. -3 At that time, for every decrease of 0.5×10 -3 Each unit of Q value corresponds to a 10% weight reduction, with a maximum reduction of 60% and a minimum of 40%. The length of the data sub-block can be set to 256 bytes or 512 bytes. Latency-sensitive sub-blocks are preferentially allocated to those with Q values ​​higher than 0.72 × 10⁻⁶. -3 The path. The data stream segmentation module can be implemented based on a circular queue, with a queue depth configurable to 8-16 sub-blocks.

[0082] During algorithm execution, the real-time value of the path quality factor Q is transmitted to the allocation decision unit via shared memory. Load weight adjustment signals are sent to the data routing controller via GPIO pins, and the routing table update cycle can be set to 10ms. The identifier field of latency-sensitive sub-blocks can occupy 2 bits in the packet header to indicate priority level. The allocation strategy decision logic can be deployed in the real-time task thread of the embedded processor, with the task scheduling cycle synchronized with channel state updates. Dynamic adjustment of path load distribution prioritizes the transmission quality of high-priority data, reducing the risk of link congestion.

[0083] The path allocation identifier field can contain a 16-bit Q-value checksum and a 32-bit sequence checksum. The Q-value checksum can be generated based on the IEEE 754 single-precision floating-point format, retaining three significant digits, for example, Q = 0.72 × 10⁻⁶. -3 The encoding is 0x3A3D70A4. The sequence check code can be generated using the CRC-32 algorithm, with a generator polynomial of 0x04C11DB7. The identifier field can be inserted at the beginning of the data sub-block, occupying 48 bits.

[0084] The data sub-block remapping operation is triggered by the routing controller. When the path load weight decreases by more than 40%, the sub-blocks that have not been transmitted are reassigned in descending order of Q value to locations with a Q value higher than 0.6 × 10⁻⁶. -3 The routing table can be stored in SRAM, supports dynamic updates, and has a maximum of 256 entries. The remapping process latency can be controlled within 5ms, accelerated by a priority sorting module implemented using a hardware description language. The routing controller should be installed close to the output interface of the data buffer to minimize signal transmission delay. The traceability of data sub-blocks is ensured through an identification field, and the remapping mechanism improves data transmission continuity during link interruptions.

[0085] Furthermore, the power control module dynamically adjusts the transmission power of each communication path based on the difference between the real-time measured signal strength and the ambient noise power spectral density, specifically including:

[0086] A mapping relationship is established between the transmit power adjustment and the signal strength-noise difference ΔS, where ΔS is defined as the difference between the current signal strength measurement and the ambient noise power spectral density. When ΔS is in the range of -90 to -85 dBm, a 2 dB step adjustment is adopted, and when ΔS is in the range of -85 to -70 dBm, a 0.5 dB step adjustment is adopted.

[0087] During power adjustment, the instantaneous interference mutation rate of the target communication path is monitored synchronously. When the change in ΔS after two consecutive power increases is less than 20% of the adjustment step size, the sudden interference suppression mode is activated, shortening the transmit power adjustment period from 100ms to 50ms, while increasing the step size to 150% of the original step size.

[0088] A power adjustment history table is established for each communication path, recording triplet data including timestamp, ΔS value and actual transmit power value. When the fluctuation of ΔS within 300ms exceeds 15dB, the step size correction coefficient for the next adjustment cycle is predicted based on the ΔS gradient values ​​of the last five cycles in the history table.

[0089] After the power boost operation is executed, the effectiveness of the power adjustment is verified by the bit error rate monitoring unit of the feedback link. If the bit error rate of two consecutive data sub-blocks after the adjustment does not decrease by 30% of the bit error rate before the adjustment, the power boost of the current communication path is stopped and the backup frequency band is switched.

[0090] A saturation protection mechanism for transmission power adjustment is set up. When the cumulative power increase of a single communication path reaches 25% of the initial transmission power, a cross-path power rebalancing operation is triggered, and the power value exceeding the threshold is proportionally allocated to other communication paths with a Q value higher than 1.5 times the switching threshold.

[0091] Specifically, the measurement range of the signal strength to noise difference ΔS can be divided into two segments: -90 to -85 dBm and -85 to -70 dBm. When ΔS is between -90 and -85 dBm, the power adjustment step size can be set to 2 dB; when ΔS is between -85 and -70 dBm, the step size can be adjusted to 0.5 dB. A digital signal strength indicator can be used to measure ΔS, with a dynamic range covering -100 dBm to -50 dBm and a measurement accuracy of ±0.5 dB. The power adjustment module can be deployed between the digitally controlled attenuator and the power amplifier at the transmitting end, converting the digital control signal into an analog voltage via a DAC module.

[0092] The ΔS value is updated every 10ms. The ADC sampling circuit of the baseband processing unit acquires the instantaneous values ​​of signal strength and ambient noise and calculates the difference. The step size mapping table can be stored in the FPGA's lookup table, and the step size is adjusted based on the real-time ΔS value index. The control voltage range of the digitally controlled attenuator can be set to 0~5V, corresponding to an attenuation of 0~30dB. The module should be mounted close to the input port of the power amplifier to reduce the transmission delay of the control signal. Through a segmented adjustment strategy, the response speed and accuracy of power control are optimized to adapt to dynamic requirements under different channel conditions.

[0093] The monitoring window for transient interference mutation rate can be set to 50ms. When the change in ΔS after two consecutive power increases is less than 20% of the adjustment step size (e.g., the change must be greater than 0.4dB when the step size is 2dB), the sudden interference suppression mode is activated. In this mode, the power adjustment cycle can be shortened from 100ms to 50ms, and the step size can be increased to 150% of the original value (e.g., from 2dB to 3dB). The monitoring module can use a digital comparator circuit, whose input comes from the differential signal output of the ΔS measurement unit. The threshold comparison result triggers mode switching via an interrupt signal.

[0094] After each power adjustment, the change in ΔS is calculated in real time by a subtractor circuit, and the result is stored in a shift register for two consecutive comparisons. When the trigger condition is met, the control logic resets the adjustment cycle counter to 50ms and modifies the step size parameter through a multiplier circuit. The activation signal for the burst interference suppression mode is transmitted to the power control unit through an optocoupler isolator to ensure signal integrity in high-noise environments. The module's circuit board material can be aluminum-based copper-clad laminate to improve heat dissipation performance. It responds quickly to burst interference events and reduces the probability of communication link interruption through dynamic adjustments.

[0095] The power adjustment history table can store a triplet of timestamp, ΔS value, and actual transmit power, with a recording interval of 100ms and a storage depth of the most recent 50 data sets. When a fluctuation of ΔS exceeding 15dB within 300ms is detected, the prediction module processes the ΔS gradient values ​​of the most recent 5 cycles using a cubic polynomial fitting algorithm to generate the step size correction coefficient K for the next adjustment cycle. The fitting operation can be deployed in a DSP chip, whose floating-point unit supports matrix inversion and polynomial coefficient calculation. Historical data can be stored in SRAM with an access latency of less than 10ns.

[0096] The gradient value of ΔS is obtained through difference calculation and stored in a circular buffer after each update. The coefficients of the cubic polynomial fitting are solved iteratively using the least squares method, with a time decay factor of 0.8. n Weighted historical data is used. The predicted K value is limited to the range of 0.7 to 1.3; if it exceeds this range, the prediction is forcibly truncated and the fitting parameters are reset. The prediction module should be installed close to the main control unit's processing core to reduce data bus transmission latency. Board-to-board high-speed connectors with an impedance matching of 50Ω can be used for the circuit connectors. Learning from historical data improves the foresight of power adjustment and reduces the impact of sudden environmental changes on system stability.

[0097] The power adjustment effectiveness verification can be set as follows: if the bit error rate (BER) decrease of two consecutive data sub-blocks does not reach 30% of the BER before adjustment, then the power boost of the current path is stopped and the system switches to a backup frequency band. The backup frequency band can be preset to the 2.4GHz or 5.8GHz ISM band, with the switching delay controlled within 20ms. The threshold for the saturation protection mechanism can be set to 25% of the initial transmit power, with the excess allocated proportionally to other paths with Q values ​​higher than 1.5 times the switching threshold. Power rebalancing can be implemented based on an analog switching matrix, with a switching speed not exceeding 5μs.

[0098] The bit error rate monitoring unit calculates the bit error rate using a CRC check circuit, and the result is transmitted to the control unit via an I2C interface. When an abort condition is triggered, a control signal drives the RF switch to switch to the backup frequency band filter path. The power allocation calculation of the saturation protection module can run in the microcontroller's dedicated coprocessor, and the allocation ratio is achieved using a lookup table method. The module should be installed close to the output matching network of the power amplifier to monitor the output power status in real time. This prevents equipment saturation losses caused by excessive power concentration and ensures balanced utilization of multi-path resources.

[0099] Furthermore, the step size correction coefficient for the next adjustment cycle is predicted based on the ΔS gradient values ​​of the most recent five cycles in the historical record table, specifically including:

[0100] The gradient values ​​of ΔS over the most recent five periods are processed using a cubic polynomial fitting algorithm to generate a prediction model that includes a time decay factor, which is set at 0.8. n The weight of historical data decays exponentially, where n represents the interval between the current period and the historical period;

[0101] Substituting the fitted polynomial coefficients into the gradient change equation ∂G / ∂t=α·G max +β·G min Where α takes values ​​of 0.6 to 0.8, β takes values ​​of 0.2 to 0.4, and G max and G min These represent the absolute values ​​of the maximum and minimum gradients within the five periods, respectively;

[0102] Based on the equation solution, generate the step size correction coefficient K = 1 + 0.15·sign(∂G / ∂t)·|∂G / ∂t| 0.5 When the K value exceeds the range of 0.7-1.3, it is forcibly limited to the interval endpoint value and the prediction model parameters are reset.

[0103] After each power adjustment operation is performed, the residual between the actual ΔS change gradient and the predicted gradient is calculated. When the absolute value of the residual exceeds 30% of the predicted value for three consecutive times, the system automatically switches to the moving weighted average prediction mode, which uses 60%, 30%, and 10% weights of the gradient values ​​of the first three periods.

[0104] Configure the effective duration parameter for the correction coefficient K. When K>1, the effective duration is set to 150~300ms. When K<1, the effective duration is set to 400~600ms. During the effective period, the power rebalancing operation of other communication paths is frozen.

[0105] Specifically, the cubic polynomial fitting algorithm can handle the ΔS gradient values ​​of the most recent five periods. The time decay factor weights the historical data according to an exponential law of 0.8^n, where n represents the interval between the current period and a historical period. The coefficients of the fitted model can be solved using the least squares method, with weighting coefficients α set to 0.6~0.8 and β set to 0.2~0.4. The gradient change equation is ∂G / ∂t=α·G max +β·G min In the middle, G max and G min These are the absolute values ​​of the maximum and minimum gradients over the five periods, respectively.

[0106] This algorithm can be deployed in a digital signal processor (DSP) whose floating-point unit supports matrix operations. Historical gradient data can be stored in SRAM with a storage depth of 5 groups, each containing a timestamp and a ΔS gradient value. The time decay factor calculation module can be integrated into the logic unit of an FPGA, using a shift register to achieve exponential weighting. The module should be mounted close to the main control unit's data bus interface to reduce data transmission latency. FR-4 epoxy resin can be used as the circuit board material, with signal trace impedance matching of 50Ω. Polynomial fitting is used to improve the accuracy of gradient prediction and adapt to dynamic changes in the channel environment.

[0107] The formula for calculating the step size correction factor K is K = 1 + 0.15·sign(∂G / ∂t)·|∂G / ∂t| 0.5 The calculation results are limited to the range of 0.7 to 1.3. When the K value exceeds this range, it is forcibly truncated to the interval endpoints and the prediction model parameters are reset. The calculation module can use the arithmetic logic unit of an embedded processor, supporting signed functions and square root operations. The parameter reset signal can be sent to the fitting module through the interrupt controller, with a reset time of 10μs.

[0108] After each gradient prediction, the calculated K value is stored in a register, and a comparator circuit checks for out-of-bounds errors. If K > 1.3 or K < 0.7, a reset pulse is sent to the fitting module, and the K value is written to the exception record area of ​​the non-volatile memory. The effective duration of the correction coefficient can be configured as follows: 150~300ms when K > 1, and 400~600ms when K < 1. The module should be installed close to the interrupt response circuit of the power control unit to shorten the signal transmission path. The stability of power adjustment is improved by constraining the correction coefficient, avoiding system oscillations caused by prediction deviations.

[0109] The residual calculation can be based on the difference between the actual ΔS gradient and the predicted gradient. When the absolute value of the residual exceeds 30% of the predicted value for three consecutive periods, it automatically switches to the moving weighted average prediction mode. The weight allocation of the moving weighted average can be set to 60%, 30%, and 10% of the gradient values ​​of the previous three periods. The residual monitoring module can use a digital subtractor and an absolute value circuit, and the threshold comparator is set to a 30% tolerance.

[0110] After each power adjustment, the actual gradient value is obtained through differential calculation and compared with the predicted value to generate residual data. The residual sequence is stored in a FIFO buffer. When three consecutive limits are exceeded, a switching control signal drives a multiplexer to switch the prediction algorithm. The calculation of the moving weighted average can be performed on the processor's fixed-point arithmetic unit, with the weighting coefficients stored in registers. The module should be assembled close to the feedback loop of the gradient prediction unit to respond to residual changes in real time. Board-to-board high-speed connectors can be used for the circuit connectors, with signal delay controlled within 2ns. Adaptive switching of the prediction algorithm is achieved through residual monitoring, enhancing the system's robustness in nonlinear environments.

[0111] Furthermore, the temporal alignment employs a cross-correlation algorithm with a sliding window length of 8~32μs, specifically including:

[0112] Calculate the maximum delay difference Δτ between each communication path at the receiving end, set the basic length of the sliding window to 3 to 5 times Δτ, and constrain it within the range of 8 to 32 μs, where Δτ is calculated by the timestamp difference of data sub-blocks of adjacent paths;

[0113] During the execution of the cross-correlation algorithm, the number and amplitude of the correlation peaks are monitored in real time. When more than two secondary peaks are detected within a 3dB bandwidth on both sides of the main peak, the sliding window length is extended to 1.2 to 1.8 times the current value, and the extended window length does not exceed 32μs.

[0114] The window movement step size is dynamically adjusted according to the length of the data sub-block. When the length of the data sub-block is 256~512 bytes, the step size is set to 1 / 8~1 / 4 of the window length. When the length of the data sub-block is 1024~2048 bytes, the step size is reduced to 1 / 16~1 / 12 of the window length.

[0115] During the window sliding process, Doppler frequency shift pre-correction is performed synchronously. The signal samples within the window are rotated using the carrier frequency offset measurement value. The rotation angle is θ = 2π·Δf·t, where Δf is the frequency offset of the current path and t is the relative time of the sampling points within the window.

[0116] After each window adjustment, the alignment effect is verified by the bit error rate monitoring unit of the feedback link. If the decrease in bit error rate of three consecutive data sub-blocks after adjustment does not reach 15% of the bit error rate before adjustment, the sliding window parameters are reset and the delay difference Δτ measurement is re-executed.

[0117] Specifically, the base length of the sliding window can be set to 3 to 5 times the maximum delay difference Δτ between communication paths, and constrained within the range of 8 to 32 μs. Δτ can be measured by the timestamp difference of each data sub-block at the receiving end, and the timestamp accuracy can be set to ±0.1 μs. The window length adjustment module can be deployed in the digital signal processing unit at the receiving end, and dynamically configured using programmable logic devices. For example, when Δτ is measured to be 6 μs, the window length can be set to 18 μs (3 times Δτ).

[0118] The received signal is sampled by the ADC and stored in a dual-port RAM. The timestamp extraction circuit uses the synchronization code in the packet header to locate the start time of each sub-block. The Δτ calculation unit uses a subtractor circuit to generate the inter-path delay difference in real time, and the result is written to a register for use by the window control module. The initial length of the sliding window is configured as an integer multiple of Δτ and is dynamically updated via the SPI interface. The module should be mounted close to the ADC output to minimize signal transmission delay. FR-4 epoxy resin can be used as the circuit board material, and gold plating is used for the RF signal lines to reduce losses. By dynamically matching the channel delay characteristics with the window length, the accuracy of time-domain alignment is improved.

[0119] The main peak detection threshold of the cross-correlation algorithm can be set to -3dB. When more than two secondary peaks are detected within a 3dB bandwidth on both sides of the main peak, the sliding window length is expanded to 1.2 to 1.8 times the current value, with an upper limit not exceeding 32μs after expansion. The correlation peak detection module can use a peak detection integrated circuit with a dynamic range covering -30 to 10dBm and a resolution of not less than 0.1dB. The number of secondary peaks is counted through a comparator array, with a threshold set to -3dB.

[0120] The received signal is input to the correlator array, and the output correlation peak data is stored in a FIFO buffer. The position of the main peak is determined by a maximum value detection circuit, and a secondary peak counter counts the number of peaks exceeding a threshold. When the number of secondary peaks is ≥2, the control logic triggers a window length multiplier, multiplying the original length by an expansion factor (e.g., 1.5 times). The expanded window parameters are transmitted to the RAM controller via a parallel bus to update the window truncation range. The module should be mounted close to the output of the digital down-converter to ensure signal phase consistency. The circuit heat dissipation design can use an aluminum-based copper-clad laminate, with an operating temperature range of -40~85℃. This suppresses the influence of secondary peaks caused by multipath interference and enhances the robustness of time-domain alignment.

[0121] The window movement step size can be dynamically adjusted according to the data sub-block length: when the sub-block length is 256~512 bytes, the step size is set to 1 / 8~1 / 4 of the window length; when the sub-block length is 1024~2048 bytes, the step size is reduced to 1 / 16~1 / 12 of the window length. The Doppler frequency shift pre-correction module can be integrated into the FPGA. The phase rotation angle θ = 2π·Δf·t, where Δf is the frequency offset of the current path and t is the relative time of the sampling point. The phase rotation operation is implemented using the CORDIC algorithm, with a calculation accuracy of ±0.01 radians.

[0122] The window sliding controller uses a preset step size ratio based on the sub-block length index; for example, a 512-byte sub-block corresponds to a 1 / 4 step size (8μs step size when the window is 32μs). Doppler frequency shift measurements are acquired via a digital frequency discriminator and input into the phase rotation calculation unit. The CORDIC algorithm processes 16 fixed-point numbers per cycle and outputs rotated I / Q signal samples. The corrected data is stored in a buffer for subsequent use by the merging module. The module should be mounted close to the clock recovery circuit for synchronized sampling timing. Low-loss PTFE vinyl board with a stable dielectric constant of 2.2 can be used for the signal path material. Dynamic optimization of window movement efficiency compensates for phase errors caused by Doppler frequency shift, improving signal merging quality.

[0123] Furthermore, during the window sliding process, Doppler frequency shift pre-correction is performed synchronously, and the phase of the signal samples within the window is rotated using the carrier frequency offset measurement value, specifically including:

[0124] The rate of change Δf is calculated in real time during the window sliding process. rate =[Δf(t)-Δf(t-Δt)] / Δt, where Δt is the time interval between two consecutive frequency offset measurements, and the phase rotation angle is corrected to θ=2π×(Δf+Δf rate ×t)×t;

[0125] Set phase rotation angle constraint conditions. When the calculated absolute value of θ exceeds π / 3, enable the angle limiter to limit θ to the range of -π / 3 to π / 3, and trigger the calibration signal generator of the frequency offset measurement module to output a test tone signal of 1 to 5 kHz.

[0126] Residual frequency offset compensation is performed after the phase rotation operation. The compensation factor C = 1 - (EVM) is calculated based on the constellation diagram divergence of the rotated signal. measured / EVM threshold ), of which EVM measured EVM represents the measured error vector magnitude. threshold Set to 8~12%, the compensation factor is applied to the Δf measurement value in the subsequent window to form a closed-loop correction;

[0127] A segmented correction strategy is adopted. When the fluctuation amplitude of Δf exceeds ±2kHz for three consecutive measurement cycles, the dense correction mode is activated, which increases the execution interval of phase rotation operation from once per window to once per sampling point, while shortening Δt to 20-30% of the original value.

[0128] After each window slide, the correction effect is verified by comparing the mean change of θ between adjacent windows. If the residual carrier frequency offset after correction is still greater than 10% of Δf, the extended Kalman filter algorithm is automatically switched to re-estimate the Δf value, and the new estimate is written to the frequency calibration field of the path allocation table.

[0129] Specifically, the phase rotation angle θ can be calculated based on the frequency offset Δf and its rate of change Δf rate The real-time measured value is corrected using the formula θ = 2π × (Δf + Δf) rate Δf is calculated as (×t)×t, where Δt is the time interval between two consecutive measurements. A digital frequency discriminator can be used to measure Δf, with a range covering ±10kHz and a resolution of at least 1Hz. rate The calculation can be implemented using a differential circuit, with the input signal coming from two consecutive output values ​​of the frequency discriminator, and the time interval Δt can be set to 1ms.

[0130] The received signal is down-converted and then input to the frequency discriminator. The Δf value is used by a counter circuit to capture the carrier offset. rate The phase rotation calculation unit is deployed in FPGA and uses a 32-bit floating-point multiplier to perform the correction formula calculation. The rotated I / Q signal sample is output to the merging module through a digital up-converter. The module should be mounted close to the local oscillator input of the receiver mixer to reduce signal path delay. FR-4 epoxy resin can be used as the circuit board material, and the RF trace impedance matching is 50Ω. This dynamically corrects the phase error caused by Doppler frequency shift, improving signal stability in high-speed moving scenarios.

[0131] The absolute value limit for the phase rotation angle θ can be set to π / 3. When the calculated value exceeds this range, the angle limiter will forcibly constrain θ between -π / 3 and π / 3. The limiting operation can be implemented through a saturation operation circuit with an input range of -π to π and an output resolution of no less than 0.01 radians. The condition for triggering frequency calibration can be set to θ exceeding the limit three times consecutively. At this time, the calibration signal generator outputs a test tone signal of 1~5kHz, and the duration of the test tone can be configured to 10ms.

[0132] The calculated phase rotation angle is input to the comparator circuit. When the limit is exceeded, the limiter is triggered to output a constraint value, and the number of exceedances is recorded by a counter. The calibration signal generator uses direct digital frequency synthesis technology, and the output signal is injected into the feedback loop of the frequency offset measurement module via a digital-to-analog converter. The module should be mounted close to the calibration port of the frequency discriminator to ensure low-loss transmission of the test tone signal. The circuit heat dissipation design can use an aluminum-based copper-clad laminate, with an operating temperature range of -20~70℃. To prevent signal distortion caused by excessive phase rotation, frequency measurement accuracy is maintained through periodic calibration.

[0133] The formula for calculating the residual frequency offset compensation factor C is C = 1 - (EVM) measured / EVM threshold ), of which EVM threshold It can be set to 10%, EVM measured The measurement accuracy is ±0.5% obtained through the constellation diagram analysis module. In the segmented correction strategy, the trigger condition for the dense correction mode is that the Δf fluctuates for three consecutive cycles exceeding ±2kHz. At this time, the phase rotation execution interval is shortened to once per sampling point, and Δt is reduced to 25% of its original value. The range of the compensation factor C can be limited to 0.8~1.2, and it will be automatically reset to 1.0 when it exceeds this range.

[0134] Constellation diagram data is input into the EVM calculation unit, and the result is transmitted to the compensation factor generation module via the SPI interface. When the Δf fluctuation exceeds the limit, the control logic switches to dense correction mode, shortening the phase rotation execution cycle to sampling clock synchronization. The compensation factor is applied to subsequent Δf measurements through a multiplier, forming a closed-loop correction. The module should be mounted close to the output of the error vector analyzer to acquire EVM data in real time. An SMA interface can be used for the circuit connector to ensure high-frequency signal integrity. Closed-loop compensation further eliminates residual frequency offset, adapting to rapidly changing channel environments.

[0135] Furthermore, phase compensation employs predistortion correction based on the minimum mean square error criterion, specifically including:

[0136] Construct a joint error function E=γ·(Δε) that includes phase difference and amplitude fluctuation. 2 +δ·(ΔA / A ref ) 2 Where Δε is the measured phase deviation, ΔA is the amplitude fluctuation, and A ref The weighting coefficient γ is set to 80-120% of the average amplitude of the received signal, and the weighting coefficient γ is set to 0.6-0.8 and δ is set to 0.2-0.4.

[0137] The minimum error function is solved using a recursive least squares algorithm to generate a predistortion vector containing both I and Q corrections. During the iterative calculation, the step size parameter μ is constrained to be 0.05–0.15, and the residual convergence threshold is set to 1 × 10⁻⁶. -4 ~5×10 -4 ;

[0138] The pre-distortion correction operation is performed in stages. In the first stage, the full correction vector is applied only to the path with a phase difference Δε exceeding π / 12. In the second stage, 50-70% of the correction vector is used to progressively compensate the remaining path.

[0139] After the calibration operation, the error vector magnitude (EVM) of the pilot symbol is extracted as a verification index. When the measured EVM value is higher than 8%, the calibration vector update module is triggered to recalculate the predistortion parameters with a period of 200~500ms.

[0140] A dynamic adjustment mechanism for correction parameters is established. The weighting coefficients γ and δ are adjusted in reverse according to the bit error rate change trend of three consecutive data sub-blocks. If the bit error rate decrease rate is less than 10% / sub-block, γ is increased by 5% to 10% and δ is reduced by the corresponding ratio.

[0141] Specifically, the joint error function can be defined as E=γ·(Δε) 2 +δ·(ΔA / A ref ) 2 Where Δε is the measured phase deviation, and ΔA is the amplitude fluctuation. Reference amplitude A ref The received signal amplitude can be set to 80%~120%, the weighting coefficient γ can be configured to range from 0.6 to 0.8, and the δ value ranges from 0.2 to 0.4. A digital phase detector can be used to measure the phase deviation Δε, with a range covering -π to π and a resolution of no less than 0.01 radians. The amplitude fluctuation ΔA can be measured based on a logarithmic detector circuit, with a dynamic range covering -30 to 10 dBm.

[0142] The I / Q component input error calculation unit of the received signal generates Δε by comparing it with the reference phase using a phase detector, and ΔA is calculated by the difference between the peak detection circuit and the reference amplitude. The error function calculation is implemented in the DSP chip, and the floating-point unit supports real-time calculation. Reference amplitude A ref The filter window length can be set to 100 sampling points and dynamically updated using a moving average filter. The module should be mounted close to the input interface of the receiver's baseband processing unit to reduce signal transmission delay. FR-4 epoxy resin can be used as the circuit board material, and silver-plated microstrip lines are used for the RF path. A joint error function is used to comprehensively evaluate phase and amplitude distortion, improving the comprehensiveness of the correction parameters.

[0143] The iteration step size parameter μ of the recursive least squares algorithm can be set to 0.05~0.15, and the residual convergence threshold can be configured to 1×10. -4 ~5×10 -4 During algorithm execution, the I / Q components of the predistortion vector are generated through matrix inversion, and the initial value of the covariance matrix can be set to 0.1 times the identity matrix. The iterative calculation module can be integrated into the logic unit of the FPGA, supporting parallel multiplication and addition operations with a calculation cycle of no more than 10μs. The residual monitoring circuit can use a digital comparator with a threshold accuracy of ±0.5%.

[0144] The initial predistortion vector is loaded into a register, and the covariance matrix and weight coefficients are updated after each iteration. The residual calculation result is compared with a threshold; if it falls below the threshold three times consecutively, the iteration terminates and the output vector is locked. The algorithm interrupt signal is transmitted to the control unit through a priority arbitrator to ensure real-time performance. The module should be mounted close to the read / write port of the calibration vector memory to shorten data access time. The circuit heat dissipation design can use a copper-based heat sink with a thermal conductivity of not less than 400 W / m·K. The predistortion parameters are optimized through adaptive iteration to reduce algorithm complexity and computational resource consumption.

[0145] In the phased correction strategy, the first stage can be set to apply a full correction vector to paths with a phase difference Δε exceeding π / 12, and the second stage uses 50%~70% of the correction vector for progressive compensation of the remaining paths. The EVM verification threshold for pilot symbols can be set to 8%. When the measured EVM is higher than this value, the predistortion parameter update cycle can be triggered to 200~500ms. In the dynamic parameter adjustment, the correction step size of the weight coefficient γ can be configured to 5%~10%, and the adjustment direction of δ is opposite to that of γ.

[0146] The phase difference Δε is determined by a comparator circuit to determine if it exceeds the π / 12 threshold, triggering a full-scale correction enable signal. In progressive compensation mode, the correction vector is scaled proportionally by a digitally controlled attenuator. The EVM monitoring unit extracts data through a constellation diagram analyzer, and the results are fed back to the control unit via the I2C bus. The dynamic parameter adjustment logic runs as a background task in the embedded processor, with lower priority than the real-time correction operation. The module should be mounted close to the feedforward correction node of the power amplifier to directly affect the output signal. High-speed board-to-board connectors can be used for the circuit connectors, with signal delay controlled within 1ns. Staged correction balances processing speed and accuracy, and the dynamic adjustment mechanism adapts to long-term changes in channel conditions.

[0147] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and embodiments shown and described herein.

Claims

1. A multi-path cooperative communication method, characterized in that, include: By deploying a channel status monitoring module at the transmitter, the channel status information of at least three independent communication paths within the target area can be obtained in real time. The channel status information includes the current signal strength measurement, frequency offset, and ambient noise power spectral density of each communication path. In the data stream segmentation module, based on a preset priority allocation algorithm, the data stream to be transmitted is divided into N data sub-blocks and dynamically allocated to each communication path. The priority allocation algorithm generates a path quality factor based on the product of the frequency offset output by the channel state monitoring module and the ambient noise power spectral density. When the path quality factor is lower than a preset switching threshold, the load weight of the communication path is reduced by 40-60%. In the power control module, the transmit power of each communication path is dynamically adjusted based on the difference between the real-time measured signal strength and the ambient noise power spectral density. The signal combining module at the receiving end performs time-domain alignment and phase compensation on the data sub-blocks from each communication path. The time-domain alignment adopts a cross-correlation algorithm with a sliding window length of 8~32μs, and the phase compensation adopts a pre-distortion correction based on the minimum mean square error criterion, with a correction angle range of -π / 6~π / 6. A bit error rate monitoring unit is set up in the feedback link. When the bit error rate of three consecutive data sub-blocks exceeds 1×10, the unit will detect the error rate. -4 At that time, the channel status monitoring module is triggered to rescan the target area and update the communication path allocation table.

2. The multi-path cooperative communication method as described in claim 1, characterized in that, The method for calculating the path quality factor includes: normalizing the frequency offset and the ambient noise power spectral density, wherein the normalization coefficient for the frequency offset is 1 / (15kHz), and the normalization coefficient for the ambient noise power spectral density is 1 / (10kHz). -3 W / Hz), generating a dimensionless path quality factor Q=Δf norm ×P noise_norm , where Δf norm P is the normalized frequency offset. noise_norm This represents the normalized environmental noise power spectral density. The priority allocation algorithm includes: dynamically calculating the load weight reduction ratio based on the difference between the path quality factor Q and the switching threshold; when Q is lower than the switching threshold, the load weight reduction ratio is increased by 0.5 × 10⁻⁶ for every 0.5 × 10⁻⁶ decrease. -3 Each unit Q value corresponds to a 10% reduction in weight, with a maximum weight reduction of 60% and a minimum of 40%. During the data sub-block segmentation process, based on the historical bit error rate statistics of the communication path, the delay-sensitive data sub-blocks in the data stream to be transmitted are preferentially allocated to the communication path with a Q value higher than 1.2 times the switching threshold. The length of the delay-sensitive data sub-block is set to 256 bytes to 512 bytes. Add a path assignment identifier field to each data sub-block. This field contains the Q-value verification code of the target communication path and the sequence verification code of the data sub-block. The Q-value verification code is generated by retaining three significant digits of the binary floating-point number of the Q-value. When the load weight of a communication path is reduced, a remapping operation of data sub-blocks is triggered, and the data sub-blocks that have not been transmitted in the original path are redistributed in descending order of Q value to communication paths with a current Q value higher than the switching threshold.

3. The multi-path cooperative communication method as described in claim 1, characterized in that, The power control module dynamically adjusts the transmission power of each communication path based on the difference between the real-time measured signal strength and the ambient noise power spectral density, specifically including: A mapping relationship is established between the transmit power adjustment and the signal strength-noise difference ΔS, where ΔS is defined as the difference between the current signal strength measurement and the ambient noise power spectral density. When ΔS is in the range of -90 to -85 dBm, a 2 dB step adjustment is adopted, and when ΔS is in the range of -85 to -70 dBm, a 0.5 dB step adjustment is adopted. During power adjustment, the instantaneous interference mutation rate of the target communication path is monitored synchronously. When the change in ΔS after two consecutive power increases is less than 20% of the adjustment step size, the sudden interference suppression mode is activated, shortening the transmit power adjustment period from 100ms to 50ms, while increasing the step size to 150% of the original step size. A power adjustment history table is established for each communication path, recording triplet data including timestamp, ΔS value and actual transmit power value. When the fluctuation of ΔS within 300ms exceeds 15dB, the step size correction coefficient for the next adjustment cycle is predicted based on the ΔS gradient values ​​of the last five cycles in the history table. After the power boost operation is executed, the effectiveness of the power adjustment is verified by the bit error rate monitoring unit of the feedback link. If the bit error rate of two consecutive data sub-blocks after the adjustment does not decrease by 30% of the bit error rate before the adjustment, the power boost of the current communication path is stopped and the backup frequency band is switched. A saturation protection mechanism for transmission power adjustment is set up. When the cumulative power increase of a single communication path reaches 25% of the initial transmission power, a cross-path power rebalancing operation is triggered, and the power value exceeding the threshold is proportionally allocated to other communication paths with a Q value higher than 1.5 times the switching threshold.

4. The multi-path cooperative communication method as described in claim 3, characterized in that, The step size correction factor for the next adjustment period is predicted based on the ΔS gradient values ​​of the most recent five periods in the historical record table, specifically including: The gradient values ​​of ΔS over the most recent five periods are processed using a cubic polynomial fitting algorithm to generate a prediction model that includes a time decay factor, which is set at 0.

8. n The weight of historical data decays exponentially, where n represents the interval between the current period and the historical period; Substituting the fitted polynomial coefficients into the gradient change equation ∂G / ∂t=α·G max +β·G min Where α takes values ​​of 0.6 to 0.8, β takes values ​​of 0.2 to 0.4, and G max and G min These represent the absolute values ​​of the maximum and minimum gradients within the five periods, respectively; Based on the equation solution, generate the step size correction coefficient K = 1 + 0.15·sign(∂G / ∂t)·|∂G / ∂t| 0.5 When the K value exceeds the range of 0.7-1.3, it is forcibly limited to the interval endpoint value and the prediction model parameters are reset. After each power adjustment operation is performed, the residual between the actual ΔS change gradient and the predicted gradient is calculated. When the absolute value of the residual exceeds 30% of the predicted value for three consecutive times, the system automatically switches to the moving weighted average prediction mode, which uses 60%, 30%, and 10% weights of the gradient values ​​of the first three periods. Configure the effective duration parameter for the correction coefficient K. When K>1, the effective duration is set to 150~300ms. When K<1, the effective duration is set to 400~600ms. During the effective period, the power rebalancing operation of other communication paths is frozen.

5. The multi-path cooperative communication method as described in claim 1, characterized in that, The temporal alignment employs a cross-correlation algorithm with a sliding window length of 8~32μs, specifically including: Calculate the maximum delay difference Δτ between each communication path at the receiving end, set the basic length of the sliding window to 3 to 5 times Δτ, and constrain it within the range of 8 to 32 μs, where Δτ is calculated by the timestamp difference of data sub-blocks of adjacent paths; During the execution of the cross-correlation algorithm, the number and amplitude of the correlation peaks are monitored in real time. When more than two secondary peaks are detected within a 3dB bandwidth on both sides of the main peak, the sliding window length is extended to 1.2 to 1.8 times the current value, and the extended window length does not exceed 32μs. The window movement step size is dynamically adjusted according to the length of the data sub-block. When the length of the data sub-block is 256~512 bytes, the step size is set to 1 / 8~1 / 4 of the window length. When the length of the data sub-block is 1024~2048 bytes, the step size is reduced to 1 / 16~1 / 12 of the window length. During the window sliding process, Doppler frequency shift pre-correction is performed synchronously. The signal samples within the window are rotated using the carrier frequency offset measurement value. The rotation angle is θ = 2π·Δf·t, where Δf is the frequency offset of the current path and t is the relative time of the sampling points within the window. After each window adjustment, the alignment effect is verified by the bit error rate monitoring unit of the feedback link. If the decrease in bit error rate of three consecutive data sub-blocks after adjustment does not reach 15% of the bit error rate before adjustment, the sliding window parameters are reset and the delay difference Δτ measurement is re-executed.

6. The multi-path cooperative communication method as described in claim 5, characterized in that, During the window sliding process, Doppler frequency shift pre-correction is performed synchronously, and the phase of the signal samples within the window is rotated using the carrier frequency offset measurement value. Specifically, this includes: The rate of change Δf is calculated in real time during the window sliding process. rate =[Δf(t)-Δf(t-Δt)] / Δt, where Δt is the time interval between two consecutive frequency offset measurements, and the phase rotation angle is corrected to θ=2π×(Δf+Δf rate ×t)×t; Set phase rotation angle constraint conditions. When the calculated absolute value of θ exceeds π / 3, enable the angle limiter to limit θ to the range of -π / 3 to π / 3, and trigger the calibration signal generator of the frequency offset measurement module to output a test tone signal of 1 to 5 kHz. Residual frequency offset compensation is performed after the phase rotation operation. The compensation factor C = 1 - (EVM) is calculated based on the constellation diagram divergence of the rotated signal. measured / EVM threshold ), of which EVM measured EVM represents the measured error vector magnitude. threshold Set to 8~12%, the compensation factor is applied to the Δf measurement value in the subsequent window to form a closed-loop correction; A segmented correction strategy is adopted. When the fluctuation amplitude of Δf exceeds ±2kHz for three consecutive measurement cycles, the dense correction mode is activated, which increases the execution interval of phase rotation operation from once per window to once per sampling point, while shortening Δt to 20-30% of the original value. After each window slide, the correction effect is verified by comparing the mean change of θ between adjacent windows. If the residual carrier frequency offset after correction is still greater than 10% of Δf, the extended Kalman filter algorithm is automatically switched to re-estimate the Δf value, and the new estimate is written to the frequency calibration field of the path allocation table.

7. The multi-path cooperative communication method as described in claim 1, characterized in that, Phase compensation employs pre-distortion correction based on the minimum mean square error criterion, specifically including: Construct a joint error function E=γ·(Δε) that includes phase difference and amplitude fluctuation. 2 +δ·(ΔA / A ref ) 2 Where Δε is the measured phase deviation, ΔA is the amplitude fluctuation, and A ref The weighting coefficient γ is set to 80-120% of the average amplitude of the received signal, and the weighting coefficient γ is set to 0.6-0.8 and δ is set to 0.2-0.

4. The minimum error function is solved using a recursive least squares algorithm to generate a predistortion vector containing both I and Q corrections. During the iterative calculation, the step size parameter μ is constrained to be 0.05–0.15, and the residual convergence threshold is set to 1 × 10⁻⁶. -4 ~5×10 -4 ; The pre-distortion correction operation is performed in stages. In the first stage, the full correction vector is applied only to the path with a phase difference Δε exceeding π / 12. In the second stage, 50-70% of the correction vector is used to progressively compensate the remaining path. After the calibration operation, the error vector magnitude (EVM) of the pilot symbol is extracted as a verification index. When the measured EVM value is higher than 8%, the calibration vector update module is triggered to recalculate the predistortion parameters with a period of 200~500ms. A dynamic adjustment mechanism for correction parameters is established. The weighting coefficients γ and δ are adjusted in reverse according to the bit error rate change trend of three consecutive data sub-blocks. If the bit error rate decrease rate is less than 10% / sub-block, γ is increased by 5% to 10% and δ is reduced by the corresponding ratio.