Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a plurality of first pixel columns and a plurality of second pixel columns which are alternately arranged in the first direction, each first pixel column comprises a plurality of first pixels and a plurality of second pixels which are alternately arranged in the second direction, and each second pixel column comprises a plurality of third pixels which are arranged in the second direction; the data signal lines are arranged in the first direction and extend in the second direction, and the data signal lines comprise the first data signal line and the last data signal line; the first data signal line, the second data signal line and the third data signal line are located between the first data signal line and the last data signal line and arranged in the first direction. The fan-out lines are arranged in the first direction; in the first direction, the front n data signal lines and the rear n data signal lines are correspondingly connected with the fan-out lines through the connecting lines, and the performance of the display panel can be improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat-panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, power saving, thin body, and wide range of applications, becoming the mainstream display device.

[0003] However, the display performance of current OLED display products needs to be improved. Summary of the Invention

[0004] The present invention provides a display panel and a display device to improve the performance of the display panel.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, including a display area and a non-display area; the display panel further includes:

[0006] A plurality of first pixel columns and a plurality of second pixel columns alternately arranged along a first direction are located in a display area, the first pixel columns including a plurality of first pixels and a plurality of second pixels alternately arranged along a second direction, and the second pixel columns including a plurality of third pixels arranged along the second direction; the first pixels, the second pixels, and the third pixels emit light of different colors;

[0007] a plurality of data signal lines arranged along a first direction and extending along a second direction, the plurality of data signal lines including a first data signal line, a last data signal line, and a first data signal line, a second data signal line, and a third data signal line located between the first data signal line and the last data signal line and arranged along the first direction; the first data signal line being connected to a first pixel in a first first pixel column, each first data signal line being connected to a first pixel in two adjacent first pixel columns, each second data signal line being connected to a second pixel in two adjacent first pixel columns; each third data signal line being connected to a third pixel in a second pixel column; the last data signal line being connected to a first pixel in a first first pixel column; or the last data signal line being connected to a second pixel in the first first pixel column;

[0008] Multiple connection lines, located in the display area;

[0009] Multiple fan-out lines arranged along a first direction are located in a non-display area; along the first direction, the first n and last n data signal lines are connected to the fan-out lines correspondingly through connecting lines, wherein the first direction intersects with the second direction, and n is an integer greater than or equal to 1.

[0010] Optionally, the connecting line includes a first connecting line and a second connecting line, the second connecting line extends along the second direction; the second connecting line is connected to the fan-out line, and the second connecting line is connected to the data signal line via the first connecting line;

[0011] Optionally, among a portion of the data signal lines, among three adjacent data signal lines, a second connecting line is provided between two data signal lines located on one side and in the middle, and no second connecting line is provided between two data signal lines located on the other side and in the middle;

[0012] Optionally, among a portion of the data signal lines, one or two second connection lines are provided between two data signal lines located on one side and in the middle of three adjacent data signal lines.

[0013] Optionally, along the first direction, the first connection lines correspondingly connected to the first data signal line to the nth data signal line are first to nth first-side first connection lines in sequence, and the lengths of the first to nth first-side first connection lines decrease in sequence; and / or,

[0014] Along the first direction, the first connection lines corresponding to the last data signal line to the M-n+1th data signal line are sequentially connected to the first to nth second-side first connection lines, and the lengths of the first to nth second-side first connection lines decrease sequentially; wherein n is an integer greater than or equal to 2, M is the number of data signal lines, and M is an integer greater than 2n;

[0015] Optionally, the length of the j-th second-side first connecting line is less than the length of the j-th first-side first connecting line, where j is an integer greater than or equal to 1 and less than or equal to n;

[0016] Optionally, the first connecting line extends along a first direction;

[0017] Optionally, the number of data signal lines overlapping with the j-th second-side first connection line is less than the number of data signal lines overlapping with the j-th first-side first connection line;

[0018] Optionally, the j-th second-side first connecting line and the j-th first-side first connecting line are located on the same straight line extending along the first direction.

[0019] Optionally, the display panel further includes n first compensation lines, and the first compensation lines are correspondingly connected to the first connecting lines on the second side;

[0020] Optionally, the first compensation line extends along the first direction;

[0021] Optionally, the first compensation line and the first connecting line on the second side are arranged in the same layer.

[0022] Optionally, along the first direction, the sum of the length of the i-th second-side first connecting line and the length of the first compensation line connected to the i-th second-side first connecting line is equal to the length of the i-th first-side first connecting line, where i is an integer greater than or equal to 1 and less than or equal to n;

[0023] Optionally, the first compensation line connected to the i-th second-side first connection line is located on a side of the i-th second-side first connection line away from the data signal line connected to the i-th second-side first connection line;

[0024] Optionally, i is equal to j.

[0025] Optionally, the display panel further includes n second compensation lines, and along the first direction, each second compensation line and the first connecting lines located on both sides of the second compensation line are located on the same straight line, and the second compensation line is insulated from the first connecting lines;

[0026] Optionally, the second compensation line and the first connection line are provided in the same layer;

[0027] Optionally, a first break is formed between the second compensation line and the first connecting line on the first side, a second break is formed between the second compensation line and the first compensation line, or a second break is formed between the second compensation line and the first connecting line on the second side;

[0028] Optionally, along the third direction, the plurality of first fractures are arranged at equal intervals; any two of the third direction, the first direction, and the second direction intersect;

[0029] Optionally, along the fourth direction, the plurality of second fractures are arranged at equal intervals; any two of the fourth direction, the third direction, the first direction, and the second direction intersect;

[0030] Optionally, the distance between adjacent first fractures is equal to the distance between adjacent second fractures;

[0031] Optionally, the second compensation line is connected to a DC potential or a power supply voltage.

[0032] Optionally, along the first direction, the second connection lines correspondingly connected to the first data signal line to the nth data signal line are sequentially the first to nth first-side second connection lines, and the lengths of the first to nth first-side second connection lines decrease sequentially; and / or,

[0033] Along the first direction, the second connection lines corresponding to the last data signal line to the M-n+1th data signal line are sequentially the first to the nth second-side second connection lines, and the lengths of the first to the nth second-side second connection lines decrease sequentially;

[0034] Optionally, the first-side second connecting line is arranged on a side of the nth data signal line away from the (n-1)th data signal line;

[0035] Optionally, the second connecting line on the second side is arranged on a side of the M-n+1th data signal line close to the Mnth data signal line;

[0036] Optionally, the length of the p-th second-side second connecting line is equal to the length of the p-th first-side second connecting line, where p is an integer greater than or equal to 1 and less than or equal to n.

[0037] Optionally, the display panel further includes n third compensation lines, and the third compensation lines are correspondingly connected to the second connecting lines on the second side;

[0038] Optionally, the third compensation line extends along the second direction;

[0039] Optionally, the third compensation line and the second connection line on the second side are provided in the same layer.

[0040] Optionally, the sum of the length of the qth second-side second connecting line, the length of the corresponding third compensation line connected thereto, and the length of the qth first-side first connecting line is greater than the sum of the length of the qth second-side first connecting line and the length of the qth first-side first connecting line, where q is an integer greater than or equal to 1 and less than or equal to n;

[0041] Optionally, the third compensation line is located on a side of the second connecting line connected to the third compensation line that is away from the fan-out line;

[0042] Optionally, p is equal to q;

[0043] Optionally, the first connection line and the second connection line are provided in different layers; optionally, the second connection line and the data signal line are provided in the same layer.

[0044] Optionally, the display panel further includes n first-side fourth compensation lines; along the second direction, each first-side fourth compensation line and a first-side second connecting line are located on the same straight line, and the first-side fourth compensation line is insulated from the first-side second connecting line;

[0045] Optionally, a third break is provided between the fourth compensation line on the first side and the second connection line on the first side; optionally, the fourth compensation line on the first side and the second connection line are provided on the same layer; optionally, the fourth compensation line on the first side is connected to a DC potential or a power supply voltage;

[0046] Optionally, the display panel further includes n second-side fourth compensation lines; along the second direction, each second-side fourth compensation line and a second-side second connecting line are located on the same straight line, and the second-side fourth compensation line is insulated from the second-side second connecting line;

[0047] Optionally, there is a fourth break between the fourth compensation line on the second side and the second connecting line on the second side; optionally, the fourth compensation line on the second side and the second connecting line are arranged on the same layer; optionally, the fourth compensation line on the second side is connected to a DC potential or a power supply voltage.

[0048] Optionally, the display panel further includes a first routing line extending along the second direction; along the first direction, the first routing line is arranged on a side of the Mth data signal line away from the M-1th data signal line; wherein M is the number of data signal lines.

[0049] Optionally, the display panel further includes a plurality of second routing lines, the second routing lines extending along the second direction, and among the first n data signal lines, a second routing line is provided between two data signal lines located on one side and in the middle of three adjacent data signal lines, and no second routing line is provided between two data signal lines located on the other side and in the middle;

[0050] Among the last n data signal lines, among the three adjacent data signal lines, a second routing line is provided between the two data signal lines located on one side and in the middle, and no second routing line is provided between the two data signal lines located on the other side and in the middle; along the first direction, a second routing line is provided between the first data signal line and the second data signal line; along the first direction, no second routing line is provided between the Mth data signal line and the M-1th data signal line;

[0051] The Mth data signal line and the M-1th data signal line are symmetrically arranged about a first axis along the second direction, and the first routing line and a second routing line adjacent to the first routing line are symmetrically arranged about the first axis; optionally, the first routing line, the second routing line, and the data signal line are arranged on the same layer; optionally, the first routing line is connected to a DC potential or a power supply voltage, and the second routing line is connected to a DC potential or a power supply voltage;

[0052] Optionally, the first data signal line is used to transmit data signals corresponding to K1 pixels; the last data signal line is used to transmit data signals corresponding to K1 pixels, and each of at least a portion of the data signal lines located between the first data signal line and the last data signal line is used to transmit data signals corresponding to K2 pixels; K1 and K2 are different positive integers;

[0053] Optionally, K2 is greater than K1. Optionally, K2 is greater than or equal to twice K1.

[0054] Optionally, the display panel further includes:

[0055] substrate;

[0056] A first conductive layer is provided on one side of the substrate, and the first conductive layer includes a first connecting line;

[0057] A second conductive layer is provided on a side of the first conductive layer away from the substrate, the second conductive layer comprising a data signal line; the first connecting line is connected to the data signal line through a first via hole;

[0058] Optionally, the second conductive layer further includes a second connecting line, the data signal line and the second connecting line are spaced apart; the second connecting line is connected to the first connecting line through a second via hole;

[0059] The spacing in the first direction between the first via hole and the second via hole corresponding to the first connection line connected to the first data signal line is greater than the spacing in the first direction between the first via hole and the second via hole corresponding to the first connection line connected to the last data signal line;

[0060] Optionally, the first conductive layer and / or the second conductive layer includes a first sublayer, a second sublayer and a third sublayer stacked in sequence, the material of the first sublayer includes titanium, the material of the second sublayer includes aluminum, and the material of the third sublayer includes titanium.

[0061] Optionally, the display panel further includes:

[0062] a third conductive layer, disposed between the substrate and the first conductive layer;

[0063] a fourth conductive layer, disposed between the third conductive layer and the first conductive layer, wherein the fan-out line is disposed in the third conductive layer and / or the fourth conductive layer;

[0064] Optionally, along the first direction, two adjacent fan-out lines are respectively arranged in the third conductive layer and the fourth conductive layer.

[0065] Optionally, except for the first n and last n data signal lines, the remaining data signal lines are correspondingly connected to the remaining fan-out lines, where n is greater than 0 and is a multiple of 4.

[0066] Optionally, the display panel further includes a plurality of columns of pixel circuits arranged along the first direction, and each column of pixel circuits includes a plurality of pixel circuits arranged along the second direction;

[0067] Each data signal line is connected to a corresponding column of pixel circuits; the first column of pixel circuits is connected to the first pixel in the first column of the first pixel column, and each column of pixel circuits in the remaining odd-numbered columns is connected to the first pixel in two adjacent columns of the first pixel column, or each column of pixel circuits in the remaining odd-numbered columns is connected to the second pixel in two adjacent columns of the first pixel column; the even-numbered column of pixel circuits is connected to the third pixel in the second pixel column, and the last column of pixel circuits is connected to the first pixel in the last column of the first pixel column, or the last column of pixel circuits is connected to the second pixel in the last column of the first pixel column;

[0068] Alternatively, each column of pixels is connected to the same column of pixel circuits, and the multiple data signal lines include a first data signal line, a last data signal line, and a first data signal line, a second data signal line, and a third data signal line located between the first data signal line and the last data signal line and arranged along the first direction; along the first direction, the first data signal line is connected to the pixel circuit corresponding to the first pixel in the first column of the first pixel column, and each first data signal line is connected to the pixel circuit corresponding to the first pixel in two adjacent columns of the first pixel column; each second data signal line is connected to the pixel circuit corresponding to the second pixel in two adjacent columns of the first pixel column; each third data signal line is connected to the pixel circuit corresponding to the third pixel in a column of the second pixel column; the last data signal line is connected to the pixel circuit corresponding to the first pixel in the last column of the first pixel column, or the last data signal line is connected to the pixel circuit corresponding to the second pixel in the last column of the first pixel column; optionally, the pixel circuits connected to two adjacent columns of the first pixel column are connected to three data signal lines; optionally, the structures of the pixel circuits of two adjacent columns of the first pixel column are symmetrical along the first direction.

[0069] In a second aspect, an embodiment of the present invention further provides a display panel, including a display area and a non-display area; the display panel further includes:

[0070] N pixel columns are located in the display area, the N pixel columns are arranged along a first direction, and the pixel columns include a plurality of pixels arranged along a second direction; N is an integer greater than 1; the N pixel columns include pixels of multiple luminous colors;

[0071] M data signal lines are arranged along a first direction and extend along a second direction, the M data signal lines being used to transmit data signals corresponding to pixels in N columns of pixels; a single data signal line is used to transmit data signals corresponding to pixels of a single luminous color; M is an integer greater than N; the M data signal lines include a first edge data signal line and a second edge data signal line located on outermost sides, the first edge data signal line and the second edge data signal line being located on opposite sides of the display area along the first direction;

[0072] a plurality of connecting lines, at least a portion of the connecting lines being located in the display area, and the first edge data signal line and the second edge data signal line being connected to different connecting lines;

[0073] A plurality of fan-out lines are located in the non-display area; the first edge data signal line and the second edge data signal line are connected to the corresponding fan-out lines via corresponding connection lines.

[0074] Optionally, M is 1 greater than N;

[0075] Optionally, the display panel further includes M columns of pixel circuit columns arranged along the first direction, each column of pixel circuit columns includes a plurality of pixel circuits arranged along the second direction, the M columns of pixel circuit columns are connected to the M data signal lines, and the M columns of pixel circuit columns are connected to the N columns of pixel columns;

[0076] Optionally, the first edge data signal line is used to transmit data signals corresponding to K1 pixels; the second edge data signal line is used to transmit data signals corresponding to K1 pixels; each of at least a portion of the data signal lines located between the first edge data signal line and the second edge data signal line is used to transmit data signals corresponding to K2 pixels, where K1 and K2 are different positive integers.

[0077] Optionally, K2 is greater than K1. Optionally, K2 is greater than or equal to twice K1.

[0078] Optionally, the N pixel columns include a plurality of first pixel columns and a plurality of second pixel columns alternately arranged along a first direction, the first pixel column includes a plurality of first pixels and a plurality of second pixels alternately arranged along a second direction, and the second pixel column includes a plurality of third pixels arranged along the second direction; the first pixels, the second pixels, and the third pixels emit light of different colors;

[0079] Each data signal line is connected to a corresponding column of pixel circuits; the first column of pixel circuits is connected to the first pixel in the first column of the first pixel column, and each column of pixel circuits in the remaining odd-numbered columns is connected to the first pixel in two adjacent columns of the first pixel column, or each column of pixel circuits in the remaining odd-numbered columns is connected to the second pixel in two adjacent columns of the first pixel column; the even-numbered column of pixel circuits is connected to the third pixel in the second pixel column, and the last column of pixel circuits is connected to the first pixel in the last column of the first pixel column, or the last column of pixel circuits is connected to the second pixel in the last column of the first pixel column;

[0080] Alternatively, each column of pixels is connected to the same column of pixel circuits; the multiple data signal lines include a first data signal line, a last data signal line, and a first data signal line, a second data signal line, and a third data signal line located between the first data signal line and the last data signal line and arranged along the first direction; the first data signal line is connected to a pixel circuit connected to a first pixel in a first column of first pixel columns, each first data signal line is connected to a pixel circuit connected to a first pixel in two adjacent columns of first pixel columns; each second data signal line is connected to a pixel circuit connected to a second pixel in two adjacent columns of first pixel columns; the third data signal line is connected to a pixel circuit connected to a third pixel in a first column of second pixel columns; and the last data signal line is connected to a pixel circuit connected to a first pixel or a second pixel in a last column of first pixel columns;

[0081] Optionally, the pixel circuits connected to two adjacent first pixel columns are connected to three data signal lines;

[0082] Optionally, along the first direction, the structures of two adjacent columns of pixel circuits are symmetrical.

[0083] In a third aspect, an embodiment of the present invention further provides a display device, comprising the display panel described in the first and second aspects.

[0084] According to the technical solution of the embodiment of the present invention, each data signal line is connected to a pixel of the same color, which can reduce the voltage jump on the data signal line, thereby reducing the power consumption of the driver chip. At the same time, the first n and last n data signal lines are connected to the fan-out lines via connecting lines, so that the data signal lines on both sides of the display panel along the first direction can be connected to the fan-out lines via the connecting lines of the display area, which can reduce the space occupied by the fan-out lines along the first direction, not only helping to reduce the frame, but also reducing the width of the fan-out area along the second direction, further reducing the frame of the display panel. By connecting the last data signal line to the fan-out line via the connecting line of the display area, rather than directly connecting the last data signal line to the fan-out line, the display effect can be improved and the risk of display split-screen problems can be reduced. And / or, by setting the value of n, the demand of the display panel for the driver chip can be met, thereby avoiding additional updates to the driver chip when the number of data signal lines changes, thereby reducing the production cost of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] Figure 1 A schematic diagram of the principle structure of a display panel provided by an embodiment of the present invention;

[0086] Figure 2 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0087] Figure 3 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0088] Figure 4 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0089] Figure 5 A schematic diagram of a portion of the structure of another display panel provided by an embodiment of the present invention;

[0090] Figure 6 for Figure 2 A schematic diagram of a partial enlarged structure of the display panel at the dotted box A is provided;

[0091] Figure 7 for Figure 2 A schematic diagram of a partial enlarged structure of the display panel at the dotted box B is provided;

[0092] Figure 8 for Figure 4 A schematic diagram of a partial enlarged structure of the display panel at the dotted box C is provided;

[0093] Figure 9 for Figure 4 A schematic diagram of a partial enlarged structure of the display panel at the dotted box E is provided;

[0094] Figure 10 for Figure 6 A partial enlarged schematic diagram of the middle dotted box A1;

[0095] Figure 11 for Figure 7 A partial enlarged schematic diagram of the middle dotted box A2;

[0096] Figure 12 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0097] Figure 13 for Figure 12 A partial enlarged schematic diagram of the display panel at the dotted box F is provided;

[0098] Figure 14 for Figure 12 A partial enlarged schematic diagram of the display panel at the dotted box G is provided;

[0099] Figure 15 for Figure 13 A partial enlarged schematic diagram of the middle dotted box A4;

[0100] Figure 16 for Figure 14 A partial enlarged schematic diagram of the middle dotted box A3;

[0101] Figure 17 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0102] Figure 18 for Figure 17 A partial enlarged schematic diagram of the display panel at the dotted frame H is provided;

[0103] Figure 19 for Figure 17 A partial enlarged schematic diagram of the display panel at the dotted frame I is provided;

[0104] Figure 20 for Figure 18 A partial enlarged schematic diagram of the middle dotted box A5;

[0105] Figure 21 for Figure 19 A partial enlarged schematic diagram of the middle dotted box A6;

[0106] Figure 22 for Figure 2 Another schematic diagram of the partial structure of the display panel at the dotted box B is provided;

[0107] Figure 23a A schematic diagram of a portion of the structure of another display panel provided by an embodiment of the present invention;

[0108] Figure 23b A schematic diagram of a portion of the structure of another display panel provided by an embodiment of the present invention;

[0109] Figure 24 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0110] Figure 25 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0111] Figure 26 for Figure 4 A schematic diagram of a cross-sectional structure of a display panel provided along section OO';

[0112] Figure 27 for Figure 4 A schematic diagram of a cross-sectional structure of a display panel provided along section SS';

[0113] Figure 28 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0114] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0115] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way are interchangeable where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. Connections may include direct connections or indirect connections.

[0116] Figure 1 A schematic diagram of the principle structure of a display panel provided by an embodiment of the present invention is provided. Figure 2 Schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Figure 1 and Figure 2 As shown, the display panel includes a display area AA and a non-display area NAA, and the display panel also includes:

[0117] A plurality of first pixel columns 110 and a plurality of second pixel columns 120 are alternately arranged along a first direction X and are located in the display area AA. The first pixel columns 110 include a plurality of first pixels P1 and a plurality of second pixels P2 alternately arranged along a second direction Y. The second pixel columns 120 include a plurality of third pixels P3 arranged along the second direction Y. The first pixels P1, the second pixels P2, and the third pixels P3 emit different luminous colors.

[0118] A plurality of data signal lines DATA arranged along the first direction X and extending along the second direction Y, the data signal lines DATA including a first data signal line DATA_1, a last data signal line DATA_M, and a first data signal line DATA1, a second data signal line DATA2, and a third data signal line DATA3 located between the first data signal line DATA_1 and the last data signal line DATA_M and arranged along the first direction X; the first first data signal line DATA_1 is connected to the first pixel P1 in the first first pixel column 110, and each first data signal line DATA1 is connected to two adjacent first pixels The first pixel P1 in the column 110 is connected, each second data signal line DATA2 is connected to the second pixel P2 in two adjacent first pixel columns 110; each third data signal line DATA3 is connected to the third pixel P3 in a column of second pixel columns 120; the last data signal line DATA_M is connected to the first pixel P1 in the last first pixel column 110 (for example, the total number of pixel columns is not an integer multiple of 4), or, the last data signal line DATA_M is connected to the second pixel P2 in the last first pixel column 110 (for example, the total number of pixel columns is an integer multiple of 4); for example, the total number of pixel columns can be an integer multiple of 2.

[0119] A plurality of connection lines 130 are located in the display area AA;

[0120] A plurality of fan-out lines 140 arranged along a first direction X are located in the non-display area NAA; along the first direction X, the first n and the last n data signal lines DATA are correspondingly connected to the fan-out lines 140 through the connecting lines 130 (e.g., one-to-one connection); wherein the first direction X intersects with the second direction Y, for example, perpendicularly, and n is an integer greater than or equal to 1.

[0121] Specifically, such as Figure 1As shown, the display panel includes pixels arranged in an array. The first direction X can be the row direction of the pixel arrangement, and the second direction Y can be the column direction of the pixel arrangement. The first pixel column 110 and the second pixel column 120 are arranged alternately along the first direction X. At the same time, the first pixel P1 and the second pixel P2 in the first pixel column 110 are arranged alternately. Along the first direction X, the first pixel P1, the third pixel P3, the second pixel P2, and the third pixel P3 form a minimum pixel arrangement repeating unit. Along the second direction Y, the first pixel P1 and the second pixel P2 form a minimum pixel arrangement repeating unit. At this time, along the first direction X, the first pixel P1 and the third pixel P3 of two adjacent columns or the second pixel P2 and the third pixel P3 of two adjacent columns can form a pixel light-emitting unit. Adjacent pixel light-emitting units can share the first pixel P1 or the second pixel P3 to achieve color display on the display panel. Pixels of different colors in the same pixel light-emitting unit are connected to different data signal lines DATA, that is, pixels in the same pixel light-emitting unit are connected to two data signal lines DATA. Along the first direction X, two data signal lines DATA correspondingly connected to pixels in the same pixel light emitting unit are arranged on both sides of the pixel light emitting unit to achieve a back-to-back arrangement.

[0122] like Figure 1 and Figure 2 As shown, each data signal line DATA extends along the second direction Y and is used to connect pixels of the same color in at least one pixel column, so that each data signal line DATA can provide data signals for pixels of the same color. Compared to the technical solution in which the same data signal line DATA provides data signals for pixels of different colors, the voltage jump on the data signal line DATA can be reduced, thereby reducing the power consumption of the driver chip. For example, when the first pixel column 110 is located in an odd column and the second pixel column 120 is located in an even column, along the first direction X, multiple pixels are arranged according to an arrangement in which the minimum repeating unit is a first pixel P1, a third pixel P3, a second pixel P2, and a third pixel P3. In this case, the multiple data signal lines DATA can be arranged according to an arrangement in which the minimum repeating unit is a first data signal line DATA1, a third data signal line DATA3, a second data signal line DATA2, and a third data signal line DATA3. For example, the first pixel P1, the third pixel P3, the second pixel P2, and the third pixel P3 are arranged in a cyclic manner along the first direction X. For example, the first data signal line DATA1 , the third data signal line DATA3 , the second data signal line DATA2 and the third data signal line DATA3 are sequentially arranged along the first direction X in a cyclic manner.

[0123] The first data signal line DATA_1 is connected only to the first pixel P1 in the first first pixel column 110 (i.e., the first pixel P1 in the first column of pixels). The number of pixels connected to the first pixel P1 is half the number of pixels in a column, or less than half the number of pixels in a column in the middle region. The first first data signal line DATA_1 is connected to the first pixel P1 in the second first pixel column 110 (i.e., the first pixel P1 in the third column of pixels) and the first pixel P1 in the third first pixel column 110 (i.e., the first pixel P1 in the fifth column of pixels). The second first data signal line DATA1 is connected to the first pixel P1 in the fourth first pixel column 110 (i.e., the first pixel P1 in the seventh column of pixels) and the first pixel P1 in the fifth first pixel column 110 (i.e., the first pixel P1 in the ninth column of pixels). This is analogous to the case. From the first first data signal line DATA1 to the last first data signal line DATA1, the number of pixels connected to the first pixel P1 is half the number of pixels in a column, or less than half the number of pixels in a column in the middle region.

[0124] The first second data signal line DATA2 is connected to the second pixel P2 in the first first pixel column 110 (i.e., the second pixel P2 in the first column) and the second pixel P2 in the second first pixel column 110 (i.e., the second pixel P2 in the third column). The second second data signal line DATA2 is connected to the second pixel P2 in the third first pixel column 110 (i.e., the second pixel P2 in the fifth column) and the second pixel P2 in the fourth first pixel column 110 (i.e., the second pixel P2 in the seventh column), and so on. The number of pixels connected from the first second data signal line DATA2 to the last second data signal line DATA2 is equal to the number of pixels in one column. Meanwhile, each third data signal line DATA3 is connected to the third pixel P3 in a second pixel column 120. This ensures that the first data signal line DATA1 provides a data signal only to the first pixel P1, the second data signal line DATA2 provides a data signal only to the second pixel P2, and the third data signal line DATA3 provides a data signal only to the third pixel P3. This reduces voltage jumps on the data signal lines DATA, thereby reducing power consumption of the driver chip. Compared to the prior art solution in which one data signal line is connected to one column of pixels, the solution provided by the present application requires an additional data signal line DATA. For example, when the resolution of the display panel is 1080, the number of data signal lines DATA required by the present application is 1080×2+1=2161.

[0125] The display panel also includes a driver chip for providing a drive signal for the display panel. The driver chip can be arranged in the non-display area NAA. The non-display area NAA also includes a fan-out line 140, and the driver chip can be connected to the display area AA through the fan-out line 140, and connected to the data signal lines DATA on both sides of the first direction X through the connecting line 130 in the display area AA. When the display panel has an R angle (that is, an arc angle), it is possible to avoid the fan-out line 140 occupying the non-display area NAA of the R angle and connecting to the data signal line DATA, thereby reducing the space occupied by the fan-out line 140 along the first direction X, which is not only conducive to reducing the frame at the R angle, but also can reduce the width of the non-display area NAA where the fan-out line 140 is located along the first direction X, that is, reduce the width of the fan-out area along the first direction X, thereby reducing the width of the fan-out area along the second direction Y, further reducing the frame of the display panel.

[0126] In addition, the first n and last n data signal lines DATA are connected to the fan-out lines 140 via connecting lines 130. When the number of data signal lines DATA changes relative to the number of data signal lines in the prior art, the last n data signal lines DATA can be connected to the fan-out lines 140 via connecting lines 130, thereby preventing the last n data signal lines DATA from being directly connected to the fan-out lines 140 through the non-display area NAA. For example, when the display panel includes an R angle, and the number of data signal lines DATA is increased by one relative to the prior art, n is an integer greater than or equal to 1. This prevents the last data signal line DATA from being connected to the fan-out lines 140 via the R angle, thereby reducing the space occupied by the fan-out lines 140 along the first direction X. When n is greater than or equal to 2, the second-to-last data signal line DATA is also connected to the fan-out lines 140 via connecting lines 130, thereby minimizing the load difference between the last data signal line DATA and the adjacent data signal lines DATA. This can improve the split screen phenomenon of the display panel at the last two data signal lines DATA, thereby enhancing the display effect of the display panel. For example, when the resolution of the display panel is 1080, the number of data signal lines DATA is 1080×2+1=2161. When n is 400, along the first direction X, the first to 400th data signal lines DATA are connected to the fan-out lines 140 in a one-to-one correspondence through the connection lines 130, and the 1762nd to 2161st data signal lines DATA are connected to the fan-out lines 140 in a one-to-one correspondence through the connection lines 130.

[0127] Furthermore, by setting the value of n, the display panel's requirements for the driver chip can be met, thereby avoiding additional driver chip updates when the number of data signal lines DATA changes, reducing the display panel's manufacturing costs. Furthermore, the driver chip can support odd and even numbers of data signal lines DATA after removing the first n and last n data signal lines. This ensures that the driver chip can properly provide drive signals to all data signal lines DATA when the data signal lines DATA change, thus ensuring the normal operation of the display panel.

[0128] In the technical solution of this embodiment, each data signal line is connected to a pixel of the same color, which can reduce the voltage jump on the data signal line, thereby reducing the power consumption of the driver chip. At the same time, the first n and last n data signal lines are connected to the fan-out lines via connecting lines, so that the data signal lines on both sides of the display panel along the first direction can be connected to the fan-out lines via the connecting lines of the display area, which can reduce the space occupied by the fan-out lines along the first direction. This is not only conducive to reducing the border at the R corner, but also can reduce the width of the fan-out area along the second direction, further reducing the border of the display panel. By connecting the last data signal line to the fan-out line via the connecting line of the display area, rather than directly connecting the last data signal line to the fan-out line, the display effect can be improved and the risk of display split-screen problems can be reduced. Moreover, by setting the value of n, the demand of the display panel for the driver chip can be met, thereby avoiding additional updates to the driver chip when the number of data signal lines changes, reducing the production cost of the display panel.

[0129] Continue to refer Figure 2 The connection lines 130 include a first connection line 131 and a second connection line 132. For example, the first connection line 131 extends along a first direction X, and / or the second connection line 132 extends along a second direction Y. The second connection line 132 is connected to the fan-out line 140, and the second connection line 132 is connected to the data signal line DATA via the first connection line 131.

[0130] Specifically, the first connection line 131 can be arranged on a different layer from the data signal line DATA to avoid short circuits between the first connection line 131 and the data signal line DATA connected to other first connection lines 131, thereby ensuring normal display of the display panel. The first connection line 131 and the second connection line 132 extend in different directions. This allows the data signal lines DATA on both sides of the display area AA of the display panel along the first direction X to approach the middle area of ​​the display area AA through the first connection line 131, and then extend to the boundary between the display area AA and the non-display area NAA through the second connection line 132. As a result, the data signal lines DATA on both sides of the display area AA of the display panel along the first direction X can be connected to the fan-out line 140 near the middle area, reducing the extension length of the fan-out line 140 along the first direction X, thereby reducing the required length of the fan-out line 140 along the second direction Y, which is beneficial to reducing the bottom frame of the display panel. When the display panel includes an R angle, the frame at the R angle can also be reduced.

[0131] Figure 3 A partial structural diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 2 and Figure 3 As shown, among a portion of the data signal lines DATA, among three adjacent data signal lines DATA, a second connection line 132 is set between the two data signal lines DATA located on one side and in the middle, and no second connection line 132 is set between the two data signal lines DATA located on the other side and in the middle.

[0132] Specifically, such as Figure 2 As shown, when the first n data signal lines DATA and the last n data signal lines DATA of the display panel are connected to the fan-out lines 140 via the connecting lines 130, the first n data signal lines DATA require n connecting lines 130 to be connected to the fan-out lines 140, and the last n data signal lines DATA require n connecting lines 130 to be connected to the fan-out lines 140. In this case, n second connecting lines 132 can be arranged along the first direction X on a side of the n-th data signal line DATA away from the (n-1)-th data signal line DATA, and n second connecting lines 132 can be arranged along the first direction X on a side of the (M-n+1)-th data signal line DATA close to the (Mn)-th data signal line DATA. This allows the data signal lines DATA on both sides of the display area AA of the display panel along the first direction X to be connected to the fan-out lines 140 near the middle area, which helps to reduce the bottom bezel of the display panel.

[0133] Moreover, if Figure 3As shown, the display panel further includes pixel circuit columns 150 arranged along a first direction X. The rth odd-numbered pixel circuit column 151 and the rth even-numbered pixel circuit column 152 are arranged back-to-back, such that the data signal line DATA adjacent to the rth odd-numbered pixel circuit column 151 is adjacent to the data signal line DATA adjacent to the rth even-numbered pixel circuit column 152, and a pixel circuit column 150 is arranged between the data signal line DATA adjacent to the rth even-numbered pixel circuit column 152 and the data signal line DATA adjacent to the r+1th odd-numbered pixel circuit column 151. In this case, a second connection line 132 can be provided between the adjacent data signal lines DATA, while no second connection line 132 is provided between the data signal lines DATA arranged between the pixel circuit columns 150. This allows full utilization of the space between two adjacent data signal lines DATA for arranging the second connection line 132, preventing the second connection line 132 from occupying the layout space of the pixel circuit columns 150, thereby ensuring the pixel density of the display panel.

[0134] For example, among a portion of the data signal lines DATA, a second connection line 132 is provided between two data signal lines DATA located on one side and in the middle of three adjacent data signal lines DATA, and a first power line is provided between two data signal lines DATA located on the other side and in the middle. For example, the first power line can transmit a first power supply voltage VDD. Among at least a portion of the first power lines, each first power line can overlap with the orthographic projections of two columns of pixel circuits on the substrate. The first power line can be connected to the pixel circuit, for example, it can be connected to a storage capacitor in the pixel circuit. The first power line can be provided on the same layer as the data signal lines DATA.

[0135] Continue to refer Figure 3 Among a part of the data signal lines DATA, among the three adjacent data signal lines DATA, a second connecting line 132 is set between the two data signal lines DATA located on one side and the middle, and there is no second connecting line 132 between the two data signal lines DATA located on the other side and the middle, for example, the first power line is between the two data signal lines DATA located on the other side and the middle.

[0136] Specifically, such as Figure 3 As shown, a second connection line 132 is provided between adjacently arranged data signal lines DATA. At this time, the data signal line DATA and the second connection line 132 are arranged in a 1-in-1 manner.

[0137] Figure 4 A schematic structural diagram of another display panel provided by an embodiment of the present invention, Figure 5 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 4 and Figure 5As shown, among a portion of the data signal lines DATA, two second connection lines 132 are provided between the two data signal lines DATA located on one side and in the middle of the three adjacent data signal lines DATA. No second connection line 132 is provided between the two data signal lines DATA located on the other side and in the middle. For example, a first power line is provided between the two data signal lines DATA located on the other side and in the middle. That is, two second connection lines 132 are provided between the adjacent data signal lines DATA. In this case, a 1-into-2 arrangement is implemented between the data signal lines DATA and the second connection lines 132.

[0138] Figure 6 for Figure 2 The provided partial enlarged structural diagram of the display panel at the dotted box A is Figure 7 for Figure 2 The provided partial enlarged structural diagram of the display panel at the dotted box B is Figure 8 for Figure 4 The provided partial enlarged structural diagram of the display panel at the dotted box C is shown. Figure 9 for Figure 4 The provided display panel is a partially enlarged structural diagram at the dotted box E. Figure 2 、 Figure 4 、 Figures 6 to 9 Along the first direction X, the first connection lines 131 corresponding to the first data signal line DATA to the n-th data signal line DATA are sequentially connected to the first to n-th first-side first connection lines 1311, and the lengths of the first to n-th first-side first connection lines 1311 decrease in sequence. For example, n first-side first connection lines 1311 are arranged in the second direction Y.

[0139] Specifically, the lengths of the first to nth first-side first connection lines 1311 decrease sequentially, which can reduce the equivalent impedance of the first connection lines 131 corresponding to the connections from the first data signal line DATA to the nth data signal line DATA, thereby gradually reducing the load corresponding to the drive signals on the first data signal line DATA to the nth data signal line DATA. When the nth data signal line DATA is connected to the fan-out line 140 through the connection line 130, and the n+1th data signal line DATA is directly connected to the fan-out line 140, the load difference between the nth data signal line DATA and the n+1th data signal line DATA can be made relatively small, thereby improving the split-screen phenomenon of the display panel at the nth data signal line DATA and the n+1th data signal line DATA, and improving the display effect of the display panel. For example, as Figure 6As shown, when the data signal line DATA and the second connection line 132 are arranged in a 1-in-1 manner, n first-side second connection lines 1321 are arranged between the n+1th to 3nth data signal lines DATA along the first direction X. Then, along the first direction X, the first data signal line DATA can be connected to the first first-side second connection line 1321 through the first first-side first connection line 1311-1, the second data signal line DATA can be connected to the second first-side second connection line 1321 through the second first-side first connection line 1311-2... The nth data signal line DATA is connected to the nth first-side second connection line 1321 through the nth first-side first connection line 1311-n. Figure 8 As shown, when the data signal line DATA and the second connection line 132 are arranged in a 1-into-2 manner, n first-side second connection lines 1321 are arranged between the n+1th to the 2nth data signal lines DATA along the first direction X. Then, along the first direction X, the first data signal line DATA can be connected to the first first-side second connection line 1321 through the first first-side first connection line 1311-1, the second data signal line DATA can be connected to the second first-side second connection line 1321 through the second first-side first connection line 1311-2... and the nth data signal line DATA can be connected to the nth first-side second connection line 1321 through the nth first-side first connection line 1311-n.

[0140] Continue to refer Figure 2 、 Figure 4 、 Figures 6 to 9 Along the first direction X, the first connection lines 131 corresponding to the last data signal line DATA to the M-n+1th data signal line DATA are sequentially connected to the first to nth second-side first connection lines 1312, and the lengths of the first to nth second-side first connection lines 1312 decrease in sequence; where M is the number of data signal lines. n is an integer greater than or equal to 2, and M is an integer greater than 2n. For example, n second-side first connection lines 1312 are arranged in the second direction Y.

[0141] Specifically, the lengths of the first to nth second-side first connection lines 1312 are successively reduced, which can gradually reduce the load corresponding to the drive signal on the last data signal line DATA to the M-n+1th data signal line DATA. When the M-n+1th data signal line DATA is connected to the fan-out line 140 through the connection line 130, and the Mnth data signal line DATA is directly connected to the fan-out line 140, the load difference between the M-n+1th data signal line DATA and the Mnth data signal line DATA can be made relatively small, thereby improving the split-screen phenomenon of the display panel at the M-n+1th data signal line DATA and the Mnth data signal line DATA, and improving the display effect of the display panel. For example, as Figure 7 As shown, when the data signal line DATA and the second connection line 132 are arranged in a 1-in-1 manner, n second-side second connection lines 1322 are arranged between the M-n+1th to the M-3nth data signal lines DATA along the first direction X. Then, along the first direction X, the last data signal line DATA can be connected to the first second-side second connection line 1322 through the first second-side first connection line 1312-1, the second-to-last data signal line DATA can be connected to the second second-side second connection line 1322 through the second second-side first connection line 1312-2... and the nth-to-last data signal line DATA can be connected to the nth second-side second connection line 1322 through the nth second-side first connection line 1312-n. Figure 8 As shown, when the data signal line DATA and the second connection line 132 are arranged in a 1-into-2 manner, there are n second-side second connection lines 1322 arranged between the M-n+1th to the M-2nth data signal lines DATA along the first direction X. Then, along the first direction X, the last data signal line DATA can be connected to the first second-side second connection line 1322 through the first second-side first connection line 1312-1, the second-to-last data signal line DATA can be connected to the second second-side second connection line 1322 through the second second-side first connection line 1312-2... and the nth-to-last data signal line DATA can be connected to the nth second-side second connection line 1322 through the nth second-side first connection line 1312-n.

[0142] Continue to refer Figures 6 to 9 , the length of the j-th second-side first connecting line 1312 is less than the length of the j-th first-side first connecting line 1311, where j is an integer greater than or equal to 1 and less than or equal to n.

[0143] Specifically, such as Figure 6 and Figure 7As shown, when the data signal line DATA and the second connection line 132 are arranged in a 1-in-1 manner, the first first-side first connection line 1311-1 is the first-side first connection line 1311 between the first data signal line DATA and the first first-side second connection line 1321-1, the second first-side first connection line 1311-2 is the first-side first connection line 1311 between the second data signal line DATA and the second first-side second connection line 1321-2… The nth first-side first connection line 1311-n is the first-side first connection line 1311 between the nth data signal line DATA and the nth first-side second connection line 1321-n. Similarly, the first second-side first connection line 1312-1 is the second-side first connection line 1312 between the last data signal line DATA (i.e., the Mth data signal line DATA) and the first second-side second connection line 1322-1. The second second-side first connection line 1312-2 is the second-side first connection line 1312 between the second-to-last data signal line DATA and the second second-side second connection line 1322-2. ... The nth second-side first connection line 1312-n is the second-side first connection line 1312 between the nth-to-last data signal line DATA and the nth second-side second connection line 1322-n. When a data signal line DATA is connected to a pixel of the same color, the number of data signal lines DATA changes (e.g., one is added), such that the distance from the jth first-side first connection line 1311 along the first direction X to the corresponding connected data signal line DATA is greater than the distance from the jth second-side first connection line 1312 along the first direction X to the corresponding connected data signal line DATA. When the first connection line 131 and the data signal line DATA are arranged in different layers, the length of the j-th second-side first connection line 1312 can be made shorter than the length of the j-th first-side first connection line 1311, so that the first connection lines 131 on both sides can be connected to the corresponding data signal line DATA in the vertical direction of the display panel. Figure 10 for Figure 6 The partially enlarged schematic diagram of the dotted box A1, Figure 11 for Figure 7 The partially enlarged schematic diagram of the dotted box A2 in the figure. Figure 11 and Figure 12 As shown, the length l2 of the n-th second-side first connection line 1312 is less than the length l1 of the n-th first-side first connection line 1311. For example, j is equal to 1, 2, 3, ..., n.

[0144] For example, the number of data signal lines DATA overlapping with the j-th second-side first connection line 1312 is less than the number of data signal lines DATA overlapping with the j-th first-side first connection line 1311. For example, the number of data signal lines DATA overlapping with the j-th second-side first connection line 1312 minus 1 is equal to the number of data signal lines DATA overlapping with the j-th first-side first connection line 1311.

[0145] For example, the j-th second-side first connecting line 1312 and the j-th first-side first connecting line 1311 are located on the same straight line extending along the first direction X.

[0146] Figure 12 A schematic structural diagram of another display panel provided by an embodiment of the present invention, Figure 13 for Figure 12 The provided partial enlarged schematic diagram of the display panel at the dotted frame F. Figure 12 and Figure 13 As shown, the display panel further includes n first compensation lines R1, and the first compensation lines R1 are correspondingly connected to the second-side first connection lines 1312;

[0147] Specifically, such as Figure 12 and Figure 13 As shown, the display panel includes n first compensation lines R1, each first compensation line R1 is connected to a second-side first connection line 1312, which is equivalent to increasing the length of the second-side first connection line 1312, thereby reducing the difference in length between the j-th second-side first connection line 1312 and the j-th first-side first connection line 1311, thereby reducing the load difference between the j-th second-side first connection line 1312 and the j-th first-side first connection line 1311, thereby improving the load consistency of the display panel, thereby improving the brightness consistency of the display panel.

[0148] Continue to refer Figure 12 and Figure 13 The first compensation line R1 extends along the first direction X, so that the first compensation line R1 and the first connecting line 131 have the same extension direction, which facilitates the connection between the first compensation line R1 and the second-side first connecting line 1312.

[0149] In some embodiments, the first compensation line R1 is disposed on the same layer as the second-side first connection line 1312, so that the first compensation line R1 and the data signal line DATA are disposed on different layers, thereby preventing a short circuit between the first compensation line R1 and the data signal line DATA. Furthermore, the first compensation line R1 and the second-side first connection line 1312 can be directly connected and formed in the same process, simplifying the display panel manufacturing process.

[0150] Figure 14 for Figure 12 The provided partial enlarged schematic diagram of the display panel at the dotted box G, continue to refer to Figures 12 to 14 , along the first direction X, the sum of the length of the i-th second-side first connecting line 1312 and the length of the first compensation line R1 connected to the i-th second-side first connecting line 1312 is equal to the length of the i-th first-side first connecting line 1311, where i is an integer greater than or equal to 1 and less than or equal to n.

[0151] Specifically, the first compensation line R1 is connected to the second-side first connection line 1312, so that the equivalent impedance corresponding to the data signal transmitted by the second-side first connection line 1312 is the sum of the equivalent impedance of the first compensation line R1 and the equivalent impedance of the second-side first connection line 1312. Along the first direction X, the sum of the length of the i-th second-side first connection line 1312 and the length of the first compensation line R1 is equal to the length of the i-th first-side first connection line 1311, so that the equivalent impedance corresponding to the data signal transmitted by the i-th second-side first connection line 1312 is approximately equal to the equivalent impedance corresponding to the data signal transmitted by the i-th first-side first connection line 1311, which can improve the load consistency of the display panel, thereby improving the brightness consistency of the display panel. The i-th second-side first connection line 1312 and the i-th first-side first connection line 1311 are located on the same straight line extending along the first direction X. Exemplarily, Figure 15 for Figure 13 A partial enlarged diagram of the dotted box A4, Figure 16 for Figure 14 The partially enlarged schematic diagram of the dotted box A3 in the figure. Figure 15 and Figure 16 As shown, the sum of the length l2 of the nth second-side first connecting line 1312 and the length l3 of the first compensatory line R1 is equal to the length l1 of the nth first-side first connecting line 1311 , that is, l2+l3 equals l1.

[0152] For example, along the first direction X, the first compensation line R1 connected to the i-th second-side first connection line 1312 is located on a side of the i-th second-side first connection line 1311 away from the data signal line DATA connected to the i-th second-side first connection line 1312. For example, i is equal to j.

[0153] Continue to refer Figures 12 to 14 The display panel further includes n second compensation lines R2. Along the first direction X, each second compensation line R2 and the first connecting lines 131 on both sides of the second compensation line R2 are located on the same straight line, and the second compensation line R2 is insulated from the first connecting lines 131.

[0154] Specifically, the first connection line 131 and the first compensation line R1 cross over some of the data signal lines DATA along the first direction X, and the second compensation line R2 can cross over the remaining data signal lines DATA (for example, located in the middle area of ​​the display area) along the first direction X, so that each data signal line DATA is crossed over by the first connection line 131, the first compensation line R1 or the second compensation line R2 along the first direction X, which can improve the load consistency of each data signal line DATA, thereby improving the brightness consistency of the display panel.

[0155] In some embodiments, the second compensation line R2 is disposed on the same layer as the first connection line 131, which can improve the consistency of the parasitic capacitance between the data signal line DATA and the first connection line 131 in the vertical direction, and the parasitic capacitance between the data signal line DATA and the second compensation line R2 in the vertical direction, thereby further improving the load consistency of the data signal line DATA. For example, the second compensation line R2 and the first connection line 131 can be formed using the same material and in the same process, that is, by patterning the same film layer, so that the second compensation line R2 and the first connection line 131 have the same unit impedance load, which can further improve the load consistency of the data signal line DATA.

[0156] In some embodiments, a first break T1 is formed between the second compensation line R2 and the first connecting line 1311 , a second break T2 is formed between the second compensation line R2 and the first compensation line R1 , or a second break T2 is formed between the second compensation line R2 and the second connecting line 1312 .

[0157] Specifically, the first compensation line R1 can be disposed on a side of the second-side first connection line 1312 that is close to the first-side first connection line 1311. In this case, the second break T2 can be the break between the second compensation line R2 and the first compensation line R1. The first compensation line R1 can also be disposed on a side of the second-side first connection line 1312 that is away from the first-side first connection line 1311. In this case, the second break T2 can be the break between the second compensation line R2 and the second-side first connection line 1312. By providing a break between the second compensation line R2 and the first connection line 131 and / or the first compensation line R1, the second compensation line R2 can be insulated from both the first-side first connection line 1311 and the second-side first connection line 1312, thereby preventing abnormal short circuits between the first-side first connection line 1311 and the second-side first connection line 1312.

[0158] For example, the first break T1 may be covered by the first electrode (e.g., an anode) of the pixel. For example, the second break T2 may be covered by the first electrode (e.g., an anode) of the pixel. Such an arrangement can improve off-screen Mura. The pixel may include a first electrode, a light-emitting layer, and a second electrode. The first electrode of the pixel may be connected to the pixel circuit. The second electrode (e.g., a cathode) may be connected to a second power line. The second power line may transmit a second power supply voltage VSS.

[0159] In some embodiments, along the third direction X1 , a plurality of first fractures T1 are arranged at equal intervals; any two of the third direction X1 , the first direction X, and the second direction Y intersect.

[0160] Specifically, such as Figures 12 to 14 As shown, along the first direction X, the lengths of the first to nth first-side first connecting lines 1311 decrease sequentially, such that the arrangement direction of the plurality of first breaks T1 forms an angle with the first direction X and the second direction Y. That is, the third direction X1 forms an angle with the first direction X and the second direction Y. By arranging the plurality of first breaks T1 at equal intervals, the consistency of the sum of the lengths of the first connecting lines 131, the first compensation lines R1, and the second compensation lines R2 on different straight lines can be improved, thereby improving the load consistency of the data signal lines DATA.

[0161] In some embodiments, the plurality of second fractures T2 are arranged at equal intervals along the fourth direction X2; any two of the fourth direction X2, the third direction X1, the first direction X, and the second direction Y intersect.

[0162] Specifically, such as Figures 12 to 14 As shown, along the first direction X, the lengths of the first to nth second-side first connecting lines 1312 decrease sequentially, such that the arrangement direction of the plurality of second breaks T2 forms an angle with the first direction X and the second direction Y. That is, the fourth direction X2 forms an angle with the first direction X and the second direction Y, and the third direction X1 and the fourth direction X2 can be arranged symmetrically along the second direction Y. By arranging the plurality of second breaks T2 at equal intervals, the consistency of the sum of the lengths of the first connecting lines 131, the first compensation lines R1, and the second compensation lines R2 on different straight lines can be improved, thereby improving the load consistency of the data signal lines DATA.

[0163] In some embodiments, the distance between adjacent first breaks T1 is equal to the distance between adjacent second breaks T2, which can improve the consistency of the sum of the lengths of the first connecting line 131, the first compensation line R1 and the second compensation line R2 on different straight lines, thereby improving the load consistency of the data signal line DATA.

[0164] In some embodiments, the second compensation line R2 is connected to a DC potential or a power supply voltage (e.g., a first power supply voltage VDD, a second power supply voltage VSS, or an initialization voltage Vref), which can provide a fixed potential on the second compensation line R2. When parasitic capacitance is formed between the second compensation line R2 and other wiring, the effect of the parasitic capacitance on the signal potential on the other wiring can be reduced. The pixel circuit can be connected to an initialization signal line, which can transmit the initialization voltage Vref.

[0165] Continue to refer Figure 2 、 Figure 4 、 Figures 6 to 9 Along the first direction X, the second connection lines 132 corresponding to the first data signal line DATA to the n-th data signal line DATA are sequentially connected to the first to n-th first-side second connection lines 1321, and the lengths of the first to n-th first-side second connection lines 1312 decrease in sequence. For example, n first-side second connection lines 1312 are arranged along the first direction X.

[0166] Specifically, the lengths of the first to nth first-side second connection lines 1312 are successively reduced, which can reduce the equivalent impedance of the second connection lines 132 corresponding to the first data signal line DATA to the nth data signal line DATA, thereby gradually reducing the load corresponding to the drive signal on the first data signal line DATA to the nth data signal line DATA. When the nth data signal line DATA is connected to the fan-out line 140 through the connection line 130, and the n+1th data signal line DATA is directly connected to the fan-out line 140, the load difference between the nth data signal line DATA and the n+1th data signal line DATA can be made relatively small, thereby improving the split-screen phenomenon of the display panel at the nth data signal line DATA and the n+1th data signal line DATA, and improving the display effect of the display panel. For example, as Figure 6 As shown, when the data signal line DATA and the second connection line 132 are arranged in a 1-in-1 manner, n first-side second connection lines 1321 are arranged between the n+1th to 3nth data signal lines DATA along the first direction X. Then, along the first direction X, the first data signal line DATA can be connected to the fan-out line 140 through the first first-side second connection line 1321-1, the second data signal line DATA can be connected to the fan-out line 140 through the second first-side second connection line 1321-2... and the nth data signal line DATA can be connected to the fan-out line 140 through the nth first-side second connection line 1321-n. Figure 8As shown, when the data signal line DATA and the second connection line 132 are arranged in a 1-into-2 manner, n first-side second connection lines 1321 are arranged between the n+1th to 2nth data signal lines DATA along the first direction X. Then, along the first direction X, the first data signal line DATA can be connected to the fan-out line 140 through the first first-side second connection line 1321-1, the second data signal line DATA can be connected to the fan-out line 140 through the second first-side second connection line 1321-2... and the nth data signal line DATA can be connected to the fan-out line 140 through the nth first-side second connection line 1321-n.

[0167] Continue to refer Figure 2 、 Figure 4 、 Figures 6 to 9 Along the first direction X, the second connection lines 132 corresponding to the last data signal line DATA to the M-n+1th data signal line DATA are sequentially connected to the first to nth second-side second connection lines 1322, and the lengths of the first to nth second-side second connection lines 1322 decrease in sequence. For example, n second-side second connection lines 1322 are arranged along the first direction X.

[0168] Specifically, the lengths of the first to nth second-side second connection lines 1322 decrease sequentially, which can gradually reduce the load corresponding to the drive signal on the last data signal line DATA to the M-n+1th data signal line DATA. When the M-n+1th data signal line DATA is connected to the fan-out line 140 through the connection line 130, and the Mnth data signal line DATA is directly connected to the fan-out line 140, the load difference between the M-n+1th data signal line DATA and the Mnth data signal line DATA can be made relatively small, thereby improving the split-screen phenomenon of the display panel at the M-n+1th data signal line DATA and the Mnth data signal line DATA, and improving the display effect of the display panel. For example, as Figure 7 As shown, when the data signal line DATA and the second connection line 132 are arranged in a 1-in-1 manner, n second-side second connection lines 1322 are arranged between the M-n+1th to M-3nth data signal lines DATA along the first direction X. Then, along the first direction X, the last data signal line DATA can be connected to the fan-out line 140 through the first second-side second connection line 1322-1. The second-to-last data signal line DATA is connected to the fan-out line 140 through the second second-side second connection line 1322-2... The nth-to-last data signal line DATA is connected to the fan-out line 140 through the nth second-side second connection line 1322-n. Figure 8As shown, when the data signal lines DATA and the second connection lines 132 are arranged in a 1-into-2 manner, n second-side second connection lines 1322 are arranged between the M-n+1th to the M-2nth data signal lines DATA along the first direction X. Then, along the first direction X, the last data signal line DATA can be connected to the fan-out line 140 via the first second-side second connection line 1322-1. The second-to-last data signal line DATA is connected to the fan-out line 140 via the second second-side second connection line 1322-2...and the nth-to-last data signal line DATA is connected to the fan-out line 140 via the nth second-side second connection line 1322-n.

[0169] For example, on the first side of the display area, such as the left side, the closer the data signal line DATA is to the middle area of ​​the display area, the larger the number, the closer the first-side second connection line 1321 is to the middle area of ​​the display area, the smaller the number, and the closer the first-side first connection line 1311 is to the fan-out area where the fan-out line is located, the larger the number. For example, on the first side of the display area, the closer the data signal line DATA is to the middle area of ​​the display area, the shorter the length of the first-side second connection line 1321 connected to the data signal line DATA is, and the closer the data signal line DATA is to the middle area of ​​the display area, the shorter the length of the first-side first connection line 1311 connected to the data signal line DATA is.

[0170] For example, on the second side of the display area, such as the right side, the data signal line DATA closer to the middle area of ​​the display area has a larger sequence number (corresponding to the inverse number), the second connection line 1322 closer to the middle area of ​​the display area has a smaller sequence number, and the first connection line 1312 closer to the second side of the fan-out area where the fan-out line is located has a larger sequence number. For example, on the second side of the display area, the length of the second connection line 1321 connected to the data signal line DATA closer to the middle area of ​​the display area is shorter, and the length of the second connection line 1311 connected to the data signal line DATA closer to the middle area of ​​the display area is shorter.

[0171] Continue to refer Figure 2 、 Figure 4 、 Figures 6 to 9 The first-side second connection line 1321 is arranged on a side of the n-th data signal line DATA away from the n-1-th data signal line DATA, so that the data signal line DATA on the side of the display panel close to the display area AA along the first direction X can be connected to the fan-out line 140 near the middle area, which is beneficial to reducing the bottom frame of the display panel.

[0172] Continue to refer Figure 2 、 Figure 4 、 Figures 6 to 9The second connecting line 1322 on the second side is arranged on the side of the M-n+1th data signal line DATA close to the Mnth data signal line DATA; the data signal line DATA on the other side of the display panel close to the display area AA along the first direction X can be connected to the fan-out line 140 near the middle area, which is beneficial to reducing the lower frame of the display panel.

[0173] Continue to refer Figure 2 、 Figure 4 、 Figures 6 to 9 The length of the p-th second-side second connection line 1322 is equal to the length of the p-th first-side second connection line 1321, where p is an integer greater than or equal to 1 and less than or equal to n. p can be equal to 1, 2, 3, ..., n.

[0174] Specifically, the length of the pth second-side second connection line 1322 is equal to the length of the pth first-side second connection line 1321, so that the equivalent impedance of the pth second-side second connection line 1322 is equal to the equivalent impedance of the pth first-side second connection line 1321. When different data signal lines DATA are connected to the fan-out line 140 through the second connection lines 132, the load consistency of the different data signal lines DATA can be improved, thereby improving the brightness consistency of the display panel.

[0175] Figure 17 A schematic structural diagram of another display panel provided by an embodiment of the present invention, Figure 18 for Figure 17 The provided partial enlarged schematic diagram of the display panel at the dotted frame H. Figure 17 and Figure 18 As shown, the display panel further includes n third compensation lines R3 , and the third compensation lines R3 are correspondingly connected to the second-side second connection lines 1322 .

[0176] Specifically, the third compensation line R3 is connected to the second-side second connection line 1322, so that the equivalent impedance corresponding to the second-side second connection line 1322 transmitting the data signal is the sum of the equivalent impedance of the third compensation line R3 and the equivalent impedance of the second-side second connection line 1322. When the length of the j-th second-side first connection line 1312 is less than the length of the j-th first-side first connection line 1311, and the length of the p-th second-side second connection line 1322 (connected to the j-th second-side first connection line 1312) is equal to the length of the p-th first-side second connection line 1321 (connected to the j-th first-side first connection line 1311), the length of the u-th second-side connection line (including the j-th second-side first connection line 1312 and the p-th second-side second connection line 1322) is less than the length of the u-th first-side connection line (including the j-th first-side first connection line 1311 and the p-th first-side second connection line 1321). The length of the u-th first-side connecting line is the sum of the length of the j-th first-side first connecting line 1311 and the length of the p-th first-side second connecting line 1321. The length of the u-th second-side connecting line is the sum of the length of the j-th second-side first connecting line 1311 and the length of the p-th second-side second connecting line 1322. By providing a third compensation line R3 correspondingly connected to the second-side second connecting line 1322, the length of the second-side connecting line can be increased, reducing the difference between the length of the u-th second-side connecting line and the length of the u-th first-side connecting line. This reduces the load difference between the u-th second-side connecting line and the u-th first-side connecting line, improves the load consistency of the display panel, and thus improves the brightness consistency of the display panel.

[0177] Continue to refer Figure 17 and Figure 18 The third compensation line R3 extends along the second direction Y, so that the third compensation line R3 and the second connection line 132 have the same extension direction, which facilitates the connection between the third compensation line R3 and the second connection line 132.

[0178] In some embodiments, the third compensation line R3 is disposed on the same layer as the second-side second connection line 1322, allowing for direct contact and connection between the third compensation line R3 and the second-side second connection line 1322. The third compensation line R3 and the second-side second connection line 1322 can be formed in the same process, simplifying the display panel manufacturing process. In this case, the third compensation line R3 and the second-side second connection line 1322 can be made of the same material, resulting in an equivalent impedance per unit length for the third compensation line R3 and the second-side second connection line 1322, simplifying the load compensation process.

[0179] Figure 19 for Figure 17 The provided display panel is a partially enlarged schematic diagram at the dotted frame I. Figures 17 to 19As shown, the sum of the length of the qth second-side second connecting line, the length of the corresponding third compensation line connected thereto, and the length of the qth first-side first connecting line is greater than the sum of the length of the qth second-side second connecting line and the length of the qth first-side first connecting line, where q is an integer greater than or equal to 1 and less than or equal to n.

[0180] Specifically, the first connection line 131 and the data signal line DATA are arranged in a different layer to avoid an abnormal short circuit between the first connection line 131 and the data signal line DATA when the first connection line 131 extends along the first direction X. Exemplarily, the film layer where the first connection line 131 is located is closer to the substrate of the display panel than the film layer where the data signal line DATA is located. The second connection line 132 can be arranged in the same layer as the data signal line DATA. When the display panel also includes other wiring, and the other wiring is arranged on the side of the first connection line 131 closer to the substrate of the display panel, the parasitic capacitance between the first connection line 131 and the other wiring in the direction perpendicular to the display panel is greater than the parasitic capacitance between the second connection line 132 and the other wiring in the direction perpendicular to the display panel. When the length of the j-th second-side first connection line 1312 is less than the length of the j-th first-side first connection line 1311, by setting the length of the third compensation line R3 to be greater than the difference between the lengths of the second-side second connection line 1322 and the first-side second connection line 1321, the equivalent impedance of the third compensation line R3 can be made approximately equal to the difference between the equivalent impedance of the second-side second connection line 1322 and the equivalent impedance of the first-side second connection line 1321, thereby reducing the load difference between the u-th first-side connection line and the u-th second-side connection line, improving the load consistency of the display panel, and thus improving the brightness consistency of the display panel. For example, Figure 20 for Figure 18 A partial enlarged diagram of the dotted box A5, Figure 21 for Figure 19 The partially enlarged schematic diagram of the dotted box A6 is shown in FIG. Figure 20 and Figure 21 As shown, the sum of the length l1 of the nth first-side first connecting line 1311 and the length l4 of the nth first-side second connecting line 1321-n is less than the sum of the length l2 of the nth second-side first connecting line 1312, the length l5 of the nth second-side second connecting line 1322-n and the length l6 of the nth third compensation line R3, that is, l1+l4 is less than l2+l5+l6.

[0181] For example, the third compensation line is located on a side of the second connecting line connected to the third compensation line that is away from the fan-out line. For example, p is equal to q.

[0182] For example, the first connection line 131 and the second connection line 132 are provided in different layers. For example, the second connection line 132 and the data signal line DATA are provided in the same layer.

[0183] Continue to refer Figures 17 to 19 The display panel further includes n first-side fourth compensation lines R41; along the second direction Y, each first-side fourth compensation line R41 and a first-side second connecting line 1321 are located on the same straight line, and the first-side fourth compensation line R41 is insulated from the first-side second connecting line 1321.

[0184] Specifically, the display panel also includes pixel circuits arranged in an array. When the first-side second connection line 1321 overlaps with a portion of a column of pixel circuits in a vertical direction (parallel to the thickness direction of the display panel), parasitic capacitance exists between the first-side second connection line 1321 and the portion of the column of pixel circuits. In this case, each first-side fourth compensation line R41 is arranged on the same straight line as a first-side second connection line 1321, so that the first-side fourth compensation line R41 overlaps with other portions of the column of pixel circuits in the vertical direction, that is, parasitic capacitance exists between the first-side fourth compensation line R41 and other portions of the column of pixel circuits. This can improve the consistency of the parasitic capacitance in the same column of pixel circuits, thereby improving the load consistency of the display panel, and thus improving the brightness consistency of the display panel. The first-side fourth compensation line R41 can be located on the side of the first-side second connection line 1321 away from the fan-out line 140.

[0185] Continue to refer Figures 17 to 19 A third break T3 is provided between the first-side fourth compensation line R41 and the first-side second connection line 1321 to prevent short circuiting between the first-side fourth compensation line R41 and the first-side second connection line 1321. The third break T3 can be covered by the first electrode (e.g., anode) of the pixel. This arrangement can improve off-screen mura.

[0186] Continue to refer Figures 17 to 19 The fourth compensation line R41 on the first side is disposed on the same layer as the second connection line 132. This can improve the consistency of the parasitic capacitance generated by the fourth compensation line R41 and the second connection line 132 with the pixel circuit, further improving the load consistency of the display panel, thereby improving the brightness consistency of the display panel. In some embodiments, the fourth compensation line R41 on the first side and the second connection line 132 can also be configured with the same material to further improve the load consistency of the fourth compensation line R41 on the first side and the second connection line 132, further improving the load consistency of the display panel.

[0187] Continue to refer Figures 17 to 19The fourth compensation line R41 on the first side is connected to a DC potential or a power supply voltage (for example, the first power supply voltage VDD or the second power supply voltage VSS or the initialization voltage Vref), so that the fourth compensation line R41 on the first side has a fixed potential. When the fourth compensation line R41 on the first side forms a parasitic capacitance with other wirings, the influence of the parasitic capacitance on the signal potential on other wirings can be reduced.

[0188] Continue to refer Figures 17 to 19 The display panel further includes n second-side fourth compensation lines R42; along the second direction Y, each second-side fourth compensation line R42 and a second-side second connecting line 1322 are located on the same straight line, and the second-side fourth compensation line R42 is insulated from the second-side second connecting line 1322.

[0189] Specifically, when the second-side second connection line 1322 vertically overlaps a portion of a column of pixel circuits, parasitic capacitance exists between the second-side second connection line 1322 and the portion of the column of pixel circuits. In this case, each second-side fourth compensation line R42 is arranged on the same straight line as a second-side second connection line 1322, so that the second-side fourth compensation line R42 vertically overlaps with other portions of the column of pixel circuits. That is, parasitic capacitance exists between the second-side fourth compensation line R42 and other portions of the column of pixel circuits. This improves the consistency of the parasitic capacitance within the same column of pixel circuits, thereby improving the load consistency of the display panel and thereby improving the brightness consistency of the display panel. For example, the second-side fourth compensation line R42 is located on the side of the second-side second connection line 1322 away from the fan-out line 140.

[0190] Continue to refer Figures 17 to 19 A fourth break T4 is formed between the second-side fourth compensation line R42 and the second-side second connection line 1322 to prevent short circuiting between the second-side fourth compensation line R42 and the second-side second connection line 1322. The fourth break T4 can be covered by the first electrode (e.g., anode) of the pixel. This configuration can improve off-screen mura.

[0191] Continue to refer Figures 17 to 19 The fourth compensation line R42 on the second side is disposed on the same layer as the second connecting line 132. This improves the consistency of the parasitic capacitance generated between the fourth compensation line R42 on the second side and the second connecting line 132 and the pixel circuit, further improving the load consistency of the display panel and thus improving the brightness consistency of the display panel. In some embodiments, the fourth compensation line R42 on the second side and the second connecting line 132 can also be configured with the same material to further improve the load consistency between the fourth compensation line R42 on the second side and the second connecting line 132, further improving the load consistency of the display panel.

[0192] Continue to refer Figures 17 to 19The fourth compensation line R42 on the second side is connected to a DC potential or a power supply voltage (for example, the first power supply voltage VDD or the second power supply voltage VSS or the initialization voltage Vref), so that the fourth compensation line R42 on the second side has a fixed potential. When the fourth compensation line R42 on the second side forms a parasitic capacitance with other wirings, the influence of the parasitic capacitance on the signal potential on other wirings can be reduced.

[0193] Figure 22 for Figure 2 Another partial structural diagram of the display panel at the dotted box B is provided. Figure 23a A partial structural diagram of another display panel provided by an embodiment of the present invention, Figure 23b A partial structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 22 、 Figure 23a and Figure 23b As shown, the display panel also includes a first routing line R5 extending along the second direction Y; along the first direction X, the first routing line R5 is arranged on the side of the Mth data signal line DATA_M (that is, the last data signal line, that is, the second edge data signal line DATA12) away from the M-1th data signal line DATA; wherein M is the number of data signal lines DATA. Figure 23a and Figure 23b It may be a partially enlarged top view of a second side edge position close to the display area. Figure 3 and Figure 5 It may be a partially enlarged top view near the middle of the display area.

[0194] Specifically, such as Figure 22 As shown in FIG23 , when the data signal lines DATA are arranged back-to-back, a second connecting line 132 or a second routing line R6 is arranged between two adjacent data signal lines DATA along the first direction X, so that each data signal line DATA is arranged adjacent to a second connecting line 132 or a second routing line R6. By arranging the first routing line R5 on the side of the Mth data signal line DATA away from the M-1th data signal line DATA, the last data signal line DATA can also have an adjacent routing line, which can improve the overall wiring consistency of the display panel, improve the load consistency of the display panel, and further improve the brightness consistency of the display panel.

[0195] Continue to refer Figure 2 、 Figure 4 、 Figures 6 to 23a 、 Figure 23bThe display panel also includes a plurality of second routing lines R6, which extend along the second direction Y. Among the first n data signal lines DATA, among the three adjacent data signal lines DATA, the second routing line R6 is arranged between the two data signal lines DATA located on one side and in the middle, and no second routing line R6 is arranged between the two data signal lines DATA located on the other side and in the middle. For example, a first power line is arranged between the two data signal lines DATA located on the other side and in the middle. Among the last n data signal lines DATA, among the three adjacent data signal lines DATA, a second routing line R6 is arranged between the two data signal lines DATA located on one side and in the middle (for example, one second routing line R6 corresponding to 1-in-1, corresponding to the 1-in-1 arrangement of the second connection line 132, or two second routing lines R6 corresponding to 1-in-2, corresponding to the 1-in-2 arrangement of the second connection line 132), and no second routing line R6 is arranged between the two data signal lines DATA located on the other side and in the middle. For example, a first power line is arranged between the two data signal lines DATA located on the other side and in the middle.

[0196] For example, along the first direction X, a second routing line R6 is provided between the first data signal line DATA (ie, the first edge data signal line DATA11 ) and the second data signal line DATA.

[0197] For example, along the first direction X, there is no second routing line R6 between the Mth data signal line DATA and the M-1th data signal line DATA.

[0198] For example, the Mth data signal line DATA and the M-1th data signal line DATA are symmetrically arranged about the first axis Y1 along the second direction Y, and the first routing line R5 and the second routing line R6 adjacent to the first routing line R5 are symmetrically arranged about the first axis Y1.

[0199] Specifically, a second connection line 132 is provided between the nth data signal line DATA and the M-n+1th data signal line DATA. When the second connection line 132 and the pixel circuit overlap in the vertical direction, parasitic capacitance exists between the second connection line 132 and the pixel circuit. By providing a second routing line R6 in the first n data signal lines DATA and the next n data signal lines DATA in the same arrangement as the second connection line 132 and the data signal lines DATA, parasitic capacitance can be provided between the second routing line R6 and the pixel circuit. This not only improves the wiring consistency of the display panel, but also improves the load consistency of the display panel and the brightness consistency of the display panel. For example, the second routing line R6 is provided between the first data signal line DATA and the second data signal line DATA, and no second routing line R6 is provided between the third data signal line DATA and the second data signal line DATA. No second routing line R6 is provided between the Mth data signal line DATA and the M-1th data signal line DATA, and a second routing line R6 is provided between the M-2th data signal line DATA and the M-1th data signal line DATA. When the first routing line R5 is arranged on the side of the Mth data signal line DATA away from the M-1th data signal line DATA, the first routing line R5 and the adjacent second routing line R6 are symmetrical about the first axis Y1, and the Mth data signal line DATA and the M-1th data signal line DATA are symmetrical about the first axis Y1, which can improve the wiring consistency of the display panel.

[0200] In some embodiments, the first routing line R5, the second routing line R6, and the data signal line DATA are arranged on the same layer, which can improve the consistency of the parasitic capacitance generated by the first routing line R5, the second routing line R6, and the data signal line DATA with the pixel circuit, further improving the load consistency of the display panel, thereby improving the brightness consistency of the display panel. In some embodiments, the first routing line R5, the second routing line R6, and the data signal line DATA can also be arranged with the same material, which can further improve the load consistency of the first routing line R5, the second routing line R6, and the data signal line DATA, further improving the load consistency of the display panel.

[0201] In some embodiments, the first routing R5 is connected to a DC potential or a power supply voltage (for example, a first power supply voltage VDD or a second power supply voltage VSS or an initialization voltage Vref), and the second routing R6 is connected to a DC potential or a power supply voltage; this allows the first routing R5 and the second routing R6 to have a fixed potential, and when the first routing R5 and the second routing R6 respectively form parasitic capacitances with other wirings, the influence of the parasitic capacitances on the signal potentials on other wirings can be reduced.

[0202] In some embodiments, the first data signal line DATA is used to transmit data signals corresponding to K1 pixels; the last data signal line DATA is used to transmit data signals corresponding to K1 pixels, and each data signal line DATA of at least a portion of the data signal lines located between the first data signal line DATA and the last data signal line DATA is used to transmit data signals corresponding to K2 pixels; K1 and K2 are different positive integers.

[0203] Specifically, such as Figure 1 As shown, the first first data signal line DATA1 is connected to the first pixel P1 in the first first pixel column 110, each of the remaining first data signal lines DATA1 is connected to the first pixel P1 in two adjacent first pixel columns 110, the last second data signal line DATA2 is connected to the second pixel P2 in the last first pixel column 110, and each of the remaining second data signal lines DATA2 is connected to the second pixel P2 in two adjacent first pixel columns 110; each third data signal line DATA3 is connected to the third pixel P3 in a column of second pixel columns 120, so that the first data signal line DATA and the last data signal line DATA are both connected to half of the pixels in a column of pixels, so that one data signal line DATA can provide data signals for pixels of the same color, reducing the voltage jump of the data signal line DATA, thereby reducing the power consumption of the driving chip.

[0204] In some embodiments, K2 is greater than K1.

[0205] In some embodiments, K2 is greater than or equal to twice K1. Due to the setting of the arc angle of the display panel, the lengths of the first data signal line DATA and the last data signal line DATA are shorter than the data signal line DATA near the middle of the display area, the number of pixel circuits in the last pixel circuit column and the last pixel circuit column is smaller than the number of pixel circuits in the pixel circuit column near the middle of the display area, and the number of pixels in the last pixel column and the last pixel column is smaller than the number of pixels in the pixel column near the middle of the display area.

[0206] Continue to refer Figure 2 、 Figure 4 、 Figures 6 to 15 , except for the first n and last n data signal lines, the remaining data signal lines DATA are correspondingly connected to the remaining fan-out lines 140 , where n is greater than 0 and a multiple of 4.

[0207] Specifically, when the data signal line DATA is connected to the fan-out line 140 via the connection line 130, the order in which the fan-out line 140 is connected to the data signal line DATA is different from the arrangement order of the fan-out lines 140. In this case, the drive signals provided by the fan-out line 140 need to be sorted between the driver chip and the fan-out line 140 according to the order in which the data signal line DATA is connected to the fan-out line 140, so as to ensure that the fan-out line 140 provides the drive signals in the arrangement order of the data signal line DATA. The data signal line DATA near the middle area of ​​the display panel is directly connected to the fan-out line 140. For example, the qth fan-out line 140 can be connected to the qth data signal line DATA, which can simplify the order in which the data signal line DATA near the middle area of ​​the display panel is connected to the fan-out line 140, avoid the need to sort the drive signals provided by the fan-out line 140 again between the driver chip and the fan-out line 140, and simplify the wiring complexity of the display panel. Furthermore, when n is greater than 0 and a multiple of 4, the first n data signal lines DATA and the last n data signal lines DATA can be connected in reverse order to the fan-out lines 140 via the connection lines 130. This can meet the display panel's requirements for the driver chip, thereby avoiding additional driver chip updates when the number of data signal lines DATA changes, thereby reducing the display panel's manufacturing cost. Furthermore, the driver chip can support the removal of the first n and last n data signal lines DATA, allowing the number of data signal lines DATA to be odd or even. When an additional data signal line DATA is added, the driver chip can still provide drive signals to all data signal lines DATA, ensuring the normal operation of the display panel.

[0208] For example, Figure 24 FIG1 is a schematic diagram of another display panel structure provided by an embodiment of the present invention. Figure 24 As shown, the display panel further includes a plurality of columns of pixel circuits arranged along a first direction X, and each column of pixel circuits includes a plurality of pixel circuits 160 arranged along a second direction Y.

[0209] The first column pixel circuit 160 is connected to the first pixel P1 in the first column of the first pixel column 110, and each column pixel circuit 160 in the remaining odd columns of pixel circuits 160 is connected to the first pixel P1 in the two adjacent columns of the first pixel column 110, or, each column pixel circuit 160 in the remaining odd columns of pixel circuits 160 is connected to the second pixel P2 in the two adjacent columns of the first pixel column 110; the even column pixel circuit 160 is connected to the third pixel P3 in the second pixel column 120, and the last column pixel circuit 160 is connected to the first pixel P1 in the last column of the first pixel column 110 (for example, the total number of pixel columns is an integer multiple of 4), or, the last column pixel circuit 160 is connected to the second pixel P2 in the last column of the first pixel column 110 (for example, the total number of pixel columns is not an integer multiple of 4); each data signal line DATA is connected to a corresponding column of pixel circuits.

[0210] Specifically, such as Figure 24 As shown, each data signal line DATA is connected to a corresponding column of pixel circuits, and each column of pixel circuits is connected to pixels of the same color in at least one pixel column. This allows a column of pixel circuits to be connected to pixels of the same color, enabling each data signal line DATA to be connected to pixels of the same color, thereby providing data signals to pixels of the same color. In this case, a column of pixel circuits 160 can be connected to pixels in another pixel column via an anode wiring.

[0211] Figure 25 FIG1 is a schematic diagram of another display panel structure provided by an embodiment of the present invention. Figure 25As shown, each pixel column 10 is connected to the same column of pixel circuits 160, and the multiple data signal lines DATA include a first data signal line DATA11, a last data signal line DATA12, and a first data signal line DATA1, a second data signal line DATA2, and a third data signal line DATA3 located between the first data signal line DATA11 and the last data signal line DATA12 and arranged along the first direction; along the first direction X, the first data signal line DATA11 is connected to the pixel circuit corresponding to the first pixel P1 in the first column of the first pixel column 110, and each first data signal line DATA1 is connected to the pixel circuit corresponding to the first pixel P1 in two adjacent columns of the first pixel column 110; each second data signal line DATA2 is connected to the pixel circuit corresponding to the second pixel P2 in two adjacent columns of the first pixel column 110; and each third data signal line DATA3 is connected to the pixel circuit corresponding to the third pixel P3 in a column of the second pixel column 120. The last data signal line DATA12 is connected to the pixel circuit corresponding to the first pixel P1 in the last column of the first pixel column 110 (for example, the total number of pixel columns is not an integer multiple of 4), or the last data signal line DATA12 is connected to the pixel circuit corresponding to the second pixel P2 in the last column of the first pixel column 110 (for example, the total number of pixel columns is an integer multiple of 4).

[0212] For example, the first pixel P1 may be a red pixel, the second pixel P2 may be a blue pixel, and the third pixel P3 may be a green pixel. Alternatively, the first pixel P1 may be a blue pixel, the second pixel P2 may be a red pixel, and the third pixel P3 may be a green pixel.

[0213] Specifically, the same data signal line DATA is connected only to the pixel circuits 160 corresponding to pixels of the same color, so that the same data signal line DATA is connected only to pixels of the same color, and is used to provide data signals to the pixels of the same color. In the above solution, by providing routing on the film layer where the data signal line DATA is located, the data signal line DATA can be connected to the pixel circuits corresponding to pixels in different columns.

[0214] Continue to refer Figure 24 and Figure 25The pixel circuits connected to two adjacent first pixel columns 110 are connected to three data signal lines DATA, which allows the same data signal line DATA to be connected to pixels of the same color, while reducing the number of additional data signal lines DATA. For example, in the first and second first pixel columns 110, the first pixel P1 in the first first pixel column 110 is connected to one data signal line DATA, the second pixel P2 in the first first pixel column 110 and the second pixel P2 in the second first pixel column 110 are connected to another data signal line DATA, and the first pixel P3 in the second first pixel column 110 is connected to a third data signal line DATA.

[0215] Continue to refer Figure 3 23 , the structures of two adjacent columns of pixel circuits 150 along the first direction X are symmetrical, which can simplify the layout design of the display panel and improve the arrangement density of the pixel circuits of the display panel. Along the first direction X, the corresponding transistors and capacitors of two adjacent columns of pixel circuits 150 are arranged symmetrically.

[0216] Figure 26 for Figure 4 A schematic diagram of a cross-sectional structure of a display panel is provided along OO'. Figure 26 As shown, the display panel also includes:

[0217] substrate 210;

[0218] A first conductive layer 220 is provided on one side of the substrate 110 . The first conductive layer 220 includes a first connecting line 131 .

[0219] The second conductive layer 230 is disposed on a side of the first conductive layer 220 that is away from or close to the substrate 110. The second conductive layer 230 includes a data signal line DATA. The first connecting line 131 is connected to the data signal line DATA through a first via DL1.

[0220] Specifically, the materials of the first conductive layer 220 and the second conductive layer 230 may include metal. The first connecting line 131 is disposed in the first conductive layer 220, and the data signal line DATA is disposed in the second conductive layer 230. This allows the first connecting line 131 and the data signal line DATA to be disposed on different layers. This prevents a short circuit between the first connecting line 131 and the data signal line DATA, which could cause display panel anomalies, when the first connecting line 131 and the data signal line DATA extend in different directions. An insulating layer, such as an organic insulating layer and / or an inorganic insulating layer, may be disposed between the first conductive layer 220 and the second conductive layer 230.

[0221] Continue to refer Figure 26The second conductive layer 230 further includes a second connection line 132. The data signal line DATA is spaced apart from the second connection line 132. The second connection line 132 is connected to the first connection line 131 through a second via DL2. The spacing between the first via DL1 and the second via DL2 corresponding to the first connection line 131 connected to the first data signal line DATA11 in the first direction X (i.e., the length of the first first-side first connection line 1311-1) is greater than the spacing between the first via DL1 and the second via DL2 corresponding to the first connection line 131 connected to the last data signal line DATA12 in the first direction X (i.e., the length of the first second-side first connection line 1312-1). The first via DL1 and the second via DL2 may correspond to Figures 6 to 22 The first via hole DL1 and the second via hole DL2 may be via holes penetrating the insulating layer.

[0222] Specifically, the second connection line 132 can reuse the film layer where the data signal line DATA resides, avoiding the need for an additional conductive layer. Furthermore, the data signal line DATA and the second connection line 132 are spaced apart to prevent a short circuit between the data signal line DATA and the second connection line 132, which could cause display panel anomalies. The spacing in the first direction X between the first via DL1 and the second via DL2 corresponding to the first connection line 131 connected to the first data signal line DATA is the length of the first connection line 131 connected to the first data signal line DATA along the first direction X. The spacing in the first direction X between the first via DL1 and the second via DL2 corresponding to the first connection line 131 connected to the last data signal line DATA is the length of the first connection line 131 connected to the last data signal line DATA along the first direction X. By setting the spacing in the first direction X between the first via DL1 and the second via DL2 corresponding to the first connection line 131 connected to the first data signal line DATA to be greater than the spacing in the first direction X between the first via DL1 and the second via DL2 corresponding to the first connection line 131 connected to the last data signal line DATA, the length of the first connection line 131 connected to the first data signal line DATA along the first direction X is greater than the length of the first connection line 131 connected to the last data signal line DATA along the first direction X. In this case, a compensation line can be provided at the first connection line 131 connected to the last data signal line DATA, which can improve the load consistency of the display panel and thus improve the brightness consistency of the display panel.

[0223] In some embodiments, the first conductive layer and / or the second conductive layer includes a first sublayer, a second sublayer, and a third sublayer stacked in sequence, the material of the first sublayer includes titanium, the material of the second sublayer includes aluminum, and the material of the third sublayer includes titanium.

[0224] Specifically, the first conductive layer can be the third metal layer of the display panel. By setting the first conductive layer to include a first sublayer, a second sublayer and a third sublayer that are stacked, the material of the first sublayer includes titanium, the material of the second sublayer includes aluminum, and the material of the third sublayer includes titanium, that is, the first conductive layer is a Ti / Al / Ti structure, which can make the equivalent impedance of the first conductive layer relatively small, reduce the equivalent impedance of the first connecting line 131, and help improve the split-screen phenomenon of the display panel.

[0225] The second conductive layer can be the fourth metal layer of the display panel. By configuring the second conductive layer to include a first sublayer, a second sublayer, and a third sublayer, wherein the first sublayer is made of titanium, the second sublayer is made of aluminum, and the third sublayer is made of titanium, i.e., the second conductive layer has a Ti / Al / Ti structure, the equivalent impedance of the second conductive layer can be relatively low, thereby reducing the equivalent impedance of the second connecting line 132 and facilitating improvement of the split-screen phenomenon of the display panel.

[0226] Figure 27 for Figure 4 A schematic diagram of a cross-sectional structure of a display panel is provided along section SS'. Figure 27 As shown, the display panel also includes:

[0227] A third conductive layer 240 is provided between the substrate 210 and the first conductive layer 220;

[0228] The fourth conductive layer 250 is disposed between the third conductive layer 240 and the first conductive layer 220 , and the fan-out line 140 is disposed in the third conductive layer 240 and / or the fourth conductive layer 250 ;

[0229] Specifically, the third conductive layer 240 can be the first metal layer of the display panel and can be made of Mo. The fourth conductive layer 250 can be the second metal layer of the display panel and can be made of Mo. The third and fourth conductive layers 240 and 250 can be fully utilized to simplify the wiring design of the display panel. An insulating layer can be provided between any two adjacent first conductive layers 220, second conductive layer 230, third conductive layer 240, and fourth conductive layer 250.

[0230] Continue to refer Figure 27 Along the first direction X, two adjacent fan-out lines 140 are respectively arranged in the third conductive layer 240 and the fourth conductive layer 250, so that multiple fan-out lines 140 can be alternately distributed in the third conductive layer 240 and the fourth conductive layer 250, which is beneficial to increase the distance between the two adjacent fan-out lines 140 and improve the reliability of the display panel.

[0231] The embodiment of the present invention further provides a display panel. Figures 1 to 27 The display panel includes a display area AA and a non-display area NAA; the display panel also includes:

[0232] N pixel columns 10 are located in the display area AA. The N pixel columns 10 are arranged along a first direction X. The pixel columns 10 include a plurality of pixels P arranged along a second direction Y. N is an integer greater than 1. The N pixel columns 10 include pixels P of multiple luminous colors.

[0233] M data signal lines DATA are arranged along a first direction X and extend along a second direction Y. The M data signal lines DATA are used to transmit data signals corresponding to pixels P in N pixel columns 10. The same data signal line DATA is used to transmit data signals corresponding to pixels P of a single luminous color. M is an integer greater than N. The M data signal lines DATA include a first edge data signal line DATA11 and a second edge data signal line DATA12 located on the outermost sides. The first edge data signal line DATA11 and the second edge data signal line DATA12 are located on opposite sides of the display area AA along the first direction X.

[0234] a plurality of connection lines 130 , at least a portion of the connection lines 130 is located in the display area AA, and the first edge data signal line DATA11 and the second edge data signal line DATA12 are connected to different connection lines 130 ;

[0235] A plurality of fan-out lines 140 are located in the non-display area NAA; the first edge data signal line DATA11 and the second edge data signal line DATA12 are connected to the corresponding fan-out lines 140 via corresponding connection lines 130 .

[0236] The technical solution of this embodiment connects the first and second edge data signal lines to the corresponding fan-out lines via corresponding connecting lines. This allows the data signal lines on both sides of the display panel along the first direction to be connected to the fan-out lines via the connecting lines in the display area. This reduces the space occupied by the fan-out lines along the first direction, not only facilitating a reduction in the border around the R corner, but also reducing the width of the fan-out area along the second direction, further reducing the border of the display panel. The first edge data signal line is also the first data signal line, and the second edge data signal line DATA12 is also the last data signal line or the Mth data signal line.

[0237] This embodiment can be combined with some or all of the features of the above embodiments, which will not be described in detail here.

[0238] In some embodiments, M is an odd number, and / or M is greater than N by 1.

[0239] In some embodiments, the display panel also includes M columns of pixel circuit columns arranged along the first direction, each column of pixel circuit columns includes multiple pixel circuits arranged along the second direction, the M columns of pixel circuit columns are connected to M data signal lines, and the M columns of pixel circuit columns are connected to N columns of pixel columns.

[0240] In some embodiments, a first edge data signal line DATA11 is used to transmit data signals corresponding to K1 pixels P; a second edge data signal line DATA12 is used to transmit data signals corresponding to K1 pixels P; and each of at least a portion of the data signal lines located between the first edge data signal line DATA11 and the second edge data signal line DATA12 is used to transmit data signals corresponding to K2 pixels, where K1 and K2 are different positive integers. In some embodiments, K2 is greater than K1. In some embodiments, K2 is greater than or equal to twice K1.

[0241] An embodiment of the present invention further provides a display device. Figure 28 Schematic diagram of the structure of a display device provided by an embodiment of the present invention. Figure 28 As shown, the display device 300 includes a display panel 301 provided by any embodiment of the present invention. Since the display device 300 includes the display panel 301 provided by any embodiment of the present invention, it has the same beneficial effects as the display panel 301 provided by any embodiment of the present invention, and will not be described in detail here. The display device 300 can be, for example, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a smart wearable device, an information inquiry machine in a public place lobby, or any other product or component with a display function.

[0242] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

[0243] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area; the display panel also includes: a plurality of first pixel columns and a plurality of second pixel columns alternately arranged along a first direction, located in the display area, wherein the first pixel columns include a plurality of first pixels and a plurality of second pixels alternately arranged along a second direction, and the second pixel columns include a plurality of third pixels arranged along the second direction; the first pixels, the second pixels, and the third pixels emit light of different colors; a plurality of data signal lines arranged along the first direction and extending along the second direction, the plurality of data signal lines including a first data signal line, a last data signal line, and a first data signal line, a second data signal line, and a third data signal line located between the first data signal line and the last data signal line and arranged along the first direction; the first data signal line is connected to a first pixel in a first first pixel column, each of the first data signal lines is connected to a first pixel in two adjacent first pixel columns, and each of the second data signal lines is connected to a second pixel in two adjacent first pixel columns; each of the third data signal lines is connected to a third pixel in a column of the second pixel columns; the last data signal line is connected to a first pixel in a first first pixel column; or the last data signal line is connected to a second pixel in the first first pixel column; a plurality of connection lines, located in the display area; Multiple fan-out lines arranged along the first direction are located in the non-display area; along the first direction, the first n and last n data signal lines are correspondingly connected to the fan-out lines through the connecting lines, wherein the first direction intersects with the second direction, and n is an integer greater than or equal to 1.

2. The display panel according to claim 1, wherein: The connecting line includes a first connecting line and a second connecting line, the second connecting line extends along the second direction; the second connecting line is connected to the fan-out line, and the second connecting line is connected to the data signal line via the first connecting line; Preferably, among a portion of the data signal lines, among three adjacent data signal lines, the second connecting line is provided between the two data signal lines located on one side and in the middle, and no second connecting line is provided between the two data signal lines located on the other side and in the middle; Preferably, among a portion of the data signal lines, one or two second connection lines are provided between two of the data signal lines located on one side and in the middle of three adjacent data signal lines.

3. The display panel according to claim 2, wherein: Along the first direction, the first connection lines corresponding to the first data signal line to the nth data signal line are sequentially the first to nth first-side first connection lines, and the lengths of the first to nth first-side first connection lines decrease sequentially; and / or, Along the first direction, the first connection lines corresponding to the last data signal line to the M-n+1th data signal line are sequentially connected to the first to nth second-side first connection lines, and the lengths of the first to nth second-side first connection lines decrease sequentially; wherein n is an integer greater than or equal to 2, M is the number of the data signal lines, and M is an integer greater than 2n; Preferably, the length of the j-th first connecting line on the second side is less than the length of the j-th first connecting line on the first side, wherein j is an integer greater than or equal to 1 and less than or equal to n; Preferably, the first connecting line extends along the first direction; Preferably, the number of the data signal lines overlapping with the j-th first connecting line on the second side is smaller than the number of the data signal lines overlapping with the j-th first connecting line on the first side; Preferably, the jth second-side first connecting line and the jth first-side first connecting line are located on the same straight line extending along the first direction.

4. The display panel according to claim 3, wherein: It also includes n first compensation lines, wherein the first compensation lines are correspondingly connected to the first connection lines on the second side; Preferably, the first compensation line extends along the first direction; Preferably, the first compensation line and the second-side first connection line are provided in the same layer.

5. The display panel according to claim 4, wherein: Along the first direction, the sum of the length of the i-th first connecting line on the second side and the length of the first compensation line connected to the i-th first connecting line on the second side is equal to the length of the i-th first connecting line on the first side, where i is an integer greater than or equal to 1 and less than or equal to n; Preferably, the first compensation line connected to the i-th second-side first connection line is located on a side of the i-th second-side first connection line away from the data signal line connected to the i-th second-side first connection line; Preferably, i is equal to j.

6. The display panel according to claim 4, wherein: Also included are n second compensation lines, each of which is located on the same straight line as the first connecting lines on both sides of the second compensation line along the first direction, and the second compensation lines are insulated from the first connecting lines; Preferably, the second compensation line and the first connection line are provided in the same layer; Preferably, there is a first break between the second compensation line and the first connecting line on the first side, there is a second break between the second compensation line and the first compensation line, or there is a second break between the second compensation line and the first connecting line on the second side; Preferably, along the third direction, a plurality of the first fractures are arranged at equal intervals; any two of the third direction, the first direction, and the second direction intersect; Preferably, along the fourth direction, a plurality of the second fractures are arranged at equal intervals; any two of the fourth direction, the third direction, the first direction, and the second direction intersect; Preferably, the distance between adjacent first fractures is equal to the distance between adjacent second fractures; Preferably, the second compensation line is connected to a DC potential or a power supply voltage.

7. The display panel according to claim 3, wherein: Along the first direction, the second connection lines corresponding to the first data signal line to the nth data signal line are sequentially the first to nth first-side second connection lines, and the lengths of the first to nth first-side second connection lines decrease sequentially; and / or, Along the first direction, the second connection lines corresponding to the last data signal line to the M-n+1th data signal line are sequentially connected to the first to nth second-side second connection lines, and the lengths of the first to nth second-side second connection lines decrease sequentially; Preferably, the second connecting line on the first side is arranged on a side of the nth data signal line away from the (n-1)th data signal line; Preferably, the second connecting line on the second side is arranged on a side of the M-n+1th data signal line close to the Mnth data signal line; Preferably, the length of the p-th second-side second connecting line is equal to the length of the p-th first-side second connecting line, wherein p is an integer greater than or equal to 1 and less than or equal to n.

8. The display panel according to claim 7, wherein: It also includes n third compensation lines, wherein the third compensation lines are correspondingly connected to the second connection lines on the second side; Preferably, the third compensation line extends along the second direction; Preferably, the third compensation line and the second connection line on the second side are provided in the same layer.

9. The display panel according to claim 8, wherein: The sum of the length of the qth second connecting line on the second side, the length of the third compensation line connected thereto, and the length of the qth first connecting line on the second side is greater than the sum of the length of the qth second connecting line on the first side and the length of the qth first connecting line on the first side, where q is an integer greater than or equal to 1 and less than or equal to n; Preferably, the third compensation line is located on a side of the second side second connection line connected to the third compensation line away from the fan-out line; Preferably, p is equal to q; Preferably, the first connecting line and the second connecting line are arranged in different layers; Preferably, the second connecting line and the data signal line are arranged in the same layer.

10. The display panel according to claim 8, wherein Also included are n first-side fourth compensation lines; along the second direction, each first-side fourth compensation line and a first-side second connecting line are located on the same straight line, and the first-side fourth compensation line is insulated from the first-side second connecting line; Preferably, a third break is provided between the fourth compensation line on the first side and the second connecting line on the first side; Preferably, the fourth compensation line on the first side and the second connecting line are provided in the same layer; Preferably, the fourth compensation line on the first side is connected to a DC potential or a power supply voltage; Preferably, the display panel further includes n second-side fourth compensation lines; along the second direction, each second-side fourth compensation line and a second-side second connecting line are located on the same straight line, and the second-side fourth compensation line is insulated from the second-side second connecting line; Preferably, a fourth break is provided between the fourth compensation line on the second side and the second connecting line on the second side; Preferably, the fourth compensation line on the second side is provided in the same layer as the second connection line; Preferably, the fourth compensation line on the second side is connected to a DC potential or a power supply voltage.

11. The display panel according to claim 2, wherein: It also includes a first routing line extending along the second direction; along the first direction, the first routing line is arranged on a side of the Mth data signal line away from the M-1th data signal line; wherein M is the number of the data signal lines.

12. The display panel according to claim 11, wherein: The display panel further includes a plurality of second routing lines, the second routing lines extending along the second direction, and among the first n data signal lines, the second routing line is provided between two data signal lines located on one side and in the middle of three adjacent data signal lines, and no second routing line is provided between two data signal lines located on the other side and in the middle; Among the last n data signal lines, among three adjacent data signal lines, the second routing line is provided between the two data signal lines located on one side and in the middle, and no second routing line is provided between the two data signal lines located on the other side and in the middle; The second wiring is arranged between the first data signal line and the second data signal line along the first direction; Along the first direction, there is no second wiring between the Mth data signal line and the M-1th data signal line; The Mth data signal line and the M-1th data signal line are symmetrically arranged about a first axis along the second direction, and the first routing line and the second routing line adjacent to the first routing line are symmetrically arranged about the first axis; Preferably, the first wiring, the second wiring, and the data signal line are arranged on the same layer; Preferably, the first wiring is connected to a DC potential or a power supply voltage, and the second wiring is connected to a DC potential or a power supply voltage; Preferably, the first data signal line is used to transmit data signals corresponding to K1 pixels; the last data signal line is used to transmit data signals corresponding to K1 pixels, and at least part of the data signal lines located between the first data signal line and the last data signal line are each used to transmit data signals corresponding to K2 pixels; K1 and K2 are different positive integers; Preferably, K2 is greater than K1, Preferably, K2 is greater than or equal to twice of K1.

13. The display panel according to claim 2, wherein: The display panel further includes: substrate; a first conductive layer, disposed on one side of the substrate, wherein the first conductive layer includes the first connecting line; a second conductive layer, disposed on a side of the first conductive layer away from the substrate, the second conductive layer comprising the data signal line; the first connecting line and the data signal line are connected through a first via hole; Preferably, the second conductive layer further includes a second connecting line, the data signal line and the second connecting line are spaced apart; the second connecting line is connected to the first connecting line through a second via hole; Preferably, a distance in the first direction between the first via hole and the second via hole corresponding to the first connection line connected to the first data signal line is greater than a distance in the first direction between the first via hole and the second via hole corresponding to the first connection line connected to the last data signal line. Preferably, the first conductive layer and / or the second conductive layer includes a first sublayer, a second sublayer and a third sublayer stacked in sequence, the material of the first sublayer includes titanium, the material of the second sublayer includes aluminum, and the material of the third sublayer includes titanium.

14. The display panel according to claim 13, wherein: The display panel further includes: a third conductive layer, disposed between the substrate and the first conductive layer; a fourth conductive layer, disposed between the third conductive layer and the first conductive layer, wherein the fan-out line is disposed in the third conductive layer and / or the fourth conductive layer; Preferably, along the first direction, two adjacent fan-out lines are respectively arranged in the third conductive layer and the fourth conductive layer.

15. The display panel according to claim 1, wherein Except for the first n and last n data signal lines, the remaining data signal lines are correspondingly connected to the remaining fan-out lines, where n is greater than 0 and is a multiple of 4.

16. The display panel according to claim 1, wherein It also includes a plurality of columns of pixel circuits arranged along the first direction, each column of pixel circuits including a plurality of pixel circuits arranged along the second direction, Each of the data signal lines is connected to a corresponding column of the pixel circuits; the pixel circuits in the first column are connected to the first pixels in the first pixel column, and each of the pixel circuits in the remaining odd-numbered columns is connected to the first pixels in the two adjacent first pixel columns, or each of the pixel circuits in the remaining odd-numbered columns is connected to the second pixels in the two adjacent first pixel columns; The pixel circuit in an even column is connected to the third pixel in the second pixel column, and the pixel circuit in the last column is connected to the first pixel in the last column of the first pixel column, or the pixel circuit in the last column is connected to the second pixel in the last column of the first pixel column; Alternatively, each column of the pixels is connected to the pixel circuit in the same column, and the plurality of data signal lines include a first data signal line, a last data signal line, and a first data signal line, a second data signal line, and a third data signal line located between the first data signal line and the last data signal line and arranged along the first direction; along the first direction, the first data signal line is connected to the pixel circuit connected to the first pixel in the first pixel column in the first column, each of the first data signal lines is connected to the pixel circuit connected to the first pixel in two adjacent columns of the first pixel columns; each of the second data signal lines is connected to the pixel circuit connected to the second pixel in two adjacent columns of the first pixel columns; each of the third data signal lines is connected to the pixel circuit connected to the third pixel in a column of the second pixel columns; the last data signal line is connected to the pixel circuit connected to the first pixel in the last column of the first pixel columns, or the last data signal line is connected to the pixel circuit connected to the second pixel in the last column of the first pixel columns; Preferably, the pixel circuits connected to two adjacent columns of the first pixel columns are connected to the three data signal lines; Preferably, along the first direction, the structures of the pixel circuits in two adjacent columns are symmetrical.

17. A display panel, characterized in that: The display panel includes a display area and a non-display area; the display panel also includes: N pixel columns are located in the display area, the N pixel columns are arranged along a first direction, and the pixel columns include a plurality of pixels arranged along a second direction; N is an integer greater than 1; the N pixel columns include pixels of multiple luminous colors; M data signal lines are arranged along the first direction and extend along the second direction, the M data signal lines being used to transmit data signals corresponding to the pixels in the N pixel columns; each data signal line is used to transmit data signals corresponding to the pixels of one luminous color; M is an integer greater than N; the M data signal lines include a first edge data signal line and a second edge data signal line located on outermost sides, the first edge data signal line and the second edge data signal line being located on opposite sides of the display area along the first direction; a plurality of connection lines, at least part of which is located in the display area, and the first edge data signal line and the second edge data signal line are connected to different connection lines; A plurality of fan-out lines are located in the non-display area; the first edge data signal line and the second edge data signal line are connected to the corresponding fan-out lines via the corresponding connection lines.

18. The display panel according to claim 17, wherein: M is 1 greater than N; Preferably, the display panel further comprises M columns of pixel circuit columns arranged along the first direction, each of the pixel circuit columns comprising a plurality of pixel circuits arranged along the second direction, the M columns of pixel circuit columns being connected to the M data signal lines, and the M columns of pixel circuit columns being connected to N columns of pixel columns; Preferably, the first edge data signal line is used to transmit data signals corresponding to K1 pixels; the second edge data signal line is used to transmit data signals corresponding to K1 pixels; Each of at least a portion of the data signal lines located between the first edge data signal line and the second edge data signal line is used to transmit data signals corresponding to K2 pixels, where K1 and K2 are different positive integers. Preferably, K2 is greater than K1, Preferably, K2 is greater than or equal to twice of K1.

19. The display panel according to claim 17, wherein: The N pixel columns include a plurality of first pixel columns and a plurality of second pixel columns alternately arranged along the first direction, the first pixel columns include a plurality of first pixels and a plurality of second pixels alternately arranged along the second direction, and the second pixel columns include a plurality of third pixels arranged along the second direction; the first pixels, the second pixels, and the third pixels emit light of different colors; Each of the data signal lines is connected to a corresponding column of the pixel circuits; the pixel circuits in the first column are connected to the first pixels in the first pixel column, and each of the pixel circuits in the remaining odd-numbered columns is connected to the first pixels in the two adjacent first pixel columns, or each of the pixel circuits in the remaining odd-numbered columns is connected to the second pixels in the two adjacent first pixel columns; The pixel circuit in an even column is connected to the third pixel in the second pixel column, and the pixel circuit in the last column is connected to the first pixel in the last column of the first pixel column, or the pixel circuit in the last column is connected to the second pixel in the last column of the first pixel column; Alternatively, each column of the pixels is connected to the pixel circuit in the same column; the plurality of data signal lines include a first data signal line, a last data signal line, and a first data signal line, a second data signal line, and a third data signal line located between the first data signal line and the last data signal line and arranged along the first direction; the first data signal line is connected to the pixel circuit connected to the first pixel in the first pixel column in the first column, each of the first data signal lines is connected to the pixel circuit connected to the first pixel in two adjacent columns of the first pixel column; each of the second data signal lines is connected to the pixel circuit connected to the second pixel in two adjacent columns of the first pixel column; the third data signal line is connected to the pixel circuit connected to the third pixel in a column of the second pixel column; and the last data signal line is connected to the pixel circuit connected to the first pixel or the second pixel in the last column of the first pixel column; Preferably, the pixel circuits connected to two adjacent columns of the first pixel columns are connected to the three data signal lines; Preferably, along the first direction, the structures of the pixel circuits in two adjacent columns are symmetrical.

20. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 19.

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