System and method for entering and exiting low power mode for aggregator-disperser

Abstract

Various embodiments discussed herein relate to circuitry for enabling a low-power, low-latency virtual pipe input / output line to seamlessly connect two substrates together. A virtual pipeline engine (VPE) operates to cycle between a low power mode and an active mode in which the VPE operates to process signals received on several ports for delivery to paired VPIO lines according to a port mapping scheme. A port activity detection line coupled to the plurality of ports is operative to instruct the VPE to exit a low power consumption mode or remain in an active mode in response to any signal activity on any of the plurality of first ports. A low power mode detection line is coupled to the port activity detection line and receives a data stream processed by the VPE or the paired VPIO line, operative to instruct the VPE to enter the low power mode when a low power mode condition is detected.

Description

Related applications

[0001] This patent application claims the benefit of Indian Provisional Patent Application No. 202241067627 filed on November 24, 2022, which is incorporated by reference in its entirety. Background Art

[0002] Electronic devices can include multiple printed circuit boards (PCBs) to accommodate various integrated circuits, connectors, and other components. When two or more PCBs are used, an interposer is typically used to connect one PCB to the other. When the two PCBs are connected, the interposer uses a combination of vias and pins to interface with each other. The number of pins and vias on the PCBs can be substantial (e.g., hundreds or more), and as a result, a significant amount of real estate on both PCBs can be consumed. Furthermore, many electronic devices can communicate using a variety of different protocols. Each of these protocols requires a dedicated interposer connection, potentially leading to excessive wires, protocols, mechanical connectors, signal integrity issues (e.g., electrostatic discharge, electromagnetic interference, crosstalk, radio frequency interference, etc.), physical links (PHYs), and / or power consumption. Consequently, supporting more protocols requires additional hardware and software components, increasing costs and real estate requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] FIG. 1 shows two legacy circuit substrates designed for a substrate-to-substrate connection connected via a conventional interposer.

[0004] Figures 2A to 2C Different exemplary circuit substrates are shown employing configurations of VPIO lines according to various embodiments discussed herein for a substrate-to-substrate connection.

[0005] Figure 3A Two exemplary circuit substrates are shown configured for a substrate-to-substrate connection using interposer sockets / through-holes, connectors, and VPIO lines according to various embodiments discussed herein.

[0006] Figure 3B Shows various embodiments discussed herein. Figure 3A An alternative to the circuit shown.

[0007] Figure 4 A system or device is shown including two printed circuit substrates having devices and circuits in communication with each other, according to some embodiments.

[0008] Figure 5Another system or device is shown that includes two printed circuit substrates having devices and circuits in communication with each other, according to some embodiments.

[0009] Figure 6A A schematic VPIO circuit according to an embodiment is shown.

[0010] Figure 6B FIG. 4 shows a schematic low power exit and low power entry circuit according to an embodiment.

[0011] Figure 7A A schematic circuit diagram of a port activity detection circuit according to an embodiment is shown.

[0012] Figure 7B A schematic timing diagram according to an embodiment is shown. Figure 7A The port activity detection line is running.

[0013] Figure 8A An alternative port activity detection circuit is shown according to one embodiment.

[0014] Figure 8B A schematic timing diagram according to an embodiment is shown. Figure 8A The port activity detection line is running.

[0015] Figure 9 A schematic bidirectional port activity detection circuit according to an embodiment is shown.

[0016] Figure 10 FIG. 4 shows an exemplary port activity detection circuit according to an embodiment.

[0017] Figure 11 FIG. 4 shows an exemplary port activity detection circuit according to an embodiment.

[0018] Figure 12 FIG. 4 shows an exemplary port activity detection circuit according to an embodiment.

[0019] Figure 13 A schematic low power mode detection circuit according to an embodiment is shown.

[0020] Figure 14A A schematic process according to an embodiment is shown.

[0021] Figure 14B Shows additional steps according to an embodiment, which can be used as Figure 14A step part of the .

[0022] Figure 15A A schematic process according to an embodiment is shown.

[0023] Figure 15B Shows additional steps according to an embodiment, which can be used as Figure 15A A step in the process.

[0024] Figure 16 A schematic process for exiting and entering a low power consumption mode according to an embodiment is shown.

[0025] Figure 17 A schematic flow chart for determining when to enter a low power consumption mode according to an embodiment is shown. DETAILED DESCRIPTION

[0026] Illustrative embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which representative examples are shown. Indeed, the disclosed communication systems and methods may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout.

[0027] In the detailed description that follows, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the various embodiments. Those skilled in the art will appreciate that these various embodiments are merely illustrative and are not intended to be limiting in any way. Other embodiments will readily suggest themselves to those skilled in the art having the benefit of this disclosure.

[0028] In addition, for clarity purposes, all conventional features of the embodiments described herein are not shown or described. Those of ordinary skill in the art will readily recognize that in the development of any such actual embodiment, many embodiment-specific decisions may be required to achieve specific design goals. These design goals will vary from one embodiment to another and from one developer to another. Furthermore, it will be appreciated that such development efforts may be complex and time-consuming, but for those of ordinary skill in the art who benefit from this disclosure, this will still be a routine engineering task.

[0029] Various embodiments discussed herein relate to systems, methods, and circuits for a virtual pipe input / output (VPIO, or virtual pipe I / O) IC, circuitry, circuit, function block, system, or module that includes one or more virtual pipe engine (VPE) circuits that facilitate data transfer for multiple communication ports (also referred to as "ports") between two or more printed circuit boards while adhering to strict maximum power consumption requirements. The VPIO circuits can function as an extremely low-power aggregator-disperser with a high level of configurability to facilitate deployment and routing between two printed circuit boards. The aggregator-disperser can function by aggregating any number of signals or protocols provided on any number of input ports onto fewer or just one conductor than the number of input ports, transmitting the aggregated data across a medium, dispersing the aggregated data, and recreating a copy of the original signal or protocol for delivery to an output port. The medium represents a connection (e.g., a wired connection or a wireless connection) between the aggregator and the disperser, wherein the aggregator resides on a first circuit substrate and the disperser resides on a second circuit substrate. The aggregation and dispersion occur with extremely low latency and power consumption. The advanced configurability is achieved by electronically remapping any of a plurality of signals or protocols on a plurality of input ports to any of a plurality of output ports. That is, the plurality of input ports may have specific positions and trace routing optimized for the circuit substrate to which the plurality of input ports are affixed, while the plurality of output ports may have completely different positions and trace routing best suited for the circuit substrate to which the plurality of output ports are affixed. This remapping enables the aggregator side (e.g., the plurality of input ports) and the disperser side (e.g., the plurality of output ports) to maintain their optimal positioning and trace routing, as any signal or protocol can be remapped port-to-port or grouped port-to-grouped port. This maximizes configurability and flexibility by leveraging the relative positions of ports or grouped ports on the disperser and aggregator.

[0030] VPIO circuitry can significantly reduce the number of ports on one or more connectors or interposers between one PCB and another, one box and another, and so on. Furthermore, VPIO circuitry provides configurability and flexibility through port mapping and ganged port mapping. By enabling the selective routing of multiple input ports to multiple output ports with minimal power penalty, VPIO circuitry can effectively replace standard interposer or standard connector type connections within a device or system. An interposer or standard connector type is typically associated with zero (or near-zero) power penalty because the connection is a direct port-to-port wired connection. In contrast, VPIO circuitry eliminates the need for individual port-to-port wired connections implemented by an interposer or wired connector, but requires power to operate an aggregator-disperser with a port mapping scheme. The power required to operate VPIO circuitry is extremely low and is designed to have a small or negligible impact on the power budget of the system in which it is implemented. For example, in one embodiment, the average power consumption of a pair of VPIO circuits is less than 10 mW. A typical range for average power consumption depends on the signal speed applied to the multiple ports, the number of low-speed, medium-speed and high-speed signals / port and the activity level on each signal / port and can range from well from 1 uW to 100 mW.

[0031] This low power consumption is achieved by implementing a clockless design that supports a sleep-centric, repetitive cycle of alternating between sleep and active modes, eliminating continuous power cycling. As defined herein, a clockless design can refer to a circuit that exits a low-power mode without requiring a clock signal from a clock source, such as an oscillator. That is, the VPIO circuit remains in a sleep mode when there is no activity, and transitions to active mode upon request in response to an activity event (e.g., a data transition provided on one of multiple input ports). While in active mode, data is quickly transferred from the aggregator to the disperser, and then the VPIO circuit quickly transitions back to sleep mode. The VPIO lines can participate in a repetitive cycle of communicating data from one substrate to another by: (1) staying in a sleep mode as much as possible, (2) detecting exit from the sleep mode, (3) quickly transitioning to an active mode, (4) receiving multiple input signals on multiple input ports, (5) intelligently aggregating the received multiple input signals, (6) transmitting the aggregated multiple input signals through a high-speed serial link, (7) receiving the aggregated multiple data signals via the high-speed serial link, (8) dispersing the received aggregated multiple data signals, (9) creating a copy of the multiple input signals, (10) outputting the copied multiple input signals to multiple output ports, and (11) quickly transitioning to the sleep mode.

[0032] As defined herein, sleep mode refers to a low-power mode in which the VPIO circuit is inactive and consumes minimal power.

[0033] As defined herein, active mode refers to a mode in which the VPIO lines are actively aggregating and transmitting data or receiving and distributing data and consuming power to do so.

[0034] As defined herein, instantaneous power consumption refers to the amount of energy consumed at any given moment in time. Instantaneous power consumption can fluctuate from low to high. Power consumption can be relatively high during full activity or nearly zero during sleep mode or a low-power mode.

[0035] As defined herein, average power consumption is the average of active, sleep, and low-power modes over a period of time. Average power can be calculated as: % Active Time * Active Power Consumption (mW) + % Low Power Time * Low Power Consumption (mW). % Active Time and % Low Power Time are application- and use-case-specific. To optimize power consumption, % Active Time and % Active Power (mW) should be minimized.

[0036] VPIO circuitry includes one or more virtual pipe engine (VPE) circuits that facilitate data transfer between multiple communication ports (also referred to as "ports") on two or more printed circuit boards or two or more devices while adhering to strict maximum power consumption requirements. Each board may include a virtual pipe I / O circuit, wherein the virtual pipe I / O circuit provides an interface between multiple ports of the coupled boards. Each VPE aggregates data from multiple ports using one or more different communication protocols according to a configurable or "universal" communication protocol and transmits the aggregated data over a wired or wireless communication link (or "virtual pipe"). VPIO circuitry allows a system to aggregate low-speed and high-speed industry standard and proprietary protocols for simultaneous transmission over one or more links using the configurable or universal communication protocol. The configurable or universal communication protocol can be firmware programmable to define the order in which data to be transmitted is input to and received data is output from multiple ports or groups of ports.

[0037] In a transmitter mode, the VPE circuit refers to the order or mapping of the ports (or groups of ports) as defined by the firmware to generate output data according to the communication protocol by selecting input data from the multiple ports according to the order or mapping of the multiple ports. In a receiver mode, the VPE circuit refers to the order of the multiple ports as defined in the firmware to disperse the data received from the communication link into output data for each of the multiple ports. The multiple ports can use different communication protocols. The mapping of the multiple ports can be configurable based on the speed or other performance of the multiple ports. In addition, the limitations caused by using multiple (for example, legacy or standard) protocols, physical layers or mechanical connectors are reduced. The pin mapping table can be programmed in a permanent manner or undergo changes before data is transmitted, or can be dynamically reprogrammed during data transmission. The VPE circuit can monitor changes in the requirements of the application or the data being transmitted and update the slot table accordingly.

[0038] Figure 1 illustrates two legacy circuit substrates designed for a substrate-to-substrate connection, connected via a conventional interposer. Figure 1 shows substrate 10, with interposer pins / vias 12 surrounding the perimeter of substrate 10 and components 13 and 14. Substrate 10 may also include circuitry 15, 16, 17, 18, 19, 20, and 21. Components and circuitry may refer to various circuits, including, but not limited to, processors, memory, graphics processors, power management, and RF circuitry. Figure 1 also shows substrate 30, with interposer pins / vias 32 surrounding the perimeter of substrate 30 and component 33. Substrate 30 may also include circuitry 35, 36, 37, 38, 40, and 41. When substrate 10 is secured to substrate 30, interposer pins / vias 12 and interposer pins / vias 32 form an electrical connection between substrates 10 and 30 via one or more interposer interfaces (not shown). In other words, substrate 10 may be soldered to an interposer (not shown), which itself may be soldered to substrate 30. The interposer pins or through-holes align with the pins or through-holes of the two substrates 10 and 30 to achieve effective electrical contact. It should be understood that the number and location of interposer pins / through-holes, as well as the components and circuitry, are merely illustrative, and any suitable number of interposer pins / through-holes, components, and circuitry may be employed. For illustrative purposes, the entire surface area of ​​each substrate 10 or 30 is defined as area A1.

[0039] Figure 2A Two exemplary circuit substrates are shown for substrate-to-substrate connections using interposer pins / vias and VPIO lines according to various embodiments discussed herein. Additionally, for comparison, the same components and lines as those included in FIG. 1 are included in FIG. Figure 2AVPIO lines 211 on substrate 210 and VPIO lines 231 on substrate 230 eliminate many of the interposer pins / vias required on substrates 10 and 30 of FIG. 1 . Furthermore, the use of VPIO lines 211 and 231 enables the rearrangement of devices 13, 14, 33, and 34 and lines 15 and 35, and reduces the overall substrate area required for substrates 210 and 230 compared to substrates 10 and 30. When substrate 210 is connected to substrate 230, VPIO lines 211 interface with VPIO lines 231, and interposer pins / vias on substrate 210 interface with interposer pins / vias on substrate 230. For illustrative purposes, the total area of ​​substrates 210 and 230, viewed individually, is A2, where A2 is less than A1.

[0040] Figure 2B Similar to Figure 2A The difference is that the line 212 and the VPIO line 232 use one or more interposer pins / vias 12, 32 to communicate with each other. This is different from the direct interface between the VPIO line 211 and the VPIO line 231. Figure 2A Create a contrast.

[0041] Figure 2C Similar to Figure 2A and Figure 2B 2. A substrate-to-substrate connection is shown, wherein the difference is that VPIO line 213 is connected to connector 215 and VPIO line 233 is connected to connector 235, and the two connectors 215 and 235 are connected to each other when the two substrates 210 and 230 are connected. In some embodiments, connectors 215 and 235 can be wired connectors. In other embodiments, connectors 215 and 235 can be wireless connectors (e.g., 60 GHz extremely high frequency connectors).

[0042] It should be recognized that although Figures 2A to 2C While different VPIO connections between the two substrates are discussed (e.g., direct VPIO line connections, connections using connectors, and connections using pins / vias), other connectors can exist on substrates 210 and 230 independently of any VPIO line. The implementation of VPIO lines according to various embodiments discussed herein can eliminate extraneous connectors and pins / vias. This is made possible by the aggregation-dispersion feature of each VPIO circuit.

[0043] Figure 3A Two exemplary circuit substrates are shown for substrate-to-substrate connections using interposer sockets / through-holes, connectors, and VPIO lines according to various embodiments discussed herein. Figures 2A to 2CIncludes the same components and circuits as included in Figure 3A The inclusion of VPIO lines 321, 322, 323 on substrate 310 and VPIO lines 341, 342, 343 on substrate 330 can eliminate all or nearly all of the interposer pins / vias required on both substrates 10 and 30 of FIG. 1 . Furthermore, the use of VPIO lines 321, 322, 323, 341, 342, 343 enables the rearrangement of devices 13 and 14, lines 15 to 21, devices 33 and 34, and lines 35 to 41, and can reduce the overall board area required for substrates 310 and 330 compared to substrates 10 and 30 (and substrates 210 and 230). When substrate 310 is connected to substrate 330, VPIO line 321 can interface directly with VPIO line 341. VPIO line 322 can be connected to connector 325, and VPIO line 342 can be connected to connector 345. When the two substrates 310 and 320 are connected, VPIO lines 322 and VPIO lines 342 can communicate with each other via two connectors 325 and 345, which can be wired or wireless connectors. VPIO lines 323 can communicate with VPIO lines 343 using one or more pins / vias 12 through an interposer (not shown) connected to one or more pins / vias 32. Interposer pins / vias 12 of substrate 310 can interface with interposer pins / vias 32 of substrate 330. For illustrative purposes, the entire area of ​​substrates 310 and 330, viewed individually, is area A3, where A3 is less than A2. As will be appreciated, any combination of direct VPIO circuit-to-circuit, VPIO-to-connector, and VPIO-to-pin / via can be implemented.

[0044] Figure 3B Shown with Figure 3A An illustrative circuit board configuration is similar but with all pins / vias eliminated and VPIO lines 322, 324, 342, 344 connected to respective connectors 325, 326, 345, 346. Connectors 325, 326, 345, 346 can be wired or wireless connectors. Figure 3B and Figure 3A Another difference is that the VPIO lines 321, 341 have been eliminated.

[0045] One benefit of including VPIO circuitry according to various embodiments is that it frees up substrate space that would otherwise be occupied by interposer pins / vias or connectors. As discussed herein, the VPIO circuitry is designed and operative to meet the latency and power requirements of a system that traditionally employs interposer pins / vias for substrate-to-substrate communication. In particular, the VPE enables the VPIO to emulate the functionality of an interposer pin / via or connector by mapping any protocol pin (e.g., a GPIO, I2C, SPI, or UART) received by a first VPIO circuit (e.g., on a first circuit substrate) to a corresponding protocol pin on a second VPIO circuit (e.g., on a second circuit substrate). The VPIO circuits and VPEs accomplish this by abstracting the link layer associated with the protocol pins into a format that can be processed by the VPE, wherein the VPE serializes and / or encodes data received from the protocol pins before transmitting it via a wired connection to another VPIO circuit, which has a respective VPE to decode the encoded data and provide the decoded data to the corresponding protocol pins. In another embodiment, the VPE may include an aggregator and serializer but no encoder, and the paired VPIO module may not have a decoder. To ensure low latency when using VPIO circuits to replace interposer pins / vias or connectors, the VPE may implement a pin mapping scheme and an interface mapping scheme to preset pin-to-pin / protocol-to-protocol correlations for systems using VPIO circuits. In addition, the VPE may also implement a low-power exit and entry scheme to quickly power up the VPIO circuits, perform necessary data transactions, and quickly power down the VPIO circuits.

[0046] Figure 4 A system or device 400 is shown that includes two printed circuit substrates 402 and 404 having devices and lines for communicating with each other, according to some embodiments. Printed circuit substrate 402 may include a master device 406, a virtual pipe I / O 408, and a wired coupler 410. Printed circuit substrate 404 may include a slave device 412, a virtual pipe I / O 414, and a wired coupler 416. For example, wired couplers 410 and 416 can be a wired connection, a connector, or an interposer that connects pins and vias in the two substrates 402 and 404. In some embodiments, couplers 410 and 416 can enable a direct connection between VPIO line 408 and VPIO line 414. In another embodiment, couplers 410 and 416 can be wireless couplers that enable contactless communication at very high frequencies (e.g., 60 gHz).

[0047] The host device 406 can be coupled to a virtual pipe I / O 408, and the virtual pipe I / O 408 is coupled to a wired coupler 410. The virtual pipe I / O 408 is an integrated circuit separate from the host device 406 and the wired coupler 410. The host device 406 can include one or more processors 418 (e.g., a host processor, such as a system on a chip (SOC)), peripheral circuits (not shown), and multiple data link layers (links), such as link 420a and link 420b. In some embodiments, the processor 418 and the links 420a and 420b are connected via the circuit substrate 402. The virtual pipe I / O 408 is connected to the links 420a and 420b on the circuit substrate 402. If desired, the virtual pipe I / O 408 can be integrated with various types of host devices 406 without requiring modifications to the host device 406. Each link 420a, 420b is a circuit that encodes bits into packets before transmission and decodes received packets back into bits. It can provide reliable data delivery by transmitting packets with necessary synchronization, error control, and flow control, and can provide logical link control, media access control, hardware addressing, error detection, and interface with the physical link (PHY). Each link 420a, 420b can be divided into sublayers, including but not limited to the media access control (MAC) sublayer and the logical link control (LLC) sublayer. Each link 420a, 420b can be a protocol layer (e.g., Layer 2) of the Open Systems Interconnection (OSI) model.

[0048] Each link 420a, 420b implements a method for enabling a port of the master device 406 to communicate with a slave device on the substrate 404. For example, the link 420a provides a port 462, and the link 420b provides another port 464. Although two ports 462, 464 are shown for simplicity, the master device 406 may include various numbers of ports. The ports may include ports for intra-system communication (e.g., substrate 402 communicates with substrate 404) or external communication, where the master device 406 communicates with a different system or device. The processor 418 may be coupled to each of the two links 420a, 420b to communicate via the two ports 462, 464. Different ports may use different protocols, including high-speed protocols and low-speed protocols. In some embodiments, one or more links 420a, 420b may be integrated with the processor 418 (e.g., as a driver).

[0049] Virtual pipe I / O 408 is a circuit that provides data transfer between host device 406 and virtual pipe I / O 414 of printed circuit substrate 404. Virtual pipe I / O 408 can operate in a transmitter mode, a receiver mode, or a transceiver mode. In transmitter mode, virtual pipe I / O 408 aggregates data from ports 462 and 464 of host device 406 for transmission via wired coupler 410. In receiver mode, virtual pipe I / O 408 parses data from wired coupler 410 for transmission to host device 406 via ports 462 and 464. In transceiver mode, virtual pipe I / O 408 operates as both a transmitter and a receiver. For example, one or more ports can be dedicated to transmission, while one or more other ports can be dedicated to reception.

[0050] The virtual pipe I / O 408 includes link abstraction layers (such as link abstraction layer 424a and link abstraction layer 424b), a virtual pipe engine (VPE) 426, and a transceiver (Tx / Rx) 428. The virtual pipe I / O 408 is coupled to the links 420a and 420b of the host device 406 via the link abstraction layers 424a and 424b of the virtual pipe I / O 408. Each link 420a and 420b of the host device 406 is coupled to a corresponding link abstraction layer 424a and 424b of the virtual pipe I / O 408 to connect a port to the VPE 426. Each link abstraction layer 424a and 424b can be adapted to communicate with the host device 406 via a transmission medium (such as a cable) suitable for the protocol used for the ports 462 and 464.

[0051] In some embodiments, each link abstraction layer 424a, 424b includes a physical layer (or PHY) that provides an electrical interface for connecting to a link 420a, 420b via a transmission medium (e.g., a cable); defines physical characteristics such as connections, voltage levels, and timing; and defines means for transmitting raw bits, rather than logical packets, over a physical link. The bit stream can be grouped into code words or code symbols and converted into a physical signal transmitted over the transmission medium. Each link abstraction layer 424a, 424b can include a standards-based PHY that includes PHY specifications for one or more standard protocols. Examples of standard protocols include Universal Serial Bus (USB), DisplayPort, I2C, GPIO, PCIe3, PCIe sideband, MIPI, or Next Gen Camera protocols. Each PHY can be a physical layer (e.g., Layer 1) of the Open Systems Interconnection (OSI) model.

[0052] VPE 426 is a circuit that controls the operation of virtual pipe I / O 408. VPE 426 is connected to multiple ports 462, 464 of master device 406 via link abstraction layers 424a, 424b. In transmitter mode, VPE 426 receives input data from each of ports 462, 464 and aggregates the input data to generate output data 466. In particular, VPE 426 generates output data 466 based on the selection of input data from ports 462, 464 according to an order of ports as defined in a mapping scheme. The aggregated output data 466 is provided to transceiver 428 for transmission by wired coupler 410 via a wired connection. In receiver mode, VPE 426 receives input data 468 from transceiver 428 and parses or disperses the input data 468 according to the order of the ports defined in the mapping scheme to generate output data for each of ports 462, 464. Input data 468 is transmitted to master device 406 via link abstraction layers 424a, 424b and links 420a, 420b via their respective ports. Input data 466 and output data 468 are transmitted to master device 406 via link abstraction layers 424a, 424b and links 420a, 420b via their respective ports. Figure 4 The input data 466 and the output data 468 are shown as being transmitted via separate connections to illustrate bidirectional data transfer, but in some embodiments, the input data 466 and the output data 468 may be transmitted using the same connection. Figure 4 4 and 5. Although shown as being transmitted via separate connections to illustrate bidirectional data transfer, in some embodiments, multiple input data 462 and output data 464 may be transmitted using the same connection.

[0053] The order of the ports in the mapping scheme defines a common communication protocol shared by the master device 406 and the slave device 412 for aggregating and parsing data transmitted through the virtual pipe I / O 408, 414. The common communication protocol integrates data from multiple ports that may employ different (e.g., standard) communication protocols. In some embodiments, the VPE 426 employs the common communication protocol to perform additional processing on the data, such as applying encryption, decryption, authentication, and / or error correction. The VPE 426 may define the order of the ports in the mapping scheme based on the bandwidth requirements of the application or the data being transferred, and may dynamically adjust (e.g., during data transfer) the order of the ports in the mapping scheme in response to changes in bandwidth requirements.

[0054] The transceiver 428 transfers data between the wired coupler 410 and the VPE 426. The transceiver 428 may include a transmitter with a serializer and a receiver with a deserializer. When operating as a transmitter, the serializer converts parallel streams of output data 466 from the VPE 426 into a serial stream of output data, which is transmitted to the wired coupler 410 for wired transmission. When operating as a receiver, the deserializer converts a serial input stream from the wired coupler 410 into a parallel stream of input data 468, which is transmitted to the VPE 426. In some embodiments, the virtual pipe I / O 408 may include separate transmitters and receivers.

[0055] Wired coupler 410 (along with wired coupler 416) provides a wired communication link between virtual pipe I / O 408 of substrate 402 and virtual pipe I / O 414 of substrate 404. Wired coupler 410 and wired coupler 416 can be wired connectors.

[0056] In some embodiments, wired coupler 410 and wired coupler 416 can be replaced by respective EHF couplers. An EHF coupler is an EHF communication device that includes an antenna for wireless transmission. The antenna can be configured to operate in an EHF spectrum (30 GHz to 300 GHz) and can be configured to transmit and / or receive electromagnetic signals via a communication link. In some embodiments, an EHF coupler can modulate transmitted data using a carrier signal and demodulate a received signal to generate received data.

[0057] The discussion regarding substrate 402 is applicable to substrate 404. For example, virtual pipe I / O 414 can operate in transmitter mode, receiver mode, or transceiver mode, just like virtual pipe I / O 408. When virtual pipe I / O 408 operates in transmitter mode, virtual pipe I / O 414 operates in receiver mode. Similarly, when virtual pipe I / O 414 operates in transmitter mode, virtual pipe I / O 408 operates in receiver mode. Thus, virtual pipe I / O 414 includes a transceiver 430 coupled to wire coupler 416 and a VPE 432 coupled to multiple link abstraction layers (such as link abstraction layer 434a and link abstraction layer 434b). Each link abstraction layer 434a, 434b is coupled to a respective link 438a, 438b of slave device 412. Slave device 412 includes links 438a, 438b providing ports 482, 484 and one or more processors 440. Two virtual pipes I / O 408 , 414 provide a communication link between the master device 406 and the slave device 412 .

[0058] Figure 5 A system or device 500 is shown including two printed circuit substrates 502, 504 having devices and circuits in communication with each other, according to some embodiments. Figure 5 Two different VPIO line configurations are shown: one is that the VPIO line exists independently of a subsystem or other integrated system existing on a printed circuit substrate (similar to Figure 4 and another is that the VPIO lines are integrated with a subsystem or some other integrated system present on a printed circuit substrate. Figure 5 An embodiment is shown in which two or more different pairs of VPIO lines (e.g., integrated VPIO lines and independent VPIO lines) can be included in a system or device to replace interposer sockets / vias. The integrated VPIO lines can provide a highly customized interconnect solution for a subsystem (e.g., a system on a chip), while the independent VPIO lines can provide a fast interconnect design and deployment solution. Figure 4 A simplified representation of the master device 506, VPIO line 508, wired coupler 510, wired coupler 516, VPIO line 514, and slave device 512 is included in Figure 5 5. The master device 506 can include one or more links 520 and one or more processors 518. The slave device 512 can include one or more links 538 and one or more processors 540. The VPIO lines 508 and VPIO lines 514 can each include their own link abstraction layer, a transmitter / receiver, and / or a VPE, all of which have been omitted to avoid cluttering the diagram.

[0059] VPIO integration is illustrated by a subsystem 540, a wired coupler 550, a subsystem 560, and a wired coupler 570. Subsystem 540 can include a processor 542, a link 544, and a VPIO line 546, and subsystem 560 can include a processor 562, a link 564, and a VPIO line 566. Here, VPIO line 546 and VPIO line 566 can be integrated logic devices of subsystem 540 and subsystem 560, respectively. Links 544 and 564 can be similar to Figure 4 The configuration of VPIO circuits 546, 566 may be similar to or different from the configuration of VPIO circuit 408 or VPIO 414. For example, each of VPIO circuits 546, 566 may include a VPE, transmitter / receiver, and link abstraction layer.

[0060] It should be understood that Figure 5The VPIO line pairs shown are merely illustrative, and additional pairs of any type may be added or a pair may be omitted. For example, two pairs of integrated VPIO circuits may exist within a device or system. As another example, two pairs of independent standing VPIO circuits and one pair of integrated VPIO circuits may exist within a device or system.

[0061] Figure 6A FIG. 6 shows an exemplary VPIO circuit 600 according to an embodiment. The VPIO circuit 600 is connected to a plurality of ports 601 and a transmitter / receiver 690 via a bidirectional consolidation circuit 603. The VPIO circuit 600 is Figures 2A to 2C 、 Figure 3A 、 Figure 3B 、 Figure 4 and Figure 5 An example of a VPIO circuit is shown. VPIO circuit 600 can include VPE 610, port activity detection circuit 650, and low power mode detection circuit 660. VPE 610 can include aggregator 612, encoder 614, port mapping coordinator 620, decoder 632, disperser 634, enabler 640, and disabler 642.

[0062] Preferably, the VPIO circuit 600 is kept in a low power or sleep mode as much as possible. Circuit 600 includes specific circuits that use several approaches to ensure minimal power consumption. In one approach, when in low power mode, circuit 600 can shut down all clocks or a subset of clocks (not shown). In another approach, the transition from low power to active power can occur almost immediately. This can be achieved using port activity detection circuit 650. In yet another approach, the transition from active power to low power can occur immediately. This can be achieved using low power mode detection circuit 660. In addition, the duration of active mode is minimized compared to the time spent in low power mode. This can be achieved by utilizing a high-speed communication link between two paired VPIO circuits that process data collectively. In yet another approach, the use of clocked functions in active mode can be minimized to minimize the dynamic power consumption that dominates in active mode. Its value is C*V 2 *f, where C is the capacitance, V is the supply voltage, and f is the clock frequency.

[0063] Typically, when VPE 610 exits sleep mode, one or more local clock oscillators can be awakened. The time used to wake up the local oscillators is preferably minimized because the longer it takes, the more likely VPE 610 is neither in active mode nor fully awakened, and energy is consumed unnecessarily. In some embodiments, VPIO line 600 can cyclically sleep and wake up using a ratio of 100:1, consuming power mostly within 1% of the time when active. However, if the time required to wake up the oscillators results in a sleep / wake cycle ratio of 50:1, this doubles the average power consumption. Thus, the longer it takes to transition into or out of a low-power mode, the more energy is wasted. Lines 650 and 660 are designed to minimize the amount of time required to enter and exit a low-power mode.

[0064] Multiple ports 601 can represent N ports connected to VPIO line 600 via bidirectional merging line 603. Transmitter / receiver (or transceiver) 690 can serially transmit and receive data over a high-speed bus. Transceiver 690 is connected to a high-speed link, either wired or wireless. Transmitter / receiver 690 can include a serializer 692 that converts data received as a parallel data stream into a serial data stream, which is sent as an output stream on bus 693; and a deserializer 694 that converts data received as a serial input data stream on bus 695 into a parallel data stream. In some embodiments, transceiver 690 can include a wakeup block 699 that causes serializer 692 to send a "wakeup" signal to its paired deserializer in another transceiver to activate operation of that other transceiver, which in turn can activate the VPIO line associated with that other transceiver. The wake-up block 699 can activate the VPE 610 by providing a signal to the enabler 640 in response to the deserializer 694 detecting a "wake-up" signal on the bus 695 (transmitted by a paired transceiver).

[0065] Multiple ports 601 can be connected to a port activity detection circuit 650, an aggregator 612, and a disperser 634 via a bidirectional merge circuit 603. Not shown in FIG6 is a link abstraction layer that can be associated with each port. An output of the port activity detection circuit 650 can be connected to an enabler 640 and to a low-power mode detection circuit 660. The low-power mode detection circuit 660 can be coupled to a high-speed transmit bus 693 and to a high-speed receive bus 695. An output of the circuit 660 can be connected to a disabler 642.

[0066] Port activity detection circuit 650 operates to detect activity on each of the plurality of ports 601 using clockless signal detection and, when any activity is detected on any of the plurality of ports 601, activate VPE 610. Circuit 650 can trigger enabler 640 to activate any state machine, clock, or other circuit within VPE 610 so that the functions of VPE 610 can be used to process data. Port activity detection circuit 650 can also detect activity on output 635 (which originates from disperser 634) via merge circuit 603.

[0067] In another embodiment, the port activity detection circuit 650 operates to detect activity on each of the plurality of ports 601 using a low power clocked signal.

[0068] In yet another embodiment, the port activity detection circuit 650 operates to detect activity on each of the plurality of ports 601 using a gated clocked signal. An enable signal that controls the gated clock may be activated based on a set of predetermined conditions. For example, an enable pin may be activated by a Figure 6A Driven by an upper function at the system level in the circuit, the enable pin can wait for incoming traffic in a predetermined time window. In one embodiment, the upper layer may have started a low-power timer that wakes up the enable signal after a certain period of time.

[0069] Circuit 650 is designed to quickly activate VPE 610 by transitioning VPE 610 from a sleep mode to an active mode. Figures 7A to 12Different circuit implementations of circuit 650 are described. The VPE 610 primarily remains in a sleep mode (e.g., a low power mode) unless the VPE 610 needs to process data. As explained above, keeping the VPE 610 in sleep mode minimizes the power consumed by the VPIO circuit 600. Additionally, the ability to quickly transition from active mode to sleep mode is another way to minimize power consumption. The low power mode detection circuit 660 operates to detect when the VPE 610 no longer needs to process data and can quickly disable the VPE 610 by asserting the disabler 642, which causes the VPE 610 to immediately enter sleep mode. Circuit 660 can cause the VPE 610 to be disabled when an end-of-frame signal is detected in both the Tx direction and the Rx direction (e.g., on the output stream 693 or the input stream 695) and there is no activity on any of the multiple ports 601. The following Figure 13 A circuit implementation of circuit 660 is described.

[0070] In response to detecting signal activity on any one or more of the plurality of ports 601, VPE 610 is activated by line 650 and aggregator 612 and programmable encoder 614 are activated to pass data from the plurality of ports 601 to transceiver 690, which serializes the data for transmission over bus 693. Aggregator 612 is coupled to the plurality of ports 601 and port mapping coordinator 620. Port mapping coordinator 620 can include a permanently configured mapping scheme that defines an order for the ports or a dynamically configurable mapping scheme. The mapping scheme can control a switch matrix that remaps a port on one substrate to another port on another substrate. In some embodiments, a data buffer (not shown) can receive input data 611 from the plurality of ports 601 and can store the input data 611. In some embodiments, the data buffer includes a first-in-first-out (FIFO) memory for each of the plurality of ports 601 to store the input data 611 received from the plurality of ports 601. According to the mapping scheme defined in the port mapping generator 620 , the aggregator 612 selects and aggregates the input data 611 received from the plurality of ports 601 (or from the FIFO memory of the data buffer) to generate output data 613 .

[0071] Programmable encoder 614 receives output data 613 from aggregator 612 and performs encoding or other processing to generate output data 615. In some embodiments, programmable encoder 614 performs authentication and / or error correction. In some embodiments, programmable encoder 614 can be bypassed, deactivated, or omitted in VPE 610. Transceiver 690 receives output data 615 and generates an output stream 693 for use with a wired connector or other communication device, such as an EHF coupler.

[0072] If data is received by transceiver 690, decoder 632 and disperser 634 can be activated to pass the received data to port 601. By coupling aggregator 612 and disperser 634 to multiple ports 601 via bidirectional merging lines 603, bidirectional communication between multiple ports 601 and transceiver 690 is enabled. Transceiver 690 receives a bus input stream 695 from a wired connector or other communication device (such as an EHF coupler). Deserializer 694 converts input stream 695 into a parallel stream of input data 631. Programmable decoder 632 receives input data 631 and decodes or otherwise processes it to generate input data 633. For example, input data 631 may be generated by another VPE in another VPIO circuit (e.g., on another substrate) that applies an encoding algorithm in its transmitter mode before transmission, and programmable decoder 632 may decode received input data 631 by applying a corresponding decoding algorithm. In some embodiments, programmable decoder 632 performs authentication and / or error correction. In some embodiments, the programmable decoder 6324 may be bypassed, deactivated, or omitted in the VPE 610 .

[0073] The disperser 634 receives input data 633 from the programmable decoder 632 and generates output data 635 by parsing the input data 633 according to the mapping scheme defined in the port mapping coordinator 620. The output data 635 is provided to the appropriate port 601. In some embodiments, the output data 635 can be stored in a data buffer that provides the output data 635 to the respective port 601. In some embodiments, the data buffer includes a FIFO memory for each port to store the output data provided to the plurality of ports.

[0074] Enabler 640 and disabler 642 may be part of a controller (not shown) that controls the operation of VPE 610. The controller can manage a state machine or clock that controls the operation of VPE 610. The controller can control operating modes including transmitter-only, receiver-only, or transceiver modes.

[0075] Figure 6B Shown according to some embodiments Figure 6A A simplified and alternative version of . Figure 6B and Figure 6A The main difference is that the VPIO line 600 and VPE 610 designations are removed and replaced by a generic aggregator-disperser module 608. Figure 6A The same reference numerals as those in the Figure 6B The devices in do not need to be re-explained. The aggregator-disperser module 608 can perform the same aggregation and dispersion functions as the VPE 610, can be instructed to exit the low power mode by the port activity detection circuit 650, and can enter the low power mode through the low power mode detection circuit 660. The port mapping coordinator can maintain a port mapping scheme for the aggregator-disperser module 608. The detection circuit 650 has been changed to include a toggle detection circuit 651 and an exit low power detection circuit 652, because these two circuit devices can jointly enable the port activity detection circuit 650 to operate. The toggle detection circuit 651 can be used to detect signal activity on a port. An example of the toggle detection circuit 651 is shown below together with Figure 7A 、 Figure 8A and Figure 9 Discussion. The exit low power detection circuit 652 may be used to instruct the aggregator-disperser module 608 to exit low power. An example of the exit low power detection circuit 652 is described below in conjunction with Figure 10 and Figure 11 discuss.

[0076] Figure 7A A schematic circuit diagram of a portion of a port activity detection circuit 700 according to one embodiment is shown. For example, the circuit 700 can be connected to Figure 10 Line 1000 or Figure 116 . In some embodiments, circuit 700 is referred to herein as a switch detection circuit because it is designed to detect a signal transition or signal activity on any given port. Circuit 700 can detect a change in state at input signal Pin_K 701 without utilizing any internal or external clock, which advantageously minimizes power consumption in low power or sleep modes. Pin_K 701 is connected to a port (e.g., one of multiple ports 601). Thus, a separate circuit 700 is included for each port connected to a VPIO line. For example, if fifty (50) ports are routed to a VPIO line, fifty (50) separate instances of circuit 700 are required. A D flip-flop 702 is connected to the pin of input signal Pin_K 701. The flip-flop output 703 is connected to a first input of an exclusive OR (XOR) gate 704. A second input of the exclusive OR gate 704 is connected to the input signal 701. An output 705 of XOR gate 704 is connected to the clock input of flip-flop 702. Output 705 also provides the Pin_K_Toggle_ON signal for quickly waking up a VPE (e.g., VPE 610). Assume that flip-flop 702 is reset and its output 703 is initially "0." When the input signal is "0," output 705 is "0." If input signal 701 causes its state to change to "1," XOR gate 704 compares input 701 with the "0" at flip-flop output 703 and causes its output to change to "1" at output 705. This positive "0" to "1" transition is applied to the clock input of flip-flop 702 and causes flip-flop 702 to change its output state 703 to "1." XOR gate 704 compares the "1" provided by input signal 701 with the "1" provided by output signal 703 and causes output 705 to change back to "0." When a negative transition at output 705 changes from "1" to "0," the "0" applied to the clock input of flip-flop 702 does not cause the state of flip-flop 702 to change, and therefore its output 703 remains at "1." The result at output Pin_K_Toggle_ON 705 is a pulse "010" that signals that a transition has been detected at Pin_K 701. Furthermore, if input signal 701 later returns to "0," the XOR gate outputs a positive transition to "1" at output 705 because flip-flop output 703 is still "1." This positive transition activates flip-flop 702, and output 703 changes to "0." As a result, output 705 of XOR gate 704 transitions back to "0." At this point, either a positive or negative transition at input signal 701 creates a pulse at output 705 of circuit 700.

[0077] Figure 7BA schematic timing diagram illustrating the operation of the port activity detection circuit 700 according to one embodiment is shown. Figure 7B 701, flip-flop output 703, and XOR gate output 705 are traced. At time t0, all three signals 701, 703, and 705 are "0." At time t1, input signal 703 transitions from state "0" to "1." This transition causes output signal 705 to transition from state "0" to "1." The "1" is fed back to the clock input of flip-flop 702, which causes output 703 to transition from "0" to "1." When the "1" from input signal 701 and the "1" from output signal 703 are input to XOR gate 702, XOR gate output 705 transitions from "1" to "0." The two signals 705 and 703 remain fixed until a new change of state occurs at input 701 at time t2, which is shown as a "1" to "0" negative transition. At this point in time, XOR gate 704 has "0" and "1" at its two inputs, and its output 705 transitions back to "1," and the pulse cycle begins again.

[0078] Figure 8A An alternative port activity detection circuit 750 is shown according to one embodiment. Circuit 750 is similar to circuit 700, but with the addition of a processing device 751 between the XOR gate output 705 and the clock input of the flip-flop 702. Circuit 750 operates substantially the same as circuit 700, except that processing device 751 increases the duration of the "010" pulse by extending the duration of the "1" portion of the pulse. This provides additional time for the VPIO line to detect the "010" transition and activate the necessary components. In some embodiments, processing device 751 can include a delay element, a state machine, a clock gating delay, a de-glitcher, a glitch filter, a noise filter, a minimum pulse length detector, a pulse handler, and a processing unit. By delaying the assertion of the "1" signal from being applied to the clock input 757 of the flip-flop 702, processing device 751 extends the "1" portion of the "010" pulse. Figure 8B A schematic timing diagram is shown showing how a “010” pulse is stretched using a processing device 751 in a circuit 750 according to an embodiment.

[0079] Figure 9 An exemplary bidirectional port activity detection circuit 900 is shown according to one embodiment. Circuit 900 can be considered herein as a switching detection circuit that operates to detect signal activity on a port. Circuit 900 can be used in applications where bidirectional communication is required and a status code of the signal state must be maintained on both the master and slave sides (such as, for example, Figure 4In an embodiment of a VPIO circuit maintained on a master substrate and a slave substrate (as shown in FIG. 2 ), bidirectional means that communication flows in both directions, from master to slave or vice versa. An example of a bidirectional signal is the I2C protocol. The I2C bus includes a clock signal and a data signal. The clock can be held from two or more sides and communication flows sequentially in several directions. For such a signal or protocol, paired VPIO circuits (e.g., VPIO 408 and VPIO 414) require a single wire or bus to be reconnected in each VPIO circuit to allow communication in either direction.

[0080] For example, port 901 can be a general-purpose input / output (GPIO) port. GPIO ports are typically associated with a signal with a low to medium communication speed. The direction of communication is left-to-right from port 901 to debounce circuit 902, D flip-flop 903 having output 905 and clock 907, and XOR gate 904 having inputs from debounce circuit 902 and flip-flop 903. The debounce circuit is activated by control signal 908. Across the right-to-left communication path, signal 909, D flip-flop 914 having output signal 918, signal 911, AND gate 915 having output signal 919, signal 912, NOR gate 916 having output signal 920, driver 917, and port 901. D flip-flop 914 can be activated by signal 910, and driver 917 has a slew rate determined by signal 913. The value driven to pin 901 by driver 917 is determined by output 918 of D flip-flop 914. When signal 912 is high, driver 917 is disabled, and NOR gate 916 is operated to drive output 920 low, enabling driver 917. When signal 911 is high and signal 912 is low (allowing the driver to be enabled), the driver is enabled, wherein when output 918 of D flip-flop 914 is zero, output 901 has a value of zero. When D flip-flop 914 has a value of one, output 919 of AND gate 915 is one, which causes output 920 of NOR gate 916 to be zero, disabling the driver. This causes pin 901 to 'float,' or follow any input signal present at the pin. This is conventionally used for "wired AND" or "OR-tied" buses, in which multiple devices (including a device such as port 901) can participate in bidirectional communication by simply driving the bus low or not driving it, where the bus is "floating" high through a resistor pulling the bus to one.

[0081] The debounce circuit 902 is used to prevent up or down switching when a noisy signal or a signal with a slow transition slope is provided as an input. The debounce circuit 902 can be used to smooth or ignore fast input changes using a digital or analog low pass filter. The debounce circuit 902 can also include a Schmitt trigger to avoid output chatter when the input 901 or the subsequently filtered signal has a slow rise time. The debounce circuit 902 can be deactivated using signal 908 to improve response time. Figure 8A Similar to the processing block 751 of circuit 750 performed externally, flip-flop 903 and XOR gate 904 collectively serve to confirm that the change registered by D flip-flop 903 and XOR gate 904 has been consumed by the VPIO line and thus transmitted. Clock signal 907 is used by D flip-flop 903 to copy the input value at pin 901, filtered by debounce circuit 902, to output 905, clearing the change condition indicated by output 906 of XOR gate 904.

[0082] Figure 10 An exemplary port activity detection circuit 1000 according to one embodiment is shown. For example, circuit 1000 can be used in conjunction with toggle detection circuits 700, 750, 800, and 900. Circuit 1000 employs a clockless design to minimize power consumption and provide a signal that can cause a VPIO line to exit a low-power or sleep mode. Circuit 1000 can include an OR gate 1010 that receives N number of Toggle_ON outputs from N instances of circuits 700, 750, 800, or 900 as multiple inputs and generates an output signal 1012, which is provided to the S input of an RS flip-flop 1020. RS flip-flop 1020 can receive an end-of-frame signal or an enter low-power signal at its R input. An end-of-frame signal can be included at the end of a packet in a serial stream transmitted or received by a transceiver (e.g., transceiver 690). An enter low-power signal can be received from a low-power mode detection circuit (e.g., circuit 660).

[0083] During operation, when a port has signal activity, the signal activity is detected by a respective one of lines 700, 750, 800, or 900 (which outputs a "010" pulse). This pulse is fed to the S input of SR flip-flop 1020 and causes output 1022 of SR flip-flop 1020 to go to "1" when "1" is applied to the S input. When the end-of-frame signal or the signal to enter low power has been detected, the R input is "0." Output 1022 is an "exit low power" signal that can be used by the VPIO line to exit low power or sleep mode.

[0084] Figure 11 1 shows an exemplary port activity detection circuit 1100 according to one embodiment. Circuit 1100 can process multiple inputs and create a signal that can be used by the VPIO line to exit low power or sleep mode. Circuit 1100 can include an OR gate 1110, where signal 1101 1-N A set of signals 1101 as the first input and an inverted end-of-frame signal 1102 as the second input. 1-N Energy is output from the respective instances of lines 700, 750, 800, or 900. Until an end-of-frame signal 1102 arrives (not in low power mode), output signal 1112 is active at "1" and will not be shut down. However, when the end of the frame arrives (at signal 1101 1-N When there is no other input signal switching on the VPIO line, the VPIO line can enter low power mode and when the signal 1101 1-N Output 1112 provides a signal Enable_VPIO_CLK that can cause one or more of the following actions: (1) powering on a VPIO clock to activate a VPIO circuit; (2) enabling the VPIO clock (which was previously powered on) for use by some or all VPIO lines; and (3) being used by the VPIO lines to exit low power mode.

[0085] Figure 12 FIG. 1 shows a schematic diagram of a port activity detection circuit 1200 according to an embodiment. The circuit 1200 may be built on Figure 8A The circuit 750 is connected to the flip-flop to address potential metastability issues. When a signal is sampled asynchronously by a clock, there is a low but non-zero probability that the clock signal and the input signal will change state simultaneously or nearly simultaneously, thereby violating the setup time requirement of a flip-flop. The result is a long period of hesitation or a false logic state at the output, which is called metastability. In the case of metastability, the output state may be incorrect (for example, a logic state "0" versus a state "1", or vice versa), and metastability with a forbidden level between logic 0 and 1 can propagate and cause a worsening of the situation.

[0086] Circuit 1200 can include a D flip-flop 1204 having an input coupled to receive an input signal 1201 from a port (e.g., one of the plurality of ports 601) and an output 1206 that stores a previous state of the D flip-flop 1204 and is provided to an input of a D flip-flop 1214. D flip-flop 1214 is connected in series with D flip-flop 1204. Circuit 1200 can also include an XOR gate 1205 having a first input coupled to input signal 1201, a second input coupled to output signal 1206, and an output 1202 coupled to a first input of an AND gate 1210. Output 1202 of XOR gate 1205 is also a Pin_K_Toggle_ON signal. XOR gate 1205 compares input signal 1201 with output signal 1206 and switches output 1202 depending on the switching of two-state signals 1201, 1206 and a clock input received from the output of AND gate 1210. Circuit 1200 also includes a D flip-flop 1214 that receives output 1206 as its input and provides an output 1215 indicating a state of Pin_K. D flip-flop 1214 receives a clock input from clock signal 1220. Clock signal 1220 is also coupled to a second input of AND gate 1210.

[0087] The serial arrangement of two flip-flops 1204, 1214 coupled to the same clock signal 1220 effectively mitigates any possibility of metastability because the low probability of a metastable state occurring with flip-flop 1204 is multiplied by the low probability of a metastable state occurring with flip-flop 1214. For example, if the probability of creating a metastable state with a flip-flop 1204 on all possible phases between the transitions 1201 and 1220 is 0.02, the probability of a metastable state for this topology is significantly reduced to approximately 0.02*0.02=0.0004. In other words, a metastable state resampled using the same clock in 1214 is less likely to propagate. The output signal 1202 (i.e., Pin_K_Toggle_ON) can be delayed and resampled and used as a wake-up signal for the VPIO line. The second output 1215 (Pin_K_State) of 1200 gives the logic value ("0" or "1") of the input 1201 at the clock rate of 1220 after a clock delay of 2 cycles without metastable state.

[0088] Figure 13A schematic diagram of a low-power mode detection circuit 1300 is shown, according to one embodiment, which operates to determine when to quickly put a VPIO line into a low-power or sleep mode. The VPIO line and the state machine running within it are intended to transmit a frame of symbols (symbols representing the state of the pin). When a frame is transmitted, a frame trailer 1301 is generated. If it does not exist, it is called Any_Pin_Toggle 1302. 1-N If a new IO pin toggle (e.g., the output of lines 700, 750, 800, or 900) is transmitted via the VPIO line, the state machine and the VPIO line enter a low-power state using function 1310 (e.g., a NAND gate). NAND gate 1310 creates an "enter low-power" signal 1312 that can be used to enter a low-power mode. Signal 1312 can also be used to gate off the main clock to the VPIO line.

[0089] In one embodiment, after a frame end has been transmitted on signal 1301, and if there is no Any_Pin_Toggle 1302 1-N If the VPIO is switched, the "enter low power" output 1312 may be provided to a processing block. Depending on its settings or programming, the processing block may include one or more of a timer, a counter, a state machine, and a delay to delay entry into low power mode. The processing block may switch off all or part of the VPIO system until the next activity is detected or until a predetermined period of time has passed.

[0090] Figure 14AAn exemplary process 1400 according to one embodiment is shown. For example, process 1400 may be implemented in VPIO line 600. Furthermore, process 1400 discusses exiting and entering a low-power mode when the VPIO is initially operating in a transmitter mode. Beginning with step 1404, a VPIO line (e.g., VPIO line 600) is operated in a low-power mode. In some embodiments, the low-power mode requires no clock or oscillator to be running. At step 1408, process 1400 may monitor multiple ports for signal activity. For example, port activity detection circuits 650, 700, 750, 800, 900, 1000, 1100, and 1200 may detect whether any activity is present on any one or more of the multiple ports. At step 1412, process 1400 may determine whether signal activity is present on at least one of the multiple ports. If no activity is present, process 1400 may return to step 1408. If there is signal activity on at least one of the plurality of ports, then at step 1418, process 1400 can instruct the VPIO line to exit the low power mode. For example, the port activity detection circuit 650 can trigger the enabler 640 to activate the necessary clocks, oscillators, processors, state machines, etc. to transition the VPIO to an active mode. Depending on the application employing the VPIO line, exiting the low power mode can result in several different active mode scenarios. For example, in one active mode, the VPIO line can be fully awakened, in which case all clocks, processors, state machines, etc. are awakened. As another example, in another active mode, the VPIO line can be partially awakened, in which case a subset or portion of the clocks, processors, state machines, etc. are awakened.

[0091] At step 1420, a plurality of signals (or data) received on a plurality of ports can be processed via the VPIO lines. The plurality of signals can be remapped according to a port mapping scheme (e.g., as defined by the port mapping coordinator 620) and the remapped plurality of signals can be aggregated, serialized, and transmitted to a paired VPIO line via a medium (e.g., a high-speed bus). An "end of frame" symbol can be generated to indicate that a data transmission event has concluded. In one embodiment, a transceiver can generate the "end of frame" symbol in response to the last signal transmitted via the medium. Further details of the specific steps that can be implemented by step 1420 are provided in conjunction with Figure 14B discuss.

[0092] Multiple signals can continue to be processed through the VPIO lines as long as there is signal activity on at least one of the multiple ports, as determined by step 1430, where a "yes" determination at step 1430 causes process 1400 to return to step 1420. If, as determined by step 1430, signal activity has ceased on the multiple ports, process 1400 can then determine whether an "end of frame" symbol has been detected at step 1440. If the determination at step 1440 is "no," process 1400 returns to step 1430. If the determination at step 1440 is "yes," then, at step 1450, the VPIO lines can be instructed to enter a low-power mode, and process 1400 can return to step 1404. For example, low-power mode detection circuitry 660 can confirm the absence of signal activity on the multiple ports using the simultaneous detection of "end of frame" symbols.

[0093] It should be recognized that Figure 14A The steps shown are merely illustrative and additional steps may be added, the order of the steps may be rearranged, or steps may be omitted.

[0094] Figure 14B Shows additional steps according to an embodiment, which can be used as Figure 14A 1420 portion. In step 1421, a plurality of signals are read from at least one of the plurality of ports. The reading of these signals can be performed in several different ways. For example, a predetermined condition may need to be met in order to read the plurality of signals, the plurality of ports may be read after a delay, the plurality of ports may be read after a predetermined process has been completed, a subset or portion of the plurality of ports may be read, all ports may be read, only switched ports may be read, ports of a certain category (e.g., signaling protocol) may be read, multiple categories of ports may be read, or a combination of ports associated with one or more categories plus only specifically designated ports may be read. It will be understood that there are many other ways that signals can be read out of ports known to those skilled in the art.

[0095] In various embodiments where bidirectional communication is employed by VPIO lines, such bidirectional signals may be merged at step 1422. Merging step 1422 may be implemented by bidirectional merge circuit 603 of FIG. The logical value (state) or sequential merging of the states in the Tx direction signal issued from the input at 601 and the Rx signal in the reverse direction issued from the disperser 634 can occur according to certain rules to produce a merged value for each port 1-N, the certain rules including one or more of the following list: connecting each of the Tx_N signal and the Rx_N signal together, connecting them with a current limit to avoid excessive current when the Tx state and the Rx state are different, binary inputs from both directions are ORed together, and ANDed together, the line input signal of the first VPIO is used (Tx), the input signal of the paired VPIO line is used (Rx, reverse signal), connecting each of the Tx_N signal and the Rx_N signal to an open collector line, connecting them to the I2C line, each of the Tx_N signal and the Rx_N signal is combined by a combinatorial function (combinatory function), function), a sequential function, a processing unit, a state machine, a function using a memory, a function processing requesting more data from another part of the system, from a user, from a graphical user interface (GUI), etc. Also, the way to merge the Tx signal and the Rx signal may depend on the type of signal, that is, if it is a GPIO signal, an I2C signal, etc., the merging may be done differently.

[0096] In step 1423, signals are processed for port mapping, grouped port mapping, or port swapping. For example, a signal associated with a first VPIO line received at port #4 may need to be mapped to port #34 associated with a second VPIO line. Port mapping ensures that the signal is routed to the appropriate port associated with the second VPIO line. For example, port mapping can improve trace routing on the PCB by minimizing trace lengths and making any trace connection from the VPIO line to one or more targets tangle-free. Grouped port mapping can remap a group of ports (e.g., ports associated with a specific protocol) to more preferred port locations associated with a paired VPIO line to optimize trace routing on the PCB. Port swapping can be used to minimize trace lengths, match trace lengths, and avoid any crossing of high-speed signals. The multiple signals processed in step 1423 can include multiple input signals, portions of multiple input signals, one or more categories of input signals, multiple high-speed serial signals, multiple control signals for VPIO lines, and multiple power signals for VPIO lines. The various categories of signals can include low speed, medium speed, high speed, GPIO, protocol, I2C, I2S, SPI, USB2, USB3, USB-SS, any USB, DP, SATA, TCP, Wi-Fi baseband, Bluetooth baseband, 3G baseband, 4G baseband, 5G baseband, 6G baseband, UART, JTAG, Ethernet, HDMI, Vx1, next gen Vx1, MIPIDSI, CSI-2, USB3+USB2, MIPICPHY, USB3.1gen2, any generation of PCIE, USB4, Thunderbolt, etc.

[0097] In step 1424, the mapped or switched signals are aggregated and subsequently serialized in step 1425. In step 1426, the serialized signals can be transmitted via a medium to a paired VPIO line. The medium can be a high-speed serial bus connecting the pair of VPIO circuits. The medium can be unidirectional or bidirectional. Bidirectional signal transmission can be synchronous or sequential.

[0098] It should be recognized that Figure 14B The steps shown are merely illustrative and additional steps may be added, the order of the steps may be rearranged, or steps may be omitted. For example, for any or all of the input signals in 601 of FIG6 , if no two-way communication is employed on any or all of the input signals, step 1422 may be omitted.

[0099] Figure 15AAn illustrative process 1500 according to one embodiment is shown. For example, process 1500 can be implemented in VPIO line 600. In addition, process 1500 discusses exiting a low power mode and entering a low power mode when the VPIO line is operating in a receiver mode. If the VPIO line is involved in bidirectional communication, both processes 1400 and 1500 can be used. Beginning with step 1505, a VPIO line is operating in a low power mode. At step 1510, a serialized signal is received via a medium (e.g., a high-speed communication bus). The serialized signal can include: a wake-up signal that operates to cause the VPIO line to exit a low power mode; and an end-of-frame symbol that indicates that a data exchange event is complete. For example, wake-up line 699 can detect the presence of a wake-up signal in serialized data 695 (or line 699 can detect the wake-up signal in deserialized data).

[0100] In another embodiment, a detection circuit similar to port activity detection circuit 650 can be used on high-speed serial bus 695 in wake-up circuit 699 to detect a toggle or change in state in a data line, clock line, or enable line. In the case where the inputs are one or more of the high-speed data line, clock line, and enable line, circuits such as 700, 750, and 800 can detect a toggle with or without an internal clock. If several inputs are checked, they can be ORed together using a circuit such as 1010, followed by an SR flip-flop 1020, to create a wake-up signal 699 to exit power mode. In step 1515, in response to detection of the wake-up signal, the VPIO line can exit low-power mode.

[0101] After the VPIO line exits the low-power state, at step 1520, the received serialized signal can be processed via the VPIO. The signal can be deserialized, dispersed according to a port mapping scheme, and selectively routed to multiple ports based on the port mapping scheme. At step 1530, process 1500 can check whether the serialized signal is still being received through the medium. If the determination is "yes," process 1500 returns to step 1520. If the determination is "no," process 1500 can proceed to step 1540, which determines whether an end-of-frame symbol has been detected. If the determination is "no," process 1500 returns to step 1530. If the determination is "yes," then, at step 1550, the VPIO line is instructed to enter low-power mode and process 1500 returns to step 1505.

[0102] It should be recognized that Figure 15AThe steps shown are merely illustrative and additional steps may be added, the order of the steps may be rearranged, or steps may be omitted.

[0103] Figure 15B Shows additional steps according to an embodiment, which can be used as Figure 15A 1520 portion. In step 1521, a serialized signal is received from a medium and deserialized in step 1522. In step 1523, the deserialized signal can be dispersed. Dispersion can identify where the signal should be routed based on port mapping, grouped port mapping, or port switching. In some embodiments, the port mapping coordinator 620 can be used to make routing determinations. In other embodiments, routing information is embedded in the signal and extracted by the disperser to determine the routing destination of the signal. If bidirectional signals are used, then, in step 1524, such signals can be merged. In step 1525, the dispersed signals are routed to the mapped ports, the mapped grouped ports, or the switched ports.

[0104] It should be recognized that Figure 15B The steps shown are merely illustrative and additional steps may be added, the order of the steps may be rearranged, or steps may be omitted.

[0105] Figure 16 An illustrative process 1600 for exiting and entering a low power mode according to one embodiment is shown. Process 1600 can be implemented in line 600 of Figure 6 and can particularly be implemented using lines 700, 750, or 800 and line 1300. Beginning with step 1610, a plurality of ports are monitored for signal activity using a plurality of port switch detection circuits, wherein each port switch detection circuit outputs a switch pulse in response to a signal transition at the port to which the port switch detection circuit is coupled, wherein each port switch detection circuit operates independently of a clock signal. The independence from the clock signal requires that the plurality of port switch detection circuits operate without using a clock signal provided externally from the port switch detection circuit or internally provided within the port switch circuit to monitor the ports. In some embodiments, the switch pulse is a 010 transition.

[0106] At step 1620, process 1600 can combine the outputs of each of the plurality of port switch detection circuits to generate a switch state output that is provided to a switch processing circuit. In one embodiment, the switch processing circuit comprises an RS flip-flop (e.g., flip-flop 1010), wherein the switch state output is coupled to a first input of the RS flip-flop. At step 1630, process 1600 can instruct the VPIO circuit to exit a low-power mode in response to the switch processing circuit receiving a switch pulse on the switch state output. The VPIO circuit can process signals as described herein before returning to the low-power state. At step 1640, the VPIO circuit can be instructed to enter the low-power state when no switch pulse is present on the switch state output and an end-of-frame symbol or enter low-power signal is received by the switch processing circuit. For example, assuming the switch processing circuit is an RS flip-flop, a first input can be connected to the switch state output and a second input can be coupled to receive a signal from a low-power detection circuit (e.g., circuit 1300) or to monitor a data line (e.g., a serialized data link or a deserialized data link) for an end-of-frame symbol. When the switching signal goes low and the second input goes high, the flip-flop can then instruct the VPIO line to enter low power mode.

[0107] It should be recognized that Figure 16 The steps shown are merely illustrative and additional steps may be added, the order of the steps may be rearranged, or steps may be omitted.

[0108] Figure 17 An exemplary process 1700 is shown for determining when to enter low-power mode according to one embodiment. For example, process 1700 can be implemented by circuit 660 or circuit 1300. At step 1710, the VPIO circuit can operate in an active mode. At step 1720, the low-power mode detection circuit can receive a switch status output indicating whether there is signal activity on any of the multiple ports and a data stream including data and an end-of-frame symbol. For example, the switch status output can be provided by port activity detection circuits 700, 750, or 800. The data stream can be a serial data stream transmitted to another VPIO circuit (e.g., high-speed transmit bus 693) or a serial data stream received from another VPIO circuit (e.g., via high-speed receive bus 695). In some embodiments, the data stream can include both transmitted serial data and received serial data. If data is received from a paired VPIO circuit, the VPIO circuit can process the received data and route it to the appropriate port. As a result, the ports will exhibit activity detected by the port activity detection circuit, providing the switch status output.

[0109] At step 1730 , the VPIO lines can be instructed to enter a low power mode when the received switch status output indicates that there is no activity on the plurality of ports and the received data stream includes an end-of-frame symbol.

[0110] It should be recognized that Figure 17 The steps shown are merely illustrative and additional steps may be added, the order of the steps may be rearranged, or steps may be omitted.

[0111] It is believed that the disclosure set forth herein includes a plurality of different inventions with independent practicality. Although each of these inventions is disclosed in its preferred form, the specific embodiments disclosed and illustrated herein should not be considered restrictive, as many variations are possible. Each example defines an embodiment disclosed in the aforementioned disclosure, but any one example is not necessarily intended to include all features or combinations that may ultimately be claimed. Where an "indefinite article of consonant (a)" or "a first" element or its equivalent is cited in the description, such description includes one or more such elements, and neither requires nor excludes two or more such elements. In addition, order indicators such as first, second or third for identifying elements are used to distinguish between these elements and do not represent a required or limited number of such elements, nor a specific position or order of such elements, unless otherwise specifically stated. In addition, ports and pins can be used interchangeably.

[0112] In addition, for Figures 14A to 17 Any of the processes illustrated in FIG. 26 , as well as any other aspects of the present invention, may be implemented using software, but may also be implemented using hardware, firmware, or any combination of software, hardware, and firmware. Each of these may also be embodied as machine- or computer-readable code recorded on a machine- or computer-readable medium. A computer-readable medium may be any data storage device capable of storing data or instructions that can subsequently be read by a computer system. Examples of computer-readable media may include, but are not limited to, read-only memory, random access memory, flash memory, CD-ROMs, DVDs, magnetic tape, and optical data storage devices. Computer-readable media may also be distributed across network-coupled computer systems so that computer-readable code is stored and executed in a distributed manner. For example, a computer-readable medium may communicate from one electronic subsystem or device to another electronic system or device using any suitable communication protocol. A computer-readable medium may be embodied as computer-readable code, instructions, data structures, program modules, or other data in a modulated data signal (such as a carrier wave or other transport mechanism), and may include any information delivery medium. A modulated data signal may be a signal having one or more of its characteristics set or changed in such a manner as to encode information in the signal.

[0113] It should be understood that any or each module or state machine discussed herein can be provided as a software construct, a firmware construct, one or more hardware devices, or a combination thereof. For example, any one or more state machines or modules can be described in the general context of computer-executable instructions (such as program modules), which can be executed by one or more computers or other devices. Typically, a program module can include one or more routines, programs, objects, components, and / or data structures that can perform one or more specific tasks or implement one or more specific abstract data types. It should also be understood that the number, configuration, functionality, and interconnection of modules or state machines are merely illustrative, and the number, structure, functionality, and interconnection of existing modules can be modified or omitted, additional modules can be added, and the interconnection of certain modules can be changed.

[0114] Although many changes and modifications of the present invention will undoubtedly become apparent to those skilled in the art after reading the foregoing description, it should be understood that the specific embodiments shown and described by way of illustration are by no means intended to be considered limiting. Therefore, reference to details of the preferred embodiments is not intended to limit their scope.

Claims

1. An electronic device comprising: A plurality of first ports are present on a first circuit substrate; A virtual pipe input / output (VPIO) line coupled to the plurality of first ports, the VPIO line comprising: a virtual pipe engine (VPE) operative to cycle between a low power mode and an active mode, wherein in the active mode, the VPE is operative to process a plurality of signals received at the plurality of first ports for delivery to paired VPIO lines according to a port mapping scheme; A port activity detection circuit is coupled to the plurality of first ports and is operable to: In response to any signal activity on any first port of the plurality of first ports, instructing the VPE to exit the low power mode or remain in the active mode; and a low power mode detection circuit coupled to the port activity detection circuit and coupled to receive a data stream processed by the VPE or the paired VPIO circuit, the low power mode detection circuit being operative to: instruct the VPE to enter a low power mode when a low power mode condition is detected; and A transceiver is configured to transmit the processed signals to the paired VPIO lines via a medium.

2. The electronic device according to claim 1, wherein The VPE includes: a port mapping coordinator that maintains the port mapping scheme; and An aggregator is operable to: remap a plurality of signals received on the plurality of first ports according to the port mapping scheme, and aggregate the remapped plurality of signals, such that the aggregated plurality of signals are transmitted to the paired VPIO lines via the transceiver.

3. The electronic device according to claim 2, wherein: The VPE further comprises: a disperser operative to: process a received data stream transmitted by the paired VPIO line, and route a plurality of signals in the received data stream to selected ports among the plurality of first ports based on a mapping scheme applied to the received data stream at the paired VPIO line, wherein the received data stream is received by the transceiver via the medium.

4. The electronic device according to claim 1, wherein The port mapping scheme includes port mapping, group port mapping or port switching.

5. The electronic device according to claim 1, wherein The port activity detection circuit operates independently of a clock signal.

6. The electronic device according to claim 1, wherein The low power mode detection circuit operates independently of a clock signal.

7. The electronic device according to claim 1, wherein The low power mode condition is met when no signal activity is detected on any first port of the plurality of first ports and an end-of-frame symbol is detected in the data stream.

8. The electronic device according to claim 1, wherein The low power mode condition is met when no change is detected in the data stream.

9. The electronic device according to claim 1, wherein The port activity detection circuit is operative to exit the low power mode in response to detection of a switch on any of the plurality of first ports or in response to a change in the data stream received from the paired VPIO line.

10. The electronic device according to claim 1, wherein The port activity detection circuit includes: For a switching detection circuit of each of the plurality of first ports, each switching detection circuit includes: a flip-flop having a first input coupled to a corresponding first port of the plurality of first ports, a clock input, and a first output; an XOR gate having a second input coupled to the first input, a third input coupled to the first output, and a second output coupled to the clock input; Wherein any transition on the first input results in a 010 pulse on the second output, and wherein the 010 pulse causes the VPE to exit low power mode.

11. The electronic device according to claim 1, wherein The port activity detection circuit includes: For a switching detection circuit of each of the plurality of first ports, each switching detection circuit includes: a flip-flop having a first input coupled to a corresponding first port of the plurality of first ports, a clock input, and a first output; an XOR gate having a second input coupled to the first input, a third input coupled to the first output, and a second output; a processing circuit coupled to the second output and the clock input; Wherein any transition on the first input results in a 010 extended pulse on the second output, wherein a pulse duration of the 010 extended pulse is artificially increased by the processing circuitry, and wherein the 010 extended pulse causes the VPE to exit low power mode.

12. The electronic device according to claim 1, wherein The port activity detection circuit includes: a plurality of switching detection circuits, one switching detection circuit for each of the plurality of first ports, wherein the plurality of outputs of the plurality of switching detection circuits are combined by a gate having a switching output; and A flip-flop has a first input coupled to the switching output and an output coupled to transmit an exit low power signal to the VPE, wherein the flip-flop is operative to transmit the exit low power signal when the switching output provides a switching pulse to the first input.

13. The electronic device according to claim 12, wherein: The trigger includes a second input coupled to receive a data stream or a signal to enter a low power mode.

14. The electronic device according to claim 1, wherein The low power consumption detection circuit comprises: A gate includes: a first input coupled to receive a switching output from the port activity detection circuit; a second input coupled to receive the data stream; and an output coupled to provide an entry into a low power mode to the VPE.

15. A method comprising, using an electronic device: Enables virtual protocol input and output (VPIO) lines to operate in a low-power mode; monitoring a plurality of ports for signal activity while the VIPO circuit operates in the low power mode; in response to detecting signal activity on at least one of the plurality of ports, instructing the VPIO line to exit a low power mode; When the VPIO lines are operating in a non-low-power mode: processing a plurality of signals received on the plurality of ports via the VPIO lines, wherein the plurality of signals are remapped, aggregated, and transmitted to paired VPIO lines via a medium according to a port mapping scheme, wherein an end-of-frame symbol is generated to indicate completion of a data exchange event; and instructing the VPIO line to enter a low power mode when no signal activity is detected on any of the plurality of ports and the end-of-frame symbol is detected; and In response to the received instruction to enter the low power consumption mode, the method returns to making the VIPO circuit operate in the low power consumption mode.

16. The method of claim 15, wherein: The monitoring of the plurality of ports is performed independently of a clock signal.

17. The method of claim 15, wherein: The processing includes: reading a plurality of signals from at least one of the plurality of ports; processing the read plurality of signals for port mapping, group port mapping, or port switching according to the port mapping scheme; aggregating the mapped or exchanged multiple signals; Serializing the aggregated plurality of signals; and The serialized plurality of signals are transmitted to the paired VPIO lines through the medium.

18. A method comprising, using an electronic device: Enable a virtual protocol input / output (VPIO) line to operate in a low power mode; A plurality of serialized signals are received via a medium, wherein The serialized signals include: a wake-up signal, which operates to cause the VPIO line to exit a low power mode; and an end-of-frame symbol, which indicates that a data exchange event is completed; In response to the detection of the wake-up signal, the VPIO line exits the low power consumption mode; When the VPIO lines are operating in a non-low-power mode: processing the received plurality of serialized signals via the VPIO lines, wherein the plurality of signals are deserialized, dispersed according to a port mapping scheme, and selectively routed to a plurality of ports based on the port mapping scheme; and instructing the VPIO lines to enter a low power mode when no serialized signals are received via the medium or when no signal activity is detected on the plurality of ports and when the end-of-frame symbol is detected; and In response to the received instruction to enter the low power consumption mode, the method returns to making the VIPO circuit operate in the low power consumption mode.

19. A method comprising, using an electronic device: Utilizes multiple port switch detection circuits to monitor multiple ports for signal activity, wherein: Each port switch detection circuit outputs a switch pulse in response to a signal transition at the port to which that port switch detection circuit is coupled, wherein each port switch detection circuit operates independently of a clock signal; combining an output of each of the plurality of port switch detection circuits to generate a switch status output provided to a switch processing circuit; In response to the switch processing circuit receiving the switch pulse on the switch state output, instructing the VPIO circuit to exit a low power mode; and When no switching pulse is present on the switching state output and an end-of-frame symbol or an enter low power signal is received by the switching processing circuit, the VPIO circuit is instructed to enter a low power mode.

20. The method of claim 19, wherein: The switching pulse is a 010 transition.

21. The method of claim 19, wherein: The plurality of port switching detection circuits are operable to monitor the plurality of ports without using a clock signal provided externally from the port switching detection circuit or provided internally within the plurality of port switching circuits.

22. The method of claim 19, wherein: The switch processing circuit includes a flip-flop, and wherein the switch state output is coupled to a first input of the flip-flop.

23. An electronic device comprising: A plurality of ports are present on a circuit substrate; an aggregator-disperser module coupled to the plurality of ports, the aggregator-disperser module operative to cycle between a low power mode and an active mode; a port activity detection circuit coupled to the plurality of ports and operable to: in response to any signal activity on any of the plurality of ports, instruct the aggregator-disperser module to exit the low power mode or remain in the active mode; as well as A low power mode detection circuit is coupled to the port activity detection circuit and is coupled to receive a data stream. The low power mode detection circuit is operable to: when a low power mode condition is detected, instruct the aggregator-disperser module to enter the low power mode.

24. The electronic device according to claim 23, wherein: In active mode, the aggregator-disperser module operates to process signals received on the ports for delivery to a paired aggregator-disperser module according to a port mapping scheme.

25. The electronic device according to claim 24, wherein The data stream is processed by the aggregator-disperser module or the paired aggregator-disperser module.

26. The electronic device of claim 24, further comprising: A transceiver is configured to transmit the processed signals to the paired aggregator-disperser modules via a medium.

27. The electronic device according to claim 26, wherein The aggregator-disperser module comprises: a port mapping coordinator that maintains the port mapping scheme; and An aggregator is operable to: remap the plurality of signals received on the plurality of ports according to the port mapping scheme, and aggregate the remapped plurality of signals, so that the aggregated plurality of signals are transmitted to the paired aggregator-disperser module via the transceiver.

28. The electronic device according to claim 27, wherein The aggregator-disperser module further comprises: a disperser operative to: process a received data stream transmitted by the paired VPIO lines, and route a plurality of signals in the received data stream to selected ports among the plurality of first ports based on a mapping scheme applied to the received data stream at the paired aggregator-disperser module, wherein the received data stream is received by the transceiver via the medium.

29. The electronic device according to claim 24, wherein The port mapping scheme includes port mapping, group port mapping or port switching.

30. The electronic device according to claim 23, wherein The port activity detection circuit operates independently of a clock signal.

31. The electronic device according to claim 23, wherein The low power mode detection circuit operates independently of a clock signal.

32. The electronic device according to claim 23, wherein The low power mode condition is met when no signal activity is detected on any of the plurality of ports and an end-of-frame symbol is detected in the data stream.

33. The electronic device according to claim 23, wherein: The low power mode condition is met when no change is detected in the data stream received from the paired aggregator-disperser module.

34. The electronic device according to claim 23, wherein The port activity detection circuit includes: For each of the plurality of ports, a switching detection circuit is provided, wherein each switching detection circuit includes: a flip-flop having a first input coupled to a corresponding port of the plurality of ports, a clock input, and a first output; an XOR gate having a second input coupled to the first input, a third input coupled to the first output, and a second output coupled to the clock input; Wherein any transition on the first input results in a 010 pulse on the second output, and wherein the 010 pulse causes the aggregator-disperser module to exit the low power mode.

35. The electronic device of claim 231, wherein: The port activity detection circuit is operative to exit the low power mode in response to detection of a switch on any of the plurality of first ports or in response to a change in the data stream received from the paired aggregator-disperser module.

36. The electronic device according to claim 23, wherein The port activity detection circuit includes: A switching detection circuit for each of the plurality of ports, each switching detection circuit comprising: a flip-flop having a first input coupled to a corresponding port of the plurality of ports, a clock input, and a first output; an XOR gate having a second input coupled to the first input, a third input coupled to the first output, and a second output; a processing circuit coupled to the second output and the clock input; wherein any transition on the first input results in a 010 extended pulse on the second output, wherein a pulse duration of the 010 extended pulse is artificially increased by the processing circuitry, and wherein the 010 extended pulse causes the aggregator-disperser module to exit the low power mode.

37. The electronic device according to claim 23, wherein: The port activity detection circuit includes: a plurality of switching detection circuits, one switching detection circuit for each of the plurality of ports, wherein the plurality of outputs of the plurality of switching detection circuits are combined by a gate having a switching output; and A flip-flop having a first input coupled to the switching output and an output coupled to transmit an exit low power signal to the aggregator-disperser module, wherein the flip-flop operates to transmit the exit low power signal when the switching output provides a switching pulse to the first input.

38. The electronic device of claim 73, wherein: The trigger includes a second input coupled to receive a data stream or a signal for entering a low power consumption mode.

39. The electronic device according to claim 22, wherein: The low power consumption detection circuit comprises: A gate includes: a first input coupled to receive a switching output from the port activity detection circuit; a second input coupled to receive the data stream; and an output coupled to provide an entry into a low power mode to the VPE.

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