Abnormality detection method and device for dual-chip control system

Abstract

The invention relates to an anomaly detection method and device for a dual-chip control system. The method comprises the steps that a first main chip and a second main chip determine data acquisition synchronization information based on a first input and output line, and after the data acquisition synchronization information is determined, the first main chip and the second main chip synchronously acquire data; the first main chip processes and packs the collected data to form a first data packet, and the second main chip processes and packs the collected data to form a second data packet; and the first main chip and the second main chip determine data transmission synchronization information based on the second input / output line, after the data transmission synchronization information is determined, the first main chip sends the first data packet to the second main chip based on the data transceiving line, and meanwhile, the second main chip sends the second data packet to the first main chip based on the data transceiving line. In this way, whether the first main chip and the second main chip of the double-chip control system are abnormal or not can be timely and accurately detected.

Description

Technical Field

[0001] The present disclosure relates to the technical field of dual-chip control systems, and more particularly, to an abnormality detection method and device for a dual-chip control system. Background Art

[0002] A single-chip control system consists of a main chip and other peripheral chips, forming a complete control system. A dual-chip control system adds a second main chip to a single-chip control system. Dual-chip control systems offer greater security and reliability than single-chip systems (even if one main chip fails, the other can still keep the control system functioning normally). Therefore, dual-chip control systems are widely used in industries such as healthcare, automotive safety, and aerospace. While dual-chip control systems offer greater security and reliability, anomalies still require prompt detection. Accurately and promptly detecting anomalies in dual-chip control systems is a pressing technical challenge.

[0003] The existing technology uses a controller within a dual-chip control system. Initially, only the first main chip operates, and the controller determines whether the first main chip is abnormal. (The controller directly verifies the input data of the first main chip. If the verification result does not meet the target verification result, the first main chip is deemed abnormal.) If the first main chip is determined to be abnormal, the second main chip is activated. This approach has the following problems: First, determining whether the first main chip is abnormal by verifying the input data alone is inaccurate. Second, there is no guarantee that the second main chip, which has not been determined to be abnormal, is normal and fault-free. If the second main chip also has a problem, the dual-chip control system will not be able to continue operating normally. Summary of the Invention

[0004] In a first aspect of an embodiment of the present disclosure, a method for detecting an abnormality in a dual-chip control system is provided. The method comprises: The first master chip and the second master chip determine data acquisition synchronization information based on the first input and output line. After the data acquisition synchronization information is determined, the first master chip and the second master chip synchronously acquire data. The first master chip processes the collected data and packages it to form a first data packet, while the second master chip processes the collected data and packages it to form a second data packet; the first master chip and the second master chip determine data transmission synchronization information based on the second input and output line. After determining the data transmission synchronization information, the first master chip sends the first data packet to the second master chip via the data transceiver line, while the second master chip sends the second data packet to the first master chip via the data transceiver line; The first master chip determines whether the second data packet is abnormal. When the second data packet is abnormal, the first master chip outputs second master chip abnormal information; at the same time, the second master chip determines whether the first data packet is abnormal. When the first data packet is abnormal, the second master chip outputs first master chip abnormal information.

[0005] Preferably, the second main chip determines whether the first data packet is abnormal by: Determining whether the first data packet is lost or whether a verification error occurs, and when the determination result is that the first data packet is lost or a verification error occurs, increasing the first abnormality accumulated value by one; otherwise, updating the first abnormality accumulated value to an initial value; Determine whether the first abnormality cumulative value is equal to the abnormality cumulative threshold, when the first abnormality cumulative value is equal to the abnormality cumulative threshold, determine that the first data packet is abnormal, and update the first abnormality cumulative value to an initial value; otherwise, determine that the first data packet is normal; The first main chip determines whether the second data packet is abnormal by: determining whether the second data packet is lost or whether a verification error occurs, and when the determination result is that the second data packet is lost or a verification error occurs, incrementing the second abnormality accumulated value by one; otherwise, updating the second abnormality accumulated value to an initial value; Determine whether the second abnormality cumulative value is equal to the abnormality cumulative threshold. When the second abnormality cumulative value is equal to the abnormality cumulative threshold, determine that the second data packet is abnormal and update the second abnormality cumulative value to the initial value; otherwise, determine that the second data packet is normal.

[0006] As an advantage, it also includes determining an abnormal accumulation threshold, specifically: Obtaining the abnormality determination accuracy of the first main chip and the second main chip of multiple dual-chip control systems under different first-level abnormality accumulation thresholds; Determine the first-level abnormality accumulation threshold value when the abnormality determination accuracy of the first main chip and the second main chip of each dual-chip control system is the highest and use it as the second-level abnormality accumulation threshold value; Determine the second-level anomaly accumulation threshold with the highest frequency and use it as the third-level anomaly accumulation threshold; Determine whether the number of three-level abnormality accumulation thresholds is one. When the number of three-level abnormality accumulation thresholds is one, use the three-level abnormality accumulation threshold as the final abnormality accumulation threshold; otherwise, select the three-level abnormality accumulation threshold with the smallest value as the final abnormality accumulation threshold.

[0007] Preferably, determining whether the first data packet is lost or whether a check error occurs is specifically as follows: After determining the data transmission synchronization information, timing is performed to determine whether the first data packet is received within a timing threshold, and when the first data packet is received within the timing threshold, it is determined that the first data packet is not lost; otherwise, it is determined that the first data packet is lost; When the first data packet is not lost, calculating a first verification calculation value based on the first data packet, and comparing the first verification calculation value with a first verification control value in the first data packet, and when the first verification calculation value is the same as the first verification control value, determining that no verification error occurs in the first data packet; otherwise, determining that a verification error occurs in the first data packet; Determining whether the second data packet is lost or whether a check error occurs is specifically as follows: After determining the data transmission synchronization information, timing is performed to determine whether the second data packet is received within a timing threshold, and when the second data packet is received within the timing threshold, it is determined that the second data packet is not lost; otherwise, it is determined that the second data packet is lost; When the second data packet is not lost, a second verification calculation value is calculated based on the second data packet, and the second verification calculation value is compared with the second verification control value in the second data packet. When the second verification calculation value is the same as the second verification control value, it is determined that no verification error occurs in the second data packet; otherwise, it is determined that a verification error occurs in the second data packet.

[0008] As an option, it also includes: After determining the data sending synchronization information, obtain the first temperature value of the first master chip and determine whether the first temperature value is less than the first temperature threshold or greater than the second temperature threshold. When the first temperature value is less than the first temperature threshold or greater than the second temperature threshold, determine that the first master chip is abnormal; at the same time, obtain the second temperature value of the second master chip and determine whether the second temperature value is less than the first temperature threshold or greater than the second temperature threshold. When the second temperature value is less than the first temperature threshold or greater than the second temperature threshold, determine that the second master chip is abnormal.

[0009] As an option, it also includes: The first master chip or the second master chip periodically verifies the random access memory to determine whether an abnormality occurs in the random access memory: obtaining a specific space value 1 of the random access memory, determining whether the specific space value 1 is the same as a specific space preset value 1, and determining that the random access memory is abnormal when the specific space value 1 is different from the specific space preset value 1; The first master chip or the second master chip periodically verifies the flash memory to determine whether the flash memory is abnormal: obtaining the second specific space value of the flash memory, determining whether the second specific space value is the same as the second specific space preset value; when the second specific space value is different from the second specific space preset value, determining that the flash memory is abnormal; The first main chip or the second main chip periodically verifies the register to determine whether there is an abnormality in the register: obtain the specific space value three of the register, determine whether the specific space value three is the same as the specific space preset value three, and when the specific space value three is different from the specific space preset value three, determine that the register is abnormal.

[0010] As an option, it also includes: Determine whether the first master chip outputs abnormal information about the second master chip. When the first master chip outputs abnormal information about the second master chip, determine whether the verification subject of the random access memory is the second master chip. When the verification subject of the random access memory is the second master chip, change the verification subject of the random access memory to the first master chip. Simultaneously, determine whether the verification subject of the flash memory is the second master chip. When the verification subject of the flash memory is the second master chip, change the verification subject of the flash memory to the first master chip. Simultaneously, determine whether the verification subject of the register is the second master chip. When the verification subject of the register is the second master chip, change the verification subject of the register to the first master chip. Determine whether the second master chip outputs abnormal information of the first master chip. When the second master chip outputs abnormal information of the first master chip, determine whether the verification subject of the random access memory is the first master chip. When the verification subject of the random access memory is the first master chip, change the verification subject of the random access memory to the second master chip; at the same time, determine whether the verification subject of the flash memory is the first master chip. When the verification subject of the flash memory is the first master chip, change the verification subject of the flash memory to the second master chip; at the same time, determine whether the verification subject of the register is the first master chip. When the verification subject of the register is the first master chip, change the verification subject of the register to the second master chip.

[0011] In a second aspect of the embodiments of the present disclosure, an abnormality detection device for a dual-chip control system is provided. The device includes: The data synchronization acquisition module is configured so that the first master chip and the second master chip determine data acquisition synchronization information based on the first input and output lines. After the data acquisition synchronization information is determined, the first master chip and the second master chip synchronously acquire data. The data synchronization transmission module is configured such that the first master chip processes the collected data and packages it to form a first data packet, while the second master chip processes the collected data and packages it to form a second data packet; the first master chip and the second master chip determine data transmission synchronization information based on the second input and output lines. After determining the data transmission synchronization information, the first master chip sends the first data packet to the second master chip via the data transceiver line, while the second master chip sends the second data packet to the first master chip via the data transceiver line. The main chip abnormality judgment module 1 is configured as the first main chip to determine whether the second data packet is abnormal. When the second data packet is abnormal, the first main chip outputs the second main chip abnormality information; at the same time, the second main chip determines whether the first data packet is abnormal. When the first data packet is abnormal, the second main chip outputs the first main chip abnormality information.

[0012] Preferably, the main chip abnormality determination module 1 includes: a first data packet anomaly determination unit configured to determine whether the first data packet is lost or whether a verification error occurs, and when the determination result is that the first data packet is lost or a verification error occurs, increase the first anomaly accumulated value by one; otherwise, update the first anomaly accumulated value to an initial value; Determine whether the first abnormality cumulative value is equal to the abnormality cumulative threshold, when the first abnormality cumulative value is equal to the abnormality cumulative threshold, determine that the first data packet is abnormal, and update the first abnormality cumulative value to an initial value; otherwise, determine that the first data packet is normal; a second data packet anomaly determination unit configured to determine whether the second data packet is lost or a verification error occurs, and when the determination result is that the second data packet is lost or a verification error occurs, increase the second anomaly accumulated value by one; otherwise, update the second anomaly accumulated value to an initial value; Determine whether the second abnormality cumulative value is equal to the abnormality cumulative threshold. When the second abnormality cumulative value is equal to the abnormality cumulative threshold, determine that the second data packet is abnormal and update the second abnormality cumulative value to the initial value; otherwise, determine that the second data packet is normal.

[0013] Preferably, the first data packet anomaly determination unit includes: a first data packet loss determination subunit configured to perform timing after determining the data transmission synchronization information, and determine whether the first data packet is received within a timing threshold, and when the first data packet is received within the timing threshold, determine that the first data packet is not lost; otherwise, determine that the first data packet is lost; a first data packet check error determination subunit configured to, when the first data packet is not lost, calculate a first check calculation value based on the first data packet, and compare the first check calculation value with a first check reference value in the first data packet; when the first check calculation value is the same as the first check reference value, determine that no check error occurs in the first data packet; otherwise, determine that a check error occurs in the first data packet; The second data packet anomaly determination unit includes: a second data packet loss determination subunit configured to perform timing after determining the data transmission synchronization information, and determine whether the second data packet is received within a timing threshold, and when the second data packet is received within the timing threshold, determine that the second data packet is not lost; otherwise, determine that the second data packet is lost; The second data packet verification error determination subunit is configured to, when the second data packet is not lost, calculate a second verification calculation value based on the second data packet, and compare the second verification calculation value with a second verification control value in the second data packet; when the second verification calculation value is the same as the second verification control value, determine that no verification error occurs in the second data packet; otherwise, determine that a verification error occurs in the second data packet.

[0014] It should be understood that the contents described in the summary section are not intended to define the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Beneficial effects

[0015] 1. The abnormality detection method and device for a dual-chip control system of the disclosed embodiment allow the first master chip to determine whether the second master chip is abnormal based on the second data packet formed by the second master chip, and at the same time allow the second master chip to determine whether the first master chip is abnormal based on the first data packet formed by the first master chip. That is, the first master chip and the second master chip perform abnormality detection synchronously with each other, and both can detect abnormalities in a timely manner. In addition, the accuracy of abnormality detection based on data packets is higher.

[0016] 2. The abnormality detection method and device for the dual-chip control system of the embodiment of the present disclosure determines that the first / second data packet is abnormal only when data packet loss or verification errors occur in the first / second data packet multiple times in a row, and then determines that the first / second main chip is abnormal. This method can improve the accuracy of the abnormality determination of the first / second main chip.

[0017] 3. In the abnormality detection method and device for the dual-chip control system of the embodiment of the present disclosure, the abnormality cumulative threshold for determining the abnormality of the first / second data packet is not randomly or arbitrarily selected, but is obtained based on the abnormality determination accuracy of the first / second main chip under different first-level abnormality cumulative thresholds of multiple dual-chip control systems. The abnormality cumulative threshold obtained in this way will further improve the accuracy of the abnormality determination of the first / second main chip.

[0018] 4. The abnormality detection method and device of the dual-chip control system of the embodiment of the present disclosure can determine whether the first main chip and the second main chip are ultimately abnormal by continuously obtaining the temperature value judgment results of the first main chip and the second main chip when processing data, thereby improving the accuracy of abnormality detection of the first main chip and the second main chip in the dual-chip control system.

[0019] 5. The abnormality detection method and device of the dual-chip control system of the embodiment of the present disclosure, in addition to being able to accurately and timely detect whether the first main chip and the second main chip of the dual-chip control system have abnormalities, can also accurately and timely detect whether the random access memory, flash memory, and registers of the dual-chip control system have abnormalities by periodically accessing the random access memory, flash memory, and registers by the first main chip or the second main chip. When the access subject of the random access memory, flash memory, and register is determined to be abnormal, the access subject of the random access memory, flash memory, and register can be automatically changed, thereby ensuring that the random access memory, flash memory, and register can always perform abnormality judgment normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein: Figure 1 A flow chart illustrating an abnormality detection method of a dual-chip control system according to some embodiments of the present disclosure is shown; Figure 2 A block diagram illustrating an abnormality detection device of a dual-chip control system according to some embodiments of the present disclosure is shown; Figure 3 A schematic diagram showing the connection between the first master chip and the second master chip in some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0021] The following describes embodiments of the present disclosure in more detail with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0022] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to." The term "based on" should be understood as "based at least in part on." The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment." The terms "first," "second," etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0023] Figure 1 A flow chart of a method 100 for detecting anomalies in a dual-chip control system according to some embodiments of the present disclosure is shown. The method 100 includes: Step 102: The first master chip and the second master chip determine data acquisition synchronization information based on the first input and output line. After the data acquisition synchronization information is determined, the first master chip and the second master chip synchronously acquire data.

[0024] The first master chip is provided with a data receiving interface, and the second master chip is also provided with a data receiving interface. External data is sent to the data receiving interface of the first master chip and the data receiving interface of the second master chip, respectively. In this embodiment, the external data can be data sent by other components within the dual-chip control system, or data sent by other components outside the dual-chip control system. Although other components send external data to the first and second master chips simultaneously, there is no guarantee that the first and second master chips will receive the external data at the same time.

[0025] When the first master chip and the second master chip collect (ie receive) external data, they receive data one frame at a time. In order to enable the first master chip and the second master chip to receive the same frame data synchronously, as shown in FIG. Figure 3 As shown, in this embodiment, a first input / output line is set between the first master chip and the second master chip.

[0026] Before receiving a frame of data, the first master chip confirms data acquisition synchronization information with the second master chip. This synchronization information can be determined by the first master chip sending a "data acquisition ready message" to the second master chip via the first input / output line. After sending this "data acquisition ready message," the first master chip immediately receives a frame of data (assuming it's data frame A). After receiving this "data acquisition ready message," the second master chip also immediately receives a frame of data (i.e., data frame A). Because the "sending" and "receiving" of information are nearly synchronous, the first and second master chips can simultaneously receive the same frame of data.

[0027] In short, before each frame of data is collected, the first and second master chips will confirm data collection synchronization information through the first input and output lines. This allows the first and second master chips to always receive the same frame of data synchronously. After the first master chip collects a frame of data, it will immediately process it. Similarly, after the second master chip collects a frame of data, it will also immediately process it. When each frame of data is collected synchronously, the subsequent processing of each frame of data can also be synchronized.

[0028] Step 104: The first master chip processes the collected data and packages it to form a first data packet, while the second master chip processes the collected data and packages it to form a second data packet; the first master chip and the second master chip determine data transmission synchronization information based on the second input and output line. After determining the data transmission synchronization information, the first master chip sends the first data packet to the second master chip based on the data transceiver line, while the second master chip sends the second data packet to the first master chip based on the data transceiver line.

[0029] After collecting a frame of data, the first master chip will immediately process the frame of data. At the same time, after collecting a frame of data, the second master chip will also immediately process the frame of data. The specific processing can directly adopt the existing technology. The difference from the existing technology is that the first master chip will also form a first data packet based on the processed data, and the second master chip will also form a second data packet based on the processed data. Or it can be understood that the collected current frame data is used as the input data of the first master chip / the second master chip, and then the first master chip / the second master chip processes the input data to obtain output data. This step exists in the existing technology itself, but this step also packages the output data to obtain the first data packet / the second data packet.

[0030] In addition, if Figure 3 As shown, in this embodiment, a second input / output line and a data transceiver line are provided between the first master chip and the second master chip. In this step, the first master chip also determines data transmission synchronization information with the second master chip based on the second input / output line. Determining the data transmission synchronization information can specifically be that the first master chip sends a "data transmission possible information" to the second master chip via the second input / output line. For a certain "data transmission possible information", after sending the "data transmission possible information", the first master chip immediately sends the first data packet to the second master chip via the data transceiver line. After receiving the "data transmission possible information", the second master chip also immediately sends the second data packet to the first master chip via the data transceiver line.

[0031] In this step, the determination of data transmission synchronization information by the first master chip and the second master chip is not necessarily related to the formation of the first data packet and the second data packet. The data transmission synchronization information is not necessarily determined after the first data packet and the second data packet are formed, but the data transmission synchronization information is determined at a certain time point or under certain conditions. If there is an abnormality in the data processing of the first master chip or the second master chip, the first data packet and the second data packet may not be formed. Even if the first data packet and the second data packet are not formed, the first master chip and the second master chip will still determine the data transmission synchronization information. It’s just that when the first data packet / the second data packet is sent based on the data transceiver line, there is no first data packet / the second data packet to send. If the data processing of the first master chip or the second master chip is normal, the first data packet and the second data packet are usually formed before the data transmission synchronization information is determined.

[0032] In short, this step is mainly used to form the first data packet and the second data packet, and after determining the data sending synchronization information, let the first main chip send the formed first data packet to the second main chip and let the second main chip send the formed second data packet to the first main chip, so that the abnormality judgment of the main chip can be realized in the subsequent steps.

[0033] Step 106: The first master chip determines whether the second data packet is abnormal. If the second data packet is abnormal, the first master chip outputs second master chip abnormal information. Meanwhile, the second master chip determines whether the first data packet is abnormal. If the first data packet is abnormal, the second master chip outputs first master chip abnormal information.

[0034] In this step, the first master chip determines whether the second master chip is abnormal by determining whether the second data packet is abnormal. If the second master chip is abnormal, the first master chip will output "second master chip abnormality information." This effectively detects an abnormality in the dual-chip control system and indicates that the abnormality is in the second master chip. Similarly, the second master chip determines whether the first master chip is abnormal by determining whether the first data packet is abnormal. If the first master chip is abnormal, the second master chip will output "first master chip abnormality information." This effectively detects an abnormality in the dual-chip control system and indicates that the abnormality is in the first master chip.

[0035] Steps 102, 104, and 106 are executed in a loop. After completing each of these steps, they are executed again. Considering steps 102, 104, and 106 as a "big step," each big step processes one frame of data. That is, each time the first and second master chips receive a frame of data, they execute the "big step" once.

[0036] In summary, the method of this embodiment executes the above steps. Once an abnormality occurs in the first main chip / second main chip (mainly an abnormality in data processing), the first data packet / second data packet will be determined to be abnormal. Once the first data packet / second data packet is determined to be abnormal, it is equivalent to detecting an abnormality of the dual-chip control system (first main chip / second main chip), and this abnormality detection is timely and accurate.

[0037] Furthermore, in this embodiment, the second master chip determines whether the first data packet is abnormal by: Step 312: Determine whether the first data packet is lost or a verification error occurs. If the determination result is that the first data packet is lost or a verification error occurs, add one to the first abnormality accumulated value; otherwise, update the first abnormality accumulated value to the initial value.

[0038] Step 314: Determine whether the first abnormality cumulative value is equal to the abnormality cumulative threshold. When the first abnormality cumulative value is equal to the abnormality cumulative threshold, determine that the first data packet is abnormal and update the first abnormality cumulative value to the initial value; otherwise, determine that the first data packet is normal.

[0039] The initial value of the first abnormality accumulation value may be 0, and the abnormality accumulation threshold may be 3.

[0040] Case 1-1: Assume that during a certain "major step" pass, in step 312, the first packet is not lost and no parity error occurs, and the first accumulated error value is 1. Since the first packet is not lost and no parity error occurs, the first accumulated error value is updated to 0. In step 314, since the first accumulated error value (0) is not equal to the accumulated error threshold (3), the first packet is determined to be normal.

[0041] Case 1-2: Assume that during a "major step" pass, the first packet is lost in step 312, and the first cumulative anomaly value is 0 at this time. Since the first packet is lost, the first cumulative anomaly value is incremented to 1. In step 314, since the first cumulative anomaly value (1) is not equal to the cumulative anomaly threshold (3), the first packet is determined to be normal.

[0042] Case 1-3: Assume that during a certain "major step" pass, in step 312, the first packet is not lost, but a parity error occurs. Assume that the first anomaly cumulative value is 2. Since the parity error occurred in the first packet, the first anomaly cumulative value is incremented by one to 3. In step 314, since the first anomaly cumulative value (3) is equal to the anomaly cumulative threshold (3), the first packet is determined to be anomaly.

[0043] During a single "big step," the first data packet only needs to be checked for abnormality once. Even if data packet loss or a checksum error occurs in step 312 of that "big step," the first data packet is not necessarily considered abnormal. Only if data packet loss or a checksum error occurs in multiple consecutive "big steps" (i.e., the first anomaly cumulative value equals the anomaly cumulative threshold) will the first data packet be considered abnormal. This improves the accuracy of first data packet anomaly determinations, and thus the accuracy of first master chip anomaly determinations.

[0044] Similarly, the first main chip determines whether the second data packet is abnormal by: Step 322: Determine whether the second data packet is lost or a verification error occurs. If the determination result is that the second data packet is lost or a verification error occurs, add one to the second abnormality accumulated value; otherwise, update the second abnormality accumulated value to the initial value.

[0045] Step 324: Determine whether the second abnormality cumulative value is equal to the abnormality cumulative threshold. When the second abnormality cumulative value is equal to the abnormality cumulative threshold, determine that the second data packet is abnormal and update the second abnormality cumulative value to the initial value; otherwise, determine that the second data packet is normal.

[0046] The initial value of the second abnormal accumulation value may be 0, and the abnormal accumulation threshold may be 3. In the same "big step", steps 322 and 324 are performed synchronously with steps 312 and 314, and the initial value of the second abnormal accumulation value is the same as the initial value of the first abnormal accumulation value.

[0047] Case 2-1: Assume that during a certain "major step" pass, in step 322, the second data packet is not lost and no parity error occurs, and assume that the second accumulated error value is 0 at this time. Since the second data packet is not lost and no parity error occurs, the second accumulated error value is updated to 0. In step 324, since the second accumulated error value (0) is not equal to the accumulated error threshold (3), the second data packet is determined to be normal.

[0048] Case 2-2: Assume that during a "major step" pass, the second packet is lost in step 322, and the second anomaly cumulative value is 2. Because the second packet is lost, the second anomaly cumulative value is incremented to 3. In step 324, since the second anomaly cumulative value (3) is equal to the anomaly cumulative threshold (3), the second packet is determined to be anomaly.

[0049] Case 2-3: Assume that during a certain "major step" pass, in step 322, the second packet is not lost, but a parity error occurs. Assume that the second error accumulation value is 0 at this time. Since the parity error occurred in the second packet, the second error accumulation value is incremented to 1. In step 324, since the second error accumulation value (1) is not equal to the error accumulation threshold (3), the second packet is determined to be normal.

[0050] During a single "big step," the second data packet only needs to be checked for abnormality once. Even if data packet loss or a checksum error occurs in step 322 of that "big step," the second data packet is not necessarily considered abnormal. Only if data packet loss or a checksum error occurs in multiple consecutive "big steps" (i.e., the second anomaly accumulation value equals the anomaly accumulation threshold) will the second data packet be considered abnormal. This improves the accuracy of second data packet anomaly determination, and thus the accuracy of second master chip anomaly determination.

[0051] Furthermore, the anomaly detection method of this embodiment further includes determining an anomaly accumulation threshold in advance, specifically: Obtain the abnormality determination accuracy of the first main chip and the second main chip of multiple dual-chip control systems under different first-level abnormality accumulation thresholds.

[0052] For example: For dual-chip control system No. 1, assuming that both the first and second main chips of dual-chip control system No. 1 are normal, first obtain the abnormality determination accuracy of the first and second main chips of dual-chip control system No. 1 when the first-level abnormality accumulation threshold is "1." This requires obtaining the abnormality determination results of the first and second main chips of dual-chip control system No. 1 multiple times (for example, 100 times) when the first-level abnormality accumulation threshold is "1." If 30 out of 100 determination results are correct, then the abnormality determination accuracy of the first and second main chips of dual-chip control system No. 1 when the first-level abnormality accumulation threshold is "1" is 30%. Next, the accuracy of abnormality determination for the first and second main chips in dual-chip control system No. 1 when the first-level abnormality cumulative threshold is "2" is obtained: This requires multiple (for example, 100) acquisitions of the abnormality determination results for the first and second main chips in dual-chip control system No. 1 when the first-level abnormality cumulative threshold is "2." If 35 out of 100 determinations are correct, then the accuracy of abnormality determination for the first and second main chips in dual-chip control system No. 1 when the first-level abnormality cumulative threshold is "2" is 35%. Next, .... Finally, the accuracy of abnormality determination for the first and second main chips in dual-chip control system No. 1 when the first-level abnormality cumulative threshold is "20" is obtained: This requires multiple (for example, 100) acquisitions of the abnormality determination results for the first and second main chips in dual-chip control system No. 1 when the first-level abnormality cumulative threshold is "20." If 60 out of 100 determinations are correct, then the accuracy of abnormality determination for the first and second main chips in dual-chip control system No. 1 when the first-level abnormality cumulative threshold is "20" is 60%.

[0053] For dual-chip control system No. 2, assume that both the first and second main chips are known to be abnormal. First, determine the abnormality accuracy of the first and second main chips when the first-level abnormality cumulative threshold is "1." Simply obtain the abnormality determination results for the first and second main chips multiple times (for example, 100 times) when the first-level abnormality cumulative threshold is "1." If 31 out of 100 determinations are correct, then the abnormality determination accuracy of the first and second main chips when the first-level abnormality cumulative threshold is "1" is 31%. Then, ...

[0054] For dual-chip control system No. 3, assume that the first main chip of the dual-chip control system No. 3 is normal and the second main chip is abnormal. First, obtain the abnormality determination accuracy of the first and second main chips of the dual-chip control system No. 3 when the first-level abnormality accumulation threshold is "1".

[0055] For a dual-chip control system numbered n, assuming that the first main chip in the control system numbered n is abnormal and the second main chip is normal, first obtain the abnormality determination accuracy of the first and second main chips in the control system numbered n when the first-level abnormality accumulation threshold is "1."

[0056] In summary, this step can be used to obtain the abnormality determination accuracy of the first main chip and the second main chip of multiple dual-chip control systems under different first-level abnormality accumulation thresholds.

[0057] Furthermore, in this embodiment, determining the abnormal accumulation threshold further includes: The first-level abnormality accumulation threshold of each dual-chip control system when the abnormality determination accuracy of the first main chip and the second main chip is the highest is determined and used as the second-level abnormality accumulation threshold.

[0058] For example: Assume that the abnormality detection accuracy of dual-chip control system No. 1 is 30% when the first-level abnormality accumulation threshold is "1," ... 90% when the first-level abnormality accumulation threshold is "5," ... and 60% when the first-level abnormality accumulation threshold is "20." Among them, the abnormality detection accuracy is the highest, at 90%, when the first-level abnormality accumulation thresholds are "5" and "6."

[0059] Assume that the abnormality detection accuracy of the dual-chip control system No. 2 is 31% when the first-level abnormality accumulation threshold is "1," ... 91% when the first-level abnormality accumulation threshold is "5," ... and 66% when the first-level abnormality accumulation threshold is "20." Among them, the abnormality detection accuracy is the highest at "4," "5," and "6," reaching 91%.

[0060] Assume that the abnormality detection accuracy of the No. 3 dual-chip control system is 29% when the first-level abnormality accumulation threshold is "1," ... 88% when the first-level abnormality accumulation threshold is "5," ... and 55% when the first-level abnormality accumulation threshold is "20." Among them, the abnormality detection accuracy is the highest, at 93%, when the first-level abnormality accumulation thresholds are "6" and "7."

[0061] Assume that the abnormality detection accuracy of the No. 4 dual-chip control system is 32% when the first-level abnormality accumulation threshold is "1," ... 92% when the first-level abnormality accumulation threshold is "5," ... and 64% when the first-level abnormality accumulation threshold is "20." Among them, the abnormality detection accuracy is the highest, at 92%, when the first-level abnormality accumulation thresholds are "5" and "8."

[0062] Then, the secondary abnormality cumulative thresholds can be obtained as "5" and "6" through the dual-chip control system No. 1; the secondary abnormality cumulative thresholds can be obtained as "4", "5" and "6" through the dual-chip control system No. 2; the secondary abnormality cumulative thresholds can be obtained as "6" and "7" through the dual-chip control system No. 3; and the secondary abnormality cumulative thresholds can be obtained as "5" and "8" through the dual-chip control system No. 4.

[0063] Furthermore, in this embodiment, determining the abnormal accumulation threshold further includes: Determine the second-level anomaly accumulation threshold with the highest frequency and use it as the third-level anomaly accumulation threshold.

[0064] Assume that the second-level anomaly accumulation thresholds are "5, 6"; "4, 5, 6"; "6, 7"; and "5, 8." Since "5" and "6" appear most frequently, they are used as the third-level anomaly accumulation thresholds.

[0065] Furthermore, in this embodiment, determining the abnormal accumulation threshold further includes: Determine whether the number of three-level abnormality accumulation thresholds is one. When the number of three-level abnormality accumulation thresholds is one, use the three-level abnormality accumulation threshold as the final abnormality accumulation threshold; otherwise, select the three-level abnormality accumulation threshold with the smallest value as the final abnormality accumulation threshold.

[0066] When the three-level abnormality accumulation threshold is "5" and "6", since the number of three-level abnormality accumulation thresholds is not one, the three-level abnormality accumulation threshold with the smallest value is selected as the final abnormality accumulation threshold, that is, "5" is used as the final abnormality accumulation threshold.

[0067] In summary, by determining the abnormality accumulation threshold value through this step, the accuracy of abnormality determination of the first master chip and the second master chip can be improved.

[0068] Furthermore, in this embodiment, determining whether the first data packet is lost or whether a check error occurs is specifically as follows: After determining the data transmission synchronization information, timing is performed to determine whether the first data packet is received within the timing threshold. When the first data packet is received within the timing threshold, it is determined that the first data packet is not lost; otherwise, it is determined that the first data packet is lost.

[0069] If the first master chip experiences data processing anomalies, it's likely that the first master chip hasn't completed processing the current frame of data before "confirming data transmission synchronization information," and thus hasn't generated the first data packet. Furthermore, after "confirming data transmission synchronization information," the first data packet isn't sent to the second master chip. Consequently, the second master chip won't receive the first data packet within the timing threshold, and the first data packet is considered lost.

[0070] When the first data packet is not lost, a first verification calculation value is calculated based on the first data packet, and the first verification calculation value is compared with the first verification control value in the first data packet. When the first verification calculation value is the same as the first verification control value, it is determined that no verification error occurs in the first data packet; otherwise, it is determined that a verification error occurs in the first data packet.

[0071] If the second master chip receives the first data packet within the timing threshold, it indicates that the first data packet has not been lost. At this point, the second master chip calculates a first checksum value based on the first data packet and obtains a first checksum comparison value based on the first data packet. Specifically, assuming the first data packet has 20 bytes, the first checksum value can be obtained by calculating the sum of the first 19 bytes; the last byte of the first data packet is used as the first checksum comparison value. Finally, by comparing the first checksum value with the first checksum comparison value, it can be determined whether the first data packet has a checksum error.

[0072] This step can promptly and accurately determine whether the first data packet is lost or whether a verification error occurs, thereby promptly and accurately helping to determine whether the first data packet is abnormal.

[0073] Similarly, determining whether the second data packet is lost or whether a check error occurs is specifically as follows: After determining the data transmission synchronization information, timing is performed to determine whether the second data packet is received within the timing threshold. When the second data packet is received within the timing threshold, it is determined that the second data packet is not lost; otherwise, it is determined that the second data packet is lost.

[0074] If the second master chip experiences data processing anomalies, it's likely that the second master chip hasn't completed processing the current frame of data before "confirming the data transmission synchronization information," and thus hasn't generated the second data packet. Furthermore, after "confirming the data transmission synchronization information," the second data packet isn't sent to the first master chip. Consequently, the first master chip won't receive the second data packet within the timing threshold, and the second data packet is considered lost.

[0075] When the second data packet is not lost, a second verification calculation value is calculated based on the second data packet, and the second verification calculation value is compared with the second verification control value in the second data packet. When the second verification calculation value is the same as the second verification control value, it is determined that no verification error occurs in the second data packet; otherwise, it is determined that a verification error occurs in the second data packet.

[0076] If the first master chip receives the second data packet within the timing threshold, it indicates that the second data packet has not been lost. At this point, the first master chip calculates a second checksum value based on the second data packet and obtains a second checksum comparison value based on the second data packet. Specifically, assuming the second data packet has 30 bytes, the second checksum value can be obtained by calculating the sum of the first 29 bytes; the last byte of the second data packet is used as the second checksum comparison value. Finally, by comparing the second checksum value with the second checksum comparison value, it can be determined whether the second data packet has a checksum error.

[0077] This step can promptly and accurately determine whether the second data packet is lost or whether a verification error occurs, thereby promptly and accurately helping to determine whether the second data packet is abnormal.

[0078] Furthermore, the abnormality detection method of the dual-chip control system of this embodiment also includes: After determining the data sending synchronization information, obtain the first temperature value of the first master chip and determine whether the first temperature value is less than the first temperature threshold or greater than the second temperature threshold. When the first temperature value is less than the first temperature threshold or greater than the second temperature threshold, determine that the first master chip is abnormal; at the same time, obtain the second temperature value of the second master chip and determine whether the second temperature value is less than the first temperature threshold or greater than the second temperature threshold. When the second temperature value is less than the first temperature threshold or greater than the second temperature threshold, determine that the second master chip is abnormal.

[0079] The abnormality detection method of this embodiment can not only detect whether the first main chip and the second main chip of the dual-chip control system are abnormal by "whether the specific data processing is abnormal", but also determine whether the first main chip and the second main chip are abnormal by the temperature when the first main chip and the second main chip process data.

[0080] Assuming the first and second master chips are processing data normally, the temperature values ​​of the first and second master chips should be within a reasonable range, that is, within a range greater than or equal to the first temperature threshold and less than or equal to the second temperature threshold. If the temperature of the first and second master chips during data processing is not within a range greater than or equal to the first temperature threshold and less than or equal to the second temperature threshold, it indicates that an abnormality has occurred during data processing by the first and second master chips.

[0081] The first temperature value of the first master chip can be obtained by a temperature sensor provided on the first master chip, and the second temperature value of the second master chip can be obtained by a temperature sensor provided on the second master chip. In this embodiment, the first temperature value of the first master chip and the second temperature value of the second master chip are obtained after the data transmission synchronization information is determined. This is because the first and second master chips have just finished processing the current frame data (or are still processing data if there is an abnormality in data processing). Therefore, the temperature values ​​obtained at this time are the most accurate, and thus it is possible to determine whether the first and second master chips are abnormal based on the temperature values.

[0082] In summary, the abnormality detection method of this embodiment can also determine whether the first main chip and the second main chip are ultimately abnormal by repeatedly obtaining the temperature value judgment results of the first main chip and the second main chip when processing data, thereby improving the accuracy of abnormality detection of the first main chip and the second main chip in the dual-chip control system. There are two situations here: 1. The first main chip and the second main chip have already output main chip abnormality information, so no matter what the temperature value judgment result is, the main chip will be judged to be abnormal. 2. Neither the first main chip nor the second main chip has output main chip abnormality information. At this time, if the temperature value judgment result is "normal", then the final judgment result of the first main chip and the second main chip is "normal"; if the temperature value judgment result is "abnormal", then the final judgment result of the first main chip and the second main chip is "abnormal".

[0083] Furthermore, the abnormality detection method of the dual-chip control system of this embodiment also includes: The first master chip or the second master chip periodically verifies the random access memory to determine whether an abnormality occurs in the random access memory: obtaining a specific space value one of the random access memory, determining whether the specific space value one is the same as a specific space preset value one, and when the specific space value one is different from the specific space preset value one, determining that the random access memory is abnormal.

[0084] The value of a section of RAM is pre-programmed. If the value of this section of RAM changes during operation of the dual-chip control system, it indicates that an abnormality has occurred in the RAM. In summary, the abnormality detection method of this embodiment can also have the first master chip or the second master chip periodically verify the value of this section of RAM (i.e., determine whether the specific space value 1 is the same as the specific space preset value 1). If the first master chip or the second master chip finds that the specific space value 1 is different from the specific space preset value 1, it can be determined that an abnormality has occurred in the RAM.

[0085] The first main chip or the second main chip periodically verifies the flash memory to determine whether the flash memory is abnormal: obtains the specific space value 2 of the flash memory, determines whether the specific space value 2 is the same as the specific space preset value 2, and when the specific space value 2 is different from the specific space preset value 2, determines that the flash memory is abnormal.

[0086] The value of a section of space in the flash memory is pre-programmed. If the value of this section of space in the flash memory changes during operation of the dual-chip control system, it indicates that the flash memory has experienced an anomaly. In summary, the anomaly detection method of this embodiment can also have the first master chip or the second master chip periodically verify the value of this section of space in the flash memory (i.e., determine whether the specific space value 2 is the same as the specific space preset value 2). If the first master chip or the second master chip finds that the specific space value 2 is different from the specific space preset value 2, then it can be determined that the flash memory has experienced an anomaly.

[0087] The first main chip or the second main chip periodically verifies the register to determine whether there is an abnormality in the register: obtain the specific space value three of the register, determine whether the specific space value three is the same as the specific space preset value three, and when the specific space value three is different from the specific space preset value three, determine that the register is abnormal.

[0088] The value of a certain range in the register is pre-programmed. If the value of this range changes during operation of the dual-chip control system, it indicates a register anomaly. In summary, the anomaly detection method of this embodiment can also have the first or second master chip periodically verify the value of this range in the register (i.e., determine whether the specific range value three is the same as the specific range preset value three). If the first or second master chip finds that the specific range value three is different from the specific range preset value three, it can determine that a register anomaly has occurred.

[0089] The abnormality detection method of this embodiment can not only accurately and promptly detect whether the first main chip and the second main chip of the dual-chip control system have abnormalities, but also accurately and promptly detect whether the random access memory, flash memory, and registers of the dual-chip control system have abnormalities.

[0090] Furthermore, the abnormality detection method of the dual-chip control system of this embodiment also includes: Determine whether the first master chip outputs abnormal information about the second master chip. When the first master chip outputs abnormal information about the second master chip, determine whether the verification subject of the random access memory is the second master chip. When the verification subject of the random access memory is the second master chip, change the verification subject of the random access memory to the first master chip. Simultaneously, determine whether the verification subject of the flash memory is the second master chip. When the verification subject of the flash memory is the second master chip, change the verification subject of the flash memory to the first master chip. Simultaneously, determine whether the verification subject of the register is the second master chip. When the verification subject of the register is the second master chip, change the verification subject of the register to the first master chip. Determine whether the second master chip outputs abnormal information of the first master chip. When the second master chip outputs abnormal information of the first master chip, determine whether the verification subject of the random access memory is the first master chip. When the verification subject of the random access memory is the first master chip, change the verification subject of the random access memory to the second master chip; at the same time, determine whether the verification subject of the flash memory is the first master chip. When the verification subject of the flash memory is the first master chip, change the verification subject of the flash memory to the second master chip; at the same time, determine whether the verification subject of the register is the first master chip. When the verification subject of the register is the first master chip, change the verification subject of the register to the second master chip.

[0091] When the first master chip and / or second master chip of a dual-chip control system starts working (including three situations: the first master chip and the second master chip are both restarted; or the first master chip is operating normally while the second master chip is restarted; or the second master chip is operating normally while the first master chip is restarted), the dual-chip control system can randomly use the first master chip or the second master chip as the verification subject of the random access memory, randomly use the first master chip or the second master chip as the verification subject of the flash memory, and randomly use the first master chip or the second master chip as the verification subject of the register. For example, the first master chip can be used as the verification subject of the random access memory (the first master chip periodically verifies the random access memory to determine whether the random access memory has an abnormality), the second master chip can be used as the verification subject of the flash memory (the second master chip periodically verifies the flash memory to determine whether the flash memory has an abnormality), and the first master chip can be used as the verification subject of the register (the first master chip periodically verifies the register to determine whether the register has an abnormality).

[0092] When the first master chip experiences an abnormality, the dual-chip control system can obtain the abnormality information of the first master chip output by the second master chip. At this time, the dual-chip control system will first determine whether the verification object is verified by the first master chip. If so, the verification subject of the verification object is changed from the first master chip to the second master chip. For example, the verification subject of the random access memory and registers can be changed from the first master chip to the second master chip, thereby ensuring that the random access memory and registers can still perform abnormality detection normally.

[0093] When the second master chip experiences an abnormality, the dual-chip control system receives the abnormality information from the first master chip. It then determines whether a verification target is being verified by the second master chip. If so, it changes the verification target from the second master chip to the first master chip. For example, changing the verification target for a flash memory from the second master chip to the first master chip ensures that subsequent abnormality determinations can continue normally.

[0094] Normally, both the first and second main chips will not experience anomalies simultaneously. If only the first or second main chip experiences an anomaly, the dual-chip control system will continue to operate normally. In this case, only the first or second main chip with the anomaly needs to be repaired or replaced. When an anomaly is detected in the first or second main chip, the dual-chip control system will temporarily suspend execution of steps 102 through 106 until the anomaly in the first or second main chip is repaired or replaced.

[0095] Assume that abnormalities occur in the first main chip and the second main chip at the same time, that is, the dual-chip control system simultaneously obtains the abnormal information of the first main chip output by the second main chip and the abnormal information of the second main chip output by the first main chip, then the first main chip and the second main chip will need to be repaired and replaced subsequently. Therefore, the dual-chip control system itself will not be able to operate normally subsequently. Therefore, it does not matter even if the random access memory, flash memory, and registers are replaced with the abnormal verification subject.

[0096] Figure 2 FIG. 2 is a block diagram of an abnormality detection device 200 for a dual-chip control system according to some embodiments of the present disclosure. The device 200 includes: The data synchronization acquisition module 202 is configured so that the first master chip and the second master chip determine data acquisition synchronization information based on the first input and output line. After the data acquisition synchronization information is determined, the first master chip and the second master chip synchronously acquire data.

[0097] The data synchronization transmission module 204 is configured such that the first master chip processes the collected data and packages it into a first data packet, while the second master chip processes the collected data and packages it into a second data packet; the first master chip and the second master chip determine data transmission synchronization information based on the second input / output line. After determining the data transmission synchronization information, the first master chip transmits the first data packet to the second master chip via the data transceiver line, while the second master chip transmits the second data packet to the first master chip via the data transceiver line. The main chip abnormality determination module 206 is configured as the first main chip to determine whether the second data packet is abnormal. When the second data packet is abnormal, the first main chip outputs the second main chip abnormality information; at the same time, the second main chip determines whether the first data packet is abnormal. When the first data packet is abnormal, the second main chip outputs the first main chip abnormality information.

[0098] In some embodiments, the main chip abnormality determination module 1 206 includes: a first data packet anomaly determination unit configured to determine whether the first data packet is lost or whether a verification error occurs, and when the determination result is that the first data packet is lost or a verification error occurs, increase the first anomaly accumulated value by one; otherwise, update the first anomaly accumulated value to an initial value; Determine whether the first abnormality cumulative value is equal to the abnormality cumulative threshold. When the first abnormality cumulative value is equal to the abnormality cumulative threshold, determine that the first data packet is abnormal and update the first abnormality cumulative value to an initial value; otherwise, determine that the first data packet is normal.

[0099] a second data packet anomaly determination unit configured to determine whether the second data packet is lost or a verification error occurs, and when the determination result is that the second data packet is lost or a verification error occurs, increase the second anomaly accumulated value by one; otherwise, update the second anomaly accumulated value to an initial value; Determine whether the second abnormality cumulative value is equal to the abnormality cumulative threshold. When the second abnormality cumulative value is equal to the abnormality cumulative threshold, determine that the second data packet is abnormal and update the second abnormality cumulative value to the initial value; otherwise, determine that the second data packet is normal.

[0100] In some embodiments, the first data packet anomaly determination unit includes: The first data packet loss determination subunit is configured to perform timing after determining the data transmission synchronization information, and determine whether the first data packet is received within a timing threshold. When the first data packet is received within the timing threshold, it is determined that the first data packet is not lost; otherwise, it is determined that the first data packet is lost.

[0101] The first data packet check error determination subunit is configured to, when the first data packet is not lost, calculate a first check calculation value based on the first data packet, and compare the first check calculation value with a first check control value in the first data packet; when the first check calculation value is the same as the first check control value, determine that no check error occurs in the first data packet; otherwise, determine that a check error occurs in the first data packet.

[0102] The second data packet anomaly determination unit includes: The second data packet loss determination subunit is configured to perform timing after determining the data transmission synchronization information, and determine whether the second data packet is received within the timing threshold. When the second data packet is received within the timing threshold, it is determined that the second data packet is not lost; otherwise, it is determined that the second data packet is lost.

[0103] The second data packet verification error determination subunit is configured to, when the second data packet is not lost, calculate a second verification calculation value based on the second data packet, and compare the second verification calculation value with a second verification control value in the second data packet; when the second verification calculation value is the same as the second verification control value, determine that no verification error occurs in the second data packet; otherwise, determine that a verification error occurs in the second data packet.

[0104] In some embodiments, the apparatus 200 further includes: The main chip abnormality judgment module 2 is configured to obtain the first temperature value of the first main chip and determine whether the first temperature value is less than the first temperature threshold or greater than the second temperature threshold after determining the data sending synchronization information. When the first temperature value is less than the first temperature threshold or greater than the second temperature threshold, the first main chip is determined to be abnormal; at the same time, the second temperature value of the second main chip is obtained and whether the second temperature value is less than the first temperature threshold or greater than the second temperature threshold. When the second temperature value is less than the first temperature threshold or greater than the second temperature threshold, the second main chip is determined to be abnormal.

[0105] In some embodiments, the apparatus 200 further includes: The memory abnormality determination module is configured as a first main chip or a second main chip to periodically verify the random access memory to determine whether an abnormality occurs in the random access memory: obtain a specific space value one of the random access memory, determine whether the specific space value one is the same as a specific space preset value one, and when the specific space value one is different from the specific space preset value one, determine that the random access memory is abnormal.

[0106] The flash memory abnormality judgment module is configured as the first main chip or the second main chip to periodically verify the flash memory to determine whether the flash memory is abnormal: obtain the specific space value 2 of the flash memory, determine whether the specific space value 2 is the same as the specific space preset value 2, and when the specific space value 2 is different from the specific space preset value 2, determine that the flash memory is abnormal.

[0107] The register abnormality judgment module is configured as the first main chip or the second main chip to periodically verify the register to determine whether the register is abnormal: obtain the specific space value three of the register, determine whether the specific space value three is the same as the specific space preset value three, and when the specific space value three is different from the specific space preset value three, determine that the register is abnormal.

[0108] In some embodiments, the apparatus 200 further includes: The first verification subject changing module is configured to determine whether the first master chip outputs the second master chip abnormality information. When the first master chip outputs the second master chip abnormality information, it is determined whether the verification subject of the random access memory is the second master chip. When the verification subject of the random access memory is the second master chip, the verification subject of the random access memory is changed to the first master chip. At the same time, it is determined whether the verification subject of the flash memory is the second master chip. When the verification subject of the flash memory is the second master chip, the verification subject of the flash memory is changed to the first master chip. At the same time, it is determined whether the verification subject of the register is the second master chip. When the verification subject of the register is the second master chip, the verification subject of the register is changed to the first master chip. The second verification subject change module is configured to determine whether the second main chip outputs the abnormal information of the first main chip. When the second main chip outputs the abnormal information of the first main chip, it is determined whether the verification subject of the random access memory is the first main chip. When the verification subject of the random access memory is the first main chip, the verification subject of the random access memory is changed to the second main chip; at the same time, it is determined whether the verification subject of the flash memory is the first main chip. When the verification subject of the flash memory is the first main chip, the verification subject of the flash memory is changed to the second main chip; at the same time, it is determined whether the verification subject of the register is the first main chip. When the verification subject of the register is the first main chip, the verification subject of the register is changed to the second main chip.

[0109] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A method for detecting anomalies in a dual-chip control system, characterized in that: include: The first master chip and the second master chip determine data acquisition synchronization information based on the first input and output line. After the data acquisition synchronization information is determined, the first master chip and the second master chip synchronously acquire data; The first master chip processes the collected data and packages it to form a first data packet, while the second master chip processes the collected data and packages it to form a second data packet; the first master chip and the second master chip determine data transmission synchronization information based on the second input and output line. After determining the data transmission synchronization information, the first master chip sends the first data packet to the second master chip based on the data transceiver line, while the second master chip sends the second data packet to the first master chip based on the data transceiver line; The first master chip determines whether the second data packet is abnormal. When the second data packet is abnormal, the first master chip outputs second master chip abnormal information; at the same time, the second master chip determines whether the first data packet is abnormal. When the first data packet is abnormal, the second master chip outputs first master chip abnormal information.

2. The method according to claim 1, characterized in that The second main chip determines whether the first data packet is abnormal specifically by: determining whether the first data packet is lost or whether a verification error occurs, and when a result of the determination is that the first data packet is lost or a verification error occurs, incrementing a first abnormality accumulation value by one; Otherwise, updating the first abnormality accumulated value to the initial value; determining whether the first abnormality cumulative value is equal to an abnormality cumulative threshold, and when the first abnormality cumulative value is equal to the abnormality cumulative threshold, determining that the first data packet is abnormal and updating the first abnormality cumulative value to an initial value; otherwise, determining that the first data packet is normal; The first main chip determines whether the second data packet is abnormal specifically by: determining whether the second data packet is lost or whether a verification error occurs, and when the determination result is that the second data packet is lost or a verification error occurs, incrementing the second abnormality accumulated value by one; Otherwise, updating the second abnormality accumulated value to the initial value; Determine whether the second abnormality cumulative value is equal to the abnormality cumulative threshold. When the second abnormality cumulative value is equal to the abnormality cumulative threshold, determine that the second data packet is abnormal and update the second abnormality cumulative value to an initial value; otherwise, determine that the second data packet is normal.

3. The method according to claim 2, characterized in that It also includes determining the abnormal accumulation threshold, specifically: Obtaining the abnormality determination accuracy of the first main chip and the second main chip of multiple dual-chip control systems under different first-level abnormality accumulation thresholds; Determine the first-level abnormality accumulation threshold value when the abnormality determination accuracy of the first main chip and the second main chip of each dual-chip control system is the highest and use it as the second-level abnormality accumulation threshold value; Determine the second-level anomaly accumulation threshold with the highest frequency and use it as the third-level anomaly accumulation threshold; determining whether the number of the three-level abnormality accumulation threshold is one, and when the number of the three-level abnormality accumulation threshold is one, using the three-level abnormality accumulation threshold as the final abnormality accumulation threshold; Otherwise, the three-level abnormality accumulation threshold with the smallest value is selected as the final abnormality accumulation threshold.

4. The method according to claim 2, characterized in that Determining whether the first data packet is lost or whether a verification error occurs is specifically as follows: After determining the data transmission synchronization information, timing is performed to determine whether the first data packet is received within a timing threshold, and when the first data packet is received within the timing threshold, determining that the first data packet is not lost; Otherwise, determining that the first data packet is lost; When the first data packet is not lost, calculating a first verification calculation value based on the first data packet, and comparing the first verification calculation value with a first verification control value in the first data packet, and when the first verification calculation value is the same as the first verification control value, determining that no verification error occurs in the first data packet; Otherwise, determining that a verification error occurs in the first data packet; Determining whether the second data packet is lost or whether a verification error occurs is specifically as follows: After determining the data transmission synchronization information, timing is performed to determine whether the second data packet is received within a timing threshold, and when the second data packet is received within the timing threshold, it is determined that the second data packet is not lost; otherwise, it is determined that the second data packet is lost; When the second data packet is not lost, calculating a second verification calculation value based on the second data packet, and comparing the second verification calculation value with a second verification control value in the second data packet, and when the second verification calculation value is the same as the second verification control value, determining that no verification error occurs in the second data packet; Otherwise, it is determined that a verification error occurs in the second data packet.

5. The method according to claim 1, characterized in that Also includes: After determining the data sending synchronization information, obtain the first temperature value of the first master chip and determine whether the first temperature value is less than the first temperature threshold or greater than the second temperature threshold. When the first temperature value is less than the first temperature threshold or greater than the second temperature threshold, determine that the first master chip is abnormal; at the same time, obtain the second temperature value of the second master chip and determine whether the second temperature value is less than the first temperature threshold or greater than the second temperature threshold. When the second temperature value is less than the first temperature threshold or greater than the second temperature threshold, determine that the second master chip is abnormal.

6. The method according to claim 1, wherein Also includes: The first master chip or the second master chip periodically verifies the random access memory to determine whether the random access memory is abnormal: obtaining a specific space value 1 of the random access memory, determining whether the specific space value 1 is the same as a specific space preset value 1, and determining that the random access memory is abnormal when the specific space value 1 is different from the specific space preset value 1; The first master chip or the second master chip periodically verifies the flash memory to determine whether the flash memory is abnormal: obtaining a second specific space value of the flash memory, determining whether the second specific space value is the same as a second specific space preset value, and determining that the flash memory is abnormal when the second specific space value is different from the second specific space preset value; The first main chip or the second main chip periodically verifies the register to determine whether the register is abnormal: obtains the specific space value three of the register, determines whether the specific space value three is the same as the specific space preset value three, and when the specific space value three is different from the specific space preset value three, determines that the register is abnormal.

7. The method according to claim 6, characterized in that Also includes: Determining whether the first master chip outputs abnormal information about the second master chip; when the first master chip outputs abnormal information about the second master chip, determining whether the verification subject of the random access memory is the second master chip; and when the verification subject of the random access memory is the second master chip, changing the verification subject of the random access memory to the first master chip; simultaneously, determining whether the verification subject of the flash memory is the second master chip; and when the verification subject of the flash memory is the second master chip, changing the verification subject of the flash memory to the first master chip; simultaneously, determining whether the verification subject of the register is the second master chip; and when the verification subject of the register is the second master chip, changing the verification subject of the register to the first master chip; Determine whether the second master chip outputs abnormal information of the first master chip. When the second master chip outputs abnormal information of the first master chip, determine whether the verification subject of the random access memory is the first master chip. When the verification subject of the random access memory is the first master chip, change the verification subject of the random access memory to the second master chip; at the same time, determine whether the verification subject of the flash memory is the first master chip. When the verification subject of the flash memory is the first master chip, change the verification subject of the flash memory to the second master chip; at the same time, determine whether the verification subject of the register is the first master chip. When the verification subject of the register is the first master chip, change the verification subject of the register to the second master chip.

8. An abnormality detection device for a dual-chip control system, characterized in that: include: The data synchronization acquisition module is configured so that the first master chip and the second master chip determine data acquisition synchronization information based on the first input and output lines. After the data acquisition synchronization information is determined, the first master chip and the second master chip synchronously acquire data. The data synchronization transmission module is configured such that the first master chip processes the collected data and packages it to form a first data packet, while the second master chip processes the collected data and packages it to form a second data packet; the first master chip and the second master chip determine data transmission synchronization information based on the second input and output line. After determining the data transmission synchronization information, the first master chip transmits the first data packet to the second master chip based on the data transceiver line, while the second master chip transmits the second data packet to the first master chip based on the data transceiver line. The main chip abnormality judgment module 1 is configured so that the first main chip determines whether the second data packet is abnormal. When the second data packet is abnormal, the first main chip outputs the second main chip abnormality information; at the same time, the second main chip determines whether the first data packet is abnormal. When the first data packet is abnormal, the second main chip outputs the first main chip abnormality information.

9. The device according to claim 8, characterized in that The main chip abnormality determination module 1 includes: a first data packet anomaly determination unit configured to determine whether the first data packet is lost or whether a verification error occurs, and when a determination result shows that the first data packet is lost or a verification error occurs, increase a first anomaly accumulated value by one; otherwise, update the first anomaly accumulated value to an initial value; determining whether the first abnormality cumulative value is equal to an abnormality cumulative threshold, and when the first abnormality cumulative value is equal to the abnormality cumulative threshold, determining that the first data packet is abnormal and updating the first abnormality cumulative value to an initial value; otherwise, determining that the first data packet is normal; a second data packet anomaly determination unit configured to determine whether the second data packet is lost or a verification error occurs, and when the determination result is that the second data packet is lost or a verification error occurs, increase the second anomaly accumulated value by one; otherwise, update the second anomaly accumulated value to an initial value; Determine whether the second abnormality cumulative value is equal to the abnormality cumulative threshold. When the second abnormality cumulative value is equal to the abnormality cumulative threshold, determine that the second data packet is abnormal and update the second abnormality cumulative value to an initial value; otherwise, determine that the second data packet is normal.

10. The device according to claim 9, characterized in that The first data packet anomaly determination unit includes: a first data packet loss determination subunit configured to, after determining the data transmission synchronization information, perform timing to determine whether the first data packet is received within a timing threshold, and determine that the first data packet is not lost if the first data packet is received within the timing threshold; otherwise, determine that the first data packet is lost; a first data packet check error determination subunit, configured to, when the first data packet is not lost, calculate a first check calculation value based on the first data packet, and compare the first check calculation value with a first check reference value in the first data packet; when the first check calculation value is the same as the first check reference value, determine that no check error occurs in the first data packet; otherwise, determine that a check error occurs in the first data packet; The second data packet anomaly determination unit includes: a second data packet loss determination subunit configured to, after determining the data transmission synchronization information, perform timing to determine whether the second data packet is received within a timing threshold, and when the second data packet is received within the timing threshold, determine that the second data packet is not lost; otherwise, determine that the second data packet is lost; The second data packet verification error determination subunit is configured to, when the second data packet is not lost, calculate a second verification calculation value based on the second data packet, and compare the second verification calculation value with a second verification control value in the second data packet; when the second verification calculation value is the same as the second verification control value, determine that no verification error occurs in the second data packet; otherwise, determine that a verification error occurs in the second data packet.

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