Adaptive virtualization of GPU cores, and engine-based virtualization

Abstract

One embodiment provides a graphics processor comprising: a memory interface; a plurality of interfaces to the plurality of compute engines; a cluster of processing resources, the cluster of processing resources comprising a plurality of processing resources configured to execute instructions on behalf of the plurality of compute engines; and virtualization circuitry configured to enable time division virtualization of the plurality of processing resources via the plurality of computing engines, the virtualization circuitry is to concurrently process workloads during a time slice via dynamic assignment of workloads from a plurality of guest machine software environments to a plurality of interfaces to a plurality of compute engines.

Description

Cross-references

[0001] This application claims priority to U.S. Provisional Application No. 63 / 565,122, filed on March 14, 2024, and U.S. Provisional Application No. 63 / 565,125, each of which is hereby incorporated by reference herein. Background Art

[0002] Data center GPUs generally possess substantial computing resources. Virtualization can improve the utilization efficiency of data center GPUs, as some workloads cannot fully utilize the entire GPU. In time-sharing virtualization, the entire GPU is dedicated to a single virtual machine (VM) for a certain period of time. During this period, the entire GPU is virtualized, and a single VM has all of the GPU's resources. However, depending on the workload, a single VM may not utilize all of the execution resources during that time frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments described herein are illustrated by way of example and not limitation in the accompanying drawings in which like reference numerals indicate like elements, and in which:

[0004] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0005] Figure 2A-2E Graphics parallel processor components, including graphics multiprocessors;

[0006] Figure 3 A graphics processing unit (GPU) is shown, which includes a dedicated collection of graphics processing resources arranged into a multi-core group;

[0007] Figures 4A-4E illustrates an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0008] Figure 5 Diagram of the graphics processing pipeline;

[0009] Figure 6 Diagram of the machine learning software stack;

[0010] Figure 7 Illustration of a general purpose graphics processing unit;

[0011] Figure 8 Diagram of a multi-GPU computing system;

[0012] Figure 9A-9Billustrates the layers of an exemplary deep neural network;

[0013] Figures 10A-10B illustrates an exemplary language model;

[0014] Figure 11 Illustrate the training and deployment of deep neural networks;

[0015] Figure 12A is a block diagram illustrating distributed learning;

[0016] Figure 12B is a block diagram illustrating a programmable network interface (NIC) and a data processing unit (DPU);

[0017] Figure 13 An exemplary inferred system on a chip (SOC) is shown;

[0018] Figure 14 It is a block diagram of the processing system;

[0019] Figures 15A-15C Graphics computing systems and graphics processors;

[0020] Figure 16 is a block diagram of a discrete or integrated graphics processor;

[0021] Figures 17A-17B A block diagram illustrating additional graphics accelerators and computing accelerators;

[0022] Figures 18A-18C Figure 1 shows the thread execution logic used in a graphics processor core;

[0023] Figure 19 illustrates a slice of a multi-chip processor according to an embodiment;

[0024] Figure 20 is a block diagram illustrating a graphics processor instruction format;

[0025] Figure 21 is a block diagram of the attached graphics processor architecture;

[0026] Figures 22A-22B Illustrate the graphics processor command format and command sequence;

[0027] Figure 23 illustrates an exemplary software architecture for a data processing system;

[0028] Figure 24 is a block diagram illustrating an IP core development system;

[0029] Figure 25Aillustrates a cross-sectional side view of an integrated circuit package assembly;

[0030] Figure 25B The illustration includes a package assembly with interchangeable chiplets;

[0031] Figure 26 is a block diagram illustrating a system-on-chip integrated circuit;

[0032] Figure 27 is a block diagram of a system including a GPU device according to an embodiment;

[0033] Figure 28 is a diagram of a system for dispatching thread groups to processing resources according to an embodiment;

[0034] Figure 29 illustrates a GPU with a compute command streamer assigned to a single VM;

[0035] Figures 30A-30B Figure 1 illustrates a GPU with a compute command streamer assigned to multiple VMs;

[0036] Figure 31 illustrates a time series for GPU ownership according to an embodiment;

[0037] Figure 32 illustratively illustrating a method for implementing adaptive virtualization of an accelerator device core according to an embodiment;

[0038] Figure 33 FIGURE 1 illustrates a system in which time-sharing virtualization is applied at the GPU granularity;

[0039] Figure 34 illustrates a system configured to perform engine-based GPU virtualization according to an embodiment;

[0040] Figure 35 illustrates a method of performing engine-based virtualization of an accelerator device according to an embodiment;

[0041] Figure 36 The diagram illustrates a system including MMIO registers for interrupt reporting for virtual and physical functions using SR-IOV;

[0042] Figure 37 Illustrate a system for facilitating GPU virtualization using SIOV; and

[0043] Figure 38 is a block diagram of a computing device including a graphics processor, according to an embodiment. DETAILED DESCRIPTION

[0044] A graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate, for example, graphics operations, machine learning operations, pattern analysis operations, and / or various general-purpose GPU (GPGPU) functions. The GPU can be coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). Alternatively, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor.

[0045] Although the techniques described herein are primarily discussed in the context of GPUs, these techniques may also be implemented in other types of processors, including but not limited to general-purpose processors and accelerator devices such as artificial intelligence accelerators, vision processors, and neural processing units.

[0046] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to those skilled in the art that the embodiments described herein can be practiced without one or more of these specific details. In other instances, well-known features are not described in order to avoid obscuring the details of the present embodiments. System Overview

[0047] Figure 1 1 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. Computing system 100 includes a processing subsystem 101 having one or more processors 102 and system memory 104 communicating via an interconnect path, which may include a memory hub 105. Memory hub 105 may be a separate component within a chipset component or may be integrated within one or more processors 102. Memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. I / O subsystem 111 includes an I / O hub 107, which enables computing system 100 to receive input from one or more input devices 108. Additionally, I / O hub 107 enables a display controller (which may be included in one or more processors 102) to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to I / O hub 107 may include local, internal, or embedded display devices.

[0048] The processing subsystem 101 includes, for example, one or more parallel processors 112 coupled to the memory hub 105 via a communication link 113 such as a bus or fabric. The communication link 113 can be one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication fabric. The one or more parallel processors 112 can form a parallel or vector processing system in a computational cluster that can include a large number of processing cores and / or processing clusters, such as, a manyintegrated core (MIC) processor. For example, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 can also include a display controller and a display interface (not shown) for enabling a direct connection to the one or more display devices 110B.

[0049] Within the I / O subsystem 111, a system storage unit 114 may be connected to the I / O hub 107, thereby providing a storage mechanism for the computing system 100. An I / O switch 116 may be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components, such as a network adapter 118 and / or a wireless network adapter 119, which may be integrated into the platform, and various other devices that may be added via one or more plug-in devices 120. The plug-in device(s) 120 may also include, for example, one or more external graphics processor devices, graphics cards, and / or computing accelerators. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of the following: Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radio devices.

[0050] The computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 107. Figure 1 The communication paths for interconnecting the various components in the system may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI Express), or any other bus or point-to-point communication interface and / or protocol(s), such as NVLink high-speed interconnect, Compute Express Link, or the like. TM(ComputeExpress Link TM , CXL TM ) (e.g., CXL.mem), Infinity Fabric (IF), Ethernet (IEEE 802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Intel Quick Path Interconnect (QPI), Intel Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omnipath, HyperTransport, Advanced Microcontroller Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Cache Coherent Interconnect for Accelerators The data may be copied or stored to the virtualized storage node using protocols such as 3GPP Accelerators (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G and variants thereof, or wired or wireless interconnect protocols known in the art. In some examples, data may be copied or stored to the virtualized storage node using protocols such as non-volatile memory express (NVMe) over Fabrics (NVME-oF) or NVMe.

[0051] One or more parallel processors 112 may include circuits optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). Alternatively or additionally, as described in more detail herein, one or more parallel processors 112 may include circuits optimized for general-purpose processing while retaining the underlying computing architecture. Components of computing system 100 may be integrated on a single integrated circuit with one or more other system elements. For example, one or more parallel processors 112, memory hub 105, (one or more) processors 102, and I / O hub 107 may be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, components of computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

[0052] In some configurations, in addition to the processor(s) 102 and the parallel processor(s) 112, the computing system 100 also includes one or more accelerator devices 130 coupled to the memory hub 105. The accelerator device(s) 130 are configured to perform domain-specific acceleration of workloads to handle computationally intensive or high-throughput tasks. The accelerator device(s) 130 can reduce the burden placed on the processor(s) 102 and / or the parallel processor(s) 112 of the computing system 100. The accelerator device(s) 130 can include, but are not limited to, intelligent network interface cards, data processing units, cryptographic accelerators, storage accelerators, artificial intelligence (AI) accelerators, neural processing units (NPUs), storage accelerators, and / or video transcoding accelerators. It will be appreciated that the computing system 100 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processor(s) 102, and the number of parallel processor(s) 112, can be modified as needed. For example, system memory 104 may be connected directly to processor(s) 102 rather than through a bridge, while other devices communicate with system memory 104 via memory hub 105 and processor(s) 102. In other alternative topologies, parallel processor(s) are connected to I / O hub 107 or directly to one of the processor(s) 102 rather than to memory hub 105. In other embodiments, I / O hub 107 and memory hub 105 may be integrated into a single chip. It is also possible for two or more sets of processors 102 to be attached via multiple sockets, which may be coupled to two or more instances of parallel processor(s) 112.

[0053] Some of the specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. Additionally, some architectures may be specific to the architecture of the computer. Figure 1 Different terminology is used for components that are similar to those illustrated in FIG. For example, memory hub 105 may be referred to as a north bridge in some architectures, while I / O hub 107 may be referred to as a south bridge.

[0054] Figure 2AThe parallel processor 200 is shown. The parallel processor 200 may be a GPU, a GPGPU, or the like as described herein. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). The parallel processor 200 may be Figure 1 One or more of the parallel processor(s) 112 shown in .

[0055] The parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices, including other instances of the parallel processing unit 202. The I / O unit 204 can be directly connected to the other devices. For example, the I / O unit 204 is connected to the other devices using a hub or switch interface (such as, a memory hub 105). The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar switch 216, wherein the host interface 206 receives commands related to performing processing operations and the memory crossbar switch 216 receives commands related to performing memory operations. In one embodiment, the I / O unit 204 is configured to enable secure I / O operations via Trusted Execution Environment (TEE)-I / O support. TEE-IO enables trusted I / O virtualization, where a trust relationship can be established directly between a secure virtual environment (such as a trusted virtual machine) and a parallel processor 200 or a secure partition of a parallel processor.

[0056] When host interface 206 receives command buffers via I / O unit 204, it can direct work operations for executing those commands to front-end 208. In one embodiment, front-end 208 is coupled to scheduler 210, which is configured to dispatch commands or other work items to processing cluster array 212. Scheduler 210 ensures that processing cluster array 212 is properly configured and in a valid state before tasks are dispatched to processing clusters within the processing cluster array 212. Scheduler 210 can be implemented via firmware logic executing on a microcontroller. A microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work dispatch operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing cluster array 212. Preferably, host software can confirm workloads for scheduling on processing cluster array 212 via one of multiple graphics processing doorbells. In other examples, polling for new workloads or interrupts can be used to identify or indicate the availability of work to be executed. The workload may then be automatically distributed across the processing cluster array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0057] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, through cluster 214N). Each cluster 214A-214N in the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may assign work to the clusters 214A-214N in the processing cluster array 212 using various scheduling and / or work distribution algorithms that may vary depending on the workload generated for each type of program or computation. Scheduling may be handled dynamically by the scheduler 210 or may be assisted in part by compiler logic during the compilation of program logic configured for execution by the processing cluster array 212. Optionally, different clusters 214A-214N in the processing cluster array 212 may be assigned to process different types of programs or to perform different types of computations.

[0058] Processing cluster array 212 may be configured to perform various types of parallel processing operations. For example, processing cluster array 212 may be configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0059] Processing cluster array 212 is configured to perform parallel graphics processing operations. In such embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute graphics processing related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and subsequently written back to system memory.

[0060] In embodiments where parallel processing units 202 are used to perform graphics processing, scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better facilitate the distribution of graphics processing operations to multiple clusters 214A-214N in processing cluster array 212. In some of these embodiments, portions of processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N may be stored in a buffer to allow the intermediate data to be transferred between clusters 214A-214N for further processing.

[0061] During operation, processing cluster array 212 may receive processing tasks to be executed via scheduler 210, which receives commands defining the processing tasks from front end 208. For graphics processing operations, a processing task may include data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and an index of commands that define how the data is to be processed (e.g., what program to execute). Scheduler 210 may be configured to fetch an index corresponding to a task, or may receive an index from front end 208. Front end 208 may be configured to ensure that processing cluster array 212 is configured in a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0062] Each of the one or more instances of parallel processing unit 202 can be coupled to parallel processor memory 222. Parallel processor memory 222 can be accessed via memory crossbar switch 216, which can receive memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar switch 216 can access parallel processor memory 222 via memory interface 218. Memory interface 218 can include a plurality of partition units (e.g., partition unit 220A, partition unit 220B, through partition unit 220N), each of which can be coupled to a portion (e.g., memory cells) of parallel processor memory 222. The number of partition units 220A-220N can be configured to be equal to the number of memory cells, such that each partition unit 220A-220N has a corresponding memory cell 224A-224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory cells.

[0063] Memory units 224A-224N may include various types of memory devices, including dynamic random-access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. Optionally, memory units 224A-224N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of memory units 224A-224N may vary and may be selected from a variety of conventional designs. Render targets, such as frame buffers or texture maps, may be stored across memory units 224A-224N, allowing partition units 220A-220N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 222. In some embodiments, local instances of parallel processor memory 222 may be eliminated in favor of a unified memory design for system memory combined with local cache memory.

[0064] Optionally, any of the clusters 214A-214N in the processing cluster array 212 has the capability to process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. The memory crossbar 216 can be configured to transmit the output of each cluster 214A-214N to any partition unit 220A-220N or to another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with a memory interface 218 via the memory crossbar 216 to read from or write to various external memory devices. In one embodiment having a memory crossbar 216, the memory crossbar 216 has connections to a memory interface 218 for communicating with the I / O unit 204 and to a local instance of parallel processor memory 222, thereby enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In general, the memory crossbar 216 may be capable of separating traffic flows between the clusters 214A-214N and the partition units 220A-220N using virtual channels, for example.

[0065] Although a single instance of parallel processing unit 202 is illustrated within parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. For example, parallel processor 200 may be a plug-in device (included in a Figure 1 (one or more) plug-in devices 120), which plug-in devices may be graphics cards (such as, for example, discrete graphics cards including one or more GPUs, one or more memory devices, and device-to-device or network or fabric interfaces). Different instances of parallel processing unit 202 may be configured to interoperate even though different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. Optionally, some instances of parallel processing unit 202 may include higher precision floating point units relative to other instances. Systems including one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems. The orchestrator may use one or more of the following to form composite nodes for workload execution: decomposed processor resources, cache resources, memory resources, storage resources, and networking resources.

[0066] In one embodiment, the parallel processing unit 202 can be partitioned into multiple instances. Those multiple instances can be configured to execute workloads associated with different clients in an isolated manner, thereby providing a predetermined quality of service for each client. For example, each cluster 214A-214N can be partitioned and isolated from other clusters, allowing the processing cluster array 212 to be divided into multiple computing partitions or instances. In such a configuration, workloads executed on isolated partitions are protected from errors or errors associated with different workloads executed on different partitions. Partition units 220A-220N can be configured to enable dedicated and / or isolated paths to the memory of the cluster 214A-214N associated with the corresponding computing partition. This data path isolation allows computing resources within a partition to communicate with one or more assigned memory units 224A-224N without being interfered with by the activities of other partitions. In one embodiment, data path isolation can be enhanced by encrypting data in the memory of each partition using an encryption key unique to the associated partition, so that data is protected on a per-partition basis both at rest and in transit.

[0067] Figure 2B is a block diagram of the partition unit 220. The partition unit 220 may be Figure 2A 20N。 As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar 216 and the ROP 226. Read misses and urgent writeback requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 is connected to the frame buffer. Figure 2A Partition unit 220 may also interface with one of the memory units in the parallel processor memory via a memory controller (not shown) in addition or alternatively.

[0068] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stenciling, z-testing, blending, and the like. ROP 226 then outputs processed graphics data, which is stored in graphics memory. In some embodiments, ROP 226 includes or is coupled to a codec (CODEC) 227 that includes compression logic for compressing depth or color data written to memory or L2 cache 221 and decompressing depth or color data read from memory or L2 cache 221. The compression logic may be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by CODEC 227 may vary based on the statistical characteristics of the data being compressed. For example, in one embodiment, delta color compression is performed on the depth and color data on a slice-by-slice basis. In one embodiment, CODEC 227 includes compression and decompression logic, which can compress and decompress the calculated data associated with the machine learning operation. CODEC 227 can, for example, compress the sparse matrix data for sparse machine learning operations. CODEC 227 can also compress the sparse matrix data encoded in a sparse matrix format (e.g., coordinate list encoding (COO), compressed sparse row (CSR), compressed sparse column (CSC), etc.) to generate compressed and encoded sparse matrix data. Compressed and encoded sparse matrix data can be decompressed and / or decoded before being processed by a processing element, or a processing element can be configured to consume compressed, encoded, or compressed and encoded data for processing. In one embodiment, CODEC 227 can be configured as a general data compression engine for use in GPU database acceleration and large-capacity data analysis.

[0069] ROP 226 may be included in each processing cluster (e.g., Figure 2A 214N) rather than being included within partition unit 220. In such embodiments, read and write requests for pixel data rather than pixel fragment data are routed through memory crossbar 216. The processed graphics data may be displayed on a display device such as a Figure 1 10B), is routed for further processing by the processor(s) 102, or is routed for processing by the processor(s) 102. Figure 2A The processing is further processed by one of the processing entities within the parallel processor 200.

[0070] Figure 2C is a block diagram of a processing cluster 214 within a parallel processing unit. For example, processing cluster 214 represents Figure 2A An instance of a processing cluster in the processing clusters 214A-214N. The processing cluster 214 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific set of input data. Optionally, a single-instruction, multiple-data (SIMD) instruction issuance technology can be used to support the parallel execution of a large number of threads without providing multiple independent instruction units. Alternatively, a single-instruction, multiple-thread (SIMT) technology can be used to use a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster in the processing cluster to support the parallel execution of a large number of generally synchronized threads. Unlike the SIMD execution mechanism in which all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0071] The operation of the processing cluster 214 may be controlled via a pipeline manager 232 that distributes processing tasks to SIMT parallel processors. The pipeline manager 232 receives data from Figure 2A The graphics multiprocessor 234 receives instructions from the scheduler 210 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures may be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 may be included in the processing cluster 214. The graphics multiprocessor 234 may also be referred to as a streaming multiprocessor (SM) and is capable of executing a large number of execution threads simultaneously. The graphics multiprocessor 234 may process data, and the data crossbar 240 may be used to distribute the processed data to one of a plurality of possible destinations, including instances of the graphics multiprocessor 234 within the processing cluster 214. The pipeline manager 232 may facilitate the distribution of the processed data by specifying a destination for the processed data to be distributed via the data crossbar 240.

[0072] Each graphics multiprocessor 234 within a processing cluster 214 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). The function execution logic may be configured in a pipelined manner, whereby new instructions may be issued before previous instructions have completed. The function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of various algebraic functions. The same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0073] Instructions transmitted to the processing cluster 214 constitute threads. A collection of threads executed across a collection of parallel processing engines is a thread group. Thread groups execute the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines can be idle during the cycles in which the thread group is being processed. A thread group can also include more threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within the graphics multiprocessor 234, processing can be performed in consecutive clock cycles. Optionally, multiple thread groups can be executed concurrently on the graphics multiprocessor 234.

[0074] The graphics multiprocessor 234 may include internal cache memory to perform load and store operations. Optionally, the graphics multiprocessor 234 may forgo the internal cache and use cache memory within the processing cluster 214 (e.g., level 1 (L1) cache 248). Each graphics multiprocessor 234 also has a partition unit (e.g., Figure 2A 20N) are shared among all instances of processing cluster 214 and can be used to transfer data between threads. Graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of local PPU memory and / or system memory. Any memory external to PPU 202 can be used as global memory. In embodiments where processing cluster 214 includes multiple instances of graphics multiprocessor 234, common instructions and data can be shared, which can be stored in L1 cache 248.

[0075] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside in Figure 2A The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of the slice, and optionally includes a cache line index. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache 248 of the processing cluster 214. Physical addresses are processed to distribute surface data access locality, thereby allowing efficient request interleaving between partition units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0076] In graphics and compute applications, the processing clusters 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown), or in some embodiments, from an L1 cache within the graphics multiprocessor 234 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A pre-raster operations unit 242 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to ROP units that may interface with partition units (e.g., Figure 2A The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0077] It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within processing cluster 214. A parallel processing unit as described herein may include any number of instances of processing cluster 214. Optionally, each processing cluster 214 may be configured to operate independently of other instances of processing cluster 214 using, for example, separate and distinct processing units, L1 cache, L2 cache, to facilitate data and fault isolation.

[0078] Figure 2D An example of a graphics multiprocessor 234 is shown, wherein the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit cores (GPGPU cores 262), and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268. The graphics multiprocessor 234 may additionally include a ray tracing core 263, which includes hardware logic for accelerating ray tracing operations, and a tensor core 264, which includes hardware logic for accelerating tensor (e.g., matrix) operations. The instruction cache 252 may receive a stream of instructions to be executed from the pipeline manager 232. Instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions as groups of threads (e.g., warps), where each thread in the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local address space, the shared address space, or the global address space by specifying an address within the unified address space. The address mapping unit 256 can be used to translate the address in the unified address space into different memory addresses that can be accessed by the load / store unit 266.

[0079] The register file 258 provides a collection of registers for the functional units of the graphics multiprocessor 234. The register file 258 provides temporary storage for operands of the data paths of the functional units (e.g., the GPGPU core 262, the load / store unit 266) connected to the graphics multiprocessor 234. The register file 258 may be divided among each of the functional units so that each functional unit is allocated a dedicated portion of the register file 258. For example, the register file 258 may be divided among different groups of units executed by the graphics multiprocessor 234.

[0080] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 234. In some implementations, the GPGPU cores 262 may include hardware logic that may otherwise reside within the tensor core 264 and / or the ray tracing core 263. The GPGPU cores 262 may be architecturally similar or architecturally different. For example, and in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. Optionally, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic, or enable variable-precision floating-point arithmetic. In one embodiment, a single-precision FPU, or a separate set of FPUs, may be configured to perform operations on 16-bit floating-point operands, such as a half-precision format or a bfloat16 format (e.g., Brain floating point), which is a 16-bit floating-point format with one sign bit, eight exponent bits, and eight significand bits (seven of which are explicitly stored). The FPUs within one or more GPGPU cores 262 may also support one or more 8-bit floating-point formats. Supported 8-bit floating-point formats include the E4M3 format with a 4-bit exponent and a 3-bit mantissa, and the E5M2 format with a 5-bit exponent and a 2-bit mantissa. The graphics multiprocessor 234 may additionally include one or more fixed-function or special-function units for performing specific functions, such as copying rectangles or pixel blending operations. One or more of the GPGPU cores may also include fixed-function or special-function logic.

[0081] GPGPU core 262 may include SIMD logic capable of executing a single instruction on multiple sets of data. Optionally, GPGPU core 262 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. SIMD instructions for GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, and in one embodiment, eight SIMT threads performing the same or similar operation can be executed in parallel as SIMD8 instructions. In one embodiment, a cell group of 32 SIMT threads can be executed as a single SIMD32 instruction. Cell group divergence can be handled via multiple SIMD instructions.

[0082] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. For example, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so data transfers between the GPGPU core 262 and the register file 258 are very low-latency. Shared memory 270 can be used to enable communication between threads executing on the functional units of the graphics multiprocessor 234. Shared memory 270 can also be used as a managed cached program. Cache memory 272 can be used as an automatically managed data cache, for example, to cache texture data transferred between the functional units and the texture unit 236. Shared memory 270 and cache memory 272 can be coupled with the data crossbar 240 to enable communication with other components of the processing cluster, thereby facilitating coordinated execution of cluster workgroups across multiple graphics multiprocessors within the processing cluster. In addition to automatically cached data stored in cache memory 272, threads executing on GPGPU core 262 can also programmatically store data in shared memory. In one embodiment, shared memory 270 and cache memory 272 can be combined into a single configurable memory unit that can be selectively configured as either cache memory 272 or shared memory 270.

[0083] Figure 2E Graphics multiprocessor 235 is shown, which has relative Figure 2DAn alternative configuration of the graphics multiprocessor 234. Any feature disclosed herein in conjunction with the graphics multiprocessor 235 also discloses the corresponding Figure 2D The graphics multiprocessor 234 may be combined with, but is not limited to, the graphics multiprocessor 234. Figure 2E The graphics multiprocessor 235 includes relative Figure 2D The graphics multiprocessor 235 may include multiple additional instances of execution resources 286A-286D for the graphics multiprocessor 234. For example, the graphics multiprocessor 235 may include multiple instruction units 254A-254D, register files 258A-258D, and texture units 280A-280D. The graphics multiprocessor 235 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 262A-262D, ray tracing cores 263A-263D, and tensor cores 264A-264D) and multiple sets of load / store units 266A-266D. The execution resources 286A-286D work in conjunction with the texture unit(s) 280A-280D for texture operations, while sharing the instruction cache 252, shared memory 270, and cache memories 272A-272B. In one embodiment, the execution resources 286A-286D additionally include multi-function units (MUFUs) and / or special-function units (SFUs) (e.g., MFUs 267A-267D) for performing specialized mathematical operations, such as transcendental operations including exponential, logarithmic, and trigonometric functions.

[0084] The components can communicate via an interconnect fabric 290. The interconnect fabric 290 may include one or more crossbar switches to enable communication between the components of the graphics multiprocessor 235. The GPGPU cores 262A-262D, the ray tracing cores 263A-263B, and the tensor cores 264A-264D can each communicate with the shared memory 270 via the interconnect fabric 290. The interconnect fabric 290 can arbitrate communications within the graphics multiprocessor 235 to ensure fair bandwidth allocation between components. In one embodiment, the interconnect fabric 290 can be a separate high-speed network fabric layer on which each component of the graphics multiprocessor 235 is stacked. The components of the graphics multiprocessor 235 can also communicate with remote components via the interconnect fabric 290.

[0085] In one embodiment, the graphics multiprocessor 235 includes a tensor transfer engine 292, which is a copy engine configurable to accelerate the movement of tensor data into and out of the graphics multiprocessor 235. The tensor transfer engine 292 can accelerate tensor memory operations by asynchronously performing address generation and data movement operations for N-dimensional blocks of tensor data, migrating operations that would otherwise be performed manually by program code executed by the graphics multiprocessor 235. The tensor transfer engine 292 can be configured to copy data between, for example, the shared memory 270 and / or cache memories 272A-272B of the graphics multiprocessor 235 and memory external to the graphics multiprocessor 235, such as graphics processor global memory (e.g., parallel processor memory 222). In one embodiment, data transfers performed by the tensor transfer engine 292 can be configured to selectively bypass various levels of intermediate data storage between source and destination memory. For example, transfers between global memory and shared memory 270 can bypass register files 258A-258D. In one embodiment, threads can synchronize on asynchronous tensor transfers via a non-blocking barrier synchronization mechanism.

[0086] In various embodiments, the graphics multiprocessor 235 can be customized for specific use cases by including or excluding certain components, thereby allowing various implementations of the graphics multiprocessor 235 to be customized according to target power, performance, and area characteristics. For example, a compute-oriented variant of the graphics multiprocessor 235 that will not perform graphics operations can exclude ray tracing cores 263A-263D. A fully graphics-oriented variant can exclude the tensor transfer engine 292, while a graphics-oriented variant that is additionally configured for accelerating neural network inference can include at least one version of the tensor transfer engine 292.

[0087] Those skilled in the art will understand that Figure 1 and Figure 2A-2E The architecture described in is illustrative and not limiting with respect to the scope of the present embodiments. Thus, the techniques described herein may be implemented on any appropriately configured processing unit without departing from the scope of the embodiments described herein, including but not limited to: one or more mobile application processors; one or more desktop or server central processing units (CPUs), including multi-core CPUs; one or more parallel processor units, such as, Figure 2A and a parallel processing unit 202 and one or more graphics processors or special purpose processing units.

[0088] The parallel processor or GPGPU described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe, NVLink, Ultra Accelerator Link (UALink) or other known, standardized, or proprietary protocols). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0089] Figure 3 The diagram shows a graphics processing unit (GPU 380) that includes a dedicated collection of graphics processing resources arranged into multiple core groups 365A-365N. Figure 2D Graphics multiprocessor 234 or Figure 2E 235. While details are provided for a single example of multi-core groups 365A-365N (e.g., multi-core group 365A), it will be appreciated that other multi-core groups 365B-365N may be equipped with the same or similar sets of graphics processing resources. Details described with respect to multi-core groups 365A-365N may also apply to the graphics multiprocessor 234 or graphics multiprocessor 235 described herein.

[0090] As shown, the multi-core group 365A may include a graphics core 370, a tensor core 371, and a ray tracing core 372. The graphics core 370 is similar to the GPGPU cores 262A-262D and is configurable to execute instructions to perform graphics and / or general computing operations. The scheduler / dispatcher 368 schedules and dispatches graphics threads for execution on the various cores within the multi-core group 365A. A register file 369 is included that stores operand values ​​used by the core when performing graphics or general computing operations on the executed threads. These register files 369 may include, for example, registers that can be configured to store integer values ​​or floating-point values, including vector registers for storing packed integer and / or floating-point data elements and slice registers for storing tensor / matrix values. The slice registers may be implemented as multi-dimensional registers including a combined set of vector registers.

[0091] One or more combined first level (L1) caches and shared memory units 373 store graphics data locally within each multi-core group 365A, such as texture data, vertex data, pixel data, ray data, bounding volume data, etc. One or more texture units 374 can also be used to perform texture operations, such as texture mapping and sampling. A second level (L2) cache 375 shared by all multi-core groups 365A-365N or a subset of multi-core groups 365A-365N stores graphics data and / or instructions for multiple concurrent graphics threads. As shown, the L2 cache 375 can be shared across multiple multi-core groups 365A-365N. One or more memory controllers 367 couple the GPU 380 to memory 366, which can be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0092] Input / output circuitry (I / O circuitry 363) couples GPU 380 to one or more I / O devices 362, such as digital signal processors (DSPs), network controllers, or user input devices. On-chip interconnects may be used to couple I / O devices 362 to GPU 380 and memory 366. At least one I / O memory management unit (IOMMU) 364 of I / O circuitry 363 directly couples I / O devices 362 to memory 366. Optionally, IOMMU 364 manages multiple sets of page tables used to map virtual addresses to physical addresses in memory 366. I / O devices 362, CPU(s) 361, and GPU 380 can then share the same virtual address space.

[0093] In one implementation of the IOMMU 364, the IOMMU 364 supports virtualization. In this case, the IOMMU 364 can manage a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses (e.g., within memory 366). The base address of each of the first set of page tables and the second set of page tables can be stored in a control register and swapped out upon context switching (e.g., so that the new context is provided with access to the relevant set of page tables). Although not described in detail in the present disclosure, the first set of page tables and the second set of page tables can be used to map guest / graphics virtual addresses to guest / graphics physical addresses. Figure 3 , but each of the cores within the multi-core group 365A-365N may include a translation lookaside buffer (TLB) for caching guest virtual to guest physical translations, guest physical to host physical translations, and guest virtual to host physical translations.

[0094] (One or more) CPUs 361, GPU 380, and I / O devices 362 can be integrated on a single semiconductor chip and / or chip package. Memory 366 can be integrated on the same chip or can be coupled to one or more memory controllers 367 via an off-chip interface. In one implementation, memory 366 includes GDDR6 memory that shares the same virtual address space as other physical system-level memory, but the basic principles described herein are not limited to this particular implementation.

[0095] Tensor Core 371 may include multiple execution units specifically designed to perform matrix operations, which are fundamental computational operations for performing deep learning operations. For example, synchronized matrix multiplication operations may be used for neural network training and inference. Tensor Core 371 may perform matrix processing using a variety of operand precisions, including single-precision floating point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half bytes (4 bits). For example, a neural network implementation extracts features from each rendered scene, potentially combining details from multiple frames to construct a high-quality final image.

[0096] In a deep learning implementation, parallel matrix multiplication work can be scheduled for execution on the Tensor Core 371. Training neural networks, in particular, requires a large number of matrix dot product operations. To handle the inner product formulation of an N x N x N matrix multiplication, the Tensor Core 371 may include at least N dot product processing elements. Before the matrix multiplication begins, a complete matrix is ​​loaded into the slice registers, and for each of N cycles, at least one column of the second matrix is ​​loaded. For each cycle, there are N dot products processed.

[0097] Depending on the specific implementation, matrix elements can be stored with different precisions, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit nibbles (e.g., INT4). Different precision modes can be specified for the tensor core 371 to ensure that the most efficient precision is used for different workloads (e.g., such as inference workloads, which can tolerate quantization down to bytes and nibbles). Supported formats additionally include 64-bit floating point (FP64) and non-IEEE floating point formats, such as bfloat16 format. One embodiment includes support for reduced precision tensor floating point (TF32) mode, which performs computations using the range of FP32 (8 bits) and the precision of FP16 (10 bits). Reduced precision TF32 operations can be performed on FP32 inputs and produce FP32 outputs with higher performance relative to FP32 and increased precision relative to FP16. In one embodiment, one or more of 8-bit floating point (FP8), 6-bit floating point (FP6), and 4-bit floating point (FP4) formats are supported, including a floating point format denoted as a microscaling (MX) format.

[0098] In one embodiment, the Tensor Core 371 supports a sparse operation mode for matrices in which the majority of values ​​are zero. The Tensor Core 371 includes support for sparse input matrices encoded in a sparse matrix representation (e.g., coordinate list encoding (COO), compressed sparse row (CSR), compressed sparse column (CSC), etc.). The Tensor Core 371 also includes support for compressed sparse matrix representations, where the sparse matrix representation can be further compressed. Compressed matrix data, encoded matrix data, and / or compressed and encoded matrix data, along with associated compression and / or encoding metadata, can be read by the Tensor Core 371, and non-zero values ​​can be extracted. For example, for a given input matrix A, non-zero values ​​can be loaded from at least a portion of the compressed and / or encoded representation of matrix A. Based on the position of the non-zero value in matrix A (which can be determined from the index or coordinate metadata associated with the non-zero value), the corresponding value in the input matrix B can be loaded. Depending on the operation to be performed (e.g., multiplication), if the corresponding value is zero, loading the value from the input matrix B can be bypassed. In one embodiment, the pairing of values ​​for certain operations (such as multiplication operations) can be pre-scanned by the scheduler logic, and only operations between non-zero inputs are scheduled. Depending on the dimensions of matrices A and B and the operations to be performed, the output matrix C can be dense or sparse. In the case where the output matrix C is sparse and depending on the configuration of the tensor core 371, the output matrix C can be output in a compressed format, sparse coding, or compressed sparse coding.

[0099] Ray tracing core 372 can accelerate ray tracing operations for both real-time and non-real-time ray tracing implementations. Specifically, ray tracing core 372 can include ray traversal / intersection circuitry for performing ray traversals using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the BVH volume. Ray tracing core 372 can also include circuitry for performing depth testing and culling (e.g., using a Z-buffer or similar arrangement). In one implementation, ray tracing core 372 performs traversal and intersection operations in conjunction with the image denoising techniques described herein, at least portions of which can be executed on tensor core 371. For example, tensor core 371 can implement a deep learning neural network to perform denoising on frames generated by ray tracing core 372. However, CPU(s) 361, graphics core 370, and / or ray tracing core 372 can also implement all or portions of the denoising and / or deep learning algorithms.

[0100] Furthermore, as described above, a distributed approach to noise reduction can be employed, wherein GPU 380 is located in a computing device coupled to other computing devices via a network or high-speed interconnect. According to this distributed approach, the interconnected computing devices can share neural network learning / training data to improve the speed at which the entire system learns to perform noise reduction for different types of image frames and / or different graphics applications.

[0101] The ray tracing cores 372 can handle all BVH traversals and / or ray-primitive intersections, thereby freeing the graphics core 370 from being overloaded with thousands of instructions for each ray. For example, each ray tracing core 372 includes a first set of specialized circuits for performing bounding box tests (e.g., for traversal operations) and / or a second set of specialized circuits for performing ray-triangle intersection tests (e.g., intersecting rays that have already been traversed). Thus, for example, the multi-core group 365A can simply start ray probing, and the ray tracing cores 372 independently perform ray traversals and intersections and return hit data (e.g., hit, no hit, multiple hits, etc.) to the thread context. While the ray tracing cores 370 perform traversal and intersection operations, the graphics core 370 and tensor cores 371 are then freed up to perform other graphics or computational work. Optionally, each ray tracing core 372 can include a traversal unit for performing BVH test operations and / or an intersection unit for performing ray-primitive intersection tests. The intersection unit generates "hit," "no hit," or "multiple hits" responses, which it provides to the appropriate threads. During the traversal and intersection operations, execution resources of other cores (e.g., graphics core 370 and tensor core 371) are freed up to perform other forms of graphics work. In one optional embodiment described below, a hybrid rasterization / ray tracing approach is used in which rendering operations are distributed between graphics core 370 and ray tracing core 372.

[0102] The ray tracing core 372 (and / or other cores 370, 371) may include hardware support for a ray tracing instruction set, such as Microsoft's DirectX Ray Tracing (DXR), which includes the DispatchRays command; and ray generation shaders, nearest hit shaders, any hit shaders, and miss shaders, which enable the assignment of a unique set of shaders and textures to each object. Another ray tracing platform that may be supported by the ray tracing core 372, graphics core 370, and tensor core 371 is the Vulkan API (e.g., Vulkan version 1.1.85, or later). However, it is to be noted that the basic principles described herein are not limited to any particular ray tracing ISA. In general, ray tracing core 372, tensor core 371, and graphics core 370 may support a ray tracing instruction set that includes instructions / functions for one or more of the following: ray generation, nearest hit, any hit, ray-primitive intersection, per-primitive and hierarchy bounding box construction, misses, visits, and exceptions. More specifically, preferred embodiments include ray tracing instructions for performing one or more of the following functions:

[0103] Light Generation- Ray generation instructions can be executed for each pixel, sample, or other user-defined work assignment.

[0104] Recent Hits - Can execute nearest hit instructions to locate the closest intersection of a ray with a primitive within the scene.

[0105] Any hit - Any hit instruction identifies multiple intersections between rays and primitives within the scene, potentially identifying a new closest intersection point.

[0106] intersect - The Intersect instruction performs a ray-primitive intersection test and outputs the result.

[0107] Per-primitive bounding box construction - This instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).

[0108] miss - Indicates that the ray missed the scene or all geometry within the specified region of the scene.

[0109] visit ——Indicates the subvolume that the ray will traverse.

[0110] abnormal - Includes various types of exception handlers (e.g., called for various error conditions).

[0111] In one embodiment, the ray tracing core 372 may be adapted to accelerate general computational operations using computational techniques similar to ray intersection testing. A computational framework may be provided that enables shader programs to be compiled into low-level instructions and / or primitives that perform general computational operations via the ray tracing core. Exemplary computational problems that may benefit from computational operations performed on the ray tracing core 372 include computations involving the propagation of beams, waves, rays, or particles within a coordinate space. Interactions associated with that propagation may be computed relative to geometry or meshes within the coordinate space. For example, computations associated with the propagation of electromagnetic signals through an environment may be accelerated using instructions or primitives that are executed via the ray tracing core. Refraction and reflection of signals through objects in the environment may be computed as direct ray tracing simulations.

[0112] The ray tracing core 372 can also be used to perform calculations that are not directly similar to ray tracing. For example, the ray tracing core 372 can be used to accelerate mesh projection, mesh refinement, and volume sampling calculations. General coordinate space calculations, such as nearest neighbor calculations, can also be performed. For example, a set of points near a given point can be found by defining a bounding box around the point in coordinate space. The BVH and ray detection logic within the ray tracing core 372 can then be used to determine the set of intersections of points within the bounding box. The intersections constitute the origin and the nearest neighbors of that origin. The calculations performed using the ray tracing core 372 can be performed in parallel with the calculations performed on the graphics core 370 and the tensor core 371. The shader compiler can be configured to compile compute shaders or other general graphics processing programs into low-level primitives that can be parallelized across the graphics core 370, the tensor core 371, and the ray tracing core 372. Technologies for GPU to host processor interconnection

[0113] Figure 4A The diagram shows a plurality of GPUs 410-413 (e.g., such as Figure 2A ) is communicatively coupled to a plurality of multi-core processors 405-406 via high-speed links 440A-440D (e.g., buses, point-to-point interconnects, etc.). Depending on the implementation, the high-speed links 440A-440D may support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput. Various interconnect protocols may be used, including but not limited to PCIe 4.0, PCIe 5.0, PCIe 6.0, and various NVLink and NVLink-C2C (chip-to-chip) interconnect protocols (e.g., NVLink v5). However, the underlying principles described herein are not limited to any particular communication protocol or throughput.

[0114] Two or more of the GPUs 410-413 may be interconnected via high-speed links 442A-442B, which may be implemented using the same or different protocols / links as those used for high-speed links 440A-440D. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 443, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or lower or higher speeds. Alternatively, Figure 4A All communications between the various system components shown in FIG. 5 can be implemented using the same protocol / links (eg, through a common interconnect structure). However, as mentioned, the basic principles described herein are not limited to any particular type of interconnect technology.

[0115] Each of multi-core processors 405 and 406 may be communicatively coupled to processor memories 401-402 via memory interconnects 430A-430B, respectively, and each GPU 410-413 may be communicatively coupled to GPU memories 420-423, respectively, via GPU memory interconnects 450A-450D. Memory interconnects 430A-430B and 450A-450D may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 401-402 and GPU memories 420-423 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D Xpoint / Optane or Nano-Ram. For example, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy). The memory subsystem described herein is compatible with several memory technologies, such as the double data rate version published by the Joint Electronic Device Engineering Council (JEDEC).

[0116] As described below, although each processor 405-406 and GPU 410-413 may be physically coupled to a specific processor memory 401-402 and GPU memory 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across all of the various physical memories. For example, processor memories 401-402 may each include 64GB of system memory address space, and GPU memories 420-423 may each include 32GB of system memory address space (yielding a total of 256GB of addressable memory in this example).

[0117] Figure 4BThe figure shows additional optional details of the interconnection between processor 407 and graphics accelerator 446. Graphics accelerator 446 may include one or more GPU chips integrated on a line card that is coupled to processor 407 via high-speed link 440. Alternatively, graphics accelerator 446 may be integrated on the same package or chip as processor 407. Processor 407 includes multiple cores 460A-460D, each of which has a translation lookaside buffer 461A-461D and one or more caches 462A-462D. The cores may include various other components for executing instructions and processing data, which are not shown to avoid obscuring the underlying principles of the components described herein (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.). Caches 462A-462D may include a level 1 (L1) cache and a level 2 (L2) cache. In addition, one or more shared caches 456 may be included in the cache hierarchy and shared by the set of cores 460A-460D. For example, one embodiment of processor 407 includes 24 cores, each of which has its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one of the L2 cache and the L3 cache is shared by two adjacent cores. Processor 407 is connected to system memory 441, which may include processor memories 401-402.

[0118] Coherence is maintained for data and instructions stored in each cache 462A-462D, the shared cache(s) 456, and the system memory 441 via inter-core communication over the coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail here to avoid obscuring the basic principles described herein. A proxy circuit 425 may be provided that communicatively couples the graphics accelerator 446 to the coherence bus 464, thereby allowing the graphics accelerator 446 to participate in the cache coherence protocol as a core peer. Specifically, an interface 435 provides connectivity to the proxy circuit 425 over a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and an interface 437 connects the graphics accelerator 446 to the high-speed link 440.

[0119] In one implementation, interface 437 is coupled to accelerator integrated circuit 436, which provides cache management, memory access, context management, and interrupt management services on behalf of graphics processing engines 431, 432, ..., N of graphics accelerator 446. Graphics processing engines 431, 432, ..., N may each include a separate graphics processing unit (GPU). Alternatively, graphics processing engines 431, 432, ..., N may include different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a block image transfer (BLIT) engine. In other words, the graphics accelerator may include graphics processing engines 431-432, ..., N of a single GPU, or graphics processing engines 431-432, ..., N may be associated with multiple GPUs integrated on a common package, line card, or chip. Graphics processing engines 431-432, ..., N may be configured with any graphics processor or computing accelerator architecture described herein. The work to be performed by graphics processing engines 431 , 432 may be specified via work descriptors that provide an indication of the work to be completed by graphics accelerator 446 .

[0120] The accelerator integrated circuit 436 may include a memory management unit (MMU 439) for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 438 stores commands and data for efficient access by graphics processing engines 431, 432...N. Data stored in cache 438 and graphics memories 433-434...M may be kept consistent with core caches 462A-462D, shared cache(s) 456, and system memory 441. As mentioned, this may be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and graphics memory 433-434...M (e.g., sending updates to cache 438 related to modifications / accesses of cache lines on processor caches 462A-462D, shared cache(s) 456, and receiving updates from cache 438).

[0121] Registers 445 store context data for threads executed by graphics processing engines 431-432...N, and context management circuitry 448 manages these thread contexts. For example, context management circuitry 448 may perform save and restore operations to save and restore the context of each thread during a context switch (e.g., where a first thread is saved and a second thread is restored so that the second thread can be executed by the graphics processing engine). For example, upon a context switch, context management circuitry 448 may store current register values ​​to a designated area in memory (e.g., identified by a context pointer). It may then restore the register values ​​upon returning to that context. Interrupt management circuitry 447 may, for example, receive interrupts from system devices and process interrupts received from system devices.

[0122] In one implementation, the virtual / effective address from the graphics processing engine 431 is translated into an actual / physical address in the system memory 441 by the MMU 439. Optionally, the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerators 446 and / or other accelerator devices. The graphics accelerator 446 can be dedicated to a single application executed on the processor 407, or can be shared between multiple applications. Optionally, a virtualized graphics execution environment is provided in which the resources of the graphics processing engines 431-432...N are shared with multiple applications, virtual machines (VMs), or containers. Resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications or based on a predetermined partition profile for the graphics accelerator 446. VM and container can be used interchangeably herein.

[0123] A virtual machine (VM) can be software that runs an operating system and one or more applications. A VM can be defined by specifications, configuration files, virtual disk files, non-volatile random access memory (NVRAM) settings files, and log files, and is backed up by the physical resources of the host computing platform. A VM can include an operating system (OS) or application environment installed on software that mimics dedicated hardware. End users have the same experience on a virtual machine as they would on dedicated hardware. Specialized software called a hypervisor completely emulates the CPU, memory, hard disk, network, and other hardware resources of a PC client or server, allowing virtual machines to share resources. A hypervisor can emulate multiple virtual hardware platforms that are isolated from each other, allowing virtual machines to run on the same underlying physical host. Server, VMware ESXi, and other operating systems.

[0124] A container is a package of applications, configurations, and dependencies so that the application runs reliably from one computing environment to another. Containers can share the operating system installed on a server platform and run as isolated processes. A container is a package of software that contains everything the software needs to run, such as system tools, libraries, and settings. Containers are not installed like traditional software programs, which allows them to be isolated from other software and from the operating system itself. The isolated nature of containers provides several benefits. First, the software in the container will run the same way in different environments. For example, a container containing PHP and MySQL can be installed in Computers and The machines will run in exactly the same way on both. Secondly, containers provide increased security because the software will not affect the host operating system. While installed applications can change system settings and modify resources (such as the Windows Registry), containers can only modify settings within the container.

[0125] Thus, the accelerator integrated circuit 436 acts as a bridge to the system for the graphics accelerator 446 and provides address translation and system memory caching services. In one embodiment, to facilitate the bridging function, the accelerator integrated circuit 436 may also include shared I / O 497 (e.g., PCIe, USB, or other elements) and hardware to implement system control for voltage, clock control, performance, thermal, and security. The shared I / O 497 may utilize separate physical connections or may span the high-speed link 440. In addition, the accelerator integrated circuit 436 may provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0126] Because the hardware resources of the graphics processing engines 431-432...N are explicitly mapped to the actual address space seen by the processor 407, any host processor can directly address these resources using effective address values. An optional function of the accelerator integrated circuit 436 is to physically separate the graphics processing engines 431-432...N so that they appear as independent units to the system. In one embodiment, the accelerator integrated circuit 436 includes a security circuit 444 that is capable of configurable cryptographic isolation of data associated with each slice of the resources. Different slices can be associated with different security domains, so that different encryption keys are used to encrypt data associated with the various security domains. In one embodiment, the security domains of the graphics accelerator 446 can be integrated into a trusted execution environment supported by the processor 407. In one embodiment, a secure I / O function can be enabled that allows each security domain to be presented as a separate trusted I / O device, thereby enabling support for trusted DMA and MMIO operations.

[0127] One or more graphics memories 433-434...M may be respectively coupled to each of the graphics processing engines 431-432...N. Graphics memories 433-434...M store instructions and data processed by each of the graphics processing engines 431-432...N. Graphics memories 433-434...M may be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D Xpoint / Optane, Samsung Z-NAND, or Nano-Ram.

[0128] To reduce the amount of data traffic on high-speed link 440, biasing techniques may be used to ensure that the data stored in graphics memory 433-434 ... M is data that will be used most frequently by graphics processing engines 431-432 ... N and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 431-432 ... N) within caches 462A-462D, shared cache(s) 456, and system memory 441.

[0129] In an alternative variation, an accelerator integrated circuit 436 is integrated within the processor 407, and the graphics processing engines 431-432, ..., N communicate with the accelerator integrated circuit 436 via an interface 437 and an interface 435 (which may also utilize any form of bus, structure, or interface protocol) over a high-speed link 440. In this variation, the accelerator integrated circuit 436 performs the same operations as those described above.

[0130] The described embodiments may support different programming models, including a dedicated process programming model (without graphics accelerator virtualization) and a shared programming model (with virtualization). The latter may include programming models controlled by accelerator integrated circuit 436 and programming models controlled by graphics accelerator 446. In the dedicated process model embodiment, graphics processing engines 431, 432, ..., N can be dedicated to a single application or process under a single operating system. A single application can leak requests from other applications to graphics engines 431, 432, ..., N, thereby providing virtualization within a VM / partition. In the dedicated process programming model, graphics processing engines 431, 432, ..., N can be shared by multiple VMs / application partitions. The shared model requires a hypervisor to virtualize graphics processing engines 431-432, ..., N to allow access by each operating system. For a single-partition system without a hypervisor, graphics processing engines 431-432, ..., N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431-432, ..., N to provide access to each process or application. For the shared programming model, the graphics accelerator 446 or each graphics processing engine 431-432, ..., N uses a process handle to select a process element. The process element can be stored in the system memory 441 and can be addressed using the effective address to real address translation technique described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432, ..., N (which can be performed by the host process by calling the system software to add the process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0131] Figure 4C The accelerator integrated slice 490 is shown. As used herein, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 436. The application's address space 482 within the system memory 441 stores a process element 483. The process element 483 can be stored in response to a GPU call 481 from the application 480 executing on the processor 407. The process element 483 contains the process state for the application 480. The work descriptor (WD) 484 contained in the process element 483 can be a single job requested by the application, or it can contain a pointer to a job queue. In the latter case, the WD 484 is a pointer to the job request queue in the application's address space 482.

[0132] The graphics accelerator 446 and / or the individual graphics processing engines 431-432, ..., N can be shared by all processes in the system or a subset of the processes in the system. For example, the techniques described herein may include infrastructure for setting process state and sending WD 484 to the graphics accelerator 446 to start a job in a virtualized environment.

[0133] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics accelerator 446 or a separate graphics processing engine (e.g., graphics processing engine 431). Because the graphics accelerator 446 is owned by a single process, when the graphics accelerator 446 is assigned, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition, and the operating system initializes the accelerator integrated circuit 436 for the owning process.

[0134] In operation, a fetch unit 491 in the accelerator integrated slice 490 fetches a WD 484 to be processed. WD 484 includes an indication of work to be performed by one or more graphics processing engines of the graphics accelerator 446. As illustrated, data from WD 484 may be stored in registers 445 and used by the MMU 439, interrupt management circuitry 447, and / or context management circuitry 448. For example, the MMU 439 may include segment / page walk circuitry for accessing segment tables / page tables 486 within the OS virtual address space 485. The interrupt management circuitry 447 may process interrupt events 492 received from the graphics accelerator 446. When executing graphics operations, effective addresses 493 generated by the graphics processing engines 431-432, ..., N are translated into real addresses by the MMU 439.

[0135] Register 445 can be replicated for each graphics processing engine 431-432, ..., N and / or graphics accelerator 446 and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integrated slice 490. In one embodiment, each graphics processing engine 431-432, ..., N can be presented to a hypervisor 496 as a different graphics processor device. Quality of Service (QoS) settings can be configured for clients of a specific graphics processing engine 431-432, ..., N. Cryptographic and physical data isolation between clients of each engine can be enabled via isolated memory access paths and automatic data encryption for each client. Exemplary registers that can be initialized by a hypervisor are shown in Table 1. Table 1 - Registers initialized by the hypervisor 1 Slice Control Register 2 Real Address (RA) scheduled process area pointer 3 Permission Mask Override Register 4 Interrupt vector table entry offset 5 Interrupt vector table entry limit 6 Status Register 7 Logical partition ID 8 Real Address (RA) Manager Accelerator Utilizes Record Pointers 9 Storage Description Register

[0136] Example registers that may be initialized by the operating system are shown in Table 2. Table 2 - Registers initialized by the operating system

[0137] Each WD 484 may be specific to a particular graphics accelerator 446 and / or graphics processing engine 431-432, ..., N. It contains all the information required by the graphics processing engine to do its work, or it may be a pointer to a memory location where a command queue is located where an application has set up work to be done.

[0138] Figure 4D The diagram illustrates additional optional details of the sharing model. It includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes the graphics processing engine to the operating system 495.

[0139] The shared programming model allows all processes or a subset of processes from all partitions in the system or a subset of partitions in the system to use the graphics accelerator 446. There are two programming models in which the graphics accelerator 446 is shared by multiple processes and partitions: time-sharing and graphics-directed sharing.

[0140] In this model, hypervisor 496 owns graphics accelerator 446 and makes its functionality available to all operating systems 495. In order for graphics accelerator 446 to support virtualization by hypervisor 496, graphics accelerator 446 may adhere to the following requirements: 1) Application job requests must be autonomous (i.e., state does not need to be maintained between jobs), or graphics accelerator 446 must provide a context save and restore mechanism. 2) Application job requests (including any translation errors) are guaranteed by graphics accelerator 446 to complete within a specified amount of time, or graphics accelerator 446 provides the ability to preempt the processing of jobs. 3) When operating in a directed-sharing programming model, graphics accelerator 446 must ensure fairness between processes.

[0141] For a directed sharing model, application 480 may be required to make an operating system 495 system call using a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics accelerator 446 type describes the acceleration function targeted by the system call. The graphics accelerator 446 type can be a system-specific value. The WD is formatted specifically for the graphics accelerator 446 and can take the form of a graphics accelerator 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure describing work to be performed by the graphics accelerator 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application setting the AMR. If the accelerator integrated circuit 436 and graphics accelerator 446 implementation do not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current Authority Mask Override Register (AMOR) value before placing the AMR into the process element 483. The CSRP may be one of the registers 445 that contains the effective address of an area in the application's address space 482 for use by the graphics accelerator 446 to save and restore context state. This pointer is optional if state saving is not required between jobs or if the job is preempted. The context save / restore area may be fixed system memory.

[0142] Upon receiving the system call, operating system 495 may verify that application 480 is registered and has been given permission to use graphics accelerator 446. Operating system 492 then calls hypervisor 496 with the information shown in Table 3. Table 3 - OS call parameters to the hypervisor

[0143] Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has registered and been given permission to use the graphics accelerator 446. The hypervisor 496 then places the process element 483 in the process element linked list for the corresponding type of graphics accelerator 446. The process element may include the information shown in Table 4. Table 4 - Process element information 1 Work Descriptor (WD) 2 The authority mask register (AMR) value (potentially masked). 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table, derived from the hypervisor call parameters. 9 Status register (SR) value 10 Logical partition ID (LPID) 11 Real Address (RA) Manager Accelerator Utilizes Record Pointers 12 Storage Descriptor Register (SDR)

[0144] The hypervisor may initialize the registers 445 of the accelerator integrated slice 490 .

[0145] like Figure 4E As shown in FIG, in one optional implementation, a unified memory addressable via a common virtual memory address space is employed that is used to access physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402 and vice versa, thereby simplifying programmability. A first portion of the virtual / effective address space may be allocated to processor memory 401, a second portion may be allocated to second processor memory 402, a third portion may be allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) may thus be distributed across each of processor memories 401-402 and GPU memories 420-423, allowing any processor or GPU to access any physical memory using a virtual address mapped to that physical memory.

[0146] Bias / coherency management circuits 494A-494E within one or more of the MMUs 439A-439E may be provided that ensure cache coherency between the caches of the host processor (e.g., multi-core processor 405) and the caches of the GPUs 410-413 and implement biasing techniques that indicate the physical memory in which certain types of data should be stored. Figure 4E Multiple instances of bias / coherence management circuits 494A- 494E are illustrated in , but bias / coherence circuits may be implemented within an MMU of one or more host processors and / or within the accelerator integrated circuit 436 .

[0147] The GPU-attached memory 420-423 can be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without the typical performance drawbacks associated with full system cache coherence. The ability of the GPU-attached memory 420-423 to be accessed as system memory without the heavy cache coherence overhead provides a beneficial operating environment for GPU migration. This arrangement allows host processor software to set up operation objects and access computation results without the overhead of traditional I / O DMA data copying. Such traditional copying involves driver calls, interrupts, and memory mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access the GPU-attached memory 420-423 without cache coherence overhead can be critical to the execution time of the migrated computation. For example, in situations with large amounts of streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 410-413. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU migration.

[0148] The selection between GPU bias and host processor bias can be driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure (i.e., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. The bias table can be implemented in the stolen memory range of one or more GPU-attached memories 420-423, with or without a bias cache in GPUs 410-413 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0149] In one implementation, the bias table entry associated with each access to the GPU-attached memory 420-423 is accessed before the actual access to the GPU memory, resulting in the following operations. First, local requests from the GPU 410-413 for pages that find their location in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPU for pages that find their location in the host bias are forwarded to the processor (e.g., as discussed above, over a high-speed link). Optionally, requests from the host processor for pages that find their location in the host processor bias complete the request like normal memory reads. Alternatively, requests involving pages in the GPU bias may be forwarded to the GPU 410-413. If the GPU is not currently using the page, the GPU may then transition the page to the host processor bias. The bias state of a page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, by a purely hardware-based mechanism. One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU directing the GPU to change the bias state and perform a cache flush operation in the host for some transitions. A cache flush operation is required for transitions from host processor bias to GPU bias, but not for the reverse transition.

[0150] Cache coherency can be maintained by temporarily rendering GPU-biased pages that are not cacheable by the host processor. To access these pages, the host processor may request access from GPU 410, which may or may not grant immediate access, depending on the implementation. Therefore, to reduce communication between the host processor and GPU 410, it is beneficial to ensure that GPU-biased pages are those required by the GPU but not by the host processor, and vice versa. Graphics processing pipeline

[0151] Figure 5 5. A graphics processing pipeline 500 is shown. A graphics multiprocessor (such as Figure 2D Graphics multiprocessor 234 or Figure 2E The graphics multiprocessor 235 of FIG. 5 may implement the graphics processing pipeline 500. The graphics multiprocessor may be included in a parallel processing subsystem as described herein, such as a parallel processing subsystem. Figure 2A The parallel processor 200 can be used with Figure 1 The various parallel processor systems may be implemented via parallel processing units (e.g., Figure 2AThe graphics processing pipeline 500 may be implemented using one or more instances of the parallel processing unit 202 of FIG. For example, a shader unit (e.g., Figure 2C The graphics multiprocessor 234 of FIG. 5 may be configured to perform the functions of one or more of the following: a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 513, a geometry processing unit 516, and a fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by a processing cluster (e.g., Figure 2A Other processing engines within the processing cluster 214 and corresponding partition units (e.g., Figure 2A The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. It is also possible that one or more portions of the graphics processing pipeline 500 are executed by parallel processing logic within a general-purpose processor (e.g., a CPU). Optionally, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., such as a CPU) via a memory interface 528. Figure 2A The parallel processor memory 222 in the memory interface 528 can be Figure 2A The graphics processing pipeline 500 may also be connected to the memory interface 218 via the graphics processing pipeline 500. Figure 3 This is achieved using the multi-core group 365A in .

[0152] The data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes vertex shader programs to illuminate and transform the vertex data as specified by the vertex shader programs. The vertex processing unit 504 reads data stored in cache, local, or system memory for use in processing vertex data and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0153] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and builds graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc., as supported by various graphics processing application programming interfaces (APIs).

[0154] The tessellation control processing unit 508 treats the input vertices as control points of a geometry patch. The control points are transformed from an input representation of the patch (e.g., a basis for the patch) into a representation suitable for use in surface estimation by the tessellation evaluation processing unit 513. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometry patch. The tessellation factors are applied to individual edges and quantize the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and to tessellate the patch into a plurality of geometric primitives (e.g., line, triangle, or quadrilateral primitives), which are passed to the tessellation evaluation processing unit 513. The tessellation evaluation processing unit 513 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0155] The second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 513 as needed, reads the stored vertex attributes, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive assembler 514 as specified by the geometry shader program. The geometry processing unit 516 can be programmed to tessellate the graphics primitive into one or more new graphics primitives and calculate parameters used to rasterize the new graphics primitives.

[0156] The geometry processing unit 516 may be capable of adding or removing elements from the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in parallel processor memory or system memory for use in processing geometry data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

[0157] The rasterizer 522 can perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute fragment shader programs or pixel shader programs. The fragment / pixel processing unit 524 transforms fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including, but not limited to, texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels that are output to the raster operation unit 526. The fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use in processing the fragment data. The fragment or pixel shader program can be configured to shade at sample, pixel, slice, or other granularity, depending on the sampling rate configured for the processing unit.

[0158] Raster operation unit 526 is a processing unit that performs raster operations and outputs pixel data to be stored in graphics memory (e.g., as Figure 2A The parallel processor memory 222 and / or Figure 1 The raster operations unit 526 may be configured to compress z-data or color data written to memory and decompress z-data or color data read from memory. Machine Learning Overview

[0159] The architecture described above can be applied to perform training and inference operations using machine learning models. Machine learning has been successful in solving many types of tasks. The calculations generated when training and using machine learning algorithms (e.g., neural networks) are naturally suitable for efficient parallel implementations. Accordingly, parallel processors such as general-purpose graphics processing units (GPGPUs) have played an important role in the actual implementation of deep neural networks. Parallel graphics processors with single instruction multiple threads (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as frequently as possible to increase processing efficiency. The efficiency provided by the parallel machine learning algorithm implementation allows the use of high-capacity networks and enables training of those networks to larger data sets.

[0160] Machine learning algorithms are algorithms that can learn from a data set. For example, machine learning algorithms can be designed to model high-level abstractions within a data set. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output a numerical value given an input; and pattern recognition algorithms can be used to generate converted text or perform text-to-speech and / or speech recognition.

[0161] An exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating the output in the output layer. The nodes of the network are fully connected to the nodes in adjacent layers via edges, but there are no edges between nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function, which calculates the state of the nodes in each successive layer of the network based on coefficients ("weights") associated with each of the edges connecting these layers. Depending on the specific model being represented by the algorithm being executed, the output from the neural network algorithm can take various forms.

[0162] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves: selecting a network topology; using a set of training data that represents the problem being modeled by the network; and adjusting weights until the network model performs with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and as the error signal is propagated backward through the layers of the network, the weights associated with the connections are adjusted to minimize that error. The network is considered "trained" when the error for each of the outputs generated from the instances of the training data set is minimized.

[0163] The accuracy of a machine learning algorithm can be significantly affected by the quality of the dataset used to train the algorithm. The training process can be computationally intensive and can take a significant amount of time on a conventional general-purpose processor. Accordingly, many types of machine learning algorithms are trained using parallel processing hardware. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are naturally suited to parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to take advantage of the parallel processing hardware within general-purpose graphics processing devices.

[0164] Figure 6 is a generalized diagram of a machine learning software stack 600. A machine learning application 602 is any logic that can be configured to train a neural network using a training dataset or to implement machine intelligence using a trained deep neural network. The machine learning application 602 may include training and inference functionality for the neural network and / or specialized software that can be used to train the neural network prior to deployment. The machine learning application 602 may implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation. Example machine learning applications 602 include but are not limited to voice-based virtual assistants, image or facial recognition algorithms, autonomous navigation, and software tools used to train the machine learning models used by the machine learning application 602.

[0165] Hardware acceleration for machine learning applications 602 can be enabled via a machine learning framework 604. The machine learning framework 604 can provide a library of machine learning primitives. Machine learning primitives are basic operations typically performed by machine learning algorithms. Without the machine learning framework 604, developers of machine learning algorithms would need to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic when new parallel processors are developed. Instead, machine learning applications can be configured to use the primitives provided by the machine learning framework 604 to perform the necessary computations. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). The machine learning framework 604 can also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations. Examples of machine learning frameworks 604 include, but are not limited to, TensorFlow, TensorRT, PyTorch, MXNet, Caffe, and other advanced machine learning frameworks.

[0166] The machine learning framework 604 can process input data received from the machine learning application 602 and generate appropriate input to the computation framework 606. The computation framework 606 can abstract the underlying instructions provided to the GPGPU driver 608, enabling the machine learning framework 604 to utilize hardware acceleration via the GPGPU hardware 610 without requiring the machine learning framework 604 to be intimately familiar with the architecture of the GPGPU hardware 610. Furthermore, the computation framework 606 can enable hardware acceleration for the machine learning framework 604 across various types and generations of GPGPU hardware 610. In one example, the computation framework 606 can include the CUDA computation framework and associated machine learning libraries, such as the CUDA Deep Neural Network (cuDNN) library. The machine learning software stack 600 can also include a communication library or framework to facilitate multi-GPU and multi-node computation. GPGPU machine learning acceleration

[0167] Figure 7 A general purpose graphics processing unit (GPGPU 700) is shown, which may be Figure 2A Parallel processor 200 or Figure 1 The general processing unit can be configured to provide hardware acceleration support for primitives provided by machine learning frameworks to accelerate the processing of computational workloads of the type associated with training deep neural networks. In addition, the GPGPU 700 can be directly linked to other instances of the GPGPU to create a multi-GPU cluster, thereby improving the training speed of deep neural networks in particular. Primitives are also supported to accelerate inference operations for deployed neural networks.

[0168] GPGPU 700 includes a host interface 702 for enabling connection to a host processor. Host interface 702 may be a PCI Express interface. However, the host interface may also be a vendor-specific communication interface or communication structure. GPGPU 700 receives commands from the host processor and uses a global scheduler 704 to distribute execution threads associated with those commands to a collection of processing clusters 706A-706H. The processing clusters 706A-706H share a cache memory 708. The cache memory 708 may act as a higher level cache for the cache memory within the processing clusters 706A-706H. The illustrated processing clusters 706A-706H may be connected to a plurality of processors such as the CPU 100 and the CPU 100. Figure 2A Corresponding to the processing clusters 214A-214N in.

[0169] GPGPU 700 includes memory 714A-714B coupled to processing clusters 706A-706H via a set of memory controllers 712A-712B. Memory 714A-714B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. Memory 714A-714B may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0170] Each of processing clusters 706A-706H may include a collection of graphics multiprocessors, such as, Figure 2E The graphics multiprocessor 235 may include Figure 3 The graphics multiprocessors of the computing clusters include multiple types of integer and floating-point logic units capable of performing computational operations with a range of precision, including those suitable for machine learning computations. For example, at least a subset of the floating-point units in each of the computing clusters 706A-706H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0171] Multiple instances of GPGPU 700 can be configured to operate as a compute cluster. The communication mechanisms used by the compute cluster for synchronization and data exchange vary across embodiments. For example, multiple instances of GPGPU 700 communicate via host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 709 that couples GPGPU 710 with a GPU link 710, which enables direct connections to other instances of the GPGPU. GPU link 710 can be coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 700. Optionally, GPU link 710 is coupled to a high-speed interconnect to transmit and receive data to and from other GPGPUs or parallel processors. Multiple instances of GPGPU 700 can be located in separate data processing systems and can communicate via a network device accessible via host interface 702. In addition to or in lieu of host interface 702 , GPU link 710 may be configured to enable connection to a host processor.

[0172] While the illustrated configuration of GPGPU 700 can be configured for training neural networks, alternative configurations of GPGPU 700 can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, GPGPU 700 includes fewer of processing clusters 706A-706H relative to the training configuration. Additionally, the memory technology associated with memory 714A-714B can differ between the inference configuration and the training configuration. In one embodiment, the inference configuration of GPGPU 700 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer or floating point dot product instructions, which are typically used during inference operations for deployed neural networks.

[0173] Figure 8 A multi-GPU computing system 800 is shown. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A-806D via a host interface switch 804. The host interface switch 804 may be a PCI Express switching device that couples the processor 802 to a PCI Express bus, over which the processor 802 can communicate with the set of GPGPUs 806A-806D. Each of the plurality of GPGPUs 806A-806D may be a Figure 7 GPGPUs 806A-806D may be interconnected via a collection of high-speed point-to-point GPU-to-GPU links (P2P GPU links 816). The high-speed GPU-to-GPU links may be connected to each of the GPGPUs 806A-806D via a dedicated GPU link, such as a dedicated GPU link. Figure 7 P2P GPU link 816 enables direct communication between each of GPGPUs 806A-806D without requiring communication over the host interface bus to which processor 802 is connected. With GPU-to-GPU traffic directed to the P2P GPU link, the host interface bus remains available for system memory access or for communicating with other instances of multi-GPU computing system 800, for example, via one or more network devices. Figure 8 GPGPUs 806A-806D are connected to processor 802 via host interface switch 804, but processor 802 may alternatively include direct support for P2P GPU link 816 and connect directly to GPGPUs 806A-806D. In one embodiment, P2P GPU link 816 enables multi-GPU computing system 800 to operate as a single logical GPU. Machine Learning Neural Network Implementation

[0174] The computing architecture described herein can be configured to perform a type of parallel processing that is particularly suitable for training and deploying neural networks for machine learning. A neural network can be summarized as a network of functions with graph relationships. As is well known in the art, there are various types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network as previously described. A second exemplary type of neural network is a convolutional neural network (CNN), and a third exemplary type of neural network is a recurrent neural network (RNN).

[0175] CNNs are specialized feedforward neural networks used to process data with a known, grid-like topology (such as image data). Accordingly, CNNs are commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a collection of "filters" (feature detectors inspired by the receptive fields found in the retina), and the output of each filter set is propagated to nodes in successive layers of the network. The computations used in a CNN involve applying a mathematical operation called convolution to each filter to produce the output of that filter. Convolution is a specialized mathematical operation performed on two functions to produce a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function to be convolved can be called the input, while the second function can be called the convolution kernel. The output can be called a feature map. The input to a convolutional layer can be a multidimensional data array defining the various color components of the input image. The convolution kernel can be a multidimensional parameter array, where the parameters are adapted through the training process used for the neural network.

[0176] An RNN is a series of feedforward neural networks that include feedback connections between layers. RNNs enable modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture for an RNN includes loops that represent the effect of a variable's current value on its own value at future moments, as at least part of the output data from the RNN is used as feedback for processing subsequent input in the sequence. This feature makes RNNs particularly useful for language processing due to the mutable nature of language data, which can be composed.

[0177] The figures described below present exemplary feedforward networks, CNN networks, and RNN networks, and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any specific embodiment described herein, and that the concepts illustrated are generally applicable to deep neural networks and machine learning techniques in general.

[0178] The deep neural networks used in deep learning typically include a front-end network for performing feature recognition, which is coupled to a back-end network that represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representations provided to the mathematical model. Deep learning enables machine learning to be performed without the need for manual feature engineering for the model. Instead, deep neural networks can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is typically dedicated to a specific task to be performed, and different models will be used to perform different tasks.

[0179] Once the neural network is structured, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Back propagation of errors is a common method for training neural networks. The input vector is presented to the network for processing. The output of the network is compared with the desired output using a loss function, and an error value is calculated for each neuron in the output layer. Subsequently, the error value is propagated backward until each neuron has an associated error value that roughly represents the contribution of the neuron to the original output. The network can then learn from those errors using an algorithm (such as a stochastic gradient descent algorithm) to update the weights of the neural network.

[0180] Figure 9A-9B Illustration of an example convolutional neural network. Figure 9A The diagram shows the various layers in CNN. Figure 9A As shown in , an exemplary CNN for modeling image processing may receive an input 902 describing the red, green, and blue (RGB) components of an input image. The input 902 may be processed by a plurality of convolutional layers (e.g., a first convolutional layer 904, a second convolutional layer 906). The outputs from the plurality of convolutional layers may optionally be processed by a fully connected layer 908. As previously described for feedforward networks, neurons in a fully connected layer have full connections to all activations in the previous layer. The outputs from the fully connected layer 908 may be used to generate output results from the network. Activations within the fully connected layer 908 may be calculated using matrix multiplication rather than convolution. Not all CNN implementations utilize a fully connected layer 908. For example, in some implementations, the second convolutional layer 906 may generate the output of the CNN.

[0181] The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 908. Traditional neural network layers are fully connected so that each output unit interacts with every input unit. However, as shown, the convolutional layers are sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state value of each node in the receptive field) is input to the nodes of the subsequent layer. The kernel associated with the convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process large images.

[0182] Figure 9B 1 illustrates exemplary computational stages within a convolutional layer of a CNN. Input 912 to a convolutional layer of the CNN can be processed in three stages of a convolutional layer 914. These three stages may include a convolution stage 916, a detector stage 918, and a pooling stage 920. The convolutional layer 914 can then output data to a subsequent convolutional layer. The final convolutional layer of the network can generate output feature map data or provide input to a fully connected layer, for example, to generate a classification value for input to the CNN.

[0183] Several convolutions are performed in parallel in the convolution stage 916 to produce a set of linear activations. The convolution stage 916 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) connected to specific regions in the input, which can be determined as local regions associated with the neuron. The neuron calculates the dot product between the weight of the neuron and the weight of the region in the local input to which the neuron is connected. The output from the convolution stage 916 defines the set of linear activations processed by the successive stages of the convolution layer 914.

[0184] The linear activations may be processed by the detector stage 918. In the detector stage 918, each linear activation is processed by a nonlinear activation function. Nonlinear activation functions increase the nonlinear nature of the overall network without affecting the receptive field of the convolutional layers. Several types of nonlinear activation functions may be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x) such that the threshold of the activation is zero.

[0185] The pooling stage 920 uses a pooling function that replaces the output of the second convolutional layer 906 with summary statistics of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that small translations to the input do not change the pooled output. The invariance of local translation can be useful in scenarios where the presence of a feature in the input data is more important than the exact location of the feature. Various types of pooling functions can be used during the pooling stage 920, including maximum pooling, average pooling, and l2 norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such implementations are alternative and additional convolution stages with an increased span relative to the previous convolution stage.

[0186] The output from the convolutional layer 914 may then be processed by the next layer 922. The next layer 922 may be an additional convolutional layer or one of the fully connected layers 908. For example, Figure 9A The first convolutional layer 904 can output to the second convolutional layer 906, and the second convolutional layer can output to the first layer in the fully connected layer 908.

[0187] A variant of CNN is the convolutional deep belief network, which has a similar structure to CNN and is trained in a similar manner to the deep belief network. A deep belief network (DBN) is a generative neural network consisting of multiple layers of stochastic (random) variables. DBNs can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining the optimal initial set of weights for the neural network.

[0188] Figures 10A-10B An exemplary language model is illustrated. Figure 10AA recurrent neural network (RNN 1000) is shown. In a recurrent neural network (RNN), the network's previous state influences the output of the network's current state. RNNs can be built in various ways and using various functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous sequences of inputs. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given a previous sequence of words. RNN 1000 can be described as having an input layer 1002 that receives an input vector, a hidden layer 1004 that implements the recurrent function, a feedback mechanism 1005 that enables "memory" of previous states, and an output layer 1006 that outputs the results. RNN 1000 operates based on time steps. The state of the RNN at a given time step is influenced by the previous time step via the feedback mechanism 1005. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1004. The second input (x2) can be processed by the hidden layer 1004 using the state information determined during the processing of the initial input (x1). The given state can be calculated as s t =f(Ux t +Ws t-1 ), where U and W are parameter matrices. Function f is generally nonlinear, such as a variant of the hyperbolic tangent function (Tanh), or a modified function f(x)=max(0,x). However, the specific mathematical function used in hidden layer 1004 may vary depending on the specific implementation details of RNN 1000. Acceleration of variations of RNN networks can also be enabled. An example RNN variant is a long short term memory (LSTM) RNN. LSTM RNNs are capable of learning long-term dependencies that may be necessary to process longer language sequences.

[0189] Figure 10B The diagram shows the baseline components of the Transformer model 1010. The Transformer model 1010 solves problems found in RNN models with long input sequences and enables increased parallelization. The Transformer model 1010 and its variants are used to build language models (LLMs) that perform various tasks such as machine translation, automatic summarization, and dialogue management. The Transformer model 1010 can also be configured to perform image generation tasks, such as text-to-image generation.

[0190] The Transformer model 1010 includes multiple instances of an encoder 1016 and a decoder 1026. The encoders are stacked end-to-end, with the output of the final encoder being routed as input to the multi-head attention layer of each decoder 1026. The input to the bottom-most instance of the encoder 1016 is processed by the input embedding 1012, which converts the input tokens into vectors that can be processed by the encoder 1016. The output dictionary is vectorized by the output embedding 1022 before entering the bottom-most instance of the decoder 1026. Positional encodings 1014 and 1024 are added to the input and output vectors at the bottom of the encoder 1016 and decoder 1026 stack. The positional encodings 1014 and 1024 inject information about the relative or absolute position of the token in the sequence of tokens to be processed, as the Transformer model 1010 does not naturally encode the order of tokens.

[0191] The encoder 1016 of the transformer model 1010 analyzes the input text and creates several hidden states that preserve the context and meaning of the text data. The encoder 1016 layer forms the core of the transformer architecture, although variants of the transformer model 1010 with only the decoder 1026 are also possible. The encoder 1016 includes two sublayers: a multi-head attention (MHA) sublayer and a feedforward network (FFN) sublayer. The MHA sublayer performs multiple concurrent self-attention operations to calculate attention scores, which enables the transformer model 1010 to weigh the importance and relative relationships of different tokens in the input sequence in a context-aware manner. The FFN sublayer is a fully connected feedforward neural network that is position-by-position. The output of each sublayer is processed through an addition and normalization (A&N) operation, defined as LayerNorm(x+Sublayer(x)), where the output of the sublayer is added to the input of the sublayer and normalized. In some implementations, the normalization operation may be performed before the sub-layer instead of after.

[0192] Decoder 1026 includes three sublayers: a masked MHA sublayer, an MHA sublayer, and an FFN sublayer. The masked MHA sublayer is similar to the MHA layer, except that masking is applied to prevent query positions from focusing on the key for future positions. The MHA sublayer of decoder 1026 is similar to the MHA sublayer of the encoder, with an additional input from encoder 1016. The FFN of decoder 1026 is the same as the FFN of encoder 1016. The linear and softmax blocks take the output of the last instance of decoder 1026 of the decoder stack and generate a probability distribution representing the output probabilities.

[0193] GPU acceleration can also be used for variants of the transformer model 1010 that replace some or all FFN sublayers with sparse mixture of experts (MoE) layers. Each MoE layer contains several experts, each of which is a neural network. The MoE layer can itself be an FFN, or it can be an MoE, allowing for a hierarchy of MoE layers.

[0194] Training of the transformer model 1010 can be optimized via the use of adaptive precision logic that adjusts the precision of calculations applied during training. The adaptive precision logic can attempt to use the smallest possible data types during training without significantly reducing training accuracy. For example, to minimize data loss due to the use of 16-bit, 8-bit, and 4-bit floating point formats, dynamic scaling and type casting can be applied during training based on statistical analysis of tensor data generated during training. The tensor data generated during training can be statistically analyzed using various analysis techniques to determine a set of scaling factors to be applied to data blocks, such as inputs to each layer of the transformer model 1010. For example, absolute minimum and / or maximum values ​​can be used to determine scaling factors that can prevent underflow or overflow of low-precision floating point data types.

[0195] Figure 11 The diagram illustrates the training and deployment of a deep neural network. Once a given network has been structured for a task, the neural network is trained using a training dataset 1102. A training framework 1104 has been developed to enable hardware acceleration of the training process. For example, Figure 6 The machine learning framework 604 can be configured as a training framework 1104. The training framework 1104 can access an untrained neural network 1106 and enable the untrained neural network to be trained using the parallel processing resources described herein to generate a trained neural network 1108. To begin the training process, weights can be randomly selected or initial weights can be selected by pre-training using a deep belief network. Subsequently, a training cycle is performed in a supervised or unsupervised manner.

[0196] Supervised learning is a learning method in which training is performed as a mediated operation, such as when the training dataset 1102 includes inputs paired with their expected outputs, or when the training dataset includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting output to the expected output or set of expected outputs. Errors are then propagated back through the system. The training framework 1104 can be adjusted to adjust the weights controlling the untrained neural network 1106. The training framework 1104 can provide tools to monitor how well the untrained neural network 1106 is converging on a model suitable for generating the correct answer based on the known input data. The training process occurs iteratively as the network's weights are adjusted to refine the outputs generated by the neural network. The training process can continue until the neural network reaches a statistically expected level of accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to implement any number of machine learning operations to generate inference results 1114 based on the input of new data 1112.

[0197] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Therefore, for unsupervised learning, the training data set 1102 will include input data without any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the entire data set. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1108 that can perform operations useful in reducing the dimensionality of data. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from the normal pattern of the data.

[0198] Variations of supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which a mixture of labeled and unlabeled data having the same distribution is included in the training data set 1102. Incremental learning is a variation of supervised learning in which input data is continuously used to further train the model. Incremental learning enables a trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge embedded in the network during initial training. Whether supervised or unsupervised, the training process for particularly deep neural networks can be too computationally intensive for a single computing node. A distributed network of computing nodes can be used instead of a single computing node to accelerate the training process.

[0199] Figure 12Ais a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. Each of the distributed computing nodes may include one or more host processors or one or more general processing nodes such as Figure 7 700. As shown, distributed learning can be performed with model parallelism 1202, data parallelism 1204, or a combination of model and data parallelism 1206.

[0200] In model parallelism 1202, different compute nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Benefits of model parallelism include the ability to scale to extremely large models. Splitting the computations associated with different layers of a neural network enables training of very large neural networks, where the weights of all layers would not fit into the memory of a single node. In some instances, model parallelism can be particularly useful when performing unsupervised training of large neural networks. Some implementations of model parallelism 1202 may also be referred to as tensor parallelism.

[0201] In data parallelism 1204, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. Although different ways to implement data parallelism are possible, all data parallel training methods require techniques to combine the results and synchronize the model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average value of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, except that updates to the model are transmitted instead of transmitting parameters from the node to the parameter server. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and transmitted between nodes.

[0202] Combined model and data parallelism 1206 can be implemented, for example, in a distributed system where each compute node includes multiple GPUs. Combined model and data parallelism 1206 can also be referred to as hybrid parallelism. Each node can have a complete instance of the model, with separate GPUs within each node being used to train different parts of the model. Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques to reduce the overhead of distributed training, including techniques for enabling high-bandwidth GPU-to-GPU data transfers and accelerated remote data synchronization. Pipeline parallelism is a variant of combined model and data parallelism 1206, in which different nodes contain less than the entire model, but more than a single layer of the model. In pipeline parallelism, different groups of layers or sub-models are distributed across different processing nodes. Another variant is expert parallelism, which routes requests to specific experts within the model to different GPUs. For example, expert parallelism can be used for MoE transformer models.

[0203] Figure 12B 1 is a block diagram illustrating a programmable network interface 1210 and a data processing unit. The programmable network interface 1210 is a programmable network engine that can be used to accelerate network-based computing tasks within a distributed environment. The programmable network interface 1210 can be coupled to a host system via a host interface 1270. The programmable network interface 1210 can be used to accelerate network or storage operations for a CPU or GPU of the host system. The host system can be, for example, a node of a distributed learning system for performing distributed training, such as Figure 12A The host system can also be a data center node within a data center.

[0204] In one embodiment, access to a remote storage device containing model data may be accelerated by the programmable network interface 1210. For example, the programmable network interface 1210 may be configured to present the remote storage device as a local storage device of the host system. The programmable network interface 1210 may also accelerate remote direct memory access (RDMA) operations performed between a GPU of the host system and a GPU of the remote system. In one embodiment, the programmable network interface 1210 may enable storage functions such as, but not limited to, NVME-oF. The programmable network interface 1210 may also accelerate encryption, data integrity, compression, and other operations for the remote storage device on behalf of the host system, thereby allowing the remote storage device to approach the latency of a storage device directly attached to the host system.

[0205] Programmable network interface 1210 can also perform resource allocation and management on behalf of the host system. Storage security operations can be migrated to programmable network interface 1210 and performed in conjunction with the allocation and management of remote storage resources. Network-based operations for managing access to remote storage devices that would otherwise be performed by the host system's processor can instead be performed by programmable network interface 1210.

[0206] In one embodiment, network and / or data security operations can be migrated from the host system to the programmable network interface 1210. Data center security policies for data center nodes can be handled by the programmable network interface 1210 rather than by the host system's processor. For example, the programmable network interface 1210 can detect and mitigate attempted network-based attacks (e.g., DDoS) on the host system, thereby preventing the attack from compromising the availability of the host system.

[0207] Programmable network interface 1210 may include a system on chip (SoC 1220) that executes an operating system via multiple processor cores 1222. Processor core 1222 may include a general-purpose processor (e.g., CPU) core. In one embodiment, processor core 1222 may also include one or more GPU cores. SoC 1220 may execute instructions stored in memory device 1240. Storage device 1250 may store local operating system data. Storage device 1250 and memory device 1240 may also be used to cache remote data for a host system. Network ports 1260A-1260B enable connection to a network or fabric and facilitate network access for SoC 1220 and for the host system via host interface 1270. Programmable network interface 1210 may also include an I / O interface 1275, such as a USB interface. I / O interface 1275 may be used to couple external devices to programmable network interface 1210 or as a debug interface. Programmable network interface 1210 also includes a management interface 1230 that enables software on a host device to manage and configure programmable network interface 1210 and / or SoC 1220. In one embodiment, programmable network interface 1210 may also include one or more accelerators or GPUs 1245 to accept migration of parallel computing tasks from SoC 1220, a host system, or a remote system coupled via network ports 1260A-1260B. Example Machine Learning Applications

[0208] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. The application range of computer vision is from reproducing human visual capabilities (such as recognizing faces) to creating new categories of visual capabilities. For example, a computer vision application can be configured to identify sound waves from vibrations induced by objects visible in a video. Parallel processor-accelerated machine learning enables computer vision applications to be trained using significantly larger training data sets than previously feasible, and enables inference systems to be deployed using low-power parallel processors.

[0209] Parallel processor-accelerated machine learning has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define appropriate responses to specific training inputs. The parallel processors described in this article enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0210] Deep neural networks accelerated by parallel processors have enabled machine learning approaches for automatic speech recognition (ASR). ASR involves creating a function that computes the most likely speech sequence given a sequence of input sounds. Accelerated machine learning using deep neural networks has enabled an alternative to the hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0211] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. The automated learning process can utilize statistical inference algorithms to generate models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0212] The parallel processing platform for machine learning can be divided into a training platform and a deployment platform. The training platform is generally highly parallel and includes optimizations for accelerating multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include Figure 7 GPGPU 700 and Figure 8 In contrast, deployed machine learning platforms typically include lower-powered parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0213] Furthermore, machine learning techniques can be applied to accelerate or enhance graphics processing activities. For example, a machine learning model can be trained to recognize the output generated by a GPU-accelerated application and generate a magnified version of that output. Such techniques can be applied to accelerate the generation of high-resolution images for gaming applications. Various other graphics pipeline activities can benefit from the use of machine learning. For example, a machine learning model can be trained to perform tessellation operations on geometric data to increase the complexity of the geometric model, thereby allowing more detailed geometry to be automatically generated from relatively low-detail geometry.

[0214] Figure 13 The diagram illustrates an exemplary inference system-on-chip (SOC) 1300 suitable for performing inference using a trained model. The SOC 1300 may integrate processing components, including a media processor 1302, a vision processor 1304, a GPGPU 1306, and a multi-core processor 1308. The GPGPU 1306 may be a GPGPU as described herein, such as GPGPU 700, and the multi-core processor 1308 may be a multi-core processor as described herein, such as multi-core processors 405-406. The SOC 1300 may additionally include on-chip memory 1305 that may enable a shared on-chip data pool accessible by each of the processing components. The processing components may be optimized for low-power operation to enable deployment of various machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of the SOC 1300 may be used as part of a master control system for an autonomous vehicle. Where the SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with relevant functional safety standards of the deployment jurisdiction.

[0215] During operation, the media processor 1302 and the vision processor 1304 can work together to accelerate computer vision operations. The media processor 1302 can enable low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1305. The vision processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video to prepare them for processing using the trained image recognition model. For example, the vision processor 1304 can accelerate convolution operations for a CNN used to perform image recognition on high-resolution video data, while the back-end model calculations are performed by the GPGPU 1306.

[0216] The multi-core processor 1308 may include control logic for facilitating the sequencing and synchronization of data transfers and shared memory operations performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also function as an application processor for executing software applications capable of utilizing the inference computing capabilities of the GPGPU 1306. For example, at least a portion of navigation and steering logic may be implemented in software executing on the multi-core processor 1308. Such software may directly issue computational workloads to the GPGPU 1306, or computational workloads may be issued to the multi-core processor 1308, which may offload at least a portion of those operations to the GPGPU 1306.

[0217] GPGPU 1306 may include a computing cluster, such as low-power configuration processing clusters 706A-706H within GPGPU 700. The computing cluster within GPGPU 1306 may support instructions specifically optimized to perform inference computations on trained neural networks. For example, GPGPU 1306 may support instructions for performing low-precision computations such as 8-bit and 4-bit integer vector operations. Additional System Overview

[0218] Figure 14 is a block diagram of processing system 1400 . Figure 14 Elements having the same or similar names as elements of any other figures herein describe the same elements as in the other figures, can operate or function in a manner similar to that in the other figures, may include the same components, and may be linked to other entities such as, but not limited to, those described elsewhere herein. Processing system 1400 can be used in: a single-processor desktop computer system, a multi-processor workstation system, or a server system having (one or more) processors 1402 or processor cores 1407. Processing system 1400 can be a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device, such as for use in an Internet-of-things (IoT) device having wired or wireless connectivity to a local or wide area network.

[0219] The processing system 1400 may be a system having Figure 1 For example, in different configurations, the processor(s) 1402 or processor core 1407 may be associated with the components of the processing system corresponding to those components. Figure 1 The graphics processor(s) 1408 may correspond to the processor(s) 102 of FIG. Figure 1The external graphics processor 1418 may be Figure 1 One of the (one or more) plug-in devices 120.

[0220] The processing system 1400 may include, be coupled with, or be integrated into: a server-based gaming platform; a gaming console, including a gaming and media console; a mobile gaming console, a handheld gaming console, or an online gaming console. The processing system 1400 may be part of a mobile phone, a smartphone, a tablet computing device, or a mobile internet-connected device, such as a laptop with low internal storage capacity. The processing system 1400 may also include, be coupled with, or be integrated into: a wearable device, such as a smartwatch wearable device; smart glasses or clothing that is enhanced with augmented reality (AR) or virtual reality (VR) features to provide visual, audio, or tactile output to supplement the real-world visual, audio, or tactile experience or otherwise provide text, audio, graphics, video, holographic images or video, or tactile feedback. The processing system 1400 may include, be part of, or be integrated into a television or set-top box device. The processing system 1400 may include, be coupled to, or be integrated into a self-driving vehicle, such as a bus, a tractor-trailer, an automobile, an electric motor or electric power cycle, an airplane, or a glider (or any combination thereof). The self-driving vehicle may use the processing system 1400 to process the environment sensed around the vehicle.

[0221] Processor(s) 1402 may include one or more instances of processor core(s) 1407 to process instructions that, when executed, perform operations for system and user software. At least one of processor core(s) 1407 may be configured to process a specific instruction set 1409. Instruction set 1409 may facilitate computations using complex instruction set computing (CISC), reduced instruction set computing (RISC), or very long instruction words (VLIW). In one embodiment, one of processor core(s) 1407 may process a different instruction set 1409, which may include instructions for facilitating emulation of other instruction sets. Processor core(s) 1407 may also include other processing devices, such as a digital signal processor (DSP).

[0222] Processor(s) 1402 may include cache memory 1404. Depending on the architecture, processor(s) 1402 may have a single internal cache or multiple levels of internal cache. In some embodiments, cache memory is shared between various components of processor(s) 1402. In some embodiments, processor(s) 1402 also uses an external cache (e.g., a Level 3 (L3) cache or a Last Level Cache (LLC)) (not shown), which may be shared between processor cores 1407 using known cache coherence techniques. A register file 1406 may additionally be included in processor(s) 1402 and may include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of processor(s) 1402.

[0223] The processor(s) 1402 may be coupled to one or more interface buses 1410 to transmit communication signals, such as address, data, or control signals, between the processor(s) 1402 and other components in the processing system 1400. In one of these embodiments, the interface bus(es) 1410 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. For example, the processor(s) 1402 may include a memory controller 1416 and a platform controller hub 1430. The memory controller 1416 facilitates communication between memory devices and other components of the processing system 1400, while the platform controller hub 1430 provides connections to I / O devices via a local I / O bus.

[0224] Memory device 1420 may be a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, a flash memory device, a phase-change memory device, or some other memory device with suitable performance to function as process memory. For example, memory device 1420 may operate as system memory for processing system 1400 to store data 1422 and instructions 1421 for use when processor(s) 1402 execute applications or processes. Memory controller 1416 may optionally be coupled to an external graphics processor 1418, which may communicate with graphics processor(s) 1408 in processor(s) 1402 to perform graphics and media operations. In some embodiments, graphics operations, media operations, and / or compute operations may be assisted by accelerator 1412, which is a coprocessor that may be configured to perform a specialized set of graphics, media, or compute operations. For example, the accelerator 1412 may be a matrix multiplication accelerator for optimizing machine learning or computational operations. The accelerator 1412 may be a ray tracing accelerator that can be used to perform ray tracing operations in collaboration with the graphics processor(s) 1408. The accelerator 1412 may also be an AI accelerator or NPU to accelerate neural network training or inference operations. In one embodiment, an external accelerator 1419 may be used in place of the accelerator 1412 or in collaboration with the accelerator 1412. The accelerator 1412 and / or the external accelerator 1419 may have the same Figure 1 The functionality of the accelerator(s) 130 is similar to functionality.

[0225] A display device 1411 may be provided and connected to the processor(s) 1402. The display device 1411 may be one or more of an internal display device, such as in a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., a display port, etc.). The display device 1411 may be a head mounted display (HMD), such as a stereoscopic display device used in VR or AR applications.

[0226] The platform controller hub 1430 can enable peripheral devices to connect to the memory device 1420 and (one or more) processors 1402 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 1446, a network controller 1434, a firmware interface 1428, a wireless transceiver 1426, a touch sensor 1425, a data storage device 1424 (e.g., non-volatile memory, volatile memory, hard drive, flash memory, NAND, 3D NAND, 3D Xpoint / Optane, etc.). The data storage device 1424 can be connected via a storage interface (e.g., SATA) or via a peripheral bus (e.g., PCI, PCI Express). The touch sensor 1425 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 1426 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, 5G, or Long-Term Evolution (LTE) transceiver. The firmware interface 1428 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). A network controller 1434 can enable network connectivity to a wired network. In some embodiments, a high-performance network controller (not shown) is coupled to the interface bus(es) 1410. An audio controller 1446 can be a multi-channel high-definition audio controller. In some of these embodiments, the processing system 1400 includes an optional legacy I / O controller 1440 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. The platform controller hub 1430 can also be connected to one or more Universal Serial Bus (USB) controllers 1442 to connect to input devices, such as a keyboard and mouse 1443 combination, a camera 1444, or other USB input devices.

[0227] 1402. It will be appreciated that the processing system 1400 shown is exemplary and non-limiting, as other types of data processing systems configured in different manners may also be used. For example, instances of the memory controller 1416 and the platform controller hub 1430 may be integrated into a discrete external graphics processor, such as the external graphics processor 1418. The platform controller hub 1430 and / or the memory controller 1416 may be external to the processor(s) 1402. For example, the memory controller 1416 and the platform controller hub 1430 may be external to the processing system 1400 and configured as a memory controller hub and a peripheral controller hub within a system chipset that communicates with the processor(s) 1402.

[0228] For example, a circuit board ("sled") can be used on which components (such as a CPU, memory, and other components) are placed, and on which components (such as a CPU, memory, and other components) are designed to achieve improved thermal performance. Processing components such as a processor can be located on the top side of the sled, while nearby memory such as DIMMs is located on the bottom side of the sled. As a result of the enhanced airflow provided by this design, components can operate at higher frequencies and power levels than in typical systems, thereby improving performance. In addition, the sled is configured to blindly mate power and data communication cables in the rack, thereby enhancing their ability to be quickly removed, upgraded, reinstalled, and / or replaced. Similarly, the various components located on the sled (such as processors, accelerators, memory, and data storage drives) are configured to be easily upgraded due to their increased spacing from each other. In an illustrative embodiment, the components additionally include hardware authentication features for proving their authenticity.

[0229] The data center can utilize a single network architecture ("fabric") that supports multiple other network architectures, including Ethernet and omni-path. The sleds can be coupled to the switches via optical fiber, which provides higher bandwidth and lower latency than typical twisted pair cabling (e.g., Category 5, Category 5e, Category 6, Category 7, Category 8, etc.). Due to the high-bandwidth, low-latency interconnect and network architecture, the data center can, in use, centralize physically dispersed resources such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network and / or artificial intelligence accelerators, etc.), and data storage drives and provide them to computing resources (e.g., processors) as needed, enabling the computing resources to access the centralized resources as if they were local.

[0230] A power supply or power source can provide voltage and / or current to the processing system 1400 or any component or system described herein. In one example, the power supply includes an AC to DC (alternating current to direct current) adapter for plugging into a wall outlet. Such AC power can be a renewable energy (e.g., solar) power source. In one example, the power source includes a DC power source, such as an external AC to DC converter. The power source or power supply can also include wireless charging hardware for charging by proximity to a charging field. The power source can include an internal battery, an AC supply, a motion-based power supply, a solar power supply, or a fuel cell source.

[0231] Figures 15A-15C Illustration of a computing system and graphics processor. Figures 15A-15C Elements having the same or similar names as elements of any other figures herein describe the same elements as those in the other figures, can operate or function in a similar manner as those in the other figures, may include the same components, and may be linked to other entities such as, but not limited to, those described elsewhere herein.

[0232] Figure 15A1402. FIGURE 15 is a block diagram of processor 1500, which may be a variant of one of processor(s) 1402 and may be used in place of one of those processors. Therefore, any feature disclosed herein in conjunction with processor 1500 also discloses the corresponding combination with processor(s) 1402, but is not limited thereto. Processor 1500 may have one or more processor cores 1502A-1502N, at least one memory controller 1514, and a graphics processor 1508. Graphics processor 1508 may be integrated within processor 1500, within a system chipset, or coupled via a system bus. Processor 1500 may include additional cores, up to and including additional core 1502N, represented by a dashed box. Each of processor cores 1502A-1502N includes one or more internal cache units 1504A-1504N. In some embodiments, each processor core 1502A-1502N also has access to one or more shared cache units 1506. The internal cache units 1504A-1504N and the shared cache unit(s) 1506 represent a cache memory hierarchy within the processor 1500. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, with the highest level of cache before external memory being classified as LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units (e.g., the shared cache unit(s) 1506 and the internal cache unit(s) 1504A-1504N).

[0233] The processor 1500 may also include one or more bus controller units 1516 and a system agent core 1510. The one or more bus controller units 1516 manage a collection of peripheral buses, such as one or more PCI buses or PCI Express buses. The one or more bus controller units 1516 may also manage one or more memory buses to various external memory devices (not shown). The system agent core 1510 provides management functions for the various processor components and may include at least one memory controller 1514.

[0234] For example, one or more of the processor cores 1502A-1502N may include support for simultaneous multi-threaded operations. The system agent core 1510 includes components for coordinating and operating the cores 1502A-1502N during multi-threaded processing. The system agent core 1510 may additionally include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 1502A-1502N and the graphics processor 1508.

[0235] Processor 1500 may additionally include a graphics processor 1508 for performing graphics processing operations. In some of these embodiments, graphics processor 1508 is coupled with one or more shared cache units 1506 and a system agent core 1510, which includes at least one memory controller 1514. System agent core 1510 may also include a display controller 1511 for driving graphics processor output to one or more coupled displays. Display controller 1511 may also be a separate module coupled to the graphics processor via at least one interconnect, or may be integrated within graphics processor 1508.

[0236] A ring-based or mesh-based interconnect 1512 may be used to couple the internal components of the processor 1500. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies (including those known in the art). In some of these embodiments having a ring-based or mesh-based interconnect 1512, the graphics processor 1508 is coupled to the ring-based or mesh-based interconnect 1512 via an I / O link 1513.

[0237] Exemplary I / O link 1513 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance memory module 1518, such as an embedded DRAM module (eDRAM) or a high-bandwidth memory (HBM) module. Optionally, when a DRAM memory system is also present, each of processor cores 1502A-1502N and graphics processor 1508 can use high-performance memory module 1518 as a unified memory and / or shared last-level cache. Optionally, one or more accelerators 1515 can also be included within processor 1500, including, for example, an NPU for accelerating certain neural network operations. The NPU can enable lower-power inference operations relative to the use of graphics processor 1508, or can operate in conjunction with graphics processor 1508 to achieve higher inference performance relative to graphics processor 1508 alone. In one embodiment, an NPU within one or more accelerators 1515 may include matrix or tensor acceleration logic and may be used to implement at least some of the computational operations described herein that may be implemented via graphics processor 1508 .

[0238] The processor cores 1502A-1502N may, for example, be homogeneous cores that execute the same instruction set architecture. Alternatively, the processor cores 1502A-1502N may be heterogeneous in terms of instruction set architecture (ISA), wherein one or more of the processor cores 1502A-1502N execute a first instruction set and at least one of the other cores executes a subset of the first instruction set or a different instruction set. The processor cores 1502A-1502N may be heterogeneous in terms of microarchitecture, wherein one or more cores having relatively high power consumption are coupled with one or more power cores having lower power consumption. As another example, the processor cores 1502A-1502N may be heterogeneous in terms of computing power. Furthermore, the processor 1500 may be implemented on one or more chips or chiplets, or as a SoC integrated circuit having the illustrated components in addition to other components. The SoC integrated circuit may be implemented using multiple chiplets.

[0239] Figure 15B is a block diagram of the hardware logic of the graphics processor core block 1519 according to some embodiments described herein. In some embodiments, Figure 15BElements having the same reference numerals (or names) as elements of any other figure herein may operate or function in a manner similar to that described elsewhere herein. In one embodiment, the graphics processor core block 1519 is an example of a partition of the graphics processor. The graphics processor core block 1519 may be included in Figure 15A 1508 or a discrete graphics processor, parallel processor, and / or compute accelerator. A graphics processor as described herein may include multiple graphics core blocks based on a target power and performance envelope. Each graphics processor core block 1519 may include a functional block 1530 coupled to multiple graphics cores 1521A-1521F, which may include modular blocks of fixed-function logic and general-purpose programmable logic. The graphics processor core block 1519 also includes a shared / cache memory 1536 accessible by all graphics cores 1521A-1521F, rasterizer logic 1537, and additional fixed-function logic 1538.

[0240] In some embodiments, functional block 1530 includes a geometry / fixed function pipeline 1531 that can be shared by all graphics cores in graphics processor core block 1519. In various embodiments, geometry / fixed function pipeline 1531 includes a 3D geometry pipeline, a video front-end unit, a thread generator, a global thread dispatcher, and a unified return buffer manager that manages the unified return buffer. In one embodiment, functional block 1530 also includes a graphics SoC interface 1532, a graphics microcontroller 1533, and a media pipeline 1534. Graphics SoC interface 1532 provides an interface between graphics processor core block 1519 and other core blocks within a graphics processor or computing accelerator SoC. Graphics microcontroller 1533 is a programmable subprocessor that can be configured to manage various functions of graphics processor core block 1519, including thread dispatching, scheduling, and preemption. Media pipeline 1534 includes media engine logic for facilitating the decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. The media pipeline 1534 implements media operations via requests to computational or sampling logic within the graphics cores 1521A-1521F. One or more pixel backends 1535 may also be included within the functional block 1530. The one or more pixel backends 1535 include buffer memory for storing pixel color values ​​and are capable of performing blending operations and lossless color compression on rendered pixel data.

[0241] In one embodiment, the graphics SoC interface 1532 enables the graphics processor core block 1519 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC or within a system host CPU coupled to the SoC via a peripheral interface. The graphics SoC interface 1532 also enables communication with off-chip memory hierarchy elements, such as shared last-level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. The graphics SoC interface 1532 can also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, and enable the use and / or implementation of global memory atomicity, which can be shared between the graphics processor core block 1519 and the CPU within the SoC. The graphics SoC interface 1532 can also implement power management controls for the graphics processor core block 1519 and enable interfaces between the clock domain of the graphics processor core block 1519 and other clock domains within the SoC. In one embodiment, graphics SoC interface 1532 enables receiving command buffers from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. Commands and instructions can be dispatched to media pipeline 1534 when media operations are to be performed, and can be dispatched to geometry and fixed function pipeline 1531 when graphics processing operations are to be performed. When compute operations are to be performed, compute dispatch logic can dispatch commands to graphics cores 1521A-1521F, thereby bypassing the geometry pipeline and media pipeline.

[0242] Graphics microcontroller 1533 can be configured to perform various scheduling and management tasks for graphics processor core block 1519. In one embodiment, graphics microcontroller 1533 can execute graphics workloads and / or compute workloads scheduled on the various vector engines 1522A-1522F, 1524A-1524F and matrix engines 1523A-1523F, 1525A-1525F within graphics cores 1521A-1521F. In this scheduling model, host software executing on a CPU core of the SoC that includes graphics processor core block 1519 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. Scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In one embodiment, the graphics microcontroller 1533 is also capable of facilitating a low power or idle state for the graphics processor core block 1519, thereby providing the graphics processor core block 1519 with the ability to save and restore registers within the graphics processor core block 1519 across low power state transitions independent of the operating system and / or graphics driver software on the system.

[0243] Graphics processor core block 1519 may have more or fewer graphics cores 1521A-1521F than those shown, up to a maximum of N modular graphics cores. For each set of N graphics cores, graphics processor core block 1519 may also include: shared / cache memory 1536, which may be configured as shared memory or cache memory; rasterizer logic 1537; and additional fixed-function logic 1538 for accelerating various graphics and compute processing operations.

[0244] Each graphics core 1521A-1521F includes a collection of execution resources that can be used to perform graphics operations, media operations, and compute operations in response to requests made by the graphics pipeline, media pipeline, or shader programs. Graphics cores 1521A-1521F include multiple vector engines 1522A-1522F, 1524A-1524F, matrix acceleration units 1523A-1523F, 1525A-1525D, cache / shared local memory (SLM), samplers 1526A-1526F, and ray tracing units 1527A-1527F.

[0245] The vector engines 1522A-1522F, 1524A-1524F are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logic operations to serve graphics operations, media operations, or compute operations (including graphics programs, media programs, or compute / GPGPU programs). The vector engines 1522A-1522F, 1524A-1524F can operate in SIMD execution mode, SIMT execution mode, or SIMT+SIMD execution mode, with variable vector widths. The matrix acceleration units 1523A-1523F, 1525A-1525D include matrix-matrix and matrix-vector acceleration logic that improves the performance of matrix operations, particularly low-precision and mixed-precision (e.g., INT8, FP16, BF16, FP8, FP4) matrix operations for machine learning. In one embodiment, the matrix acceleration units 1523A-1523F, 1525A-1525D support microscaling (MX) format. In one embodiment, each of the matrix acceleration units 1523A-1523F, 1525A-1525D includes one or more systolic arrays of processing elements capable of performing concurrent matrix multiplication or dot product operations on matrix elements.

[0246] Samplers 1526A-1526F can read media data or texture data into memory and can sample the data in different ways based on the configured sampler state and the texture / media format being read. Threads executing on vector engines 1522A-1522F, 1524A-1524F or matrix acceleration units 1523A-1523F, 1525A-1525D can utilize caches / SLMs 1528A-1528F within each of graphics cores 1521A-1521F. Caches / SLMs 1528A-1528F can be configured as a pool of cache memory or shared memory local to each of the corresponding graphics cores 1521A-1521F. Ray tracing units 1527A-1527F within graphics cores 1521A-1521F include ray traversal / intersection circuitry for performing ray traversals using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the BVH volumes. In one embodiment, ray tracing units 1527A-1527F include circuitry for performing depth testing and culling (e.g., using a depth buffer or similar arrangement). In one implementation, ray tracing units 1527A-1527F perform traversal and intersection operations in conjunction with image denoising, at least in part of which may be performed using associated matrix acceleration units 1523A-1523F, 1525A-1525D.

[0247] Figure 15C 15 is a block diagram of a general-purpose graphics processor unit (GPGPU 1570) that can be configured as a graphics processor (e.g., graphics processor 1508) and / or a computing accelerator, according to embodiments described herein. GPGPU 1570 can be interconnected with a host processor (e.g., one or more CPUs 1546) and memories 1571 and 1572 via one or more system and / or memory buses. Memory 1571 can be system memory that can be shared with one or more CPUs 1546, while memory 1572 is device memory dedicated to GPGPU 1570. For example, components within GPGPU 1570 and memory 1572 can be mapped to memory addresses accessible to one or more CPUs 1546. Access to memories 1571 and 1572 can be facilitated via memory controller 1568. Memory controller 1568 can include an internal direct memory access (DMA) controller 1569, or can include logic for performing operations that would otherwise be performed by a DMA controller. In one embodiment, at least one of the one or more CPUs 1546 may include one or more accelerators 1545, including but not limited to a neural network accelerator.

[0248] GPGPU 1570 includes multiple global cache memories, including an L2 cache 1553, an L1 cache 1554, an instruction cache 1555, and a shared memory 1556. At least a portion of the shared memory 1556 may also be partitioned as cache memory. GPGPU 1570 also includes multiple compute units 1560A-1560N. Each compute unit 1560A-1560N includes a set of vector registers 1561, a set of scalar registers 1562, a set of vector logic units 1563, a set of scalar logic units 1564, and a scheduler 1584. Compute units 1560A-1560N may also include a local shared memory 1565 and a local cache memory 1566. Compute units 1560A-1560N may be coupled with a constant cache 1567 that can be used to store constant data, which is data that will not change during the execution of a kernel or shader program executed on GPGPU 1570. Constant cache 1567 may be a scalar data cache, and the cached data may be directly fetched into scalar registers 1562. In one embodiment, compute units 1560A-1560N additionally include at least one matrix unit 1580 and at least one ray tracing unit (RT unit 1582), wherein at least one matrix unit 1580 is used to accelerate matrix, tensor, or artificial intelligence operations, and at least one ray tracing unit (RT unit 1582) is used to accelerate ray tracing operations. At least one matrix unit 1580 and RT unit 1582 may include functionality similar to other matrix / tensor accelerators and ray tracing accelerators described herein.

[0249] During operation, one or more CPUs 1546 may write commands to registers in GPGPU 1570 or to memory in GPGPU 1570 that has been mapped into an accessible address space. Command processor 1557 may read commands from registers or memory and determine how those commands will be processed within GPGPU 1570. Threads may then be dispatched to compute units 1560A-1560N using thread dispatcher 1558 to execute those commands. Each compute unit 1560A-1560N may execute threads independently of other compute units. Additionally, each compute unit 1560A-1560N may be independently configured for conditional computation and may conditionally output computation results to memory. Command processor 1557 may interrupt one or more CPUs 1546 when a submitted command is completed.

[0250] Figure 161 is a block diagram of a graphics processor 1600, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores or other semiconductor devices, such as, but not limited to, memory devices or network interfaces. Elements of graphics processor 1600 having the same or similar names as elements in any other figures herein describe the same elements as in the other figures, may operate or function in a similar manner as in the other figures, may include the same components, and may be linked to other entities such as those described elsewhere herein, but not limited thereto. For example, graphics processor 1600 may be a variant of graphics processor 1508 and may be used in place of graphics processor 1508, and vice versa. The graphics processor may communicate via a memory-mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. Graphics processor 1600 may include a memory interface 1614 for accessing local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0251] Graphics processor 1600 may include a display controller 1602 for driving display output data to a display device 1618. Display controller 1602 includes hardware for compositing one or more overlay planes and multiple layers of video or user interface elements for the display. Display device 1618 may be an internal or external display device. In one embodiment, display device 1618 is a head-mounted display device, such as a VR display device or an AR display device. The graphics processor 1600 may include a video codec engine 1606 for encoding media into one or more media coding formats, decoding media from one or more media coding formats, or transcoding media between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC, H.265 / HEVC, Alliance for Open Media (AOMedia) VP8, VP9), and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG) formats).

[0252] Graphics processor 1600 may include a block image transfer (BLIT) engine 1603 for performing two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. Alternatively, 2D graphics operations may be performed using one or more components of a graphics processing engine (GPE 1610). GPE 1610 may include a 3D pipeline 1612 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 1612 includes programmable and fixed-function elements that perform various tasks within the element and / or spawn execution threads to a 3D / media subsystem 1615. While 3D pipeline 1612 may be used to perform media operations, GPE 1610 may also include a media pipeline 1616 specifically for performing media operations, such as image or video decoding, encoding, post-processing, and enhancement. The media pipeline 1616 may include fixed-function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of, or on behalf of, the video codec engine 1606. The media pipeline 1616 may additionally include a thread generation unit for generating threads for execution on the 3D / media subsystem 1615. The generated threads perform calculations for the media operations on one or more graphics execution units included in the 3D / media subsystem 1615.

[0253] Figure 17A The graphics processor 1720 is shown in FIG. Figure 161600 and may be used in place of graphics processor 1600, and vice versa. Therefore, any feature disclosed herein in conjunction with graphics processor 1600 also discloses the corresponding combination with graphics processor 1720, but is not limited thereto. According to the embodiments described herein, graphics processor 1720 has a sliced ​​architecture. Graphics processor 1720 may include a graphics processing engine cluster 1722 having multiple graphics processing engines within multiple graphics engine slices. Each graphics engine slice 1710A-1710D may be interconnected via a set of slice interconnects 1723A-1723F. Each graphics engine slice 1710A-1710D may also be connected to a memory module or memory device 1726A-1726D via a memory interconnect 1725A-1725D. Memory devices 1726A-1726D may use any graphics memory technology. For example, the memory devices 1726A-1726D may be graphics double data rate (GDDR) memory. The memory devices 1726A-1726D may be high bandwidth memory (HBM) modules that may be on the die with their corresponding graphics engine slices 1710A-1710D. The memory devices 1726A-1726D may be stacked memory devices that may be stacked on top of their corresponding graphics engine slices 1710A-1710D. Each graphics engine slice 1710A-1710D and associated memory devices 1726A-1726D may reside on separate chiplets that are bonded to a base die or base substrate, as in Figures 25A-25B As described in further detail in .

[0254] Graphics processor 1720 may be configured with a non-uniform memory access (NUMA) system in which memory devices 1726A-1726D are coupled to associated graphics engine slices 1710A-1710D. A given memory device may be accessed by a different slice than the graphics engine slice to which it is directly connected. However, access latency to memory devices 1726A-1726D may be minimized when accessing the local slice. In one embodiment, a cache coherent NUMA (ccNUMA) system is enabled that uses slice interconnects 1723A-1723F to enable communication between cache controllers within graphics engine slices 1710A-1710D to maintain consistent memory mirroring when more than one cache stores the same memory location.

[0255] Graphics processing engine cluster 1722 may be connected to an interconnect fabric 1724, which may interconnect on-chip or on-package structures. In one embodiment, interconnect fabric 1724 includes a network processor, a network on a chip (NoC), or another switching processor that enables interconnect fabric 1724 to function as a packet-switched interconnect fabric for exchanging data packets between components of graphics processor 1720. Interconnect fabric 1724 may enable communication between graphics engine slices 1710A-1710D and components such as video codec engine 1706 and one or more replication engines 1704. One or more copy engines 1704 may be used to move data out of memory devices 1726A-1726D and memory external to graphics processor 1720 (e.g., system memory), to memory devices 1726A-1726D and memory external to graphics processor 1720 (e.g., system memory), and between memory devices 1726A-1726D and memory external to graphics processor 1720 (e.g., system memory). Interconnect fabric 1724 may also be used to interconnect graphics engine slices 1710A-1710D. Graphics processor 1720 may optionally include a display controller 1702 to enable connection to display device 1718. The graphics processor may also be configured as a graphics or computing accelerator. In an accelerator configuration, display controller 1702 and display device 1718 may be omitted.

[0256] The graphics processor 1720 can be connected to the host system via a host interface 1728. The host interface 1728 can enable communication between the graphics processor 1720, system memory, and / or other system components. The host interface 1728 can be, for example, a PCI Express bus or another type of host system interface. For example, the host interface 1728 can be an NVLink, NVSwitch, or UALink switching interface. The host interface 1728 and the interconnect structure 1724 can cooperate to enable multiple instances of the graphics processor 1720 to act as a single logical device. The cooperation between the host interface 1728 and the interconnect structure 1724 can also enable each graphics engine slice 1710A-1710D to be presented to the host system as a different logical graphics device.

[0257] Figure 17B FIGURE 17 illustrates a computing accelerator 1730 according to embodiments described herein. The computing accelerator 1730 may include Figure 17BThe compute engine cluster 1732 may include a collection of compute engine slices 1740A-1740D, each of which includes execution logic optimized for parallel or vector-based general-purpose compute operations. In one embodiment, the compute accelerator 1730 may be configured as an AI accelerator or an NPU. In such embodiments, the execution logic of the compute engine slices 1740A-1740D may be primarily focused on matrix or tensor operations and include the tensor cores or matrix engines described herein. The compute engine slices 1740A-1740D may not include fixed-function graphics processing logic, but in some embodiments, one or more of the compute engine slices 1740A-1740D may include logic for performing media acceleration. The compute engine slices 1740A-1740D may be connected to memory devices 1726A-1726D via memory interconnects 1725A-1725D. The memory devices 1726A-1726D and memory interconnects 1725A-1725D may be similar technologies as in the graphics processor 1720, or may be different technologies. The compute engine slices 1740A-1740D may also be interconnected via a set of slice interconnects 1723A-1723F, and may be connected to and / or interconnected by the interconnect structure 1724. In one embodiment, the compute accelerator 1730 includes a large L3 cache 1736 that may be configured as a device-wide cache. The compute accelerator 1730 may also be configured as a processor-wide cache. Figure 17B The graphics processor 1720 is similarly connected to a host processor and memory via a host interface 1728 .

[0258] Computing accelerator 1730 may also include an integrated network interface 1742. In one embodiment, integrated network interface 1742 includes a network processor and controller logic that enables computing engine cluster 1732 to communicate via physical layer interconnect 1744 without requiring data to traverse the host system's memory. In one embodiment, one of computing engine slices 1740A-1740D is replaced by network processor logic, and data to be transmitted or received via physical layer interconnect 1744 can be transmitted directly to or from memory devices 1726A-1726D. Multiple instances of computing accelerator 1730 can be combined into a single logical device via physical layer interconnect 1744. Alternatively, each computing engine slice 1740A-1740D can be presented as a different network-accessible computing accelerator device. Graphics processing resources

[0259] Figures 18A-18CIllustration of execution logic including an array of processing elements employed in a graphics processor according to embodiments described herein. Figure 18A Illustrated is a graphics core cluster according to an embodiment. Figure 18B Illustrated is a vector engine of a graphics core according to an embodiment. Figure 18C Illustrated is a matrix engine of a graphics core according to an embodiment. Figures 18A-18C Elements having the same reference numerals as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto. For example, Figures 18A-18C The components can be Figure 15B In one embodiment, Figures 18A-18C The components have Figure 15A Graphics processor 1508 or Figure 15C The GPGPU 1570 is an equivalent component with similar functionality.

[0260] like Figure 18A As shown in FIG, in one embodiment, graphics core cluster 1800 includes graphics processor core block 1519, which may include any number of graphics cores (e.g., graphics core 1815A, graphics core 1815B, through graphics core 1815N). Multiple instances of graphics processor core block 1519 may be included. In one embodiment, the elements of graphics cores 1815A-1815N have the same Figure 15B In one embodiment, graphics cores 1815A-1815N each include circuitry including, but not limited to, vector engines 1802A-1802N, matrix engines 1803A-1803N, memory load / store units 1804A-1804N, instruction caches 1805A-1805N, data caches / shared local memories 1806A-1806N, ray tracing units 1808A-1808N, and samplers 1810A-1810N. The circuitry of graphics cores 1815A-1815N may additionally include fixed-function logic 1812A-1812N. The number of vector engines 1802A-1802N and matrix engines 1803A-1803N within a design's graphics cores 1815A-1815N may vary based on the workload, performance, and power targets for the design.

[0261] Referring to graphics core 1815A, vector engine 1802A and matrix engine 1803A can be configured to perform parallel computations on data in various integer and floating-point data formats based on instructions associated with a shader program. Each vector engine 1802A and matrix engine 1803A can act as a programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. Vector engine 1802A and matrix engine 1803A support processing variable-width vectors in various SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32. Input data elements can be stored in registers as packed data types, and vector engine 1802A and matrix engine 1803A can process each element based on its data size. For example, when operating on a 256-bit wide vector, the bits of the vector are stored in registers, and the vector is processed as four separate 64-bit packed data elements (quad-word (QW) size data elements), eight separate 32-bit packed data elements (double-word (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible. In one embodiment, the vector engine 1802A and the matrix engine 1803A can also be configured to perform SIMT operations on various sizes of cell groups and thread groups (e.g., 8, 16, or 32 threads).

[0262] Continuing with the graphics core 1815A, the memory load / store unit 1804A services memory access requests issued by the vector engine 1802A, the matrix engine 1803A, and / or other components of the graphics core 1815A that have access to memory. The memory access request may be processed by the memory load / store unit 1804A to load or store the requested data into a cache or memory, or from a cache or memory into a register file associated with the vector engine 1802A and / or the matrix engine 1803A. The memory load / store unit 1804A may also perform prefetch operations. Also referring to Figure 19In one embodiment, the memory load / store unit 1804A is configured to provide SIMT scatter / gather prefetches or block prefetches for data stored in memory 1910, from memory local to other slices via the slice interconnect 1908, or from system memory. Prefetches can be performed for a specific L1 cache (e.g., data cache / shared local memory 1806A), the L2 cache 1904, or the L3 cache 1906. In one embodiment, a prefetch to the L3 cache 1906 automatically causes the data to be stored in the L2 cache 1904.

[0263] Instruction cache 1805A stores instructions to be executed by graphics core 1815A. In one embodiment, graphics core 1815A also includes instruction fetch and prefetch circuitry that fetches or prefetches instructions into instruction cache 1805A. Graphics core 1815A also includes instruction decode logic for decoding instructions within instruction cache 1805A. Data cache / shared local memory 1806A can be configured as a data cache managed by a cache controller that implements a cache replacement policy and / or configured as explicitly managed shared memory. Ray tracing unit 1808A includes circuitry for accelerating ray tracing operations. Sampler 1810A provides texture sampling for 3D operations and media sampling for media operations. Fixed function logic 1812A includes fixed function circuitry that is shared between instances of vector engine 1802A and matrix engine 1803A. Graphics cores 1815B-1815N can operate in a manner similar to graphics core 1815A.

[0264] The functions of the instruction caches 1805A-1805N, data cache / shared local memory 1806A-1806N, ray tracing units 1808A-1808N, samplers 1810A-1812N, and fixed function logic 1812A-1812N correspond to the equivalent functions in the graphics processor architecture described herein. For example, the instruction caches 1805A-1805N can be used in conjunction with Figure 15C The data cache / shared local memory 1806A-1806N, ray tracing units 1808A-1808N and samplers 1810A-1812N can operate in a similar manner to the instruction cache 1555 of FIG. Figure 15B The fixed function logic 1812A-1812N may include: Figure 15B In one embodiment, ray tracing units 1808A-1808N include components for performing the ray tracing operations performed by Figure 3 The ray tracing core 372 performs circuitry for ray tracing acceleration operations.

[0265] like Figure 18B As shown in FIG, in one embodiment, vector engine 1802 includes an instruction fetch unit 1837, a general register file (GRF) 1824, an architectural register file (ARF) 1826, a thread arbiter 1822, an issue unit 1830, a branch unit 1832, a SIMD FPU 1834, and, in one embodiment, a SIMD ALU 1835. GRF 1824 and ARF 1826 comprise a set of general register files and architectural register files associated with each hardware thread that can be active in vector engine 1802. In one embodiment, per-thread architectural state is maintained in ARF 1826, while data used during thread execution is stored in GRF 1824. The execution state of each thread, including the instruction pointer for each thread, can be stored in thread-specific registers in ARF 1826. Register renaming can be used to dynamically assign registers to hardware threads.

[0266] In one embodiment, vector engine 1802 has an architecture that is a combination of simultaneous multi-threading (SMT) and fine-grained interleaved multi-threading (IMT). This architecture has a modular configuration that can be fine-tuned at design time based on the target number of simultaneous threads and the number of registers per graphics core, where graphics core resources are divided across the logic used to execute multiple simultaneous threads. The number of logical threads that can be executed by vector engine 1802 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

[0267] In one embodiment, vector engine 1802 can collaboratively issue multiple instructions, each of which can be different instructions. Thread arbiter 1822 can dispatch instructions to one of issue unit 1830, branch unit 1832, or SIMD FPU 1834 for execution. Each execution thread can access 128 general-purpose registers within GRF 1824, each of which can store 32 bytes accessible as a variable-width vector with 32-byte data elements. In one embodiment, each thread has access to 4 kilobytes within GRF 1824, but embodiments are not limited thereto, and more or fewer register resources may be provided in other embodiments. In one embodiment, vector engine 1802 is partitioned into seven hardware threads that can independently execute computational operations, but the number of threads per vector engine 1802 may vary depending on the embodiment. For example, in one embodiment, a maximum of 16 hardware threads are supported. In an embodiment where seven threads have access to 4 kilobytes, GRF 1824 can store a total of 28 kilobytes. With 16 threads accessing 4 kilobytes, a total of 64 kilobytes can be stored in GRF 1824. Flexible addressing modes allow registers to be addressed together, effectively creating wider registers or representing strided rectangular block data structures.

[0268] In one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched via "send" instructions executed by message passing send unit 1830. In one embodiment, branch instructions are dispatched to branch unit 1832 to facilitate SIMD scatter and eventual convergence.

[0269] In one embodiment, the SIMD FPU 1834 of the vector engine 1802 performs floating-point operations. In one embodiment, the SIMD FPU 1834 also supports integer computations. In one embodiment, the SIMD FPU 1834 can perform up to M 32-bit floating-point (or integer) operations, or up to 2M 16-bit integer or 16-bit floating-point operations. In one embodiment, at least one of the FPUs provides extended math capabilities that support high-throughput transcendental math functions and double-precision 64-bit floating-point. In some embodiments, a SIMD ALU 1835 configured to perform 8-bit integer operations is also present and can be specifically optimized to perform operations associated with machine learning calculations. In one embodiment, the SIMD ALU 1835 is replaced by a SIMD ALU 1834 that can be configured to perform both integer and floating-point operations. In one embodiment, the SIMD FPU 1834 and the SIMD ALU 1835 can be configured to execute SIMT programs. In one embodiment, combined SIMD+SIMT operations are supported.

[0270] In one embodiment, an array of multiple instances of vector engine 1802 can be instantiated within a graphics core. For scalability, product architects can choose the exact number of vector engines grouped per graphics core. In one embodiment, vector engine 1802 can execute instructions across multiple execution lanes. In further embodiments, each thread executing on vector engine 1802 executes on a different lane.

[0271] like Figure 18C As shown in , in one embodiment, the matrix engine 1803 includes an array of processing elements configured to perform tensor operations, including vector / matrix operations and matrix / matrix operations, such as but not limited to matrix multiplication and / or dot product operations. The matrix engine 1803 can be configured using M rows and N columns of processing elements 1852AA-1852MN, and the processing elements PE 1852AA-PE 1852MN include multipliers and adder circuits organized in a pipelined manner. In one embodiment, the processing elements 1852AA-1852MN form a physical pipeline stage of an N-wide and M-deep systolic array, which can be used to perform vector / matrix operations or matrix / matrix operations in a data-parallel manner, including matrix multiplication, fused multiply-add, dot product or other general matrix-matrix multiplication (GEMM) operations. In one embodiment, the matrix engine 1803 supports 16-bit and 8-bit floating-point operations, as well as 8-bit, 4-bit, 2-bit and binary integer operations. The matrix engine 1803 can also be configured to accelerate specific machine learning operations. In such embodiments, the matrix engine 1803 may be configured with support for a bfloat (brain floating point) 16-bit floating point format, or a tensor float 32-bit floating point format (TF32), having a different number of mantissa bits and exponent bits relative to the Institute of Electrical and Electronics Engineers (IEEE) 754 format.

[0272] In one embodiment, during each cycle, each stage can add the result of the operation performed in that stage to the output of the previous stage. In other embodiments, after a set of computation cycles, the pattern of data movement between processing elements 1852AA-1852MN can vary based on the instruction or macro-operation being executed. For example, in one embodiment, partial sum loopback is enabled, and the processing elements can instead add the output of the current cycle to the output generated in the previous cycle. In one embodiment, the final stage of the systolic array can be configured with a loopback to the initial stage of the systolic array. In such embodiments, the number of physical pipeline stages can be decoupled from the number of logical pipeline stages supported by the matrix engine 1803. For example, if processing elements 1852AA-1852MN are configured as a systolic array of M physical stages, a loopback from stage M to the initial pipeline stage can enable processing elements 1852AA-1852MN to operate as a systolic array of, for example, 2M, 3M, 4M, and so on, logical pipeline stages.

[0273] In one embodiment, matrix engine 1803 includes memories 1841A-1841N, 1842A-1842M for storing input data in the form of row and column data for input matrix. Memories 1842A-1842M can be configured to store the row elements (A0-Am) of the first input matrix, and memories 1841A-1841N can be configured to store the column elements (B0-Bn) of the second input matrix. Row elements and column elements are provided as input to processing elements 1852AA-1852MN for processing. In one embodiment, the element rows and column elements of the input matrix can be stored in the systolic register file 1840 in the matrix engine 1803 before these elements are provided to memories 1841A-1841N, 1842A-1842M. In one embodiment, systolic register file 1840 is excluded and the registers (e.g., Figure 18B 1802 of the vector engine 1802) or other memory of the graphics core including the matrix engine 1803 (e.g., Figure 18A The results generated by the processing elements 1852AA-1852MN are then output to output buffers and / or written to register files (e.g., systolic register file 1840, GRF 1824, data cache / shared local memory 1806A-1806N) for further processing by other functional units of the graphics processor or for output to memory.

[0274] In some embodiments, matrix engine 1803 is configured to support input sparsity, where multiplication operations on sparse regions of input data can be bypassed by skipping multiplication operations on operands with zero values. In one embodiment, processing elements 1852AA-1852MN are configured to skip the execution of certain operations with zero-valued inputs. In one embodiment, sparsity within the input matrix can be detected, and operations with known zero output values ​​can be bypassed before being submitted to processing elements 1852AA-1852MN. Loading zero-valued operands into processing elements can be bypassed, and processing elements 1852AA-1852MN can be configured to perform multiplication on non-zero-valued input elements. Matrix engine 1803 can also be configured to support output sparsity, allowing operations with predetermined zero results to be bypassed. In one embodiment, metadata is provided to processing elements 1852AA-1852MN regarding input sparsity and / or output sparsity to indicate which processing elements and / or data paths will be active during a given processing cycle.

[0275] In one embodiment, the matrix engine 1803 includes hardware for enabling operations on sparse data with a compressed representation of a sparse matrix that stores non-zero values ​​and metadata identifying the location of the non-zero values ​​within the matrix. Exemplary compressed representations include, but are not limited to, compressed tensor representations, such as compressed sparse row (CSR) representation, compressed sparse column (CSC) representation, and compressed sparse fiber (CSF) representation. Support for compressed representations enables operations to be performed on inputs in compressed tensor format without requiring the compressed representation to be decompressed or decoded. In such embodiments, operations can be performed only on non-zero input values, and the resulting non-zero output values ​​can be mapped into the output matrix. In some embodiments, hardware support is also provided for machine-specific lossless data compression formats that are used when transferring data within the hardware or across a system bus. Such data can be retained in the compressed format used for sparse input data, and the matrix engine 1803 can use the compression metadata for the compressed data to enable operations to be performed only on non-zero values ​​or to bypass blocks of zero data input for multiplication operations.

[0276] In various embodiments, the input data may be provided by the programmer in a compressed tensor representation, or the codec may compress the input data into a compressed tensor representation or another sparse data encoding. In addition, to support the compressed tensor representation, streaming compression of the sparse input data may be performed before the input data is provided to the processing elements 1852AA-1852MN. In one embodiment, compression is performed on data written to a cache memory associated with the graphics core cluster 1800, where the compression is performed using an encoding supported by the matrix engine 1803. In one embodiment, the matrix engine 1803 includes support for inputs with structured sparsity, in which a predetermined level or predetermined pattern of sparsity is imposed on the input data. The data may be compressed to a known compression ratio, where the compressed data is processed by the compression elements 1852AA-1852MN based on metadata associated with the compressed data.

[0277] Figure 19 FIG. 19 shows a slice 1900 of a multi-slice processor according to an embodiment. In one embodiment, the slice 1900 represents Figure 17A Graphics engine chips 1710A-1710D or Figure 17B Slice 1900 of a multi-slice graphics processor includes an array of graphics core clusters (e.g., graphics core cluster 1800A, graphics core cluster 1800B, through graphics core cluster 1800N), each of which has an array of graphics cores 1815A-1815N. Slice 1900 also includes a global dispatcher 1902 for dispatching threads to processing resources of slice 1900.

[0278] Slice 1900 may include or be coupled with an L3 cache 1906 and a memory 1910. In various embodiments, L3 cache 1906 may be excluded, or slice 1900 may include additional levels of cache, such as an L4 cache. In one embodiment, such as Figure 17A and Figure 17B, each instance of a slice 1900 in a multi-slice graphics processor is associated with a memory 1910. In one embodiment, the multi-slice processor may be configured as a multi-chip module in which the L3 cache 1906 and / or the memory 1910 reside on a separate chiplet that is distinct from the graphics core clusters 1800A-1800N. In this context, a chiplet is an at least partially packaged integrated circuit that includes different logic units that can be assembled into a larger package with other chiplets. For example, the L3 cache 1906 may be included in a dedicated cache chiplet, or reside on the same chiplet as the graphics core clusters 1800A-1800N. In one embodiment, the L3 cache 1906 may be included in an active base die or an active interposer.

[0279] Memory structure 1903 enables communication between graphics core cluster 1800A-1800N, L3 cache 1906, and memory 1910. L2 cache 1904 is coupled to memory structure 1903 and is configurable to cache transactions executed via memory structure 1903. Slice interconnect 1908 enables communication with other slices on the graphics processor and may be Figure 17A and Figure 17B 1723F. In embodiments where L3 cache 1906 is excluded from slice 1900, L2 cache 1904 may be configured as a combined L2 / L3 cache. Memory structure 1903 may be configured to route data to L3 cache 1906 or to a memory controller associated with memory 1910 based on the presence or absence of L3 cache 1906 in a particular implementation. L3 cache 1906 may be configured as a per-tile cache that is dedicated to the processing resources of slice 1900 or may be part of a GPU-wide L3 cache.

[0280] Figure 20 is a block diagram illustrating a graphics processor instruction format 2000. A graphics processor execution unit supports an instruction set having instructions in a variety of formats. Solid-line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include components that are optional or included only in a subset of instructions. In some embodiments, the described and illustrated graphics processor instruction format 2000 is a macroinstruction, as it is an instruction supplied to the execution unit, as opposed to micro-operations that result from instruction decoding once the instruction is processed. Thus, a single instruction can cause the hardware to execute multiple micro-operations.

[0281] As described herein, the graphics processor execution unit can natively support instructions in the 128-bit instruction format 2010. Based on the selected instruction, instruction options, and number of operands, a compact 64-bit instruction format 2030 can be used for some instructions. The native 128-bit instruction format 2010 provides access to all instruction options, while some options and operations are restricted in the 64-bit instruction format 2030. The native instructions available in the 64-bit instruction format 2030 vary depending on the embodiment. Instructions are partially compressed using a set of index values ​​in the index field 2013. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instruction in the 128-bit instruction format 2010. Instructions of other sizes and formats may be used.

[0282] For each format, the instruction opcode 2012 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs a synchronous addition operation across each color channel representing a texture element or picture element. By default, the execution unit executes each instruction across all data channels of the operand. The instruction control field 2014 can enable control of certain execution options such as channel selection (e.g., predication) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction format 2010, the execution size field 2016 limits the number of data channels that will be executed in parallel. The execution size field 2016 may not be available for the compact 64-bit instruction format 2030.

[0283] Some execution unit instructions have up to three operands, including two source operands src0 2020 and src1 2022 and one destination operand (dest 2018). Other instructions (such as, for example, data manipulation instructions, dot product instructions, multiply-add instructions, or multiply-accumulate instructions) may have a third source operand (e.g., src2 2024). The instruction opcode 2012 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction. The execution unit may also support multiple destination instructions, where one or more of the destinations are implicit or implicit based on the instruction and / or the specified destination.

[0284] The 128-bit instruction format 2010 may include an access / addressing mode field 2026 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register addresses of one or more operands are directly provided by bits in the instruction.

[0285] 128-bit instruction format 2010 may also include an access / addressing mode field 2026 that specifies the addressing mode and / or access mode of the instruction. The access mode may be used to define the data access alignment of the instruction. Access modes including a 16-byte aligned access mode and a 1-byte aligned access mode may be supported, wherein the byte alignment of the access mode determines the access alignment of the instruction operand. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands, and when in a second mode, the instruction may use 16-byte aligned addressing for all source and destination operands.

[0286] The addressing mode portion of the access / addressing mode field 2026 may determine whether the instruction uses direct or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands may be calculated based on the address register value and the address immediate field in the instruction.

[0287] Instructions can be grouped based on the instruction opcode 2012 bit fields to simplify opcode decoding 2040. For 8-bit opcodes, bit 4, bit 5, and bit 6 allow execution units to determine the type of opcode. The exact opcode grouping shown is only an example. Move and logic opcode group 2042 can include data movement and logic instructions (e.g., move (mov), compare (cmp)). Move and logic opcode group 2042 can share five least significant bits (leastsignificant bit, LSB), wherein the move (mov) instruction adopts the form of 0000xxxxb, and the logic instruction adopts the form of 0001xxxxb. Flow control instruction group 2044 (e.g., call (call), jump (jmp)) includes the instruction of 0010xxxxb (e.g., 0x20) form. Miscellaneous instruction group 2046 includes a mixture of instructions, including synchronization instructions (e.g., wait (wait), send (send)) of 0011xxxxb (e.g., 0x30) form. The parallel math instruction group 2048 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) of the form 0100xxxxb (e.g., 0x40). The parallel math instruction group 2048 performs arithmetic operations in parallel across the data lanes. The vector math group 2050 includes arithmetic instructions (e.g., dp4) of the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic on vector operands, such as dot product calculations. In one embodiment, opcode decode 2040 may be used to determine which portion of the execution unit will be used to execute the decoded instruction. For example, some instructions may be designated as systolic instructions to be executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), may be routed to a ray tracing core or ray tracing logic within a slice or partition of the execution logic. Graphics pipeline

[0288] Figure 21 is a block diagram of a graphics processor 2100 according to another embodiment. Figure 21 Elements having the same or similar names as elements of any other figures herein describe the same elements as those in the other figures, can operate or function in a similar manner as those in the other figures, may include the same components, and may be linked to other entities such as, but not limited to, those described elsewhere herein.

[0289] The graphics processor 2100 may include various types of graphics processing pipelines, such as a geometry pipeline 2120, a media pipeline 2130, a display engine 2140, thread execution logic 2150, and a render output pipeline 2170. The graphics processor 2100 may be a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor may be controlled by register writes to one or more control registers (not shown) or by commands issued to the graphics processor 2100 via a ring or mesh interconnect 2102. The ring or mesh interconnect 2102 may couple the graphics processor 2100 to other processing components (such as other graphics processors or general-purpose processors). Commands from the ring or mesh interconnect 2102 are interpreted by a command stream converter 2103, which supplies instructions to various components of the geometry pipeline 2120 or the media pipeline 2130.

[0290] The command stream converter 2103 may direct the operation of the vertex fetcher 2105, which reads vertex data from memory and executes vertex processing commands provided by the command stream converter 2103. The vertex fetcher 2105 may provide the vertex data to the vertex shader 2107, which performs coordinate space transformation and lighting operations on each vertex. The vertex fetcher 2105 and the vertex shader 2107 may execute the vertex processing instructions by dispatching execution threads to the graphics cores 2152A-2152B via the thread dispatcher 2131.

[0291] Graphics cores 2152A-2152B may be arrays of vector processors with instruction sets for performing graphics and media operations. Graphics cores 2152A-2152B may have an attached L1 cache 2151 that is dedicated to each array or shared between arrays. The cache may be configured as a data cache, an instruction cache, or a single cache partitioned to contain data and instructions in different partitions.

[0292] The geometry pipeline 2120 may include a tessellation component for performing hardware-accelerated tessellation of 3D objects. The programmable hull shader 2111 may configure tessellation operations. The programmable domain shader 2117 may provide back-end evaluation of the tessellation output. The tessellator 2113 may operate under the direction of the programmable hull shader 2111 and may contain specialized logic for generating a detailed set of geometric objects based on a coarse geometric model provided as input to the geometry pipeline 2120. Furthermore, if tessellation is not used, the tessellation component (e.g., the programmable hull shader 2111, the tessellator 2113, and the programmable domain shader 2117) may be bypassed. The tessellation component may operate based on data received from the vertex shader 2107.

[0293] The complete geometric object may be processed by the geometry shader 2119 via one or more threads dispatched to the graphics cores 2152A-2152B, or may proceed directly to the clipper 2129. The geometry shader may operate on entire geometric objects, rather than on vertices or patches of vertices as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2119 receives input from the vertex shader 2107. The geometry shader 2119 may be programmable by a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0294] Before rasterization, the clipper 2129 processes the vertex data. The clipper 2129 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. The rasterizer and depth test component 2173 in the render output pipeline 2170 can dispatch a pixel shader to convert geometric objects into a pixel-by-pixel representation. The pixel shader logic can be included in the thread execution logic 2150. Optionally, the application can bypass the rasterizer and depth test component 2173 and access the unrasterized vertex data via the outflow unit 2123.

[0295] The graphics processor 2100 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some embodiments, the graphics cores 2152A-2152B and associated logic units (e.g., L1 cache 2151, samplers 2154, texture cache 2158, etc.) are interconnected via data ports 2156 to perform memory accesses and communicate with the processor's rendering output pipeline components. The samplers 2154, L1 cache 2151, texture cache 2158, and graphics cores 2152A-2152B can each have a separate memory access path. Optionally, the texture cache 2158 can also be configured as a sampler cache.

[0296] The render output pipeline 2170 may include a rasterizer and depth test component 2173 that converts vertex-based objects into associated pixel-based representations. The rasterizer logic may include a windower / masker unit for performing fixed-function triangle and line rasterization. In some embodiments, an associated render buffer 2178 and depth buffer 2179 are also available. A pixel operation component 2177 performs pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image transfers) are performed by the 2D engine 2141 or replaced by a display controller 2143 using an overlay display plane when displaying. A shared L3 cache 2175 may be available to all graphics components, allowing data to be shared without using main system memory.

[0297] The media pipeline 2130 may include a media engine 2137 and a video front end 2134. The video front end 2134 may receive pipeline commands from the command stream converter 2103. The media pipeline 2130 may include a separate command stream converter. The video front end 2134 may process media commands before sending them to the media engine 2137. The media engine 2137 may include thread generation functionality for generating threads for dispatching to the thread execution logic 2150 via the thread dispatcher 2131.

[0298] The graphics processor 2100 may include a display engine 2140. The display engine 2140 may be external to the graphics processor 2100 and may be coupled to the graphics processor via a ring or mesh interconnect 2102, or some other interconnect bus or structure. The display engine 2140 may include a 2D engine 2141 and a display controller 2143. The display engine 2140 may contain dedicated logic capable of operating independently of the 3D pipeline. The display controller 2143 may be coupled to a display device (not shown), which may be a system-integrated display device such as in a laptop computer or an external display device attached via a display device connector.

[0299] The geometry pipeline 2120 and the media pipeline 2130 can be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). Driver software for the graphics processor can convert API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. Support can be provided for all of the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and / or Vulkan graphics and computing APIs from the Khronos Group. Support can also be provided for the Direct3D library from Microsoft. Combinations of these libraries can be supported. Support can also be provided for the Open Source Computer Vision Library (OpenCV). If a mapping can be performed from the pipeline of a future API to the pipeline of the graphics processor, future APIs with compatible 3D pipelines will also be supported. Graphics pipeline programming

[0300] Figure 22A is a block diagram illustrating a graphics processor command format 2200 for programming a graphics processing pipeline, such as, for example, the graphics processing pipeline described herein in conjunction with Figure 16 and Figure 21 Describe the pipeline. Figure 22Bis a block diagram illustrating a graphics processor command sequence 2210 according to an embodiment. Figure 22A Solid-line boxes in illustrate components that are generally included in the graphics commands, while dashed lines include components that are optional or included only in a subset of the graphics commands. Figure 22A The graphics processor command format 2200 includes fields for identifying the client 2202 of the command, a command operation code (opcode 2204), and a data field 2206. A sub-opcode 2205 and a command size 2208 are also included in some commands.

[0301] Client 2202 may specify a client unit of a graphics device that processes command data. A graphics processor command parser may examine the client field of each command to adjust further processing of the command and route the command data to the appropriate client unit. A graphics processor client unit may include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit may have a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads the opcode 2204 and sub-opcode 2205 (if present) to determine the operation to be performed. The client unit uses the information in the data field 2206 to execute the command. For some commands, expected command size 2208 explicitly specifies the size of the command. The command parser may automatically determine the size of at least some of the commands based on the command opcode. Commands may be aligned to multiples of double words. Other command formats may also be used.

[0302] Figure 22B The flowchart in FIG2 illustrates a graphics processor command sequence 2210. Software or firmware of a data processing system featuring an exemplary graphics processor can use a version of the illustrated command sequence to establish, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for illustrative purposes only and is not limited to these specific commands or command sequences. Furthermore, commands can be issued as batches in the command sequence so that the graphics processor will process the command sequence at least partially concurrently.

[0303] Graphics processor command sequence 2210 may begin with a pipeline flush command 2212 to cause any active graphics pipeline to complete currently pending commands for that pipeline. Optionally, 3D pipeline 2222 and media pipeline 2224 may not operate concurrently. A pipeline flush is performed to cause active graphics pipelines to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will suspend command processing until the active paint engines complete pending operations and the associated read buffers are invalidated. Optionally, any data marked as "dirty" in the render buffers may be flushed to memory. Pipeline flush command 2212 may be used for pipeline synchronization or may be used before placing the graphics processor into a low-power state.

[0304] When a command sequence requires the graphics processor to explicitly switch between pipelines, a pipeline select command 2213 may be used. A pipeline select command 2213 may only be required once in an execution context before issuing a pipeline command, unless the context is issuing commands for both pipelines. A pipeline flush command 2212 may be required immediately before a pipeline switch via a pipeline select command 2213.

[0305] Pipeline control commands 2214 can configure the graphics pipeline for operation and can be used to program the 3D pipeline 2222 and the media pipeline 2224. Pipeline control commands 2214 can configure the pipeline state for the active pipeline. Pipeline control commands 2214 can be used for pipeline synchronization and to flush data from one or more cache memories within the active pipeline before processing a batch of commands.

[0306] Commands related to return buffer status 2216 may be used to configure a set of return buffers for a corresponding pipeline for writing data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operation writes intermediate data during processing. A graphics processor may also use one or more return buffers to store output data and perform cross-thread communication. Return buffer status 2216 may include selecting the size and number of return buffers to be used for a set of pipeline operations.

[0307] The remaining commands in the command sequence differ based on the active pipeline for the operation. Based on pipeline decision 2220 , the command sequence is tailored for the 3D pipeline 2222 starting at 3D pipeline state 2230 or the media pipeline 2224 starting at media pipeline state 2240 .

[0308] The commands used to configure the 3D pipeline state 2230 include 3D state setup commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that will be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. The 3D pipeline state 2230 commands can also selectively disable or bypass certain pipeline elements if those elements will not be used.

[0309] 3D primitive 2232 commands can be used to submit 3D primitives for processing by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 2232 commands are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 2232 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. The 3D primitive 2232 commands can be used to perform vertex operations on the 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 2222 dispatches the shader execution thread to the graphics processor execution unit.

[0310] The 3D pipeline 2222 can be triggered via an execute 2234 command or event. Registers can be written to trigger command execution. Execution can be triggered via a "go" or "kick" command in a command sequence. Command execution can be triggered using pipeline synchronization commands to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for 3D primitives. Once the operation is complete, the resulting geometry is rasterized and the pixel engine shades the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0311] When performing media operations, the graphics processor command sequence 2210 may follow the media pipeline 2224 path. Generally speaking, the specific purpose and manner of programming the media pipeline 2224 depends on the media or compute operation to be performed. During media decoding, certain media decoding operations may be migrated to the media pipeline. The media pipeline may also be bypassed and the media decoding may be performed in whole or in part using resources provided by one or more general-purpose processing cores. The media pipeline may also include elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is configured to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

[0312] The media pipeline 2224 can be configured in a similar manner to the 3D pipeline 2222. A set of commands for configuring the media pipeline state 2240 is dispatched or placed into a command queue before the media object commands 2242. The commands for the media pipeline state 2240 may include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. The commands for the media pipeline state 2240 may also support the use of one or more pointers to "indirect" state elements that contain batches of state settings.

[0313] Media object commands 2242 may supply a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer containing the video data to be processed. Optionally, all media pipeline states must be valid before issuing media object commands 2242. Once the pipeline state is configured and media object commands 2242 are queued, the media pipeline 2224 is triggered via an execute command 2244 or an equivalent execute event (e.g., a register write). The output from the media pipeline 2224 may then be post-processed by operations provided by the 3D pipeline 2222 or the media pipeline 2224. GPGPU operations can be configured and executed in a manner similar to media operations. Graphics software architecture

[0314] Figure 23 An exemplary graphics software architecture for data processing system 2300 is illustrated. Such a software architecture may include a 3D graphics application 2310, an operating system 2320, and a processor 2330. Processor 2330 may include a graphics processor 2332 and one or more general-purpose processor cores 2334. Processor 2330 may be a variant of, and may be used in place of, one of processor(s) 1402 or any other of the processors described herein. Thus, disclosure of any feature in conjunction with processor(s) 1402 or any other of the processors described herein also discloses the corresponding combination with graphics processor 2332, but is not limited thereto. Furthermore, Figure 23 Elements having the same or similar names as elements in any other figures herein describe the same elements in the other figures, can operate or function in a similar manner to the other figures, may include the same components, and may be linked to other entities such as, but not limited to, those described elsewhere herein. 3D graphics application 2310 and operating system 2320 each execute in system memory 2350 of the data processing system.

[0315] 3D graphics application 2310 may include one or more shader programs that include shader instructions 2312. The shader language instructions may be in a high-level shader language, such as Direct3D's High-Level Shader Language (HLSL), OpenGL Shader Language (GLSL), or the like. The application may also include executable instructions 2314 in a machine language suitable for execution by a general-purpose processor core(s) 2334. The application may also include graphics objects 2316 defined by vertex data.

[0316] The operating system 2320 may be from Microsoft Corporation. An operating system, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. The operating system 2320 may support a graphics API 2322, such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating system 2320 uses a front-end shader compiler 2324 to compile any shader instructions 2312 using HLSL into a lower-level shader language. The compilation may be just-in-time (JIT) compilation or application executable shader precompilation. During the compilation of the 3D graphics application 2310, high-level shaders may be compiled into low-level shaders. The shader instructions 2312 may be provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0317] The user-mode graphics driver 2326 may include a backend shader compiler 2327 to compile shader instructions 2312 into a hardware-specific representation. When the OpenGL API is in use, shader instructions 2312 in the GLSL high-level language are passed to the user-mode graphics driver 2326 for compilation. The user-mode graphics driver 2326 may use operating system kernel-mode functions 2328 to communicate with the kernel-mode graphics driver 2329. The kernel-mode graphics driver 2329 may communicate with the graphics processor 2332 to dispatch commands and instructions. IP core implementation

[0318] One or more aspects may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit (such as a processor). For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to fabricate logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit that can be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to each customer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0319] Figure 24 2 is a block diagram illustrating an IP core development system 2400 that can be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 2400 can be used to generate modular, reusable designs that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SoC integrated circuit). A design facility 2430 can generate a software simulation 2410 of the IP core design in a high-level programming language (e.g., C / C++). The software simulation 2410 can be used to design, test, and verify the behavior of the IP core using a simulation model 2412. The simulation model 2412 may include functional simulation, behavioral simulation, and / or timing simulation. A register transfer level (RTL) design (RTL design 2415) can then be created or synthesized from the simulation model 2412. The RTL design 2415 is an abstraction of the behavior of the integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 2415, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. As a result, the specific details of the initial design and simulation may vary.

[0320] The RTL design 2415 or an equivalent solution can be further synthesized by the design facility into a hardware model 2420, which can be in a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. Non-volatile memory 2440 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a manufacturing facility 2465. Manufacturing facility 2465 can be a third-party manufacturing facility. Alternatively, the IP core design can be transmitted via a wired connection 2450 or a wireless connection 2460 (e.g., via the Internet). Manufacturing facility 2465 can then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0321] Figure 25A A cross-sectional side view of a package assembly 2590 for an integrated circuit is shown, comprising multiple units of hardware logic chiplets connected to a substrate 2580 (e.g., a base die). Graphics processing units, parallel processors, and / or compute accelerators as described herein may be comprised of various separately fabricated silicon chiplets. In this context, a chiplet is an at least partially packaged integrated circuit that includes different logic units that can be assembled into a larger package with other chiplets. A variety of chiplet collections with different IP core logic can be assembled into a single device. Additionally, chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable interconnection and communication between different forms of IP within a GPU. IP cores can be manufactured using different process technologies and constructed during manufacturing, which avoids the complexity of converging multiple IP cores into the same manufacturing process, particularly for large SoCs with several flavors of IP. Enabling the use of multiple process technologies improves time to market and provides a cost-effective approach to creating multiple product SKUs. Additionally, separate IP is more easily modified to be independently power-gated; components not in use for a given workload can be shut down, thereby reducing overall power consumption.

[0322] In various embodiments, the package assembly 2590 may include a fewer or greater number of components and chiplets interconnected by an interconnect structure 2585 or a bridge fabric 2587. The bridge fabric 2587 may be used to facilitate point-to-point interconnection between, for example, a logic or I / O chiplet 2574 and a memory chiplet 2575. In some implementations, the bridge fabric 2587 may also be embedded within the substrate 2580. The chiplets within the package assembly 2590 may have a 2.5D arrangement using chip-on-wafer-on-substrate (CoWoS) stacking, where multiple dies are stacked side-by-side on a silicon interposer that includes through-silicon vias (TSVs) to couple the chiplets to the substrate 2580, which includes electrical connections to the package interconnects 2583.

[0323] In one embodiment, the silicon interposer is an active interposer 2589 that includes embedded logic in addition to TSVs. In such an embodiment, the chiplets within the package assembly 2590 are arranged on top of the active interposer 2589 using 3D face-to-face die stacking. The active interposer 2589 may also include I / O hardware logic 2591, cache memory 2592, and other hardware logic 2593 in addition to the interconnect structure 2585 and bridge fabric 2587. The interconnect structure 2585 enables communication between the various logic chiplets within the active interposer 2589. The interconnect structure 2585 may be a NoC interconnect or another form of packet-switched fabric that exchanges data packets between components of the package assembly. For complex assemblies, the interconnect structure 2585 may be a dedicated chiplet that enables communication between the various hardware logic of the package assembly 2590.

[0324] The hardware logic chiplets may include dedicated hardware logic chiplets 2572, logic or I / O chiplets 2574, and / or memory chiplets 2575. The dedicated hardware logic chiplets 2572 and logic or I / O chiplets 2574 may be implemented at least in part in configurable logic or fixed-function logic hardware and may include one or more portions of any of the processor core(s), graphics processor(s), parallel processor(s), or other accelerator devices described herein. The memory chiplets 2575 may be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory. The cache memory 2592 within the active interposer 2589 (or substrate 2580) may serve as a global cache for the package assembly 2590, as part of a distributed global cache, or as a dedicated cache for the interconnect structure 2585.

[0325] Each chiplet can be fabricated as a separate semiconductor die and can be coupled to a base die that is embedded within or coupled to a substrate 2580. Coupling to the substrate 2580 can be performed via an interconnect fabric 2573. The interconnect fabric 2573 can be configured to route electrical signals between the various chiplets and logic within the substrate 2580. The interconnect fabric 2573 can include interconnects such as, but not limited to, bumps or pillars. In some embodiments, the interconnect fabric 2573 can be configured to route electrical signals such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic, I / O, and memory chiplets. In one embodiment, an additional interconnect fabric couples the active interposer 2589 to the substrate 2580.

[0326] Substrate 2580 may be an epoxy-based laminate substrate and / or may also include other suitable types of substrates. Package assembly 2590 can be connected to other electrical devices via package interconnects 2583. Package interconnects 2583 may be coupled to the surface of substrate 2580 to route electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

[0327] The logic or I / O chiplet 2574 and the memory chiplet 2575 can be electrically coupled via a bridge fabric 2587 that is configured to route electrical signals between the logic or I / O chiplet 2574 and the memory chiplet 2575. The bridge fabric 2587 can be a dense interconnect fabric that provides routing for electrical signals. The bridge fabric 2587 can include a bridge substrate composed of glass or a suitable semiconductor material. Circuit features can be formed on the bridge substrate to provide chip-to-chip connections between the logic or I / O chiplet 2574 and the memory chiplet 2575. The bridge fabric 2587 can also be referred to as a silicon bridge or an interconnect bridge. For example, the bridge fabric 2587 is an embedded multi-die interconnect bridge (EMIB). Alternatively, the bridge fabric 2587 can simply be a direct connection from one chiplet to another.

[0328] Figure 25BFIG200100] A package assembly 2594 including interchangeable chiplets 2595 is shown according to an embodiment. The interchangeable chiplets 2595 can be assembled into standardized chiplet sockets or chiplet receptacles on base chiplets 2596, 2598. The base chiplets 2596, 2598 can be coupled via a bridge interconnect 2597, which can be similar to other bridge interconnects described herein and can be, for example, EMIB. Memory chiplets can also be connected to logic or I / O chiplets via the bridge interconnect. The I / O and logic chiplets can communicate via the interconnect structure. The base chiplets can each support one or more sockets in a standardized format for one of logic or I / O or memory / cache.

[0329] The SRAM and power delivery circuitry can be fabricated into one or more of the base chiplets 2596, 2598, which can be fabricated using a different process technology than the interchangeable chiplets 2595, which are stacked on top of the base chiplets. For example, the base chiplets 2596, 2598 can be fabricated using a larger process technology, while the interchangeable chiplets can be fabricated using a smaller process technology. One or more of the interchangeable chiplets 2595 can be memory (e.g., DRAM) chiplets. Different memory densities can be selected for the package assembly 2594 based on the power and / or performance requirements of the product using the package assembly 2594. Additionally, logic chiplets with different numbers of functional units of different types can be selected at assembly time based on the power and / or performance requirements of the product. Additionally, chiplets containing IP logic cores of different types can be inserted into the interchangeable chiplet socket, enabling hybrid processor designs that can mix and match IP blocks of different technologies. Exemplary System-on-Chip Integrated Circuit

[0330] Figure 26 The diagram illustrates an exemplary integrated circuit that can be manufactured using one or more IP cores. In addition to what is illustrated, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. Figure 26 Elements having the same or similar names as elements of any other figures herein describe the same elements as the other figures, may operate or function in a similar manner as the other figures, may include the same components, and may be linked to other entities such as, but not limited to, those described elsewhere herein.

[0331] The system-on-chip integrated circuit 2600 includes one or more application processors 2605 (e.g., CPUs), a graphics processor 2610, which may be a variant of the graphics processor(s) 1408, or may be a variant of any of the graphics processors described herein and may be used in place of any of the graphics processors described. Thus, the disclosure of any feature herein in conjunction with a graphics processor also discloses the corresponding combination with the graphics processor 2610, but is not limited thereto. The system-on-chip integrated circuit 2600 may additionally include an image processor 2615 and / or a video processor 2620, either of which may be modular IP cores from the same design facility or from multiple different design facilities. The system-on-chip integrated circuit 2600 may include peripheral or bus logic, including a USB controller 2625, a UART controller 2630, an SPI / SDIO controller 2635, and an I / O controller. 2 S / I 2 Controller 2640. Additionally, the integrated circuit may include a display device 2645 coupled to a high-definition multimedia interface (HDMI) controller 2650 and one or more of a reliability, availability, and serviceability (RAS) engine (RAS engine 2655). The RAS engine 2655 is used to identify potential failures that may occur during device runtime to minimize downtime that would result if those potential failures occur. Storage may be provided by a flash memory subsystem 2660 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2665 to obtain access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2670. Adaptive virtualization of GPU cores

[0332] GPU time slicing is a virtualization technology that allows multiple workloads or virtual machines (VMs) to share a single GPU by dividing their processing time into discrete slices. During each time slice, the GPU's compute and memory resources are assigned to a VM to execute its workload. When a VM cannot effectively utilize its assigned resources during its time slice, overall computing efficiency is reduced.

[0333] Described herein are techniques for enabling adaptive virtualization of GPU cores. A GPU core is a slice or portion of a GPU that includes GPU functional units. A GPU core may include, or have control over, a rendering engine, a compute engine, a decoder engine, an encoder engine, a video processing engine, and the like. Virtualizing a GPU core grants a virtual environment access to the functions of that GPU core. Adaptive virtualization of the GPU core allows time-sharing virtualization to be performed for less than the entire GPU, so that within a given time slice, multiple VMs or guest environments can have concurrent access to the GPU. Instead of applying time-sharing full GPU virtualization, the GPU core is virtualized, allowing different portions of the GPU to be assigned to different VMs or other guest software environments.

[0334] Figure 27 2702, and a plurality of compute engines 2710. The graphics microcontroller 2761 may execute firmware to manage global scheduling and operations for the GPU device 2702. In various embodiments, the graphics microcontroller 2761 is a processor or controller within the GPU device 2702, or coupled to the GPU device 2702 in a graphics SoC. In one embodiment, the graphics microcontroller 2761 is a processor or controller within the GPU device 2702, or coupled to the GPU device 2702 in a graphics SoC. Figure 15B A version of the graphics microcontroller 1533 shown in .

[0335] The graphics microcontroller 2761 may be implemented using programmable logic, such as, for example, a programmable logic array (PLA), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or any combination thereof. In one embodiment, the graphics microcontroller 2761 is a custom ASIC. In one embodiment, the graphics microcontroller 2761 is a low-power version of a full-featured general-purpose processor core that includes the following: Figure 14The graphics microcontroller 2761 may have an instruction set similar to the instruction set 1409 of the processor core 1407. In one embodiment, there may be multiple instances of the graphics microcontroller 2761. The multiple instances of the graphics microcontroller 2761 may be associated with separate instances of isolated device partitions of the GPU device 2702. In one embodiment, the graphics microcontroller 2761 may be virtualized to create multiple virtual instances of the graphics microcontroller 2761. The multiple virtual instances of the graphics microcontroller 2761 may be associated with multiple partitions of the GPU device 2702. Alternatively, a single instance of the graphics microcontroller 2761 may handle workload submission to the graphics engine of each separate partition of the graphics processor.

[0336] The graphics engine 2708 can process command lists or command buffers of instructions received from the graphics driver. The graphics engine 2708 performs graphics operations in response to these commands. A render command streamer (RCS) (RCS 2716) associated with the graphics engine 2708 can stream rendering commands for executing shader operations. A thread dispatcher 2720 dispatches threads for these shader operations to processing resources within compute blocks 2720A-2720N. The dispatched threads are executed via hardware threads within the processing resources. Similarly, multiple compute engines 2710 and the graphics engine 2708, operating asynchronously with each other, can dispatch commands for compute shaders and / or GPGPU programs via multiple compute command streamers (CCS) (CCSn 2718). The thread dispatcher 2720 dispatches threads to processing resources within compute blocks 2720A-2720N to execute compute shaders and / or GPGPU programs. The dispatched threads are executed via hardware threads within the processing resources.

[0337] In one embodiment, the thread dispatcher 2720 includes a computation walker circuit 2722 to facilitate the execution of computational programs on the graphics processor hardware. In one embodiment, the processing device may be segmented into multiple parts, including one or more computational blocks 2724A-2724N and / or one or more parts of a single computational block. Each computational block 2724A-2724N may include various instruction execution processing resources described herein. Each part may be assigned to process commands from a specific source. When a single source (e.g., CCS1 in CCSn 2718) provides commands, the entire processing device (all segments) may be assigned to process commands from the single source. When a second source (e.g., CCS1 and CCS2) provides commands, some segments may be assigned to execute commands from the first source, and other segments may be assigned to execute commands from the second source. Thus, commands from multiple applications may be executed simultaneously by the processing unit.

[0338] The adaptive virtualization of GPU cores will be described below in the context of the computing functions of a GPU or accelerator device. Compute commands are used by VMs to perform parallel general computing operations, AI operations, high-performance computing (HPC) operations, and other operations suitable for execution by GPUs, computing accelerators, AI accelerators, or NPUs. Instead of full GPU virtualization with application time-slicing, CCS engine-based virtualization is enabled, where the CCS is assigned to multiple VMs. Operations for multiple VMs are then performed during each time slice. Depending on the usage of the workload, each VM can have one or more CCS engines. Graphics microcontrollers (GUCs) (e.g., Figure 15B The graphics microcontroller 1533 can dynamically assign CCS engines based on incoming requests from VMs. The scheduler can dynamically allocate a number of processing resources (cores, EUs, SMs) to each VM / CCS, depending on the workload. By doing so, data center tenants can fully utilize all available resources in the GPU.

[0339] Figure 28 is a diagram of a system 2800 for dispatching thread groups to processing resources 2820 according to an embodiment. In one embodiment, thread group dispatch is performed using a hierarchy of hardware units that handle the dispatch of thread groups. The command stream converters (shown as CCS0-CCS3) are Figure 272718. The command stream converter provides thread group information to the global compute front end (CFEG) 2810. The thread group information includes information for one or more compute kernels to be executed by the graphics processor. The CFEG 2810 then dispatches the thread group to the CFE 2815 (shown as CFE0-CFE7). Each CFE further dispatches the received thread group to the processing resource 2820. The processing resource 2820 may be included in Figure 27 or within computation blocks 2724A-2724N Figure 27 In one embodiment, the processing resource 2820 is divided into a plurality of slices 2817 (shown as slice 0-slice 15), wherein each of the CFEs 2815 is coupled to at least two slices of the plurality of slices 2817. Each slice of the plurality of slices 2817 is an individually assignable unit of the processing resource 2820. In one embodiment, each slice can be associated with a plurality of slices such as Figure 4D The accelerator integration slice 490 in the accelerator integration slice 490 is associated to enable the slice to be presented as a virtualizable sub-device. In one embodiment, each slice can be dedicated to a virtual machine or virtualized graphics execution environment, such as a container. Each slice in the plurality of slices 2817 may include one or more sub-slices, where each sub-slice includes one or more separate groups of processing resources and / or execution units.

[0340] The specific hardware composition of each slice may vary across embodiments. Figure 18A , in one embodiment, a slice may include one or more graphics cores, such as one or more of graphics cores 1815A-1815N. A slice may also include a graphics processor core block 1519, which includes all associated graphics cores 1521A-1521F. In one embodiment, a slice may include a graphics core cluster 1714. In such embodiments, sub-slices may include groups of separate processing resources and / or execution units, each group including multiple vector engines 1802A-1802N and matrix engines 1803A-1803N. Depending on the granularity of the slice, graphics core 1815A may be a single slice, a single sub-slice, and / or include multiple sub-slices. Alternatively, referring to Figure 2C , a slice may include a processing cluster 214 , where each sub-slice includes one or more instances of a graphics multiprocessor 234 or one or more portions of a graphics multiprocessor 234 .

[0341] In one thread group dispatch strategy, the CFEG 2810 dispatches thread groups to CFEs in a round-robin manner, where each CFE is coupled to two consecutive slices. For example, CFE0 dispatches thread groups to slice 0 and slice 1. In this example, there are 8 CFEs (CFE0 to CFE7) in a system with 16 slices. Each cluster of eight (8) slices is coupled to four (4) consecutive CFEs. If a CFE cannot accept a thread group and each dispatch cycle starts from the first CFE (CFE0), the thread group dispatch strategy may skip that CFE. Therefore, the strategy is likely to dispatch consecutive thread groups to different CFE clusters, resulting in the strategy not being able to fully utilize the sequential memory addresses accessed by consecutive / nearby thread groups. However, the dispatch strategy can result in workload slowdown, where the workload suffers a significantly lower L2 hit rate (relative to the baseline) and / or suffers a relatively large number of stall cycles at the interface. This may be due to low data reuse within a particular L2 cache partition and / or potential congestion of the interface due to duplication of memory requests from multiple L2 cache partitions.

[0342] In some embodiments, to improve memory access efficiency, a scheduling strategy can be implemented that provides for scheduling of consecutive thread groups to a specific CFE cluster before switching to another cluster. In one embodiment, thread groups can be over-scheduled to a cluster so that multiple threads or thread groups that can be executed concurrently by the cluster can be scheduled to the cluster. Over-scheduled threads can be scheduled to the cluster and will execute when resources of that cluster become available (e.g., when the executing thread or thread group is preempted during a latency event).

[0343] Figure 29 The figure shows a GPU 2900 with a compute command streamer assigned to a single VM. GPU 2900 may include four CCSs 2718A-2718D (CCS0-CCS3), which enable access to processing resources 2820. In one embodiment, GPU 2900 includes 512 processing resources. However, in various embodiments, more or fewer processing resources may be included. All of CCSs 2718A-2718D can be assigned to VM 2902, which will assign all of the GPU's computing power to that VM 2902. If VM 2902 cannot saturate processing resources 2820 during its assigned time slice, processing resources 2822 will be underutilized. Virtualization and scheduling can be implemented on a per-computing engine basis to enhance GPU utilization.

[0344] Figures 30A-30B Illustrated is a GPU with a compute command streamer assigned to multiple VMs. Figure 30A A GPU 3000 is shown, which includes Figure 29 2820 of the GPU 2900. The GPU 3000 includes four CCSs 2718A-2718D, each of which is assigned to a different VM 3002A-3002D. If the GPU 3000 includes 512 processing resources 2820, each of the VMs 3002A-3002D can be assigned 128 of the 512 processing resources 2820 within the GPU 3000. Figure 30B A GPU 3010 is shown including four CCSs 2718A-2718D, wherein processing resources 2820 may be assigned asymmetrically. VMs 3012A-3012D of the GPU 3010 may be assigned different numbers of instances of processing resources 2820 via the asymmetrical assignment of processing resources 2820 to CCSs 2718A-2718D. When a CCS is assigned to a VM 3012A-3012D, the VM receives the processing resources 2820 assigned to each CCS respectively. In one embodiment, the number of processing resources may be dynamically configured by a scheduler based on workload. In one embodiment, the assignment of processing resources 2820 to CCSs 2718A-2718D is performed by a graphics microcontroller 2761 within the GPU 3010. In one embodiment, processing resources 2820 are assigned at a slice granularity from Figure 28 A plurality of slices 2817 are assigned as shown in FIG.

[0345] Figure 31 102D. Figure 29 Similar to the GPU 2900, each VM is assigned all available processing resources. However, during at least some of the time periods, the processing resources of the GPU may not be fully utilized.

[0346] The second time series 3110 illustrates an even division of the GPU's processing resources across multiple VMs 3112A-3112D. The GPU associated with the second time series 3110 processes the workload from each of the multiple VMs 3112A-3112D during each 4 ms time period. While the workload from each of the multiple VMs 3112A-3112D is processed continuously, only a portion of the GPU's processing resources is available to each VM. The assignment of VMs to processing resources is determined based on the CCS assigned to each VM and the processing resources assigned to each corresponding CCS. This assignment may result in better overall utilization of the GPU, allowing more computational operations to be performed within a time period.

[0347] The third time series 3120 illustrates the uneven partitioning of the GPU's processing resources across multiple VMs 3122A-3122D. Because the assignment of VMs to processing resources is based on the CCS assigned to each VM and the processing resources assigned to each corresponding CCS, a different amount of processing resources can be assigned to each CCS. Resource utilization can be dynamically reassigned based on workload demand, thereby maintaining high QoS for each VM. Thus, VMs with higher workload demands can be assigned more processing resources, while VMs with lower workload demands can be assigned fewer processing resources.

[0348] Table 5 illustrates exemplary performance differences when virtualization is optimized using adaptive EU-based scheduling. Table 5 - Performance improvements via adaptive processing resource (PR)-based scheduling

[0349] Figure 32 3200 for implementing adaptive virtualization of an accelerator device core according to an embodiment. The method 3200 may be implemented at least in part by device configuration, scheduling, and / or management logic within or associated with an accelerator device, such as a GPU, a computing accelerator, an AI accelerator, or an NPU. The device configuration, scheduling, and / or management logic may include, for example, Figure 27 The graphics microcontroller 2761 or graphics driver (e.g., Figure 23 The method 3200 may also be implemented in part via the processing resources 2820 described herein.

[0350] In one embodiment, the configuration, scheduling, and / or management logic may assign a set of processing resources to a compute command streamer (CCS) of an accelerator device (3202). The configuration, scheduling, and / or management logic may then assign at least one compute command streamer to each of a plurality of virtual machines (VMs) associated with the accelerator device (3204). The accelerator device may then process workloads from the VMs via processing resources associated with the CCSs assigned to the plurality of VMs, respectively (3206). In one embodiment, the configuration, scheduling, and / or management logic may then dynamically reconfigure the processing resource assignments and CCS assignments based on VM workload requirements (3208).

[0351] The above-described techniques implement time-sharing virtualization, which allows multiple workloads or virtual machines (VMs) to share a single GPU by dividing the processing time of the GPU into discrete slices.

[0352] One embodiment provides a graphics processor comprising: a memory interface; multiple interfaces to multiple compute engines; a processing resource cluster comprising multiple processing resources configured to execute instructions on behalf of the multiple compute engines; and virtualization circuitry configured to enable time-sharing virtualization of the multiple processing resources via the multiple compute engines, wherein the virtualization circuitry is used to concurrently process workloads during time slices by dynamically assigning workloads from multiple guest software environments to the multiple interfaces to the multiple compute engines.

[0353] In one embodiment, the virtualization circuitry is configured to: assign a first slice of a plurality of processing resources to a first interface; assign a second slice of the plurality of processing resources to a second interface; process a first workload from a first guest software environment on the first slice of the plurality of processing resources via the first interface; and concurrently process a second workload from a second guest software environment on the second slice of the plurality of processing resources via the second interface. In one embodiment, the first interface includes a first command stream converter configured to send a command stream to a first compute engine among the plurality of compute engines, and the second interface includes a second command stream converter configured to send a command stream to a second compute engine among the plurality of compute engines. In one embodiment, the first compute engine is configured to process the first workload from the first guest software environment via the first slice of the plurality of processing resources, and the second compute engine is configured to process the second workload from the second guest software environment via the second slice of the plurality of processing resources.

[0354] In one embodiment, the virtualization circuitry is configured to: process a first workload from a first guest software environment and a second workload from a second guest software environment during a first virtualization time slice. In one embodiment, the virtualization circuitry is configured to: assign a third slice of the plurality of processing resources to the first interface in response to an increase in workload demand associated with the first guest software environment. In one embodiment, the virtualization circuitry is configured to: process a third workload from the first guest software environment on the first slice of the plurality of processing resources and the third slice of the plurality of processing resources via the first interface during a second virtualization time slice; and concurrently process a fourth workload from the second guest software environment on the second slice of the plurality of processing resources via the second interface.

[0355] In one embodiment, a third slice of the plurality of processing resources includes a smaller number of processing resources than the first slice and the second slice. In one embodiment, the first guest software environment and the second guest software environment include virtual machines or containers. In one embodiment, the plurality of processing resources include single instruction multiple data (SIMD) processing resources and are configurable to support a single instruction multiple thread (SIMT) execution mode.

[0356] One embodiment provides a method, comprising: assigning a first slice of multiple processing resources of an accelerator device to a first interface to multiple computing engines of the accelerator device; assigning a second slice of the multiple processing resources of the accelerator device to a second interface to the multiple computing engines of the accelerator device; processing a first workload from a first guest software environment on the first slice of the multiple processing resources via the first interface; and concurrently processing a second workload from a second guest software environment on the second slice of the multiple processing resources via the second interface.

[0357] In one embodiment, the method includes: enabling time-sharing virtualization of a plurality of processing resources via a plurality of compute engines, the time-sharing virtualization being enabled via virtualization circuitry of an accelerator device. In one embodiment, the method includes: processing a first workload and a second workload during a first virtualized time slice. In one embodiment, the method includes: dynamically assigning a third slice of the plurality of processing resources to a first interface, and processing a third workload from a first guest software environment on the first slice and the third slice via the first interface. In one embodiment, the method includes: processing the third workload concurrently with processing a fourth workload from a second guest software environment during a second virtualized time slice.

[0358] One embodiment provides a data processing system comprising: one or more processors configured to execute operations associated with a first guest software environment and a second guest software environment; an accelerator device coupled to the one or more processors, the accelerator device comprising: a plurality of interfaces to a plurality of compute engines; a processing resource cluster comprising a plurality of processing resources configured to execute instructions on behalf of the plurality of compute engines; and virtualization circuitry configured to enable time-slicing virtualization of the plurality of processing resources via the plurality of compute engines. The virtualization circuitry can concurrently process workloads from the plurality of guest software environments during time slicing by dynamically assigning the workloads to the plurality of interfaces to the plurality of compute engines.

[0359] In one embodiment, the virtualization circuitry is configured to: assign a first slice of a plurality of processing resources to a first interface; assign a second slice of the plurality of processing resources to a second interface; process a first workload from a first guest software environment on the first slice of the plurality of processing resources via the first interface; and concurrently process a second workload from a second guest software environment on the second slice of the plurality of processing resources via the second interface. In one embodiment, the first interface includes a first command stream translator configured to send a command stream to a first compute engine of the plurality of compute engines, and the second interface includes a second command stream translator configured to send a command stream to a second compute engine of the plurality of compute engines. In one embodiment, the first compute engine is configured to process the first workload from the first guest software environment via the first slice of the plurality of processing resources, and the second compute engine is configured to process the second workload from the second guest software environment via the second slice of the plurality of processing resources. In one embodiment, the virtualization circuitry is configured to process the first workload from the first guest software environment and the second workload from the second guest software environment during a first virtualized time slice.

[0360] Other aspects of the above-described techniques may be included in other embodiments. GPU engine-based virtualization

[0361] GPU engine-based virtualization is another method for enhancing the utilization of time-sharing virtualization architectures. Adaptive virtualization of GPU cores is useful in computing virtualization scenarios, but may not be useful in all scenarios. For example, in some embodiments, a rendering engine cannot be used concurrently by multiple guest software environments. Instead, the rendering engine is shared between multiple guests in a time-sharing manner. Although some engines of a GPU or accelerator may not be used concurrently by multiple VMs, the efficiency of assigning engines to VMs can be improved. Described herein is a time-sharing virtualization method based on a GPU engine, in which once a VM completes operation on the engine and before the VM time slice is completed, the GPU engine can be reassigned between VMs. A GPU engine is a component of a GPU core (such as a rendering engine, a computing engine, and a video engine) that can act independently of other engines of the GPU core (such as a rendering engine, a computing engine, and a video engine).

[0362] Figure 33 The diagram illustrates a system 3300 in which time-sharing virtualization is applied at the GPU granularity. In one embodiment, the system 3300 includes a host 3302, a scheduler 3305, and a GPU 3306 or other accelerator device. The host 3302 includes a processor configured to execute multiple VMs 3304A-3304B. The host 3302 is configured to enable the VMs 3304A-3304B to submit workloads for execution by the GPU 3306 in a time-sharing manner via a virtual GPU (vGPU) hardware interface provided by, for example, single root I / O virtualization (SR-IOV) or scalable I / O virtualization (SIOV). The scheduler 3305 can be, for example, an OS scheduler associated with the host 3302 or a GPU scheduler associated with the GPU 3306. For example, the scheduler 3305 can be Figure 27 A component of the graphics microcontroller 2761.

[0363] In one embodiment, GPU 3306 is Figure 27 A version of GPU device 2702 or including Figure 27 Components of the GPU device 2702. The GPU 3306 includes the RCS 2716, the CCSn 2718, and the media engine 3307 including multiple video encoders 3308A-3308B. The media engine 3307 can be Figure 213304B and 3304B. In one embodiment, the system 3300 may be configured to execute operations for a cloud gaming system. An execution timeline 3309 for VMs 3304A-3304B is shown. Assuming that rendering and encoding each take 2ms, the total rendering and encoding time for each of VMs 3304A-3304B is 4ms, where VM1 3304A executes Render 1 3310A and Encode 1 3312A within a 4ms time slice. VM2 3304B then executes Render 2 3310B and Encode 2 3312B within a 4ms time slice. For example, the system 3300 may allow four to eight 1080p cloud gaming sessions at 30fps. However, the utilization of total processing resources (e.g., GPU cores, compute units (CUs), execution units (EUs), streaming multiprocessors (SMs)) is 50%, and on some systems, the utilization of the video encoding engine can be as low as 6.25%.

[0364] Described herein is a technique that employs engine-based virtualization instead of full-GPU-based virtualization. For example, a GPU is considered a collection of engines comprising at least one of a rendering engine, a compute engine, a video codec (encoding / decoding) engine, and a video enhancement engine. In one embodiment, media and rendering virtual functions (VFs) are scheduled separately, and each VM can have one or more engines depending on workload requirements. A graphics microcontroller (GUC, such as the graphics microcontroller 2761) can flexibly assign engines based on incoming software requests. Each VM can use one engine to render or compute, and at the next quantum, the VM can use a media engine to encode, thereby allowing better utilization of the various engines.

[0365] Figure 34The diagram shows a system 3400 configured to perform engine-based GPU virtualization according to an embodiment. Through engine-based GPU virtualization, the scheduler 3305 can schedule workloads at the granularity of each engine across time slices, allowing the rendering engine (via RCS2716) to be fully utilized. Due to the ability of the encoders 3308A-3308B of the media engine 3307 to be scheduled to multiple VMs 3304A-3304B, engine-based GPU virtualization allows the GPU 3306 to be virtualized to support multiple VMs 3304A-3304B concurrently. The video encoders 3308A-3308B of the system 3400 represent any independently assignable GPU engine, such as a video decoding engine, a video enhancement engine, a matrix engine, an AI engine, or an NPU. The video encoders 3308A-3308B can be used in series with rendering operations for a cloud gaming system. Different engines can be used for other system implementations. Additionally, compute operations via CCSn 2718 may be performed concurrently with rendering operations via RCS 2716 .

[0366] An execution timeline 3409 for VMs 3304A-3304B is shown. In one implementation, when VM1 3304A completes rendering (Render 1 3310A), scheduler 3305 can immediately schedule work from VM2 3304B to begin rendering (Render 2 3310B) without waiting for VM1 3304B to complete encoding (Encode 1 3312A). By doing so, rendering utilization can reach 100% because the rendering engine is always executing operations for the VM. However, in this implementation, multiple encoder engines can still be serialized.

[0367] In one embodiment, the number of VFs can be increased to support concurrent use of multiple encoders 3308A-3308B and / or multiple instances of the media engine 3307. In one embodiment, each instance of the media engine 3307 can support up to 12x1080p30 encoded streams, and additional VFs allow multiple encoding operations to be performed concurrently. For this implementation, an execution timeline 3411 is shown, where an encoding operation (encode 1 3412A) for VM1 3304A is performed by a first video device (e.g., vd1, encoder 1 3308A). Before VM1 3304A completes encode 1 3412A, VM2 3304B can initiate an additional encoding operation (encode 2 3412B) using a second video device (e.g., vd2, encoder 2 3308B). Additional VFs for video devices can enable support for an additional VM (VM3 3304C). Alternatively, VM3 3304C may represent operations that may be performed by VM1 3304A. These operations include rendering operations (render 3 3310C), and while encoding 2 3412B is in progress, additional encoding operations (encode 3 3412C) may be performed by the first video device (vd1, encoder 1 3308A). In one embodiment, any of VMs 3304A-3304C may perform compute operations concurrently with its own rendering operations via CCSn 2718, or during a rendering operation being performed by another VM.

[0368] Figure 35 3500 of performing engine-based virtualization of an accelerator device according to an embodiment. The method 3500 may be performed by engine-based virtualization logic that includes virtualization hardware and scheduling logic of the accelerator device. In one embodiment, as Figure 27 As shown in , at least a portion of the scheduling logic and virtualization hardware may reside within the graphics microcontroller 2761.

[0369] The engine-based virtualization logic can configure the engines of the accelerator device to be independently assigned during time-sharing virtualization (3502). In one embodiment, independent assignment of the engines of the accelerator device is achieved by assigning interfaces to different VFs or otherwise enabling the engine front end, command queue, and / or command stream converter to be independently assigned to VMs. For example, similar to how CCSs are assigned to different VMs to enable adaptive virtualization of GPU cores, RCS2716 can be dynamically reassigned after a VM completes a rendering operation but before the VM's time slice is completed.

[0370] When the engine-based virtualization logic receives a first workload to be executed on behalf of the first VM and a second workload to be executed on behalf of the second VM, method 3500 continues (3504). For example, the workload can be received at a scheduler 3305, which can be included in the graphics microcontroller 2761. The scheduler can assign the first part of the first workload to the first accelerator engine (3506) during the first part of the time slice of the first VM. For example, for a 3D rendering or gaming application executed in the first VM, the first part of the first workload can be a rendering workload assigned to the rendering engine of the accelerator device. The scheduler can then assign the second part of the first workload to the second accelerator engine (3508) during the second part of the time slice of the first VM. For a cloud gaming server executed in the first VM, the second part of the first workload can be an encoding workload for encoding rendered frames for transmission to the client of the cloud gaming server. For a 3D rendering or gaming application executing in a VM on the client, the second portion of the workload may be a post-processing workload performed via a video enhancement engine, or matrix operations performed for an AI anti-aliasing, scaling, supersampling, or frame generation engine. In another configuration, a VM-based cloud gaming client executing in a first VM may perform video decoding operations using a video decoding engine during a first portion of the first VM's time slice, and then perform rendering operations via a rendering engine, perform video enhancement operations via a video enhancement engine, or perform matrix operations for an AI anti-aliasing, scaling, supersampling, or frame generation engine.

[0371] Independent engine virtualization enables the scheduler to assign a first portion of the second workload to the first accelerator engine during a first portion of a time slice of the second VM, the first portion of the time slice of the second VM being concurrent with a second portion of the time slice of the first VM (3510). Once the first VM no longer requires use of the first accelerator engine, the first accelerator engine can be immediately assigned to perform operations for the second VM, thereby allowing the time slices of the first VM and the second VM to overlap.

[0372] Described above is an engine-based time-slicing virtualization method in which an accelerator engine can be reassigned between VMs once a VM completes operation on the engine and before the VM time slice is completed. One embodiment provides a graphics processor comprising a rendering engine, multiple media engines, and a microcontroller, the microcontroller including a scheduler configured to schedule workloads received from multiple guest software environments to the rendering engine and the multiple media engines at a per-engine granularity.

[0373] In one embodiment, a scheduler is configured to enable time-sharing virtualization of a rendering engine and a plurality of media engines, and the scheduler is configured to: receive a first workload to be executed on behalf of a first guest software environment and a second workload to be executed on behalf of a second guest software environment; schedule a first portion of the first workload to the rendering engine during a first virtualization time slice; and after the rendering engine completes the first portion of the first workload and before completion of the first virtualization time slice, schedule the first portion of the second workload to the rendering engine to begin a second virtualization time slice, the second virtualization time slice overlapping the first virtualization time slice. In one embodiment, the scheduler is configured to: schedule the second portion of the first workload to a first media engine among the plurality of media engines before completion of the first virtualization time slice; and after the rendering engine completes the first portion of the second workload and before completion of the second virtualization time slice, schedule the second portion of the second workload to a second media engine among the plurality of media engines.

[0374] In one embodiment, the graphics processor includes multiple processing resources, the multiple processing resources including single instruction multiple data (SIMD) processing resources, and can be configured to support a single instruction multiple thread (SIMT) execution mode. The multiple processing resources are configured to execute instructions on behalf of the rendering engine. In one embodiment, the graphics processor includes multiple compute engines, and the multiple processing resources are configured to execute instructions on behalf of the multiple compute engines. The scheduler can be configured to: receive a third workload to be executed on behalf of a third guest software environment and a fourth workload to be executed on behalf of a fourth guest software environment; schedule a first portion of the third workload to a first compute engine of the multiple compute engines within a third virtualization time slice; and concurrently schedule a first portion of the fourth workload to a second compute engine of the multiple compute engines within the third virtualization time slice. The multiple guest software environments can include virtual machines or containers.

[0375] One embodiment provides a method comprising: configuring engines of an accelerator device for independent assignment during time-sharing virtualization; receiving a first workload to be executed on behalf of a first guest software environment and a second workload to be executed on behalf...

Claims

1. A graphics processor, comprising: Memory interface; Multiple interfaces to multiple computing engines; a processing resource cluster, the processing resource cluster comprising a plurality of processing resources configured to execute instructions on behalf of the plurality of computing engines; as well as A virtualization circuit configured to enable time-sharing virtualization of the plurality of processing resources via the plurality of compute engines, wherein the virtualization circuit is configured to concurrently process workloads from a plurality of guest software environments during time slices by dynamically assigning the workloads to the plurality of interfaces to the plurality of compute engines.

2. The graphics processor according to claim 1, wherein: The virtualization circuit is configured to: assigning a first slice of the plurality of processing resources to a first interface; assigning a second slice of the plurality of processing resources to a second interface; processing a first workload from a first guest software environment on the first slice of the plurality of processing resources via the first interface; and A second workload from a second guest software environment is concurrently processed on the second slice of the plurality of processing resources via the second interface.

3. The graphics processor according to claim 2, wherein: The first interface includes a first command stream converter, which is configured to send a command stream to a first computing engine among the multiple computing engines, and the second interface includes a second command stream converter, which is configured to send a command stream to a second computing engine among the multiple computing engines.

4. The graphics processor according to claim 3, wherein: The first compute engine is used to process the first workload from the first guest software environment via the first slice of the plurality of processing resources, and the second compute engine is used to process the second workload from the second guest software environment via the second slice of the plurality of processing resources.

5. The graphics processor according to claim 4, wherein: The virtualization circuitry is configured to process the first workload from the first guest software environment and the second workload from the second guest software environment during a first virtualization time slice.

6. The graphics processor according to claim 5, wherein: The virtualization circuitry is configured to assign a third slice of the plurality of processing resources to the first interface in response to an increase in workload demand associated with the first guest software environment.

7. The graphics processor according to claim 6, wherein: During a second virtualization time slice, the virtualization circuit is configured to: processing a third workload from the first guest software environment on the first slice of the plurality of processing resources and the third slice of the plurality of processing resources via the first interface; as well as A fourth workload from the second guest software environment is concurrently processed on the second slice of the plurality of processing resources via the second interface.

8. The graphics processor according to claim 7, wherein: The third slice of the plurality of processing resources includes a smaller number of processing resources relative to the first slice and the second slice.

9. The graphics processor according to claim 7, wherein: The first guest software environment and the second guest software environment include virtual machines or containers.

10. The graphics processor according to any one of claims 1 to 9, wherein: The plurality of processing resources include single instruction multiple data (SIMD) processing resources and are configurable to support a single instruction multiple thread (SIMT) execution mode.

11. A method comprising: assigning a first slice of a plurality of processing resources of an accelerator device to a first interface of a plurality of compute engines of the accelerator device; assigning a second slice of the plurality of processing resources of the accelerator device to a second interface of the plurality of compute engines of the accelerator device; processing a first workload from a first guest software environment on the first slice of the plurality of processing resources via the first interface; and A second workload from a second guest software environment is concurrently processed on the second slice of the plurality of processing resources via the second interface.

12. The method of claim 11, comprising: Time-division virtualization of the plurality of processing resources is enabled via the plurality of compute engines, the time-division virtualization being enabled via virtualization circuitry of the accelerator device.

13. The method of claim 12, comprising: The first workload and the second workload are processed during a first virtualization time slice.

14. The method of claim 13, comprising: A third slice of the plurality of processing resources is dynamically assigned to the first interface, and a third workload from the first guest software environment is processed on the first slice and the third slice via the first interface.

15. The method of claim 14, comprising: During a second virtualization time slice, the third workload is processed concurrently with processing a fourth workload from the second guest software environment.

16. A system comprising means for performing the method according to any one of claims 11 to 15.

17. A data processing system comprising: one or more processors configured to perform operations associated with the first guest software environment and the second guest software environment; as well as An accelerator device is coupled to the one or more processors, the accelerator device comprising a rendering engine, a plurality of media engines, and a microcontroller, the microcontroller comprising a scheduler configured to schedule workloads received from a plurality of guest software environments to the rendering engine and the plurality of media engines at a per-engine granularity, wherein the scheduler is configured to enable time-division virtualization of the rendering engine and the plurality of media engines.

18. The data processing system according to claim 17, wherein: The scheduler is configured to: receiving a first workload to be executed on behalf of a first guest software environment and a second workload to be executed on behalf of a second guest software environment; During a first virtualized time slice, scheduling a first portion of the first workload to the rendering engine; as well as After the first portion of the first workload is completed by the rendering engine and before completion of the first virtualization time slice, the first portion of the second workload is scheduled to the rendering engine to start a second virtualization time slice, the second virtualization time slice overlapping the first virtualization time slice.

19. The data processing system of claim 18, wherein: The scheduler is configured to: Prior to completion of the first virtualized time slice, scheduling a second portion of the first workload to a first media engine of the plurality of media engines; as well as After the first portion of the second workload is completed by the rendering engine, a second portion of the second workload is scheduled to a second media engine of the plurality of media engines before completion of the second virtualized time slice.

20. The data processing system of claim 19, comprising a plurality of processing resources, wherein The plurality of processing resources include single instruction multiple data (SIMD) processing resources and are configurable to support a single instruction multiple thread (SIMT) execution mode.

21. The data processing system of claim 20, wherein: The plurality of processing resources are configured to execute instructions on behalf of the rendering engine.

22. The data processing system of claim 21, comprising a plurality of computing engines, wherein: The plurality of processing resources are configured to execute instructions on behalf of the plurality of compute engines.

23. The data processing system of claim 22, wherein: The scheduler is configured to: receiving a third workload to be executed on behalf of a third guest software environment and a fourth workload to be executed on behalf of a fourth guest software environment; scheduling a first portion of the third workload to a first computing engine of the plurality of computing engines within a third virtualized time slice; as well as A first portion of the fourth workload is concurrently scheduled to a second compute engine of the plurality of compute engines within the third virtualization time slice.

24. The data processing system according to any one of claims 17 to 23, wherein: The plurality of guest software environments include virtual machines or containers.

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