IO scheduling method and device for operating IO scheduling method

Abstract

The invention provides an IO scheduling method and a device for operating the IO scheduling method. A device connected to a host device through a CXL protocol includes a device memory storing a query schedule and a query plan status message synchronized with the host device, and a device processor processing a task according to the query schedule, and update the query plan state information upon receiving an operation command from the host device.

Description

Technical Field

[0001] The present invention relates to an I / O (Input / Output) scheduling method in a query processing device. Background Art

[0002] A host device can provide commands (e.g., read and write commands) for processing to multiple devices. The host device can perform database scanning operations. The host device uses queries to request or manipulate information in a database. For example, the host device inputs and outputs data to read and write data that meets the query criteria in the database.

[0003] However, when it takes a long time to load or process data requested by one of the plurality of devices, there is a difficulty in that task execution proceeding to the next stage may be delayed, and thus the overall command execution thereof may be delayed. Summary of the Invention

[0004] Aspects of the present invention provide an I / O scheduling method and apparatus thereof for improving operation performance.

[0005] According to aspects of the present disclosure, a device connected to a host device via a CXL protocol is provided, the device including: a device memory storing a query plan table and query plan status information synchronized with the host device; and a device processor processing tasks according to the query plan table and updating the query plan status information upon receiving an operation command from the host device.

[0006] According to aspects of the present disclosure, a host device connected to multiple devices via a CXL protocol is provided, the host device including: a host memory storing query plan status information synchronized with the multiple devices; and a host processor sending an operation command to any one of the multiple devices based on the query plan status information.

[0007] According to another aspect of the present disclosure, an I / O scheduling method between a host device and multiple devices is provided, and the I / O scheduling method includes: the host device checks query plan status information about the multiple devices; the host device sends an operation command to any one of the multiple devices based on the query plan status information; the device that has received the operation command updates the task corresponding to the operation command to a pre-stored query plan table; the device that has received the operation command executes the task according to the updated query plan table, and replies to the host device with the updated content of the query plan status information.

[0008] However, the various aspects of the present invention are not limited to the aspects set forth herein. The above and other aspects of the present invention will become more apparent to those skilled in the art to which the present invention pertains by referring to the detailed description of the present invention given below.

[0009] The I / O scheduling method and device of the present invention can reduce frequent I / O commands and significantly reduce the bottleneck phenomenon of the I / O channel.

[0010] The I / O scheduling method and device of the present invention can ensure the resources of the host device and effectively manage each device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 and Figure 2 This diagram is a conceptual diagram used to explain the bottleneck phenomenon of the I / O interface.

[0012] Figure 3 and Figure 4 is a block diagram for explaining an I / O scheduling system according to some embodiments.

[0013] Figure 5 is a block diagram for explaining I / O scheduling operations according to some embodiments.

[0014] Figure 6 is a table used to explain query plan state information according to some embodiments.

[0015] Figure 7 is a table explaining a query plan table for each device according to some embodiments.

[0016] Figure 8 is a flowchart for explaining an I / O scheduling method according to some embodiments. DETAILED DESCRIPTION

[0017] Below, we will refer to Figures 1 to 8 An I / O scheduling method and apparatus thereof according to some embodiments of the present invention are described.

[0018] Figure 1 and Figure 2 This is a conceptual diagram used to explain the bottleneck phenomenon of I / O interfaces. A single query is executed through multiple stages, where each stage handles at least one task. Each stage is implemented by dividing the entire task for executing the query according to each of the arbitrary functions and purposes.

[0019] refer to Figure 1, the host can read data from various storage devices in a desired format. For example, assume that data p is read from a plurality of blocks included in the storage device in stage 0, and data p is read from a plurality of blocks included in the storage device in stage 1. This example also assumes that the data p read in stages 0 and 1 are received in stage 2, the received data p undergoes processing such as addition, filtering, or selection to generate data r, and the data r is stored.

[0020] Assume that a first time to read data p stored in any block in stage 1 is much slower than a second time to read data p in stage 0, and much slower than a third time to read data p stored in the remaining blocks in stage 1. In this case, the time required to generate data r in stage 2 is determined based on the first time. That is, when data loading in a specific block is significantly slower than data loading in other blocks, it can be considered that a data I / O bottleneck has occurred due to the specific block.

[0021] refer to Figure 2 For example, in stage 1, task A is grouped into task B (group). In stage 2, data on task C is mapped to data on task D, and data on task F is generated by combining task D and task E. In stage 3, data on task G is generated by merging data on task F and data on task B. That is, in order to obtain the data for stage 3, the data for stages 1 and 2 should be provided simultaneously or at close times. However, since stage 2 has more tasks than stage 1, more processing may be required to obtain tasks C, D, E, and F, and subsequent data loading may be further delayed. The data processing of task G may be delayed depending on the processing in stage 2. That is, stage 2 may cause a bottleneck phenomenon.

[0022] In the bottleneck phenomenon, such as Figure 1 and Figure 2 As shown, the CXL interconnect becomes increasingly busy due to command I / O as the number of devices 200 connected to the host device 100 increases and / or as the complexity of the stages increases. For example, if there are 64 devices 200 connected to the host device 100, for example, 64 storage devices, 64 I / O commands are generated for each stage of the 64 storage devices. If two I / O commands, including a send and a reply, are issued in one stage for each of the 64 storage devices, a total of 128 (= 64 x 2) I / O commands may be issued. Furthermore, assuming the number of stages is 100, at least 12,800 (= 128 x 100) I / O commands will be generated in total.

[0023] 12,800 I / O commands are stacked in a command queue and can then be transmitted in any specified manner, such as FIFO (first-in, first-out). However, if the processing time of a particular stage increases, the processing speed of another stage may also be delayed. To alleviate this bottleneck phenomenon, more efficient I / O scheduling between the host and the device is required.

[0024] Figure 3 and Figure 4 is a block diagram illustrating an I / O scheduling system according to some embodiments.

[0025] refer to Figure 3 and Figure 4 The I / O scheduling system may include a host device 100 and multiple devices (device 1 to device N, 201 to 204; 200). Multiple devices 200 may be connected to the host device 100 via a CXL (Compute Express Link) interface. Device 200 may be, for example, a storage device such as a database.

[0026] Host device 100 may include a host processor 110, a host memory 120, and a host interface 130. Host processor 110 may be, for example, a general-purpose processor, such as a central processing unit (CPU) core of host device 100. Host memory 120 may include, for example, random access memory (RAM) (e.g., dynamic random access memory (DRAM)), read-only memory (ROM), etc. Host interface 130 may communicate with device 200. For example, host interface 130 may include a CXL interface.

[0027] The host memory 120 may store query plan status information, which may include the task progress status of each query, the current progress stage, the progress status of each device, the delay time, etc.

[0028] Device 200 may include a device controller 210, a device memory 220, and a device interface 230. Device controller 210 may be a processor, such as a regional processing unit core. Device memory 220 may include, for example, random access memory (RAM) (e.g., dynamic random access memory (DRAM)), read-only memory (ROM), etc. Device interface 230 may be capable of communicating with host device 100. For example, device interface 230 may include a CXL interface.

[0029] The device memory 220 can store query plan status information (QS). Figure 5 The device memory 220 may also include a query plan table. Figure 6 Explain query plan tables in more detail.

[0030] Communications may be performed using wired and / or wireless communication media, interfaces, networks, interconnects, protocols, etc. These may include coherent protocols such as PCIe (Peripheral Component Interconnect Express), NVMe (Non-Volatile Memory Express), NVMe-oF (NVMe over Fabric), CXL (Compute Express Link), and / or CXL.mem, CXL.cache, and CXL.IO, Gen-Z, OpenCAPI (Open Coherent Accelerator Processor Interface), CCIX (Cache Coherent Interconnect for Accelerators), AXI (Advanced Extensible Interface), DMA (Direct Memory Access), RDMA (Remote DMA), ROCE (RDMA over Converged Ethernet), AMQP (Advanced Message Queuing Protocol), Ethernet, TCP / IP (Transmission Control Protocol / Internet Protocol), FibreChannel, InfiniBand, SATA (Serial ATA), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), iWARP, any generation of wireless networks including 2G, 3G, 4G, 5G, and 6G, any generation of WiFi, Bluetooth, NFC (Near Field Communication), or any combination thereof.

[0031] While the host interface 130 and the device interface 230 are not limited to any particular implementation details, for purposes of illustrating the principles of the present disclosure, they may be implemented using a CXL interconnect. The CXL interconnect is an open industry-standard interconnect that provides high-bandwidth, low-latency connectivity between the host processor 110 and devices 200, such as intelligent I / O devices, accelerators, and memory buffers. The CXL interconnect implements cache coherence and memory semantics for multi-dimensional processing and memory systems to optimize performance in evolving usage models. Additionally, the CXL interconnect can support cache line segmentation, i.e., 64-byte memory accesses, and can support switching that allows fan-out to many devices, which may be useful for memory expansion. The host interface 130 can connect to the device 200, for example, via the CXL.mem protocol, the CXL.cache protocol, and the CXL.io protocol.

[0032] The CXL.cache protocol is a link that allows device 200 to access host memory 120, while the CXL.mem protocol is a link that allows host 100 to access device memory 220. The CXL.io protocol is based on the PCIe (Peripheral Component Interconnect Express) specification and is a link related to device discovery, configuration, register access, suspend, etc.

[0033] Figure 5 is a block diagram illustrating I / O scheduling operations according to some embodiments, and Figure 6 is a table showing query plan status information according to some embodiments. Figure 7is a table showing a query plan table for each device according to some embodiments.

[0034] refer to Figure 5 , the host device 100 sends a query to the device 200 requesting information or manipulation. To send the query, the host device 100 controls the query transmission for each phase and device by referring to the query plan status information QS. For example, when task processing of at least one device X among the multiple devices 200 is delayed in phase K (M is a natural number of two or more) among M phases, the host device 100 may execute other tasks that can be combined by referring to the query plan status information (QS). The other tasks that can be combined may belong to the same phase K, or may belong to another phase L that can be processed in parallel with phase K.

[0035] Host device 100 stores the query plan state information in host memory 120. Device 200 may synchronously store the query plan state information QS stored in device memory 220 in host memory 120 through the CXL.cache protocol.

[0036] Device 200 can store query plans QP in device memory 220. Query plans QP are managed independently for each device. That is, query plan QP1 for the first device (Device 1) 201 is different from query plan QP2 for the second device (Device 2) 202. In other words, because query plans are managed within device 200, they are not intermingled with progress information regarding queries from other devices and are not stored within host device 100. This allows for more efficient use of host memory 120 resources.

[0037] The host device 100 may learn the expected time (or waiting time) required for each device's task by synchronously querying the plan status information, and may execute other tasks based on the expected waiting time.

[0038] According to some embodiments, the device controller 210 (e.g., the device processor) updates the query plan status information of the device memory 220 after executing a task, and then transmits the updated query plan status information to the host device 100. According to some embodiments, the device 200 may transmit the query plan status information to the host device 100 each time the query plan status information is updated, may periodically transmit the query plan status information to the host device 100, or may transmit the query plan status information to the host device 100 upon request by the host device 100.

[0039] refer to Figure 6The query plan status information QS synchronized between the host device 100 and the device 200 includes factors that affect the query execution speed between the host device 100 and the device 200. For example, the query plan status information QS may include the task progress status of each query (indicated by the field "Stage"), the current progress stage (indicated by the field "Progress"), the progress status (or progress stage) of each device (indicated by the field "Device"), the delay time (indicated by the field "Delay"), etc.

[0040] The task progress status is displayed for each of a plurality of stages (e.g., 1 through 7). The current progress stage is indicated by the "True" field when all tasks in that stage have been completed or are being processed, and by the "False" field before the first task in that stage begins processing. The progress status of each device is represented by a binary symbol for each device, including a "1" indication when processing is complete and a "0" indication before processing is complete. The delay time indicates the remaining time until the tasks in that stage are completed, based on the expected processing wait time of each task in that stage.

[0041] Figure 6 The figure shows a case where seven devices 200 are connected to the host device 100. The progress status of the device 200 can be represented by binary symbols (such as 0000000 to 1111111). For example, when the stage is completed, it can be represented by 1, and before processing or in an unfinished state, it can be represented by 0.

[0042] During the task progress stage, in the query plan status information QS of Stage 1 , when progress in all devices is completed, the progress status of each device may be indicated by 1111111, the current progress stage (Progress) may be indicated by True, and the delay time may be indicated by 0.

[0043] During the task progress stage, since the query plan status information QS of stage 2 (Stage 2) is currently in progress, the current progress stage (Process) is indicated by True, when the progress in any one device is not completed, for example, when the task of the fourth device is not completed, it can be indicated by 1110111, and the waiting time until the task of the fourth device is completed and all tasks of Stage 2 are completed can be indicated by 10 seconds (10s).

[0044] Since Stage 3 to Stage 7 after Stage 2 occur before task processing starts, the current progress status (Progress) is indicated by False. The progress status and delay time of each device can be set to Null.

[0045] As described above, since the host device 100 stores the synchronized query plan status information QS in the host memory 120, the stage progress status and processing status of each device 200 can be known. Figure 6 The delay time of the fourth device in the example shown is 10 seconds, and the host device 100 can control the device 200 to perform other tasks that can be processed in parallel or pre-processed.

[0046] refer to Figure 5 and Figure 7 Each device 200 stores its query plan table QP. The device controller 210 (e.g., a device processor) processes tasks according to the query plan table QP stored in the device memory 220 and updates the query plan status information QS after processing the tasks. Therefore, the host device 100 can manage the query plan table (e.g., QP1 and QP2) of each device using the query plan status information QS.

[0047] The query plan table QP may include, for example, a stage, a local stage progress, an input address, an output address, and a calculation level. Stage is the stage level of the query and can be reference information used for synchronization with the query plan status information QS. The local stage progress indicates the internal stage progress of each device 200 among all stages, the input address indicates the address of the device memory 220 read by the query request, and the output address indicates the address of the host memory 120 to which the data read from the device memory 220 is to be output. The calculation level indicates the stage at which calculations are performed.

[0048] For example, in Stage 1, when the internal stage processing of the first device 201 is three stages in total and one stage is currently in progress, the first device 201 indicates the local stage progress as "001." The input address and the output address may be determined as an address range of 0 for the first stage, an address range of 1 for the second stage, and an address range of 2 for the third stage, among the three stages.

[0049] The input address indicates an address in the device memory 220 to be read based on the progress stage of the local phase progress. For example, since the current local phase progress is in the first stage, the input address is within the address range of 0 (0x00 to 0x20), and the device controller 210 (e.g., the device processor) can read the query-requested data in 0x00 to 0x20 of the device memory 220.

[0050] The output address indicates the address of the host memory 120 to be output based on the progress stage of the local phase progress. For example, since the current local phase progress is in the first stage, the output address is within the address range of 0 (0x900 to 0x920), and the device controller 210 (e.g., the device processor) outputs the data read through the CXL.mem protocol within the address range of 0 of the host memory 120.

[0051] The calculation level may be indicated as “100” to execute the accelerator third among a total of three local stage schedules. For example, the latency of the query plan state information may be calculated based on the calculation level.

[0052] Figure 8 1 is a flowchart illustrating an I / O scheduling method according to some embodiments. For ease of explanation, although the I / O scheduling method between the host device 100 and the first device 201 will be described below, the method is applicable to Figure 3 All devices described in.

[0053] The host device 100 and the first device 201 synchronize query plan status information QS via the CXL.cache protocol ( S10 ). Step S10 may be performed after the host device 100 and the first device 201 are booted, or after step S13 .

[0054] The host device 100 checks the query plan status information of each device 200 (S11). Based on the query plan status information QS, the host device 100 sends an operation command to the first device 201 capable of parallel processing during a delay period (S12). When the first device 201 receives the operation command (S21), it checks the query plan table QP1 of the first device (S22) and updates the task corresponding to the operation command in the query plan table (S23). The first device 201 updates the query plan status information QS based on the updated query plan table QP1 and responds to the host device 100 with the updated information (S24). The first device 201 executes the assigned task based on the query plan table QP1 (S25), and the host device 100 updates the query plan status information (S13) by reflecting the responded update information in the stored query plan status information.

[0055] As shown in the example, since the device 200 operates based on the query plan table QP, it can predict the use of query processing and prepare task processing, and the host device 100 can control the number of I / O commands of the network interface of the device while efficiently processing queries only based on the query plan state information QS. Therefore, it is possible to save host memory resources and reduce the network complexity of the device.

[0056] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms. It will be understood by those skilled in the art that the present invention can be embodied in other specific forms without changing the technical spirit or basic characteristics of the present invention. Therefore, the above embodiments should be understood in all aspects as illustrative and not restrictive.

Claims

1. A device connected to a host device via a CXL protocol, the device comprising: a device memory storing a query plan table and query plan status information synchronized with the host device; as well as A device processor processes tasks according to the query plan table and updates the query plan status information when receiving an operation command from the host device.

2. The device according to claim 1, in, The updated query plan state information is sent to the host device via the CXL.cache protocol.

3. The device according to claim 1, in, The query plan table is stored and updated in the device memory according to the CXL.mem protocol.

4. The device according to claim 1, in, The query plan status information includes task progress status, current progress stage, progress stage of each device, and delay time.

5. The device according to claim 1, in, The query plan table includes a phase of each query of the device, a local phase schedule, an input address of a memory of the device, an output address of a host memory of the host device, and a calculation level.

6. The device according to claim 5, in, The local phase progress indicates the progress stage of the internal phase of the device in each queried phase.

7. The device according to claim 6, in, The input address and the output address are determined based on a progress stage of the local stage progress.

8. A host device connected to a plurality of devices via a CXL protocol, the host device comprising: a host memory storing query plan status information synchronized with the plurality of devices; as well as A host processor is configured to send an operation command to any one of the plurality of devices based on the query plan status information.

9. The host device according to claim 8, in, The query plan status information includes the task progress status, current progress stage, progress status of the device, and delay time of the query request of each device by the host device.

10. The host device according to claim 8, in, The device that receives the operation command updates the task corresponding to the operation command to a query plan table pre-stored in the device, and executes the assigned task based on the query plan table.

11. The host device according to claim 10, in, The query plan table includes the phase of each query of the device, the local phase progress, the input address of the device memory, the output address of the host memory, and the calculation level.

12. The host device according to claim 10, in, The host device receives updated content regarding the updated query schedule from the device.

13. The host device according to claim 12, in, The query plan status information is received via the CXL.cache protocol.

14. The host device according to claim 11, in, The device accesses an output address of the host memory determined based on a progress stage of the local stage progress.

15. A method for I / O scheduling between a host device and a plurality of devices, the method comprising: checking, by the host device, query plan status information about the plurality of devices; The host device sends an operation command to any one of the plurality of devices based on the query plan status information; The device that has received the operation command updates the task corresponding to the operation command to a pre-stored query plan table; and The device that has received the operation command executes the task according to the updated query plan table and replies to the host device with the updated content of the query plan status information.

16. The I / O scheduling method according to claim 15, in, The query plan status information of the host device is updated and synchronized with the multiple devices through the CXL.cache protocol.

17. The I / O scheduling method according to claim 15, in, The query plan status information includes the task progress status, current progress stage, progress status of the device, and delay time of the query request of each device by the host device.

18. The I / O scheduling method according to claim 17, in, The host device selects any one of the plurality of devices based on the delay time and transmits the operation command to the any one device to process a task or stage that can be combined among the plurality of stages.

19. The I / O scheduling method according to claim 15, in, The query plan table is stored in a device memory belonging to each of the plurality of devices according to a CXL.mem protocol.

20. The I / O scheduling method according to claim 19, in, The query plan table includes the phase of each query, local phase progress, input address of the device memory, output address of the host memory, and calculation level.

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