Differential bus transmission verification system based on digital ink-jet printer and printer

Abstract

The invention discloses a differential bus transmission verification system based on a digital ink-jet printer and a printer, and relates to the technical field of printing equipment data transmission, the system comprises a first main control module, a second main control module, 14 pairs of differential signal lines, a downlink channel and an uplink channel, a dynamic verification module adjusts the bit width of a verification code according to the type of a data packet, and the downlink adopts an enhanced CRC algorithm. An odd-even, accumulation and combination algorithm is used for uplink, the algorithm can be switched and retransmission is carried out when continuous error data packets are encountered; a time sequence control module is used for measuring transmission delay, adjusting a clock phase and guaranteeing transmission accuracy; a self-defined bus protocol is divided into three layers; a data packet structure and printing instruction analysis are stipulated; the system has an exception handling mechanism, speed reduction, redundant channel cutting, error recording and diagnosis report generation are performed when verification fails and exceeds a threshold value, a differential signal line is of a twisted-pair structure, signal stability is ensured, and the system is used for connecting a printer with a printing head drive and a motion platform and transmitting a control instruction to ensure reliable and stable data transmission.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission of printing equipment, and more particularly to a differential bus transmission verification system based on a digital inkjet printer and a printer. Background Art

[0002] In the field of modern digital inkjet printers, with the continuous improvement of printing accuracy and speed, the performance requirements for data transmission between main control chips are becoming more and more stringent. Traditional bus communication technologies mostly use TTL level single IO signal transmission and realize data exchange through parallel port data transmission mode. However, this method is easily interfered by external signals, resulting in poor data transmission stability and difficulty in meeting the data accuracy requirements of high-precision printing tasks. At the same time, the traditional CRC verification algorithm commonly used in the existing technology has obvious disadvantages. Its verification efficiency is low and there is a certain risk of missed detection. It cannot provide solid and reliable protection for data transmission in complex working conditions and high data flow printing scenarios. This may not only affect the printing quality, but also cause System failures have restricted the further improvement of printer performance and the expansion of its application in the high-end printing market. In addition, traditional bus designs lack flexibility and intelligence in timing control, and are difficult to adapt to signal timing changes under different transmission distances and working conditions, which in turn affects the real-time and accuracy of data transmission. To address the above problems, a new differential bus transmission verification system is urgently needed to optimize the signal transmission mode, improve verification efficiency, and enhance timing control capabilities, so as to meet the development needs of digital inkjet printers in future high-performance printing tasks, promote the continuous advancement of printer technology in the direction of high reliability and high efficiency, and better adapt to the complex application environment of intelligent industrial production and refined office printing scenarios.

[0003] Therefore, existing printing transmission verification technology has problems such as poor anti-interference, low verification efficiency, and inflexible timing adjustment. Summary of the Invention

[0004] In order to overcome the problems of poor anti-interference, low verification efficiency, inflexible timing adjustment and other problems in the existing printing transmission verification technology, the present invention discloses a differential bus transmission verification system based on a digital inkjet printer, which can effectively solve the above technical problems.

[0005] In order to solve the above technical problems, the technical solutions of the present invention are as follows:

[0006] A differential bus transmission verification system based on a digital inkjet printer includes: a first main control module and a second main control module;

[0007] The differential bus transmission channel includes 14 pairs of differential signal lines, of which 8 pairs constitute the downlink channel from the first main control module to the second main control module, and 6 pairs constitute the uplink channel from the second main control module to the first main control module;

[0008] A dynamic check module, embedded in the first main control module and the second main control module, is used to generate an adaptive check code during data transmission, wherein the bit width of the adaptive check code is dynamically adjusted according to the type of the current transmission data packet;

[0009] The timing control module is connected to the differential bus transmission channel to monitor the signal transmission delay in real time and automatically adjust the clock phase offset;

[0010] The protocol parsing engine executes the custom bus protocol, encapsulates the printing instruction data into a data packet with a checksum, and transmits it bidirectionally through the differential bus transmission channel.

[0011] Preferably, the downlink channel is implemented using a first type differential driver chip, and the first type differential driver chip is SN65LVDS047ADR;

[0012] The uplink channel is implemented using a second type differential driver chip, which is SN65LVDS048ADR.

[0013] Preferably, the dynamic verification module performs the following operations:

[0014] Generate a first check code using an enhanced CRC algorithm for downlink channel data;

[0015] A parity check and cumulative sum combination algorithm is used to generate a second check code for the uplink channel data;

[0016] When continuous error packets are detected, the verification algorithm is automatically switched and data retransmission is triggered.

[0017] Preferably, the enhanced CRC algorithm includes: initializing the polynomial to ; Append a dynamic salt value to the end of the data packet, the salt value is generated by hashing the data packet length and the transmission timing parameters.

[0018] Preferably, the timing control module comprises: a delay locked loop circuit for measuring the transmission delay of the signal in the differential channel in real time; and a clock phase compensator for adjusting the transmission end clock to advance or lag according to the measurement result.

[0019] Preferably, the hierarchical structure of the custom bus protocol includes: physical layer: defining the voltage swing and impedance matching requirements of the differential signal; data link layer: stipulating that the data packet structure includes a header identifier, an instruction type field, a data length field, a check code field and payload data; application layer: parsing printing instructions into nozzle control parameters, ink volume control parameters and motion control parameters.

[0020] Preferably, the protocol parsing engine performs the following operations for different transmission directions when encapsulating data packets:

[0021] Adding a first direction identifier to the downlink channel data and activating a downlink check code generation unit;

[0022] A second direction identifier is added to the uplink channel data, and an uplink check code generation unit is activated.

[0023] Preferably, an exception handling mechanism is also included: when the number of verification failures exceeds a threshold, the transmission rate is automatically reduced and switched to a redundant channel transmission mode; the characteristic vector of the error data packet is recorded and a fault diagnosis report is generated.

[0024] Preferably, the differential signal line adopts a twisted pair structure: the line pair spacing is 0.8mm±0.1mm; the single wire diameter is 30AWG, covered with a double shielding layer; the impedance is controlled at 100Ω±5%.

[0025] Preferably, a digital inkjet printer includes a print head, an ink cartridge and a motion platform, and also includes: a differential bus transmission verification system as described above; a first main control module is connected to the print head drive circuit, and a second main control module is connected to the motion control platform; the differential bus transmission system transmits printing control instructions.

[0026] Compared with the prior art, the beneficial effects of the present invention are as follows: the traditional printing transmission verification technology often causes data errors due to environmental electromagnetic interference. The present invention adopts a differential bus transmission channel, which contains 14 pairs of differential signal lines. The differential signal has anti-interference characteristics and can effectively resist external electromagnetic interference. At the same time, the downlink channel adopts the SN65LVDS047ADR chip and the uplink channel adopts the SN65LVDS048ADR chip. These chips have excellent signal driving ability and stability, which enhances the reliability of signal transmission and reduces the data error rate caused by interference. The verification efficiency of the prior art is low and it is difficult to meet the needs of high-speed data transmission. The dynamic verification module in the solution can adaptively adjust the verification code bit width and flexibly match the verification strength according to different data packet types, avoiding the redundancy or insufficiency of the fixed verification method and improving the downlink data transmission efficiency. The enhanced CRC algorithm is adopted, and its complex mathematical characteristics make the verification more accurate; the parity check and cumulative sum combination algorithm is adopted for the uplink data, which is simple to calculate and can quickly verify the integrity of the data. This targeted verification method improves the verification efficiency and ensures the fast and accurate transmission of the printing instruction data; the timing adjustment of the traditional verification technology is not flexible, and often causes data synchronization problems due to transmission delays. The timing control module of this solution includes a delay locked loop circuit and a clock phase compensator. The delay locked loop circuit can measure the transmission delay of the signal in the differential channel in real time, and the clock phase compensator adjusts the sending end clock to advance or lag according to the measurement results. This combination of real-time monitoring and dynamic adjustment ensures the timing accuracy of data transmission, effectively solves the synchronization problem caused by transmission delay, and improves the overall performance and stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the implementation methods of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the implementation methods or the description of the prior art. Obviously, the drawings described below are merely exemplary. For ordinary technicians in this field, other implementation drawings can be derived based on the provided drawings without any creative work.

[0028] Figure 1 This is a system architecture diagram of the present invention;

[0029] Figure 2 This is a flow chart of the system of the present invention;

[0030] Figure 3 This is a data transmission verification flow chart of the present invention. DETAILED DESCRIPTION

[0031] The accompanying drawings are for illustrative purposes only and are not to be construed as limiting this patent;

[0032] In order to better illustrate this embodiment, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product size;

[0033] It is understandable to those skilled in the art that some well-known structures and descriptions thereof may be omitted in the drawings.

[0034] The technical solution of the present invention is further described below with reference to the accompanying drawings and embodiments.

[0035] Example

[0036] A differential bus transmission verification system based on a digital inkjet printer includes: a first main control module and a second main control module;

[0037] The differential bus transmission channel includes 14 pairs of differential signal lines, of which 8 pairs constitute the downlink channel from the first main control module to the second main control module, and 6 pairs constitute the uplink channel from the second main control module to the first main control module;

[0038] A dynamic check module, embedded in the first main control module and the second main control module, is used to generate an adaptive check code during data transmission, wherein the bit width of the adaptive check code is dynamically adjusted according to the type of the current transmission data packet;

[0039] The timing control module is connected to the differential bus transmission channel to monitor the signal transmission delay in real time and automatically adjust the clock phase offset;

[0040] The protocol parsing engine executes the custom bus protocol, encapsulates the printing instruction data into a data packet with a checksum, and transmits it bidirectionally through the differential bus transmission channel.

[0041] The downlink channel is implemented using a first type differential driver chip, which is SN65LVDS047ADR;

[0042] The uplink channel is implemented using a second type differential driver chip, which is SN65LVDS048ADR.

[0043] The dynamic verification module performs the following operations:

[0044] Generate a first check code using an enhanced CRC algorithm for downlink channel data;

[0045] A parity check and cumulative sum combination algorithm is used to generate a second check code for the uplink channel data;

[0046] When continuous error packets are detected, the verification algorithm is automatically switched and data retransmission is triggered.

[0047] The enhanced CRC algorithm includes: initializing the polynomial to ; Append a dynamic salt value to the end of the data packet, the salt value is generated by hashing the data packet length and the transmission timing parameters.

[0048] The timing control module includes: a delay locked loop circuit for measuring the transmission delay of the signal in the differential channel in real time; and a clock phase compensator for adjusting the transmission end clock to advance or lag according to the measurement result.

[0049] The hierarchical structure of the custom bus protocol includes: a physical layer: defining the voltage swing and impedance matching requirements of the differential signal; a data link layer: stipulating that the data packet structure includes a header identifier, an instruction type field, a data length field, a check code field, and payload data; and an application layer: parsing printing instructions into nozzle control parameters, ink volume control parameters, and motion control parameters.

[0050] The protocol parsing engine performs the following operations for different transmission directions when encapsulating data packets:

[0051] Adding a first direction identifier to the downlink channel data and activating a downlink check code generation unit;

[0052] A second direction identifier is added to the uplink channel data, and an uplink check code generation unit is activated.

[0053] It also includes an exception handling mechanism: when the number of verification failures exceeds the threshold, the transmission rate is automatically reduced and switched to redundant channel transmission mode; the feature vector of the error data packet is recorded and a fault diagnosis report is generated.

[0054] The differential signal line adopts a twisted pair structure: the line pair spacing is 0.8mm±0.1mm; the single wire diameter is 30AWG, covered with a double shielding layer; the impedance is controlled at 100Ω±5%.

[0055] A digital inkjet printer includes a print head, an ink cartridge and a motion platform, and also includes: the differential bus transmission verification system as described above; a first main control module is connected to the print head drive circuit, and a second main control module is connected to the motion control platform; the differential bus transmission system transmits printing control instructions.

[0056] Hardware Connection

[0057] Main control module: The system consists of a first main control module and a second main control module. The first main control module is connected to the print head drive circuit and is responsible for controlling the inkjet action of the print head, ink volume adjustment and other detailed operations; the second main control module is connected to the motion control platform to control the movement of the printer's scanning mechanism to ensure precise positioning of the print head. For example, in large-format printers, the second main control module accurately controls the lateral movement of the print carriage and the longitudinal feeding of the paper. The movement accuracy can reach the micron level, providing a mechanical foundation for high-quality printing.

[0058] Differential bus transmission channel: It consists of 14 pairs of differential signal lines, of which 8 pairs build the downlink channel from the first main control module to the second main control module, and 6 pairs build the reverse uplink channel. The downlink channel uses the SN65LVDS047ADR differential driver chip, which has signal driving capabilities and can maintain signal integrity in high-speed transmission scenarios. For example, when printing high-resolution photos, it can stably transmit the printing instructions corresponding to high-definition image data; the uplink channel is equipped with the SN65LVDS048ADR differential driver chip to ensure the accurate upload of feedback data, such as the return of information such as the current status of the print head and the remaining ink level. The two work together to achieve efficient two-way data flow.

[0059] Twisted-pair cabling: Differential signal lines use a twisted-pair structure with line-pair spacing strictly controlled at 0.8mm±0.1mm. The single-wire diameter is 30AWG and is covered with a double shielding layer. The impedance is precisely matched at 100Ω±5%. This design effectively resists external electromagnetic interference. For example, printers in industrial environments may be surrounded by strong interference sources such as large motors and inverters. The twisted-pair structure ensures that printing instructions are not interfered with, and the printing tasks of complex industrial logos can be completed stably.

[0060] Software Architecture

[0061] Dynamic check module: embedded in the two main control modules, dynamically adjusts the check code width according to the type of transmitted data packet. For downlink channel data, the enhanced CRC algorithm is used to generate the first check code, and its initialization polynomial is set to , and appends a dynamic salt value generated by hashing the packet length and transmission timing parameters to the end of the data packet. Taking printing an image containing multiple color gradients as an example, the enhanced CRC algorithm can accurately detect data integrity and prevent color blocks or missing images due to data errors. Once erroneous data packets are detected continuously, the module quickly switches to the backup verification algorithm and triggers retransmission to ensure the continuous progress of the printing task.

[0062] Timing control module: tightly connected to the differential bus transmission channel, with built-in delay-locked loop circuit and phase compensator. The delay-locked loop circuit monitors the transmission delay of the signal in the differential channel in real time. When the delay exceeds the preset threshold, such as when printing data over long distances, the phase compensator adjusts the sending end clock to advance or lag according to the monitoring results to ensure that the receiving end can accurately sample the data and avoid data errors or printing jams caused by timing deviations.

[0063] The protocol parsing engine follows a custom bus protocol, which is divided into three layers. The physical layer specifies a differential signal voltage swing of ±3.3V and an impedance matching requirement of 100Ω±5%, ensuring a stable physical foundation for signal transmission. The data link layer defines the packet structure, including a header identifier (2 bytes, used to identify the start of the packet), a command type field (1 byte, such as an inkjet command or a cleaning command), a data length field (2 bytes, indicating the payload size), a checksum field (dynamically changing based on the transmission direction and data type), and payload data (flexible in length, carrying specific print command content, such as printhead drive waveform parameters). The application layer is responsible for parsing print commands into printhead control parameters, such as inkjet voltage and frequency, ink volume control parameters (single inkjet volume, droplet size), and motion control parameters (printhead movement speed, acceleration, etc.). When encapsulating data, the protocol parsing engine adds a direction identifier based on the transmission direction: 0x01 is added to downlink packets as an identifier, and 0x02 is added to uplink packets. It also activates the corresponding checksum generation unit to ensure that data is accurately and correctly transmitted between the main control module and the print actuator.

[0064] See also Figure 1-3 The operator sends a print command through the printer operation interface or the host computer. After the command is entered, the protocol parsing engine parses the command and encapsulates it into a data packet with a checksum based on the custom bus protocol. For example, to print an engineering drawing containing complex lines, the command will be refined into a series of parameters such as the start and stop of the print head, the movement trajectory, the thickness of the ink line, etc., and packaged in the format specified by the data link layer, and the corresponding header information and the checksum reserved bit will be added.

[0065] The system determines the transmission direction based on information such as the target address of the data packet. If the data needs to be transmitted from the first master control module to the second master control module, the downlink channel is activated, and the SN65LVDS047ADR driver chip is started to send the packaged data through 8 pairs of differential lines at high speed and stability; conversely, if the second master control module feeds back information to the uplink channel, the SN65LVDS048ADR driver chip takes over to ensure that the feedback data is uploaded smoothly, opening an orderly channel for two-way data interaction.

[0066] In downlink data transmission, the dynamic check module generates the first check code for the data according to the enhanced CRC algorithm. The check code is precisely connected to the end of the data packet and appended together with the dynamic salt value. For uplink data, the second check code is generated by the parity check and cumulative sum combination algorithm. Subsequently, the data enters the differential transmission stage. With the help of the differential bus with a twisted pair structure, it quickly runs to the target main control module in an anti-interference environment, realizing the physical transmission of data.

[0067] The timing control module monitors signal delays during transmission in real time. When a delay caused by environmental interference or line length differences is detected, the phase compensator responds quickly and compensates for the clock phase of the transmitter. If the printer is operating in a factory environment with high temperatures and complex electromagnetic interference, the timing control module can ensure that the clock at the data receiving end is precisely synchronized with the sending end, maintain data sampling accuracy, and allow printing tasks to proceed steadily even under complex working conditions.

[0068] After the data arrives at the receiving end, the verification program is started again. If the verification passes, the main control module at the receiving end executes the corresponding printing instructions based on the content of the data packet, accurately controls the inkjet of the print head, the movement of the platform, and other actions, and converts the digital instructions into physical printing results; if the verification fails, the system triggers the retransmission mechanism, and the lost or erroneous data packets are quickly marked and retransmitted to ensure that the printing task is not interrupted due to data problems until the complete and accurate data-driven printing job is successfully completed.

[0069] When multiple consecutive data packet verifications fail, exceeding the system's preset tolerance threshold, the system triggers a retransmission mechanism to quickly resend the erroneous data packets. At the same time, to ensure the reliability of data transmission, the system automatically reduces the transmission rate and switches to redundant channel transmission mode. The redundant channel takes over at critical moments to ensure that the printing job is not stalled due to a failure in the main channel, thereby ensuring production efficiency.

[0070] The system synchronously records the characteristic vectors of erroneous data packets, including key information such as packet length, checksum value, and transmission timestamp, and generates a detailed fault diagnosis report based on this data. Maintenance personnel can use the report to quickly locate the source of the fault, whether it is a hardware failure such as performance degradation of the differential driver chip, or abnormal software protocol parsing, or increased external interference, providing strong support for the precise maintenance of the printer and shortening the fault repair cycle.

[0071] The same or similar reference numerals correspond to the same or similar components;

[0072] The terms used in the drawings to describe positional relationships are for illustrative purposes only and should not be construed as limiting this patent;

[0073] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the implementation methods of the present invention. For ordinary technicians in the field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation methods here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A differential bus transmission verification system based on a digital inkjet printer, characterized in that: include: a first main control module and a second main control module; The differential bus transmission channel includes 14 pairs of differential signal lines, of which 8 pairs constitute the downlink channel from the first main control module to the second main control module, and 6 pairs constitute the uplink channel from the second main control module to the first main control module; A dynamic check module, embedded in the first main control module and the second main control module, is used to generate an adaptive check code during data transmission, wherein the bit width of the adaptive check code is dynamically adjusted according to the type of the current transmission data packet; The timing control module is connected to the differential bus transmission channel to monitor the signal transmission delay in real time and automatically adjust the clock phase offset; The protocol parsing engine executes the custom bus protocol, encapsulates the printing instruction data into a data packet with a checksum, and transmits it bidirectionally through the differential bus transmission channel.

2. The system according to claim 1, wherein: The downlink channel is implemented using a first type differential driver chip, which is SN65LVDS047ADR; The uplink channel is implemented using a second type differential driver chip, which is SN65LVDS048ADR.

3. The system according to claim 1, wherein: The dynamic verification module performs the following operations: Generate a first check code using an enhanced CRC algorithm for downlink channel data; A parity check and cumulative sum combination algorithm is used to generate a second check code for the uplink channel data; When continuous error packets are detected, the verification algorithm is automatically switched and data retransmission is triggered.

4. The system according to claim 3, characterized in that The enhanced CRC algorithm includes: initializing the polynomial to ; Append a dynamic salt value to the end of the data packet, the salt value is generated by hashing the data packet length and the transmission timing parameters.

5. The system according to claim 1, wherein: The timing control module includes: a delay locked loop circuit for measuring the transmission delay of the signal in the differential channel in real time; and a clock phase compensator for adjusting the transmission end clock to advance or lag according to the measurement result.

6. The system according to claim 1, wherein: The hierarchical structure of the custom bus protocol includes: a physical layer: defining the voltage swing and impedance matching requirements of the differential signal; a data link layer: stipulating that the data packet structure includes a header identifier, an instruction type field, a data length field, a check code field, and payload data; and an application layer: parsing printing instructions into nozzle control parameters, ink volume control parameters, and motion control parameters.

7. The system according to claim 6, characterized in that The protocol parsing engine performs the following operations for different transmission directions when encapsulating data packets: Adding a first direction identifier to the downlink channel data and activating a downlink check code generation unit; A second direction identifier is added to the uplink channel data, and an uplink check code generation unit is activated.

8. The system according to claim 1, wherein: It also includes an exception handling mechanism: when the number of verification failures exceeds the threshold, the transmission rate is automatically reduced and switched to redundant channel transmission mode; the feature vector of the error data packet is recorded and a fault diagnosis report is generated.

9. The system according to claim 1, wherein: The differential signal line adopts a twisted pair structure: the line pair spacing is 0.8mm±0.1mm; the single wire diameter is 30AWG, covered with a double shielding layer; the impedance is controlled at 100Ω±5%.

10. A digital inkjet printer, comprising a print head, an ink cartridge and a motion platform, characterized in that: Also includes: The differential bus transmission verification system according to any one of claims 1 to 9; The first main control module is connected to the print head driving circuit, and the second main control module is connected to the motion control platform; the differential bus transmission system transmits printing control instructions.

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