Comprehensive performance evaluation method and system for computer mainboard

Abstract

The invention relates to the technical field of computer performance evaluation, and particularly discloses a computer mainboard comprehensive performance evaluation method and system.The computer mainboard comprehensive performance evaluation method comprises the steps that a matched test assembly list is provided according to a mainboard model to build a test host, and hardware information is recognized; performing conjoint analysis on hardware identification information and expected standardized BIOS configuration parameters by utilizing a trained machine learning model so as to generate an optimized bottom BIOS setting value and an operation sequence by utilizing an optimal configuration strategy learned from massive historical tuning data by the model; and the method is automatically applied to mainboard firmware of the computer mainboard to be tested for CPU, memory, storage and image performance testing and comprehensive performance scoring. By means of the method, the computer mainboard performance testing process is effectively simplified, dependence on experience of technicians is reduced, and automatic deep evaluation on the computer mainboard performance is achieved through intelligent BIOS optimization.

Description

Technical Field

[0001] The present application relates to the technical field of computer performance evaluation, and more specifically, to a method and system for evaluating the comprehensive performance of a computer motherboard. Background Art

[0002] As the platform that supports core components like the CPU, memory, storage, and graphics cards, the computer motherboard's design, materials, and firmware (BIOS / UEFI) optimization directly determine the performance ceiling and stability of the entire computer system. With the rapid advancement of hardware technology, compatibility and interoperability between components are becoming increasingly complex. Users, review agencies, and manufacturers face the challenges of complex configuration, difficult optimization, and inconsistent standards when evaluating and comparing the actual performance of different motherboards. BIOS settings, in particular, offer numerous and interconnected options, and even subtle adjustments can significantly impact performance on a specific hardware configuration.

[0003] Currently, industry-wide evaluation of computer motherboard performance typically relies on experienced technicians manually selecting and pairing components, setting up the BIOS based on the motherboard and component official guides, or using the motherboard's preset performance modes (such as XMP and PBO). They then run a series of industry-standard benchmarks to test CPU, memory, storage, and graphics performance, and summarize and analyze the test results. However, under this testing approach, setting up the test environment is highly dependent on the engineer's experience, and component pairing lacks systematic guidance, resulting in inconsistent and reproducible test results. Furthermore, optimizing BIOS parameters in different testing scenarios requires repeated attempts. Manually searching for the global optimal configuration is not only inefficient but also struggles to cover the optimal configuration across different hardware combinations. It's impossible to achieve optimal performance for specific hardware configurations, often leading to biased evaluation results.

[0004] Therefore, an optimized computer motherboard comprehensive performance evaluation method and system are expected. Summary of the Invention

[0005] In order to solve the above technical problems, the present application is proposed. The embodiment of the present application provides a computer motherboard comprehensive performance evaluation method and system, which provides a list of matching test components based on the motherboard model to build a test host and identify hardware information. Then, the trained machine learning model is used to jointly analyze the hardware identification information and the expected standardized BIOS configuration parameters, so as to use the optimal configuration strategy learned by the model from massive historical tuning data to generate optimized underlying BIOS setting values ​​and operation sequences, and automatically apply them to the motherboard firmware of the computer motherboard to be tested to perform CPU, memory, storage and image performance testing and comprehensive performance scoring. This method effectively simplifies the computer motherboard performance testing process, reduces the dependence on the experience of technical personnel, and realizes the automated in-depth evaluation of computer motherboard performance through intelligent BIOS optimization.

[0006] Accordingly, according to one aspect of the present application, a method for evaluating the comprehensive performance of a computer motherboard is provided, comprising: Based on the motherboard model of the computer motherboard to be tested, a list of components to be tested is provided, wherein the computer motherboard to be tested and the list of components to be tested are used to guide the construction of the test host; After inserting the pre-OS boot medium, the test host runs a hardware identification tool to obtain hardware identification information; Obtain the standardized BIOS configuration parameters expected in the task; Inputting the hardware identification information and the standardized BIOS configuration parameters expected in the task into the trained machine learning model to obtain optimized underlying BIOS setting values ​​and operation sequences; Applying the optimized underlying BIOS setting values ​​and operation sequences to the motherboard firmware of the computer motherboard to be tested through the underlying interface; The test host starts a performance test process to obtain CPU performance test data, memory performance test data, storage performance test data, and image performance test data; Generate a comprehensive performance score based on CPU performance test data, memory performance test data, storage performance test data, and image performance test data.

[0007] According to another aspect of the present application, a computer motherboard comprehensive performance evaluation system is provided, comprising: A component list configuration module, configured to provide a list of components to be tested based on the motherboard model of the computer motherboard to be tested, wherein the computer motherboard to be tested and the list of components to be tested are used to guide the construction of a test host; A hardware information identification module, configured to enable the test host to run a hardware identification tool to obtain hardware identification information after the pre-OS boot medium is inserted; Configuration parameter acquisition module, used to obtain the standardized BIOS configuration parameters expected in the task; a configuration parameter optimization module, configured to input the hardware identification information and the standardized BIOS configuration parameters expected in the task into the trained machine learning model to obtain optimized underlying BIOS setting values ​​and operation sequences; A configuration parameter application module, configured to apply the optimized underlying BIOS setting values ​​and operation sequences to the motherboard firmware of the computer motherboard to be tested through an underlying interface; The performance test module is used to test the host to start the performance test process to obtain CPU performance test data, memory performance test data, storage performance test data and image performance test data; The performance scoring module is used to generate a comprehensive performance scoring value based on CPU performance test data, memory performance test data, storage performance test data and image performance test data.

[0008] Compared with the existing technology, the computer motherboard comprehensive performance evaluation method and system provided by this application provides a list of matching test components based on the motherboard model to build a test host and identify hardware information. Then, a trained machine learning model is used to jointly analyze the hardware identification information and the expected standardized BIOS configuration parameters. The model uses the optimal configuration strategy learned from massive historical tuning data to generate optimized underlying BIOS setting values ​​and operation sequences, and automatically applies them to the motherboard firmware of the computer motherboard to be tested to perform CPU, memory, storage and image performance testing and comprehensive performance scoring. This method effectively simplifies the computer motherboard performance testing process, reduces dependence on the experience of technical personnel, and realizes automated and in-depth evaluation of computer motherboard performance through intelligent BIOS optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other purposes, features, and advantages of the present application will become more apparent through a more detailed description of the embodiments of the present application in conjunction with the accompanying drawings. The accompanying drawings are intended to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the drawings, the same reference numerals generally represent the same components or steps.

[0010] Figure 1 Flowchart of a method for evaluating the comprehensive performance of a computer motherboard according to an embodiment of the present application.

[0011] Figure 2 This is a flowchart of step S4 in the computer motherboard comprehensive performance evaluation method according to an embodiment of the present application.

[0012] Figure 3This is a flowchart of step S7 in the computer motherboard comprehensive performance evaluation method according to an embodiment of the present application.

[0013] Figure 4 4 is a block diagram of a computer motherboard comprehensive performance evaluation system according to an embodiment of the present application. DETAILED DESCRIPTION

[0014] Below, an example embodiment according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiment is only a part of the embodiment of the present application, not all of the embodiments of the present application, and it should be understood that the present application is not limited to the example embodiment described herein. It is worth noting that in the present application, all actions to obtain data are carried out in compliance with the relevant data protection laws and policies of the country where they are located, and with the authorization of the corresponding device owner.

[0015] Figure 1 Flowchart of the method for evaluating the comprehensive performance of a computer motherboard according to an embodiment of the present application. Figure 1 As shown, the computer motherboard comprehensive performance evaluation method according to the embodiment of the present application includes the following steps: S1, based on the motherboard model of the computer motherboard to be tested, providing a list of components to be tested, wherein the computer motherboard to be tested and the list of components to be tested are used to guide the construction of a test host; S2, after inserting the pre-OS boot medium, the test host runs a hardware identification tool to obtain hardware identification information; S3, obtains the standardized BIOS configuration parameters expected in the task; S4, inputs the hardware identification information and the standardized BIOS configuration parameters expected in the task into the trained machine learning model to obtain optimized underlying BIOS setting values ​​and operation sequences; S5, applies the optimized underlying BIOS setting values ​​and operation sequences to the motherboard firmware of the computer motherboard to be tested through the underlying interface; S6, the test host starts a performance test process to obtain CPU performance test data, memory performance test data, storage performance test data and image performance test data; S7, generates a comprehensive performance score value based on the CPU performance test data, memory performance test data, storage performance test data and image performance test data.

[0016] In the above-mentioned computer motherboard comprehensive performance evaluation method, the step S1 provides a list of components that need to be tested based on the motherboard model of the computer motherboard to be tested, wherein the computer motherboard to be tested and the list of components that need to be tested are used to guide the construction of the test host. It should be understood that the lack of systematic guidance on component matching in existing tests often leads to the lack of comparability of test results between different test platforms, and it is difficult to reflect the actual performance of the motherboard in typical or optimal compatibility scenarios. Therefore, in order to ensure the standardization and representativeness of the test environment and provide a stable and reproducible baseline platform for subsequent performance evaluation, this application is based on the motherboard compatibility database and typical application scenario analysis, and by clarifying the motherboard model to be tested, a recommended list of matching components is systematically provided to achieve standardization of test host construction.

[0017] In one specific embodiment of the present application, a detailed hardware compatibility and performance grading database is first established. This database contains detailed specifications for mainstream and tested motherboard models, such as chipsets, supported CPU socket types, memory types and maximum capacities, PCIe lane count and version, and M.2 interface specifications. The database also includes specifications and market positioning information for various CPU types (categorized by generation, core count, frequency, and TDP), memory modules (categorized by DDR generation, frequency, timings, capacity, and brand series), graphics cards (categorized by GPU core, memory type and capacity, and interface type), and storage devices (NVMe SSDs, SATA SSDs, and HDDs, categorized by interface, protocol, and performance level). When a motherboard model to be tested (e.g., the ASUS ROG MAXIMUS Z790 HERO) is entered, the system queries the motherboard's technical specifications and, based on pre-defined test objectives (e.g., "high-end gaming performance evaluation," "professional workstation stability testing," or "entry-level price / performance verification"), selects components from the database that are compatible with the motherboard and meet the target positioning. For example, high-end gaming performance testing targets are associated with high-end hardware, resulting in a recommended component list consisting of a current flagship or mid-range CPU (such as the Intel Core i9-13900K), paired with a high-speed DDR5 memory kit (such as 32GB 6000MHz CL30), a high-performance discrete graphics card (such as the NVIDIA GeForce RTX 4090), and a high-speed PCIe 4.0 / 5.0 NVMe SSD as both the system and test drives. For office scenario assessments, this is associated with mainstream mid-range hardware, resulting in a recommended component list. Furthermore, after obtaining the component list, potential conflicts between components are further checked, such as graphics card size compatibility with the chassis and radiator height restrictions. This ensures that the listed components can coexist harmoniously in the test host, avoiding physical incompatibilities during actual setup. Once the component list is finalized, it is presented electronically or through a specific software interface to guide testers through accurate hardware assembly.

[0018] When setting up the test host, technicians must strictly follow the list to install and connect the components. They must accurately insert the CPU into the corresponding slot on the motherboard, ensuring that the pins fit perfectly. When installing the memory, they must correctly insert the memory according to the slot identification and the direction of the memory notch to ensure good contact. The graphics card must be installed in the PCI-E slot and the power cord must be connected. The storage device must be connected to the motherboard via the SATA interface or the M.2 interface and must be fixed and arranged accordingly. At the same time, the installation process of all components must be recorded in detail, including information such as the installation time, the installer, and the component serial number for subsequent traceability and review. In this way, the problem of insufficient performance or hardware conflicts caused by improper component matching is effectively avoided. Each test is based on the same or similar hardware environment, thereby improving the consistency and reproducibility of the test results and laying a solid foundation for accurately evaluating the performance of the motherboard.

[0019] In the aforementioned computer motherboard comprehensive performance evaluation method, in step S2, after inserting the pre-OS boot medium, the test host runs a hardware identification tool to obtain hardware identification information. It should be understood that motherboard hardware information is an important foundation for performance evaluation and optimizing BIOS settings. Manually recording hardware information is not only inefficient but also prone to omissions or errors. Therefore, in order to accurately and comprehensively obtain the actual hardware configuration details of the test host, this application implements precise collection of the test host's hardware information by running a specialized hardware identification tool in a pre-operating system (Pre-OS) environment.

[0020] In a specific embodiment of the present application, the hardware identification information includes the motherboard manufacturer, model, sub-model, BIOS version string, CPU model, stepping, number of cores, base frequency, TDP, memory module information, graphics card model and connection method. Specifically, the pre-OS boot medium is a USB flash drive or network boot image that contains a lightweight operating system (such as a customized Linux distribution or Windows PE) and a series of hardware diagnostic and identification tools. After the test host is set up, this medium is set as the preferred boot device. After startup, the system will automatically or according to a preset script execute the hardware identification process, call tools such as CPU-Z, the command line version of HWiNFO, the report generation module of AIDA64, or dmidecode, lshw, lspci, lsusb under Linux, directly read the detailed information of the motherboard and its connected components, and summarize them into a hardware identification report. For example, dmidecode can extract the motherboard's manufacturer (e.g., ASUSTeK COMPUTER INC.), product name (e.g., ROG MAXIMUS Z790 HERO), and BIOS version string (e.g., Version 1203). CPUID information combined with a lookup table can determine the CPU's specific model (e.g., Intel Core i9-13900K), stepping, number of cores, base frequency, cache sizes at all levels, and TDP. Reading the memory SPD can obtain each memory module's manufacturer, model, serial number, capacity, nominal frequency, timings in the XMP / EXPO configuration file (e.g., CL30-38-38-96), and voltage. lspci can identify the graphics card model (e.g., NVIDIA GeForce RTX 4090), manufacturer, bus type, and actual operating bandwidth (e.g., PCIe 4.0 x16). Ultimately, all hardware identification information is consolidated into a standardized report format (e.g., JSON or XML file) and stored in the test host's local database for easy retrieval and analysis. This method helps to fully understand the detailed parameters of the hardware devices, providing rich and reliable data for subsequent BIOS configuration optimization based on hardware characteristics, so that the BIOS settings can better adapt to the hardware and improve the motherboard performance.

[0021] In the above-mentioned computer motherboard comprehensive performance evaluation method, the step S3 obtains the expected standardized BIOS configuration parameters in the task. It should be understood that different test tasks or application scenarios have different performance tendencies and functional requirements for the motherboard BIOS settings. For example, extreme overclocking pursues the highest frequency, while stability testing may require conservative settings. Specific applications may require turning on or off certain special functions such as virtualization technology, Resizable BAR, etc. Therefore, in order to provide a clear optimization direction and high-level constraints for the subsequent BIOS configuration parameter optimization, so that it can adjust the BIOS optimization strategy according to the specific test intention, this application is based on the goal-oriented configuration management principle, by defining and obtaining the expected standardized BIOS configuration parameters corresponding to the current test task, so as to achieve customization and targeting of the model output.

[0022] Specifically, the standardized BIOS configuration parameters expected in the task do not refer to specific low-level BIOS settings, but rather to a set of high-level instructions or target states that describe the desired system behavior or performance characteristics. These parameters can be defined through a user interface or configuration file. For example, users can select predefined test scenarios or performance profiles, such as maximum CPU performance release, memory bandwidth priority, balanced gaming performance, and enterprise application stability. Each scenario is mapped to a specific set of standardized BIOS configuration parameters. In practice, after the tester initiates the evaluation process, the system will prompt them to select or load a preset task configuration file, which defines the standardized BIOS configuration parameter set for the selected test scenario. For example, a configuration file for gaming performance testing might contain the following: {Test Scenario: Gaming High Performance; Target CPU Overclocking Settings: Max All Cores; Target Memory Speed: XMP Rating; Target PCIe Gen: Latest Supported; Enable Adjustable BARs: Yes; Disable CPU Power Saving Mode: Yes}. This allows subsequent BIOS optimization solutions to be accurately aligned with the predefined test objectives and scenario requirements, making the final BIOS configuration more targeted and practical, avoiding blind optimization or failure to meet test intent.

[0023] In the above-mentioned computer motherboard comprehensive performance evaluation method, in step S4, the hardware identification information and the expected standardized BIOS configuration parameters in the task are input into the trained machine learning model to obtain optimized underlying BIOS setting values ​​and operation sequences. It should be understood that manually searching for the global optimal configuration for a specific hardware combination and a specific performance target in a large number of BIOS options is extremely time-consuming and has a low success rate. In addition, the option names, structures and interdependencies of different motherboard manufacturers and different BIOS versions are complex and changeable. Traditional rule-based or experience-based optimization methods are difficult to adapt to this complexity and diversity. Therefore, in order to intelligently generate a refined underlying BIOS setting solution for the current specific hardware configuration and task objectives, this application is based on supervised learning and sequence generation models. By inputting the hardware identification information and the expected standardized BIOS configuration parameters in the task into the trained machine learning model, the model can utilize the prior knowledge learned by the model based on a large amount of historical data and expert experience to intelligently infer the optimal underlying BIOS setting values ​​and operation sequences.

[0024] Figure 2 FIG. 4 is a flow chart of step S4 in the method for evaluating the comprehensive performance of a computer motherboard according to an embodiment of the present application. Figure 2 As shown, the step S4 includes: S41, performing structured encoding on the hardware identification information to obtain a hardware identification information structured encoding vector; S42, performing structured encoding on the standardized BIOS configuration parameters expected in the task to obtain a target function description structured encoding vector; S43, performing vector splicing on the hardware identification information structured encoding vector and the target function description structured encoding vector to obtain a hardware information-target function splicing structured encoding vector; S44, inputting the hardware information-target function splicing structured encoding vector into the trained machine learning model to obtain the optimized underlying BIOS setting value and operation sequence.

[0025] Specifically, the step S41 performs structured encoding on the hardware identification information to obtain a hardware identification information structured encoding vector. It should be understood that the hardware identification information itself contains multiple data types, such as motherboard model (text), number of CPU cores (numeric value), graphics card connection method (category), etc. Since the original data format is not uniform and there are high-cardinality category features (such as hundreds or thousands of specific motherboard or CPU models), direct input into the model will lead to dimensionality disasters or inability to effectively extract information. Therefore, in order to convert the diverse hardware information into a unified numerical representation suitable for machine learning model processing, this application is based on the principle of feature embedding, and adopts different encoding strategies for various hardware parameters to integrate them into a fixed-dimensional hardware identification information structured encoding vector to achieve a comprehensive and concise mathematical description of the hardware configuration.

[0026] In a specific embodiment of the present application, word embedding technology is used to encode high-cardinality text strings, such as motherboard manufacturer, model, sub-model, CPU model, and graphics card model. Each text string is mapped into a high-dimensional continuous vector space, so that similar strings are closer in the vector space (for example, motherboard models from the same series or manufacturer may be closer in the embedding space), thereby effectively capturing the potential connections and similarities between hardware models. For numerical features such as the number of CPU cores, base frequency, TDP, and number of memory modules, normalization (such as minimum-maximum normalization) is used to scale the values ​​to a fixed interval (such as [0,1]) to eliminate the influence of different numerical feature dimensions, prevent features with larger values ​​from dominating the model training, and help optimize the convergence of the algorithm. Memory module information may include multiple aspects, such as total capacity (numeric value, which needs to be normalized), single-line capacity, frequency (numeric value, which needs to be normalized), time series (multiple values, normalized separately), brand (category, which needs to be embedded), and model (category, which needs to be embedded). Graphics card connection methods (e.g., PCIe 4.0x16, PCIe 3.0x8) are broken down into PCIe version (ordered categories) and lane number (numeric values), each of which is one-hot encoded and normalized to clearly distinguish between different connection methods. Finally, the encoded hardware information features are concatenated in a fixed order to form a structured encoding vector of the hardware identification information.

[0027] Specifically, the step S42 performs structured encoding on the standardized BIOS configuration parameters expected in the task to obtain a target function description structured encoding vector. It should be understood that the standardized BIOS configuration parameters expected in the task are descriptive target setting requirements. Similarly, in order to convert them into numerical representations that can be understood by the machine learning model, the present application adopts natural language processing (NLP) technology to embed the standardized BIOS configuration parameters expected in the task to obtain a target function description structured encoding vector, thereby achieving accurate characterization of the optimization intention. In a specific embodiment of the present application, a pre-trained word embedding model (such as Word2Vec) is used to convert each key-value pair in the standardized BIOS configuration parameters expected in the task into a word vector, and then the self-attention mechanism is used to perform attention fusion on each word vector to capture the correlation between different key-value pairs and generate the final target function description structured encoding vector.

[0028] Specifically, in step S43, the hardware identification information structured coding vector and the target function description structured coding vector are vector-joined to obtain a hardware information-target function spliced ​​structured coding vector. It should be understood that the hardware identification information structured coding vector only reflects the characteristics of the hardware itself, and the target function description structured coding vector only reflects the performance optimization goal. In order to enable the machine learning model to fully understand the correlation between the current hardware configuration and the expected task goal, and thus make reasonable BIOS setting adjustments, the present application forms a joint representation containing hardware information and task target information, namely, a hardware information-target function spliced ​​structured coding vector, by vector-joining the hardware identification information structured coding vector and the target function description structured coding vector, thereby providing a comprehensive information basis for subsequent BIOS setting optimization.

[0029] Specifically, in step S44, the hardware information-target function concatenated structured coding vector is input into the trained machine learning model to obtain the optimized underlying BIOS setting value and operation sequence. More specifically, the input trained machine learning model is a Seq2Seq model, and the Seq2Seq model includes an encoder based on a Transformer architecture and a decoder based on an RNN network. That is, in order to convert the joint features of high-level hardware configuration and performance targets into a series of low-level BIOS settings and operation steps, the present application utilizes the powerful feature extraction and sequence generation capabilities of the deep learning model, and designs a Transformer Encoder + RNNDecoder neural network structure based on the sequence-to-sequence learning (Seq2Seq) framework, so as to utilize the self-attention mechanism of the Transformer encoder to capture the complex correlation and dependency between the hardware configuration and the task target, and gradually decodes the captured hardware information-target function joint features into a series of ordered BIOS setting values ​​and operation sequences through the RNN decoder.

[0030] In a specific embodiment of the present application, during the Seq2Seq model training phase, a large number of historical motherboard BIOS configuration cases under high-performance conditions are collected as training data. These data cover the optimal underlying BIOS settings and operation sequences for motherboards of different brands and models, under various hardware combinations, and under different task requirements. This data is divided into training, validation, and test sets according to a specific ratio (e.g., 7:2:1). During training, the hardware configuration information and corresponding task requirement descriptions in the historical BIOS configuration cases are converted into a historical case hardware information-target function concatenation structured encoding vector using the aforementioned hardware identification information structured encoding method and target function description structured encoding method, respectively. This vector serves as the input for the Seq2Seq model. A Transformer-based encoder first encodes the input historical case hardware information-target function concatenation structured encoding vector. Using its multi-head attention mechanism, it concurrently captures the feature associations between hardware information and performance targets in the historical case hardware information-target function concatenation structured encoding vector from different perspectives, encoding them into a higher-level feature representation. Next, the encoded feature representation is passed to a decoder based on an RNN network. Based on the encoder's output feature representation and its own recurrent connectivity structure, the decoder sequentially generates optimized underlying BIOS settings and operation sequences. During this sequence generation process, the RNN network, thanks to its recurrent connectivity structure, leverages previously generated sequence information and conveys contextual information through hidden states, ensuring that the generated optimized underlying BIOS settings and operation sequences are logically coherent and consistent with the actual configuration logic. During training, the optimal BIOS settings and operation steps from historical BIOS configuration examples are used as the target output. By minimizing the difference between the predicted output and the optimal BIOS settings and operation steps from historical BIOS configuration examples (using a cross-entropy loss function), the encoder and decoder parameters of the Seq2Seq model are continuously adjusted until the model converges on the validation set, completing model training. After model training is complete, the trained Seq2Seq model can be used for new BIOS settings optimization tasks by inputting the structured encoding vector of the concatenation of the current hardware information and target function into the trained model. The trained Seq2Seq model uses the encoder to extract and encode features from the input vector. Based on the encoded feature representation, the decoder gradually generates optimized low-level BIOS settings and operation sequences for the current hardware combination and performance goals. This reveals the specific settings for each BIOS parameter and the order in which operations are executed. For example, the CPU multiplier and voltage are set first, followed by memory timing adjustments, and finally the graphics card parameters.In this way, with the powerful sequence learning and prediction capabilities of the Seq2Seq model, it is possible to quickly and accurately generate optimized underlying BIOS setting values ​​and operation sequences for different hardware combinations and performance targets, greatly improving the efficiency and accuracy of BIOS configuration optimization, effectively solving the problems of traditional manual configuration, and helping to fully tap the performance potential of the motherboard.

[0031] In particular, here, when the hardware information-target function splicing structured coding vector is input into the encoder based on the Transformer architecture to obtain the coding feature vector, since it is necessary to consider the coding structure consistency of the hardware identification information and the expected standardized BIOS configuration parameters in the task under different data modalities, the hardware information-target function splicing structured coding vector will have a low embedding density problem due to the sparsification of self-attention consistency, which affects the circular convolution regression effect of the decoder.

[0032] Based on this, in a preferred embodiment of the present application, the step S44 includes: first, performing feature embedding density adaptive modulation on the hardware information-target function splicing structured coding vector to obtain an optimized hardware information-target function splicing structured coding vector; and then inputting the optimized hardware information-target function splicing structured coding vector into the trained machine learning model to obtain the optimized underlying BIOS setting value and operation sequence.

[0033] Specifically, first, the covariance gradient matrix of the hardware information-target function splicing structured coding vector is calculated to obtain a first hardware information-target function feature covariance gradient matrix and a second hardware information-target function feature covariance gradient matrix. More specifically, for the hardware information-target function splicing structured coding vector (e.g., ) for each pair of eigenvalues and , calculate its class covariant derivative to obtain the covariant gradient matrix and ,Right now:

[0034] in, and Respectively represent the hardware information-target function concatenation structured coding vector Position and The eigenvalues ​​at the positions, Indicates taking the absolute value, Represents the first hardware information-target function feature covariant gradient matrix, Represents the second hardware information-target function feature covariant gradient matrix, Representation matrix Middle ( ) position, Representation matrix Middle ( ) position.

[0035] In this way, it is possible to use covariant gradient representation to enhance the covariant density with eigenvalues, and reconstruct the geometric density relationship under the encoder self-attention architecture, that is, to enhance the geometric density relationship into a discretized mapping with eigenvalues ​​as manifold vertices.

[0036] Then, based on the first hardware information-target function feature covariance gradient matrix and the second hardware information-target function feature covariance gradient matrix, the hardware information-target function splicing structured encoding vector is modulated by long-range dependency to obtain the hardware information-target function splicing structured long-range dependency encoding vector. That is, the geometric density long-range dependency is performed through an explicit memory modulation mechanism based on mapping, namely:

[0037] in, represents the matrix multiplication operation, Indicates positional subtraction, ⊕ indicates positional addition, Representing hardware information-target function concatenation with structured long-range dependency encoding vectors.

[0038] In this way, while preserving the local geometric density relationship in the feature space, the long-range dynamic mapping modulation of the geometric density of the feature can be achieved by constructing a dual memory.

[0039] Furthermore, in order to enhance the sensitivity of feature distribution to geometric density changes, a covariant parameterized group action space is constructed so that the feature distribution can adaptively modulate the embedding density through the joint curvature representation in the group action space, and further based on the first hardware information-target function feature covariant gradient matrix and the second hardware information-target function feature covariant gradient matrix, the hardware information-target function splicing structured coding vector is subjected to local covariant sensitivity modulation to obtain a hardware information-target function splicing structured local sensitivity enhanced coding vector. ,Right now:

[0040] Finally, based on the hardware information-target function splicing structured long-range dependency coding vector and the hardware information-target function splicing structured local sensitivity enhancement coding vector, the hardware information-target function splicing structured coding vector is subjected to feature collaborative modulation to obtain the optimized hardware information-target function splicing structured coding vector. That is, based on the distribution restoration under the covariant density, the optimized hardware information-target function splicing structured coding vector is obtained. ,Right now:

[0041] in, and is the weight parameter, for example =0.6, =0.4, of course. This is just an example, and ⊙ represents the point product by position.

[0042] Therefore, the local embedding density enhancement of eigenvalues ​​is modeled by reconstructing the geometric density relationship with the point-to-point covariant derivatives of the eigenvalues, and the geometric density dependence is introduced through dynamic connection through explicit memory modulation, and adaptive modulation is performed. This can enable the feature distribution to maintain the local continuous differentiable covariance characteristics and satisfy the memory retention mechanism under the dual constraints of dependency-sensitivity, thereby improving the embedding density of the hardware information-target function splicing structured coding vector in its feature space, and then improving the cyclic convolution regression effect of the subsequent decoder.

[0043] In the above-mentioned computer motherboard comprehensive performance evaluation method, the step S5 applies the optimized underlying BIOS setting values ​​and operation sequence to the motherboard firmware of the computer motherboard to be tested through the underlying interface. Considering that manually searching and modifying these parameters one by one in the graphical BIOS interface is not only time-consuming and labor-intensive, but also prone to errors. Therefore, in order to ensure that the optimized configuration generated by the model can be accurately, completely and efficiently applied to the motherboard firmware, and to avoid errors and inconsistencies introduced by manual operations, this application is based on the technical principles of the firmware automatic configuration interface. Through a special underlying interface program or script, the BIOS settings and operation sequence output by the model are directly written or acted on the firmware storage area (such as NVRAM) of the motherboard to be tested, so as to realize the automated application of the BIOS configuration.

[0044] In a specific embodiment of the present application, the underlying interface relies on features provided by the motherboard firmware itself or a standardized firmware interaction mechanism. For example, this utilizes the UEFI (Unified Extensible Firmware Interface) environment. In addition to the hardware identification tool, the pre-OS boot media also includes a UEFI Shell application that receives a structured BIOS setting sequence output by a machine learning model (e.g., a JSON array, where each element contains the BIOS variable's GUID, name / offset, data type, data size, and the value to be set). The application parses the structured BIOS setting sequence and uses functions provided by UEFI Runtime Services (such as GetVariable and SetVariable) to directly read and write the NVRAM variables storing the BIOS settings. For example, if the model outputs setting the CPU core ratio to 50, and the NVRAM variable corresponding to this setting is known to be named CpuRatioVar, has a specific GUID, and has a data type of UINT8, the UEFI application constructs the corresponding parameters and calls SetVariable("CpuRatioVar", &VendorGuid, Attributes, DataSize, &Value50). Operation sequences are also executed at this stage. For example, if the sequence includes a "save and reboot" instruction, the UEFI application will execute the corresponding reset command (e.g., gRT->ResetSystem(EfiResetWarm, EFI_SUCCESS, 0, NULL)). Alternatively, if the motherboard manufacturer provides specific command-line tools or APIs (such as the out-of-band management interface provided by some server motherboards or specific motherboard series, or the configuration functions included in firmware update tools), the underlying interface will encapsulate calls to these tools, converting the settings output by the model into the command format of the corresponding tool and executing them. For example, a setting might be translated into VendorTool.exe --set_option "Path.To.Option" --value "DesiredValue". Furthermore, the interface program should include error handling capabilities. For example, if a variable does not exist or the value set is out of range, the error should be logged and the process should be skipped or terminated. In this way, the underlying BIOS settings and operation steps are accurately and automatically applied to the motherboard firmware, ensuring the faithful implementation of the optimization solution. This provides a deeply optimized BIOS environment for subsequent performance testing, significantly improving configuration efficiency and repeatability.

[0045] In the above-mentioned computer motherboard comprehensive performance evaluation method, in step S6, the test host starts a performance test process to obtain CPU performance test data, memory performance test data, storage performance test data, and image performance test data. Specifically, in order to quantitatively test the actual performance of the motherboard after the BIOS configuration is optimized by the machine learning model, this application is based on standardized benchmark testing and automated test execution principles. By starting a predefined performance test process on a test host that has applied the optimized BIOS settings, the performance data of the four core components of CPU, memory, storage, and image are systematically collected.

[0046] In one specific embodiment of the present application, after the underlying BIOS settings and operation sequence are successfully applied to the motherboard firmware and a reboot is completed as needed, the test host automatically boots into a preconfigured test operating system environment (e.g., a specific version of Windows or Linux, including all necessary drivers and benchmark software). This test process is scheduled and executed by a master control script or test management software. This script sequentially launches a series of industry-recognized, representative benchmark programs. For example, for CPU performance testing, Cinebench R23 is used. This software simulates 3D rendering tasks to test CPU performance in both multi-core and single-core modes, accurately assessing the CPU's computing power and multi-threaded processing capabilities. During testing, Cinebench R23 is installed on the test host and, after running the software, selected in both multi-core and single-core test modes. The software automatically utilizes CPU resources for rendering calculations, recording CPU operating frequency, temperature, power consumption, and other parameters in real time during the test. Upon completion, a detailed CPU performance test data report is generated, including multi-core and single-core scores. For memory performance testing, MemTest86, a software specifically designed to test memory stability and performance, is used. Create a bootable disk with MemTest86 and boot it from it on the test host. The software will automatically perform a comprehensive memory scan, testing performance metrics such as read and write speeds and error rates. During the test, the software continuously writes and reads data to and from memory, simulating actual memory usage. It records various performance parameters, such as memory bandwidth and latency, and ultimately generates a memory performance report. Storage performance testing uses CrystalDiskMark, which tests both sequential and random read and write performance of hard drives. After installing CrystalDiskMark on the test host, select the storage device to test (such as a solid-state drive or mechanical hard drive), set the test data volume and number of tests, and the software will begin performing read and write tests on the storage device, measuring read and write speeds at different data block sizes. A storage performance report will be generated, including sequential read and write speeds, sequential write speeds, and 4K random read speeds. Graphics performance testing uses 3DMark, which evaluates the graphics processing capabilities and performance of the graphics card by running various 3D gaming scenarios and graphics tests. After installing 3DMark on the test host, select a test scenario suitable for the current graphics card performance (such as FireStrike, Time Spy, etc.). After starting the software, render complex 3D graphics and scenes, and monitor the graphics card's core frequency, memory usage, temperature and other parameters in real time. After the test, generate an image performance test data report, including graphics card score, frame rate and other indicators.In this way, using professional performance testing software, we can comprehensively and accurately obtain the performance data of key hardware such as CPU, memory, storage and imaging, providing a detailed and reliable data foundation for subsequent comprehensive performance evaluation.

[0047] In the above-mentioned computer motherboard comprehensive performance evaluation method, the step S7 generates a comprehensive performance score value based on the CPU performance test data, memory performance test data, storage performance test data and image performance test data. It should be understood that a single performance indicator or original test data is difficult to intuitively reflect the overall performance level of the computer motherboard, and different users or evaluation agencies have different emphases on various performances. Therefore, in order to convert multi-dimensional and multi-type original performance test data into comparable comprehensive performance score values, this application is based on a multi-index comprehensive evaluation method and a weighted scoring principle, by processing and scoring the collected four types of performance test data of CPU, memory, storage and image respectively, and further combining the preset weights for weighted aggregation to generate a comprehensive performance score value for the computer motherboard. As Figure 3 As shown, the step S7 includes: S71, generating a CPU performance test score value based on the CPU performance test data; S72, generating a memory performance test score value based on the memory performance test data; S73, generating a storage performance test score value based on the storage performance test data; S74, generating an image performance test score value based on the image performance test data; S75, calculating the comprehensive performance score value based on the CPU performance test score value, the memory performance test score value, the storage performance test score value and the image performance test score value.

[0048] In one specific embodiment of the present application, various raw performance test data are first normalized and converted into individual scores. For example, for CPU performance test data, the multi-core and single-core scores generated by Cinebench R23 testing vary in numerical range and unit depending on the test item. To facilitate unified comparison and calculation, a CPU performance scoring standard library is established. Based on the industry's general CPU performance level and performance differences, different performance ranges are divided and assigned corresponding scores. For example, multi-core scores above 12,000 are classified as excellent, with scores of 90-100; scores between 10,000 and 12,000 are classified as good, with scores of 80-89, and so on, until lower performance ranges and corresponding scores are established. The multi-core and single-core scores obtained from the Cinebench R23 test are weighted according to their respective importance in CPU performance evaluation. Generally, multi-core performance, which is more critical in modern multitasking and complex computing, can be weighted 70%, while single-core performance can be weighted 30%. Map the multi-core score and single-core score to the corresponding intervals in the scoring standard library to obtain the multi-core score and single-core score. Then calculate the weighted CPU performance test score based on the weight, that is, CPU performance test score = multi-core score × 70% + single-core score × 30%.

[0049] Next, for the memory performance test data, the memory bandwidth, latency, and error rate parameters obtained by the MemTest86 test also need to be normalized. Since the higher the memory bandwidth, the shorter the latency, and the lower the error rate, the better the memory performance, the memory bandwidth is divided into different bandwidth level intervals according to industry standards. Each interval corresponds to a certain score range, such as the high bandwidth interval corresponds to 90-100 points, the medium bandwidth interval corresponds to 70-89 points, etc. For latency, it is sorted from small to large and divided into different intervals, with short latency intervals corresponding to high scores and long latency intervals corresponding to low scores. The error rate is scored in reverse, that is, an error rate of 0 corresponds to a full score, and the score decreases as the error rate increases. Based on the importance of memory bandwidth, latency, and error rate in memory performance evaluation, they are assigned weights of 40%, 40%, and 20%, respectively. The memory bandwidth, latency, and error rate data obtained from the test are mapped to the corresponding scoring ranges based on the scoring model to obtain their respective scores. The memory performance test score is then calculated through weighted calculation, i.e., memory performance test score = memory bandwidth score × 40% + latency score × 40% + error rate score × 20%.

[0050] Next, regarding storage performance test data, CrystalDiskMark tests generate sequential read speed, sequential write speed, and 4K random read speed. Due to significant differences in performance characteristics and data volumes across different storage device types (e.g., SSDs and HDDs), data standardization is required. Different scoring criteria are then developed for each storage device type. For SSDs, 4K random read speed and sequential read / write speed are the primary focus; for HDDs, sequential read / write speed is more critical. Sequential read speed, sequential write speed, and 4K random read speed are divided into performance ranges based on storage device type and assigned corresponding scores. For example, a 4K random read speed of 50MB / s or higher for an SSD would be in the high-score range, while a sequential read speed of 150MB / s or higher for an HDD would be in the high-score range. Weighting is assigned to each speed metric based on its importance in the storage performance evaluation. For SSDs, 4K random read speed is weighted 50%, while sequential read speed and sequential write speed are each weighted 25%. For HDDs, sequential read speed is weighted 60%, and sequential write speed is weighted 40%. The storage performance data obtained from the test is mapped to the corresponding score range according to the evaluation system to obtain the score value of each speed indicator. The storage performance test score value is then obtained through weighted calculation, that is, the storage performance test score value = the sum of the scores of each speed indicator × the corresponding weights.

[0051] Similarly, for graphics performance test data, such as graphics scores and frame rates obtained from 3DMark tests, based on the aforementioned conversion principle and the difficulty and scoring criteria of different test scenarios (such as Fire Strike and Time Spy), and based on extensive statistical analysis of test data, we determined the correspondence between scores and actual graphics performance in different test scenarios. The graphics scores and frame rates obtained from 3DMark in different test scenarios were then mapped to standardized scores in the range [0, 100]. Furthermore, based on their importance in graphics performance evaluation, weights of 70% and 30% were assigned to the graphics score and frame rate, respectively. The converted graphics score and frame rate scores were then weighted together to produce the graphics performance test score: Graphics Performance Test Score = Graphics Score × 70% + Frame Rate Score × 30%.

[0052] Finally, calculate the weighted sum of the CPU performance test score, memory performance test score, storage performance test score, and image performance test score to obtain the comprehensive performance score. Since users have different demands for device performance in different application scenarios, when calculating the comprehensive performance score, first determine the weight of each hardware performance score based on the importance of each hardware performance of the motherboard in different application scenarios. For example, in office application scenarios, CPU performance and storage performance are relatively important. The weight of the CPU performance test score can be set to 40%, the weight of the storage performance test score can be set to 30%, the weight of the memory performance test score can be set to 20%, and the weight of the image performance test score can be set to 10%. In gaming application scenarios, image performance and CPU performance are more critical. The weight of the image performance test score can be set to 40%, the weight of the CPU performance test score can be set to 30%, the weight of the memory performance test score can be set to 20%, and the weight of the storage performance test score can be set to 10%. Multiply each hardware performance test score by the corresponding weight, and then add the products to obtain the comprehensive performance score. After the calculation is completed, the comprehensive performance score is rounded to one decimal place and a detailed performance evaluation report is generated. The report not only includes the comprehensive performance score, but also lists the scores of each hardware performance test, the weight distribution and the calculation process in detail, so that users and R&D personnel can fully understand the performance of the motherboard.

[0053] In this way, the hardware performance data of CPU, memory, storage and image are systematically integrated and quantitatively calculated to fully reflect the comprehensive performance level of the computer motherboard in different application scenarios, thereby providing users with a scientific reference basis when purchasing a motherboard and helping users choose a motherboard with performance adaptation according to their own needs; at the same time, it also provides quantitative performance indicators for R&D personnel in the process of motherboard development and optimization, facilitates the analysis of motherboard performance bottlenecks, and makes targeted improvements and optimizations, effectively improving the practicality and effectiveness of computer motherboard performance evaluation.

[0054] In summary, a comprehensive performance evaluation method for a computer motherboard according to an embodiment of the present application is described. It provides a list of matching test components based on the motherboard model to build a test host and identify hardware information. Then, a trained machine learning model is used to jointly analyze the hardware identification information with the expected standardized BIOS configuration parameters. The model uses the optimal configuration strategy learned from massive historical tuning data to generate optimized underlying BIOS setting values ​​and operation sequences, which are automatically applied to the motherboard firmware of the computer motherboard to be tested to perform CPU, memory, storage, and image performance testing and comprehensive performance scoring. This method effectively simplifies the computer motherboard performance testing process, reduces reliance on technician experience, and achieves automated, in-depth evaluation of computer motherboard performance through intelligent BIOS optimization.

[0055] Furthermore, the present application also provides a computer motherboard comprehensive performance evaluation system.

[0056] Figure 4 FIG. 1 is a block diagram of a computer motherboard comprehensive performance evaluation system according to an embodiment of the present application. Figure 4 As shown, according to an embodiment of the present application, a computer motherboard comprehensive performance evaluation system 100 includes: a component list configuration module 110, which is used to provide a component list to be tested based on the motherboard model of the computer motherboard to be tested, wherein the computer motherboard to be tested and the component list to be tested are used to guide the construction of a test host; a hardware information identification module 120, which is used to run a hardware identification tool on the test host to obtain hardware identification information after inserting a pre-OS boot medium; a configuration parameter acquisition module 130, which is used to obtain standardized BIOS configuration parameters expected in a task; a configuration parameter optimization module 140, which is used to combine the hardware identification information with the expected hardware identification information in the task. Standardized BIOS configuration parameters are input into the trained machine learning model to obtain optimized underlying BIOS setting values ​​and operation sequences; a configuration parameter application module 150 is used to apply the optimized underlying BIOS setting values ​​and operation sequences to the motherboard firmware of the computer motherboard to be tested through the underlying interface; a performance testing module 160 is used to test the host to start the performance testing process to obtain CPU performance test data, memory performance test data, storage performance test data and image performance test data; a performance scoring module 170 is used to generate a comprehensive performance scoring value based on the CPU performance test data, memory performance test data, storage performance test data and image performance test data.

[0057] Here, those skilled in the art will appreciate that the specific operations of each module in the above-mentioned computer motherboard comprehensive performance evaluation system have been described in the above-mentioned Figures 1 to 3 The method for evaluating the comprehensive performance of a computer motherboard has been described in detail, and therefore, its repeated description will be omitted.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A computer motherboard comprehensive performance evaluation method, characterized in that: include: Based on the motherboard model of the computer motherboard to be tested, a list of components to be tested is provided, wherein the computer motherboard to be tested and the list of components to be tested are used to guide the construction of the test host; After inserting the pre-OS boot medium, the test host runs a hardware identification tool to obtain hardware identification information; Obtain the standardized BIOS configuration parameters expected in the task; Inputting the hardware identification information and the standardized BIOS configuration parameters expected in the task into the trained machine learning model to obtain optimized underlying BIOS setting values ​​and operation sequences; Applying the optimized underlying BIOS setting values ​​and operation sequences to the motherboard firmware of the computer motherboard to be tested through the underlying interface; The test host starts a performance test process to obtain CPU performance test data, memory performance test data, storage performance test data, and image performance test data; Generate a comprehensive performance score based on CPU performance test data, memory performance test data, storage performance test data, and image performance test data.

2. The computer motherboard comprehensive performance evaluation method according to claim 1, characterized in that: The hardware identification information includes motherboard manufacturer, model, sub-model, BIOS version string, CPU model, stepping, number of cores, base frequency, TDP, memory module information, graphics card model and connection method.

3. The computer motherboard comprehensive performance evaluation method according to claim 2, characterized in that: Inputting the hardware identification information and the standardized BIOS configuration parameters expected in the task into the trained machine learning model to obtain optimized underlying BIOS setting values ​​and operation sequences, including: Performing structured coding on the hardware identification information to obtain a hardware identification information structured coding vector; Performing structured encoding on the standardized BIOS configuration parameters expected in the task to obtain a target function description structured encoding vector; Performing vector splicing on the hardware identification information structured coding vector and the target function description structured coding vector to obtain a hardware information-target function splicing structured coding vector; The hardware information-target function splicing structured coding vector is input into the trained machine learning model to obtain the optimized underlying BIOS setting value and operation sequence.

4. The computer motherboard comprehensive performance evaluation method according to claim 3, characterized in that: The machine learning model after input training is a Seq2Seq model, which includes an encoder based on a Transformer architecture and a decoder based on an RNN network.

5. The computer motherboard comprehensive performance evaluation method according to claim 3, characterized in that: Inputting the hardware information-target function concatenated structured coding vector into the trained machine learning model to obtain the optimized underlying BIOS setting value and operation sequence, including: Performing feature embedding density adaptive modulation on the hardware information-target function splicing structured coding vector to obtain an optimized hardware information-target function splicing structured coding vector; The optimized hardware information-target function splicing structured coding vector is input into the trained machine learning model to obtain the optimized underlying BIOS setting value and operation sequence.

6. The computer motherboard comprehensive performance evaluation method according to claim 5, characterized in that: Performing feature embedding density adaptive modulation on the hardware information-target function splicing structured coding vector to obtain an optimized hardware information-target function splicing structured coding vector, including: Calculating a covariant gradient matrix of the hardware information-target function concatenated structured coding vector to obtain a first hardware information-target function feature covariant gradient matrix and a second hardware information-target function feature covariant gradient matrix; Based on the first hardware information-target function feature covariance gradient matrix and the second hardware information-target function feature covariance gradient matrix, performing long-range dependency modulation on the hardware information-target function splicing structured coding vector to obtain a hardware information-target function splicing structured long-range dependency coding vector; Based on the first hardware information-target function feature covariance gradient matrix and the second hardware information-target function feature covariance gradient matrix, performing local covariance sensitivity modulation on the hardware information-target function splicing structured coding vector to obtain a hardware information-target function splicing structured local sensitivity enhanced coding vector; Based on the hardware information-target function splicing structured long-range dependency coding vector and the hardware information-target function splicing structured local sensitivity enhancement coding vector, the hardware information-target function splicing structured coding vector is feature collaboratively modulated to obtain the optimized hardware information-target function splicing structured coding vector.

7. The computer motherboard comprehensive performance evaluation method according to claim 1, characterized in that: Generates a comprehensive performance score based on CPU performance test data, memory performance test data, storage performance test data, and image performance test data, including: Generate a CPU performance test score based on the CPU performance test data; Generating a memory performance test score value based on the memory performance test data; Generating a storage performance test score value based on the storage performance test data; generating an image performance test score value based on the image performance test data; The comprehensive performance score is calculated based on the CPU performance test score, the memory performance test score, the storage performance test score, and the image performance test score.

8. The computer motherboard comprehensive performance evaluation method according to claim 7, characterized in that: Calculating the comprehensive performance score based on the CPU performance test score, the memory performance test score, the storage performance test score, and the image performance test score includes: A weighted sum of the CPU performance test score, the memory performance test score, the storage performance test score, and the image performance test score is calculated to obtain the comprehensive performance score.

9. A computer motherboard comprehensive performance evaluation system, characterized in that: include: A component list configuration module, configured to provide a list of components to be tested based on the motherboard model of the computer motherboard to be tested, wherein the computer motherboard to be tested and the list of components to be tested are used to guide the construction of a test host; A hardware information identification module, configured to enable the test host to run a hardware identification tool to obtain hardware identification information after the pre-OS boot medium is inserted; Configuration parameter acquisition module, used to obtain the standardized BIOS configuration parameters expected in the task; a configuration parameter optimization module, configured to input the hardware identification information and the standardized BIOS configuration parameters expected in the task into the trained machine learning model to obtain optimized underlying BIOS setting values ​​and operation sequences; A configuration parameter application module, configured to apply the optimized underlying BIOS setting values ​​and operation sequences to the motherboard firmware of the computer motherboard to be tested through an underlying interface; The performance test module is used to test the host to start the performance test process to obtain CPU performance test data, memory performance test data, storage performance test data and image performance test data; The performance scoring module is used to generate a comprehensive performance scoring value based on CPU performance test data, memory performance test data, storage performance test data and image performance test data.

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