A method and system for improving bandwidth optimization of neural network accelerators
By optimizing the data processing pipeline and cache structure of the neural network accelerator, the memory bandwidth bottleneck problem was solved, memory bandwidth utilization and hardware accelerator performance were improved, and more efficient parallel computing was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- RICE MICROELECTRONICS
- Filing Date
- 2025-07-09
- Publication Date
- 2026-07-24
AI Technical Summary
Existing neural network accelerators suffer from low memory bandwidth utilization due to memory bandwidth bottlenecks, which affects computing speed and overall performance. Existing solutions also increase hardware power consumption and cost.
It employs a convolutional pipeline, a single data processor, an on-chip cache, planar and channel data processors, and a data reassembly engine. By replacing traditional storage with an on-chip cache, it optimizes data transmission and caching, reduces external storage reads and writes, and improves memory bandwidth utilization.
Without increasing hardware power consumption, it improves memory bandwidth utilization, reduces single-process time, and enhances the performance and parallel computing efficiency of hardware accelerators.
Smart Images
Figure CN120654757B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of neural network accelerator technology, and more specifically, to a method and system for optimizing the bandwidth of neural network accelerators. Background Technology
[0002] Convolutional Neural Networks (CNNs) are widely used in various deep learning fields, especially in edge computing applications. In mobile devices, the availability of computing and storage resources is often limited, necessitating more efficient hardware to achieve smaller storage requirements, faster inference, and lower power consumption. However, the increasing complexity of CNN algorithms leads to significantly higher computational and storage demands, posing a significant challenge to the design of Deep Neural Network (DNN) hardware accelerators. In fields such as artificial intelligence and visual inspection, a large number of matrix operations are required. To process signals as quickly as possible, hardware accelerators are typically needed to improve the efficiency of parallel computing to enable rapid algorithm inference.
[0003] With the emergence of various neural network algorithms, various neural network accelerators have also appeared. Early neural network accelerators were designed for specific networks. To improve the versatility and flexibility of neural network accelerators, general-purpose neural network accelerators were designed.
[0004] Currently, mainstream hardware accelerators have the following drawback: because each step of the computation after convolution processing needs to be cached in memory, the memory bandwidth bottleneck limits the memory bandwidth utilization of a single operation, resulting in insufficient overall computational speed and significant room for improvement in overall accelerated computational performance.
[0005] The current solution to the problem of low memory bandwidth utilization in hardware accelerators is mainly to improve storage performance by using high-performance external storage units, such as HBM. However, this results in higher overall power consumption and cost for the hardware accelerator, while bandwidth utilization remains limited by the memory, making it impossible to break through the bottleneck.
[0006] There are currently no effective solutions to the problems in the relevant technologies. Summary of the Invention
[0007] In view of the problems in the related technologies, the present invention proposes a method and system for improving the bandwidth optimization of neural network accelerators, so as to overcome the above-mentioned technical problems existing in the existing related technologies.
[0008] Therefore, the specific technical solution adopted by the present invention is as follows:
[0009] According to one aspect of the present invention, a method for improving the bandwidth optimization of a neural network accelerator is provided, the method comprising the following steps:
[0010] S1. Perform convolution processing on the input data using a convolution pipeline;
[0011] S2. Use a single data processor to process the data after convolution using an activation function.
[0012] S3. An on-chip cache is used instead of traditional on-chip storage for caching, and the data processed by the activation function is pooled and local response normalized by a plane data processor and a channel data processor.
[0013] S4. The data format of the data after local response normalization is converted by the data reconstruction engine, and the data transfer between the dynamic random access memory and the high-performance storage interface is realized.
[0014] Furthermore, the convolutional processing of the input data through the convolution pipeline includes the following steps:
[0015] S11. Use code division multiple access to read the images, feature values and weights to be convolved in batches, and store them in the convolution buffer in the order of the data required for convolution.
[0016] S12. Transfer data from the convolution buffer to the convolution sequence controller to calculate and control the decomposition of the convolution sequence and execute the logic of loading the feature, pixel, and weight sequences.
[0017] Furthermore, the data is transferred from the convolutional buffer to the convolutional sequence controller for calculating and controlling the decomposition of the convolutional sequence, and for executing the logic of loading the feature, pixel, and weight sequences, including the following steps:
[0018] S121. The data and weights processed by the convolution sequence controller are transmitted to the multiply-accumulate unit and multiply-accumulate calculation is performed.
[0019] S122. Transfer the result of the multiplication and accumulation calculation to the accumulator, perform accumulation calculation on the partial sum, retain the significant number of bits of the calculation result, and use it as input to the single data processor.
[0020] Furthermore, the activation function processing of the convolutional data using a single data processor includes the following steps:
[0021] S21. Bias addition using a linear function in the convolutional layer;
[0022] S22. Operate the activation layer using nonlinear functions;
[0023] S23. In the batch normalization stage, perform batch normalization operation on each layer of parameters and provide the standard deviation parameter.
[0024] S24. Using element-wise operations, perform element-wise multiplication on two sets of data matrices of the same size to obtain two sets of input data.
[0025] S25. The two sets of input data are converted in format by a single data processor and adapted to different hardware layers;
[0026] S26. Extract the two sets of input data after format conversion and compare their values.
[0027] Furthermore, using on-chip caches instead of traditional on-chip storage for caching, and performing pooling and local response normalization on the data processed by the activation function through a planar data processor and a channel data processor, includes the following steps:
[0028] S31. Use a planar data processor to perform maximum, minimum, and partial summation operations on the two sets of input data after format conversion;
[0029] S32. Perform pooling operations on the two sets of input data after performing maximum, minimum operations and partial summation in the plane.
[0030] S33. After the pooling operation is completed, if the pooling type is max pooling, the two sets of input data in the shared row cache are used as the final result. If the pooling type is average pooling, the two sets of input data are extracted from the shared row cache and a division operation is performed to calculate the average value.
[0031] S34. The channel data processor receives two sets of pooled input data from the on-chip buffer and performs local response normalization on the two sets of input data.
[0032] Furthermore, the channel data processor receives the two sets of pooled input data from the on-chip buffer and performs local response normalization on the two sets of input data, including the following steps:
[0033] S341. Process the two sets of input data using local response normalization, and determine whether to use the channel data processor by configuring the corresponding registers;
[0034] S342. After processing, the channel data processor writes the two sets of input data that have undergone local response normalization into the buffer.
[0035] Furthermore, the data format is converted after the local response normalization is processed by the data reconstruction engine, and the data transfer between the dynamic random access memory and the high-performance storage interface is realized through the following steps:
[0036] S41. The mapping format of the two sets of input data that have undergone local response normalization is changed by the data reconstruction engine.
[0037] S42. The data copy engine moves the two sets of input data between the dynamic random access memory and the high-performance storage interface.
[0038] Furthermore, the working modes of the data reconstruction engine include: 3D data stitching, 3D data to planar data conversion, and planar data merging with 3D data.
[0039] Furthermore, methods for changing the mapping format of data include: splitting, slicing, merging, shrinking, and reshaping / transposing.
[0040] According to another aspect of the present invention, a system for improving the bandwidth optimization of a neural network accelerator is also provided, the system comprising:
[0041] The convolution pipeline module is used to perform convolution processing on the input data through the convolution pipeline.
[0042] The single data processor module is used to process the convolutional data using activation functions.
[0043] An on-chip cache module is used to replace traditional on-chip storage for caching.
[0044] The planar data processor module is used to perform pooling processing on the data processed by the activation function.
[0045] The channel data processor module is used to perform local response normalization on the pooled data through the channel data processor.
[0046] The data reconstruction engine module is used to convert the data format of the data after local response normalization processing through the data reconstruction engine.
[0047] The data copy engine module is used to realize data transfer between dynamic random access memory and high-performance storage interface.
[0048] The beneficial effects of this invention are as follows:
[0049] 1. This invention optimizes the data storage and read / write process during accelerated computation in hardware accelerators, reducing the two read / write processes between the single data processor, the planar data processor, and external storage. Instead, on-chip caches are used to replace them. Without affecting data caching and read / write speeds, this invention effectively improves memory bandwidth utilization, reduces the time consumed in a single accelerated computation, and enhances the performance of the hardware accelerator.
[0050] 2. This invention utilizes an on-chip cache to replace static random access memory (SRAM) when data is transmitted between a single data processor, a planar data processor, and a channel data processor. This reduces the amount of SRAM and double the bandwidth required for a single operation, thereby improving memory bandwidth utilization during parallel operations. Attached Figure Description
[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0052] Figure 1 This is a flowchart of a method for improving the bandwidth optimization of neural network accelerators according to an embodiment of the present invention;
[0053] Figure 2 This is a block diagram of a system for optimizing the bandwidth of a neural network accelerator according to an embodiment of the present invention.
[0054] Figure 3 This is a pre-optimization design diagram of a method for improving the bandwidth of a neural network accelerator according to an embodiment of the present invention;
[0055] Figure 4 This is an optimized design diagram of a method for improving the bandwidth of a neural network accelerator according to an embodiment of the present invention;
[0056] Figure 5 This is a schematic diagram of the structure of an on-chip cache according to an embodiment of the present invention;
[0057] Figure 6 This is the timing flowchart of the present invention;
[0058] Figure 7 It is a traditional sequence flowchart.
[0059] In the picture:
[0060] 1. Convolutional Pipeline Module; 2. Single Data Processor Module; 3. On-Chip Buffer Module; 4. Planar Data Processor Module; 5. Channel Data Processor Module; 6. Data Reassembly Engine Module; 7. Data Copy Engine Module. Detailed Implementation
[0061] To further illustrate the various embodiments, the present invention provides accompanying drawings, which are part of the disclosure of the present invention. These drawings are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these drawings, those skilled in the art should be able to understand other possible implementation methods and the advantages of the present invention. The components in the drawings are not drawn to scale, and similar component symbols are generally used to represent similar components.
[0062] According to embodiments of the present invention, a method and system for improving the bandwidth optimization of neural network accelerators are provided.
[0063] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments, such as... Figure 1 As shown, according to an embodiment of the present invention, a method for improving the bandwidth of a neural network accelerator includes the following steps:
[0064] S1. Perform convolution processing on the input data using the convolution pipeline;
[0065] It's important to explain that the input data is processed through a convolution pipeline. The convolution pipeline is one of the core logic components of the hardware accelerator, used to accelerate convolution algorithms and support programmable control of the convolution size. Winograd and Multi-Batch technologies are applied in the convolution pipeline to improve the efficiency of the multiply-accumulate unit and computational performance. In this step, the images, feature values, weights, and other data to be convolved are first read in batches via Code Division Multiple Access (CDMA) and stored in the convolution buffer (CBUF) according to the data order required for convolution to meet the computational needs of the convolution engine. Subsequently, the data is transferred from the convolution buffer (CBUF) to the Convolution Sequence Controller (CSC) to calculate and control the decomposition of the convolution sequence and execute the logic for loading the feature, pixel, and weight sequences. The data and weights processed by the Convolution Sequence Controller (CSC) are then transferred to the Multiply-Accumulate Unit (CMAC), where its 16 integrated multiply-accumulate units perform INT16 and FP16 calculations, POA-based addition, and other operations. The accumulator (CACC) is the last module in the convolution pipeline. It is mainly responsible for receiving the data output from the multiply-accumulator (CMAC), accumulating the partial sums, retaining the number of significant bits in the result, and using it as the input to the single data processor (SDP).
[0066] S2. Use a single data processor (SDP) to process the convolutional data using an activation function;
[0067] It should be explained that the Single Data Processor (SDP) processes the single data after convolution calculation using activation functions, applying linear and nonlinear functions to the target data. First, SDP uses linear functions to perform simple bias addition or scaling on convolutional layers. Second, it uses non-linear functions to perform operations on activation layers. Third, it performs batch normalization, supporting batch normalization of parameters per layer or per channel, and providing mean / standard variance parameters. Next, it performs element-wise operations (Element-Wise Layer), multiplying or otherwise calculating corresponding elements between two data matrices of the same size. In online mode, one set of data comes from the convolution pipeline, and the other set comes from memory; in offline mode, SDP retrieves both sets of input data from memory. SDP also provides a PReLU mode, where multipliers ignore positive values and only scale negative values. Next, SDP performs input data format conversion, supporting INT8, INT16, and FP16 precision to adapt to different hardware layers, allowing SDP to perform precision conversion and other operations simultaneously. Finally, it performs numerical comparison, retrieving two sets of input data from storage and comparing them. To save bandwidth, no output is written to external memory in comparison mode.
[0068] S3. An on-chip buffer (FIFO) is used instead of traditional on-chip storage for caching, and the data processed by the activation function is pooled and local response normalization (LRN) is performed through a plane data processor (PDP) and a channel data processor (CDP).
[0069] It's important to explain that, without external memory, the data processed by the SDP is directly transferred to the Plane Data Processor (PDP) via an on-chip FIFO for pooling. The PDP performs planar operations along the width × height, and is configurable at runtime, supporting max, min, and average pooling. The calculation method involves sending several adjacent inputs within the plane to a nonlinear function to calculate a local result. Pooling operations are completed within a single plane. There is no interference between different planes. The main logic processing in the PDP is handled by the preprocessing and postprocessing units. These two units are responsible for the main size comparison operations or averaging calculations: First, preprocessing is performed, mainly handling max, min, and partial summation operations; second, postprocessing is performed, mainly for average pooling. If it's max / min pooling, the shared line buffer is the final result; if it's average pooling, the postprocessing unit retrieves data from the shared line buffer and performs division operations.
[0070] It's important to explain that the Channel Data Processor (CDP) receives data buffered by the PDP from the on-chip FIFO, uses it for the Local Response Normalization (LRN) function, and finally writes the processed data back to the buffer for subsequent processing by the Data Reassembly Engine (RUBIK) and Data Copy Engine (BDMA). The CDP primarily performs LRN, mainly for Lateral Inhibition. The CDP can be used or skipped by configuring the appropriate registers. Besides LRN, the CDP can also accelerate per-channel quantization calculations.
[0071] It needs to be explained that, for example Figure 5 As shown, an on-chip FIFO (First-In-First-Out) data buffer has no external read / write address lines and only performs sequential read / write operations. The FIFO has a built-in clock, pointer, and full / empty flags to ensure sequential read / write operations. After the FIFO is reset, the read and write pointers are equal and both are empty; at this time, the FIFO is empty, and read operations are only possible for write operations. When there is no space to write, the pointer position is SIZE-1. Performing a write operation at this time will cause the pointer to roll back to 0, and the read and write pointers will be equal again. When the FIFO is full or about to be full, a full flag is sent to prevent further write operations and overflow; when the FIFO is empty or about to be empty, an empty flag is sent to prevent further read operations and invalid data from being read.
[0072] S4. The data format of the data after Local Response Normalization (LRN) is converted by the Data Reassembly Engine (RUBIK), and data transfer between Dynamic Random Access Memory (DRAM) and High-Performance Storage Interface is realized.
[0073] It's important to explain that the Data Reconstruction Engine (RUBIK) receives processed data from the Channel Data Processor (CDP) and performs data format conversion. During inference in convolutional networks, data in memory often needs to be reconfigured or reshaped. The Data Reconstruction Engine (RUBIK) does not perform any data computation; it includes three working modes: 3D data stitching, 3D data to planar data, and planar data merging with 3D data. It is responsible for changing the data mapping format, such as segmentation, slicing, merging, shrinking, and reshaping / transposing.
[0074] It's important to explain that the Data Copy Engine (BDMA) handles data transfer between Dynamic Random Access Memory (DRAM) and the high-performance storage interface. This is an acceleration channel that directly connects DRAM and the high-performance storage interface. In this invention, both the input image and the final processed result need to be stored in external DRAM. However, the bandwidth and latency of external DRAM are limited, thus requiring Static Random Access Memory (SRAM) as auxiliary memory. To ensure data synchronization between SRAM and DRAM, BDMA acts as the mechanism for moving data between them.
[0075] Preferably, the convolution processing of input data through a convolution pipeline includes the following steps:
[0076] S11. Use code division multiple access to read the images, feature values and weights to be convolved in batches, and store them in the convolution buffer in the order of the data required for convolution.
[0077] S12. Transfer data from the convolution buffer to the convolution sequence controller to calculate and control the decomposition of the convolution sequence and execute the logic of loading the feature, pixel, and weight sequences.
[0078] Preferably, transferring data from the convolutional buffer to the convolutional sequence controller for calculating and controlling the decomposition of the convolutional sequence, and executing the logic of loading the feature, pixel, and weight sequences, includes the following steps:
[0079] S121. The data and weights processed by the convolution sequence controller are transmitted to the multiply-accumulate unit and multiply-accumulate calculation is performed.
[0080] S122. Transfer the result of the multiplication and accumulation calculation to the accumulator, perform accumulation calculation on the partial sum, retain the significant number of bits of the calculation result, and use it as input to the single data processor.
[0081] Preferably, the activation function processing of the convolutional data using a single data processor includes the following steps:
[0082] S21. Bias addition using a linear function in the convolutional layer;
[0083] S22. Operate the activation layer using nonlinear functions;
[0084] S23. In the batch normalization stage, perform batch normalization operation on each layer of parameters and provide the standard deviation parameter.
[0085] S24. Using element-wise operations, perform element-wise multiplication on two sets of data matrices of the same size to obtain two sets of input data.
[0086] S25. The two sets of input data are converted in format by a single data processor and adapted to different hardware layers;
[0087] S26. Extract the two sets of input data after format conversion and compare their values.
[0088] Preferably, using an on-chip cache instead of traditional on-chip storage for caching, and performing pooling and local response normalization on the data processed by the activation function using a planar data processor and a channel data processor, includes the following steps:
[0089] S31. Use a planar data processor to perform maximum, minimum, and partial summation operations on the two sets of input data after format conversion;
[0090] S32. Perform pooling operations on the two sets of input data after performing maximum, minimum operations and partial summation in the plane.
[0091] S33. After the pooling operation is completed, if the pooling type is max pooling, the two sets of input data in the shared row cache are used as the final result. If the pooling type is average pooling, the two sets of input data are extracted from the shared row cache and a division operation is performed to calculate the average value.
[0092] S34. The channel data processor receives two sets of pooled input data from the on-chip buffer and performs local response normalization on the two sets of input data.
[0093] Preferably, the process of receiving two sets of pooled input data from the on-chip buffer using a channel data processor and performing local response normalization on the two sets of input data includes the following steps:
[0094] S341. Process the two sets of input data using local response normalization, and determine whether to use the channel data processor by configuring the corresponding registers;
[0095] S342. After processing, the channel data processor writes the two sets of input data that have undergone local response normalization into the buffer.
[0096] Preferably, the data format conversion of the data after local response normalization processing by the data reconstruction engine, and the data transfer between the dynamic random access memory and the high-performance storage interface, includes the following steps:
[0097] S41. The mapping format of the two sets of input data that have undergone local response normalization is changed by the data reconstruction engine.
[0098] S42. The data copy engine moves the two sets of input data between the dynamic random access memory and the high-performance storage interface.
[0099] Preferably, the working modes of the data reconstruction engine include: 3D data stitching, 3D data to planar data conversion, and planar data merging with 3D data.
[0100] Preferably, the methods for changing the mapping format of data include: splitting, slicing, merging, shrinking, and reshaping / transposing.
[0101] According to another embodiment of the invention, such as Figure 2 As shown, a system for improving the bandwidth optimization of neural network accelerators is also provided, the system comprising:
[0102] Convolutional pipeline module 1 is used to perform convolution processing on the input data through the convolutional pipeline;
[0103] Single data processor module 2 is used to perform activation function processing on the convolutional data using a single data processor;
[0104] On-chip cache module 3 is used to replace traditional on-chip storage for caching;
[0105] Planar data processor module 4 is used to perform pooling processing on the data processed by the activation function through the planar data processor;
[0106] Channel data processor module 5 is used to perform local response normalization processing on the pooled data through the channel data processor;
[0107] Data reconstruction engine module 6 is used to convert the data format of the data after local response normalization through the data reconstruction engine;
[0108] Data copy engine module 7 is used to realize data transfer between dynamic random access memory and high-performance storage interface.
[0109] In summary, by means of the above-mentioned technical solution of the present invention, the present invention utilizes an on-chip cache to replace the static random access memory for caching when data is transmitted between a single data processor, a planar data processor, and a channel data processor, thereby reducing the occupation of static random access memory and double the bandwidth of a single operation, and thus improving the memory bandwidth utilization during parallel operation.
[0110] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for optimizing the bandwidth of neural network accelerators, characterized in that, The method for improving the bandwidth optimization of neural network accelerators includes the following steps: S1. Perform convolution processing on the input data using a convolution pipeline; S2. Use a single data processor to process the data after convolution using an activation function. S3. An on-chip cache is used instead of traditional on-chip storage for caching, and the data processed by the activation function is pooled and local response normalized by a plane data processor and a channel data processor. S4. The data format of the data after local response normalization is converted by the data reconstruction engine, and the data transfer between the dynamic random access memory and the high-performance storage interface is realized. The convolution process for input data using a convolution pipeline includes the following steps: S11. Use code division multiple access to read the images, feature values and weights to be convolved in batches, and store them in the convolution buffer in the order of the data required for convolution. S12. Transfer data from the convolution buffer to the convolution sequence controller to calculate and control the decomposition of the convolution sequence and execute the logic of loading the feature, pixel, and weight sequences. The process of transferring data from the convolutional buffer to the convolutional sequence controller for calculating and controlling the decomposition of the convolutional sequence, and executing the logic for loading the feature, pixel, and weight sequences, includes the following steps: S121. The data and weights processed by the convolution sequence controller are transmitted to the multiply-accumulate unit and multiply-accumulate calculation is performed. S122. Transfer the result of the multiplication and accumulation calculation to the accumulator, perform accumulation calculation on the partial sum, retain the significant number of bits of the calculation result, and use it as the input of the single data processor. S3 includes the following steps: S31. Use a planar data processor to perform maximum, minimum, and partial summation operations on the two sets of input data after format conversion; S32. Perform pooling operations on the two sets of input data after performing maximum, minimum operations and partial summation in the plane. S33. After the pooling operation is completed, if the pooling type is max pooling, the two sets of input data in the shared row cache are used as the final result. If the pooling type is average pooling, the two sets of input data are extracted from the shared row cache and a division operation is performed to calculate the average value. S34. Utilize the channel data processor to receive two sets of pooled input data from the on-chip buffer, and perform local response normalization processing on the two sets of input data. S34 includes the following steps: S341. Process the two sets of input data using local response normalization, and determine whether to use the channel data processor by configuring the corresponding registers; S342. After processing, the channel data processor writes the two sets of input data that have undergone local response normalization into the buffer.
2. The method for optimizing bandwidth of neural network accelerators according to claim 1, characterized in that, The process of using a single data processor to perform activation function processing on the convolutional data includes the following steps: S21. Bias addition using a linear function in the convolutional layer; S22. Operate the activation layer using nonlinear functions; S23. In the batch normalization stage, perform batch normalization operation on each layer of parameters and provide the standard deviation parameter. S24. Using element-wise operations, perform element-wise multiplication on two sets of data matrices of the same size to obtain two sets of input data. S25. The two sets of input data are converted in format by a single data processor and adapted to different hardware layers; S26. Extract the two sets of input data after format conversion and compare their values.
3. The method for optimizing bandwidth of neural network accelerators according to claim 1, characterized in that, The process of converting the data format of the data after local response normalization through a data reconstruction engine and realizing data transfer between dynamic random access memory and high-performance storage interface includes the following steps: S41. The mapping format of the two sets of input data that have undergone local response normalization is changed by the data reconstruction engine. S42. The data copy engine moves the two sets of input data between the dynamic random access memory and the high-performance storage interface.
4. The method for optimizing bandwidth of neural network accelerators according to claim 3, characterized in that, The working modes of the data reconstruction engine include: 3D data stitching, 3D data to planar data conversion, and planar data merging with 3D data.
5. The method for optimizing bandwidth of a neural network accelerator according to claim 3, characterized in that, The methods for changing the mapping format of the data include: splitting, slicing, merging, shrinking, and reshaping / transposing.
6. A system for optimizing the bandwidth of a neural network accelerator, used to implement the method for optimizing the bandwidth of a neural network accelerator as described in any one of claims 1-5, characterized in that, The system for improving bandwidth optimization in neural network accelerators includes: The convolution pipeline module is used to perform convolution processing on the input data through the convolution pipeline. The single data processor module is used to process the convolutional data using activation functions. An on-chip cache module is used to replace traditional on-chip storage for caching. The planar data processor module is used to perform pooling processing on the data processed by the activation function. The channel data processor module is used to perform local response normalization on the pooled data through the channel data processor. The data reconstruction engine module is used to convert the data format of the data after local response normalization processing through the data reconstruction engine. The data copy engine module is used to realize data transfer between dynamic random access memory and high-performance storage interface.