Chip-type piezoresistor and electronic device
By employing a multi-layer ceramic material stacking design and internal electrode structure in the chip varistor, a multi-layer potential gradient is formed, solving the problem that existing chip varistors cannot cope with wide-range surge impacts, and achieving broader surge protection and a longer service life.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN SUNLORD ELECTRONICS
- Filing Date
- 2025-06-16
- Publication Date
- 2026-06-26
Smart Images
Figure CN120656807B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic equipment technology, and in particular to a chip varistor and an electronic device. Background Technology
[0002] Currently, surface-mount varistors are commonly found in electronic devices. Compared to traditional overcurrent and overvoltage protection components, surface-mount varistors offer advantages such as fast response, small size, light weight, and low power consumption. However, in some electronic devices, surface-mount varistors may be exposed to wide-range surges, such as current surges and voltage surges. Taking voltage surges as an example, multilayer varistors can typically be subjected to voltage surges ranging from 10V to 2.8KV.
[0003] In related technologies, surface-mount varistors often use a single base material. Due to the limitation of this single material, the surface-mount varistor can usually only respond to a single current surge or voltage surge, or its surge response range is fixed. When the surge range exceeds the surge response range of the surface-mount varistor, long-term use may cause the surface-mount varistor to overheat or even burn out, affecting the reliability of electronic equipment. Summary of the Invention
[0004] This application discloses a chip varistor and electronic device for improving the surge protection range of the chip varistor.
[0005] To achieve the above objectives, in a first aspect, this application discloses a chip varistor, comprising:
[0006] A varistor ceramic body includes a first material layer and a second material layer, which are stacked along the thickness direction of the varistor ceramic body. The ceramic materials of the first material layer and the second material layer are different, so that a potential gradient difference is formed between adjacent first material layers and second material layers.
[0007] The cover plate structure includes an upper cover plate and a lower cover plate. Along the thickness direction of the pressure-sensitive ceramic body, the upper cover plate is located on the upper side of the first material layer, and the lower cover plate is located on the lower side of the second material layer.
[0008] Two external electrodes are respectively disposed at both ends of the piezoresistive ceramic body and the cover plate structure along the length direction of the piezoresistive ceramic body.
[0009] The inner electrode, which is at least three in number, is provided between the upper cover plate and the first material layer, between the lower cover plate and the second material layer, and between the first material layer and the second material layer, along the thickness direction of the pressure-sensitive ceramic body. Each inner electrode extends along the length direction of the pressure-sensitive ceramic body, so that one end of each inner electrode is alternately connected to the outer electrode.
[0010] As an optional implementation, the potential gradient difference between adjacent first material layers and second material layers is ΔE, wherein ΔE satisfies: 100V / mm≤ΔE≤500V / mm.
[0011] As an optional implementation, the dielectric constant of the first material layer is ε1 and the dielectric constant of the second material layer is ε2, satisfying: ε1 / ε2≥1.5, or ε2 / ε1≥1.5.
[0012] As an optional implementation, the bismuth content of the first material layer is a1, the bismuth content of the second material layer adjacent to the first material layer is a2, and the difference between a1 and a2 is Δa, wherein Δa satisfies: Δa≥1wt%.
[0013] As an optional implementation, both the adjacent first material layer and the second material layer contain a variety of additives. The number of different types of additives in the first material layer is S1, and the number of different types of additives in the second material layer is S2. The difference between S1 and S2 is ΔS, and ΔS satisfies: ΔS≥2.
[0014] As an optional implementation, the upper cover plate is made of ceramic material, and the upper cover plate may be made of the same or different ceramic material as the first material layer and / or the second material layer; and / or,
[0015] The lower cover plate is made of ceramic material, and the ceramic material of the lower cover plate may be the same as or different from that of the first material layer and / or the second material layer.
[0016] As an optional implementation, when the ceramic material of the upper cover plate is different from that of the first material layer and / or the second material layer, the inner electrode is provided between the upper cover plate and the pressure-sensitive ceramic body along the thickness direction of the pressure-sensitive ceramic body; and / or,
[0017] When the ceramic material of the lower cover plate is different from that of the first material layer and / or the second material layer, the inner electrode is provided between the lower cover plate and the pressure-sensitive ceramic body.
[0018] As an optional implementation, the pressure-sensitive ceramic body further includes at least two first material layers, at least two second material layers, and at least two third material layers;
[0019] Along the thickness direction of the pressure-sensitive ceramic body, the first material layer, the second material layer, and the third material layer are sequentially disposed to construct a composite material layer, with two of the composite material layers stacked on top of each other; or,
[0020] Along the thickness direction of the pressure-sensitive ceramic body, two first material layers and two second material layers are alternately arranged, and two third material layers are respectively located on the outermost side of the pressure-sensitive ceramic body.
[0021] As an optional implementation, when the first material layer, the second material layer, and the third material layer are sequentially arranged along the thickness direction of the varistor ceramic body, the potential gradients of the first material layer, the second material layer, and the third material layer change sequentially, and / or the dielectric constants of the first material layer, the second material layer, and the third material layer change sequentially.
[0022] Secondly, this application also discloses an electronic device, comprising:
[0023] As described in the first aspect, the chip varistor.
[0024] Compared with the prior art, the beneficial effects of this application are as follows:
[0025] This application discloses a chip varistor and an electronic device. The chip varistor includes a varistor ceramic body, a cover plate structure, an external electrode, and an internal electrode. The varistor ceramic body includes a first material layer and a second material layer, which are stacked along the thickness direction of the varistor ceramic body. The first material layer and the second material layer are made of different ceramic materials, so that a potential gradient difference is formed between adjacent first material layers and second material layers. The upper cover plate of the cover plate structure is disposed on the first material layer, and the lower cover plate is disposed below the second material layer. The internal electrode is disposed between adjacent first material layers and second material layers, between the upper cover plate and the first material layer, and between the lower cover plate and the second material layer. In the chip varistor disclosed in this application, since adjacent first material layers and second material layers are made of different ceramic materials, a potential gradient difference can be formed between adjacent material layers. Thus, a potential gradient layer is formed between two adjacent internal electrodes of the three internal electrodes, that is, at least two potential gradient layers are formed between the three internal electrodes. Since a set of potential gradient layers can respond to surges within a certain range, when two potential gradient layers are superimposed, the surge response range of the chip varistor is increased, enabling the chip varistor to cope with larger current surges or voltage surges, avoiding damage caused by the chip varistor being subjected to surges exceeding the surge range, and improving the service life of the chip varistor. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 This is a schematic diagram of the structure of the chip varistor disclosed in the embodiments of this application;
[0028] Figure 2 This is a schematic diagram of the first internal structure of the chip varistor disclosed in the embodiments of this application;
[0029] Figure 3 This is a schematic diagram of the second internal structure of the chip varistor disclosed in the embodiments of this application;
[0030] Figure 4 This is a schematic diagram of the third internal structure of the chip varistor disclosed in the embodiments of this application;
[0031] Figure 5 This is a schematic diagram of the fourth internal structure of the chip varistor disclosed in the embodiments of this application;
[0032] Figure 6 This is a schematic diagram of the fifth internal structure of the chip varistor disclosed in the embodiments of this application;
[0033] Figure 7 This is a schematic diagram of the sixth internal structure of the chip varistor disclosed in the embodiments of this application;
[0034] Figure 8 This is a schematic diagram of the seventh internal structure of the chip varistor disclosed in the embodiments of this application;
[0035] Figure 9 This is a schematic diagram of the structure of the electronic device disclosed in the embodiments of this application.
[0036] Explanation of reference numerals in the attached figures:
[0037] 100. Chip varistor; 1. Varistor ceramic body; 1a. Composite material layer; 11. First material layer; 12. Second material layer; 13. Third material layer; 2. External electrode; 3. Internal electrode; 41. Upper cover plate; 42. Lower cover plate;
[0038] 200. Electronic equipment; 201. Circuit board. Detailed Implementation
[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0040] In this application, the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.
[0041] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.
[0042] Furthermore, the terms "installation," "setup," "equipped with," and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.
[0043] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, elements, or components (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, elements, or components. Unless otherwise stated, "a plurality of" means two or more.
[0044] Surface mount varistors are commonly found in electronic devices, serving functions such as overvoltage protection, lightning protection, surge current suppression, spike pulse absorption, voltage limiting, high-voltage arc suppression, noise reduction, and protection of semiconductor components. Compared to traditional overcurrent and overvoltage protection components, surface mount varistors offer advantages such as fast response, small size, light weight, and low power consumption. However, in some electronic devices, surface mount varistors may face wide-range surge impacts, such as current surges and voltage surges. For example, multilayer varistors can typically be subjected to voltage surges ranging from 10V to 2.8KV.
[0045] In related technologies, surface-mount varistors often use a single substrate material, such as zinc oxide (ZnO), and optimize their performance by adjusting the number of zinc oxide substrate layers through stacking. However, due to the limitation of the single material, the homogeneous structure results in a fixed potential gradient (e.g., a potential gradient of 200V / mm-400V / mm). This means that the surface-mount varistor can usually only respond to single current surges or voltage surges, or its surge response range is fixed. When the surge range exceeds the surge response range of the surface-mount varistor, such as during wide-area surge impacts in high-power scenarios like new energy, power systems, and 5G base stations, long-term use may cause the surface-mount varistor to overheat or even burn out, affecting the reliability of electronic equipment.
[0046] Based on this, this application discloses a chip varistor that, through the stacking and structural design of different ceramic material layers, forms a multi-layer potential gradient inside the chip varistor, thereby expanding the surge protection range and improving the service life of the chip varistor.
[0047] The technical solution of this application will be further described below with reference to the embodiments and accompanying drawings.
[0048] Firstly, please refer to the following: Figures 1 to 3 This application discloses a chip varistor 100, which includes a varistor ceramic body 1, external electrodes 2, internal electrodes 3, and a cover plate structure. The varistor ceramic body 1 includes a first material layer 11 and a second material layer 12, which are stacked along the thickness direction of the varistor ceramic body 1. The ceramic materials of the first material layer 11 and the second material layer 12 are different, so that a potential gradient difference is formed between adjacent first material layers 11 and second material layers 12. The cover plate structure includes an upper cover plate 41 and a lower cover plate 42. Along the thickness direction of the varistor ceramic body, the upper cover plate 41 is disposed above the first material layer 11, and the lower cover plate 42 is disposed below the second material layer 12. The two external electrodes 2 are respectively disposed at both ends of the varistor ceramic body 1 and the cover plate structure along the length direction. There are at least three internal electrodes 3. An internal electrode 3 is provided between the upper cover plate 41 and the first material layer 11, between the lower cover plate 42 and the second material layer 12, and between the first material layer 11 and the second material layer 12 along the thickness direction of the pressure-sensitive ceramic body 1. Each internal electrode 3 extends along the length direction of the pressure-sensitive ceramic body 1 so that one end of each internal electrode 3 is alternately connected to the external electrode 2.
[0049] Because the ceramic materials between adjacent first material layer 11 and second material layer 12 are different, a potential gradient can be formed between two adjacent internal electrodes 3. Therefore, when there are at least three internal electrodes 3 in the varistor ceramic body 1, at least two potential gradients can be formed. When the two potential gradients are superimposed, the surge response range of the chip varistor increases, enabling the chip varistor 100 to cope with larger current or voltage surges, avoiding damage caused by the chip varistor 100 being subjected to surges exceeding its range, and improving the service life of the chip varistor 100.
[0050] For example, such as Figure 2 As shown, in the thickness direction of the pressure-sensitive ceramic body 1, the bottommost layer can be the lower cover plate 42, and then from bottom to top, the second material layer 12, the first material layer 11, and the upper cover plate 41 are arranged in sequence.
[0051] Optionally, the upper cover plate 41 is made of the same material as the second material layer 12, and the lower cover plate 42 is made of the same material as the second material layer 12.
[0052] For example, such as Figure 3 As shown, in the thickness direction of the pressure-sensitive ceramic body 1, the bottommost layer can be the first material layer 11, followed by the second material layer 12, the first material layer 11, and the second material layer 12 sequentially from bottom to top. An internal electrode 3 is provided between adjacent first material layers 11 and second material layers 12. It is understood that the bottommost position of the first material layer 11 and the second material layer 12 is not limited. For example, the bottommost layer could be the second material layer 12, followed by the second material layer 12, the first material layer 11, the second material layer 12, and the first material layer 11 sequentially from bottom to top.
[0053] Optionally, the first material layer 11 can be multiple layers, and the second material layer 12 can be multiple layers, with multiple first material layers 11 and multiple second material layers 12 alternately arranged in sequence.
[0054] It is understandable that when multiple layers of first material 11 and multiple layers of second material 12 are alternately arranged, the number of internal electrodes 3 increases accordingly, which can form multiple sets of potential gradient differences. For example, when there are two or more first material layers 11 and two or more second material layers 12, there can be four or more internal electrodes 3, as long as one internal electrode 3 is located between adjacent first material layers 11 and second material layers 12.
[0055] Optionally, the first material layer 11 and the second material layer 12 may be made of pressure-sensitive ceramic materials such as silicon carbide, titanium dioxide, strontium titanate or zinc oxide as substrates, and this application does not make specific limitations.
[0056] It should be noted that, in Figure 2In the example, X indicates the length direction of the pressure-sensitive ceramic body 1, and Y indicates the thickness direction of the pressure-sensitive ceramic body 1. Of course, the above directions are only examples.
[0057] In some embodiments, the potential gradient difference between adjacent first material layer 11 and second material layer 12 is ΔE, where ΔE satisfies: 100V / mm≤ΔE≤500V / mm.
[0058] For example, ΔE can be 100V / mm-150V / mm, 150V / mm-200V / mm, 200V / mm-250V / mm, 250V / mm-300V / mm, 300V / mm-350V / mm, 350V / mm-400V / mm, 400V / mm-450V / mm, 450V / mm-500V / mm, etc. For example, ΔE can be 100V / mm, 125V / mm, 150V / mm, 175V / mm, 200V / mm, 225V / mm, 250V / mm, 275V / mm, 300V / mm, 325V / mm, 350V / mm, 375V / mm, 400V / mm, 425V / mm, 450V / mm, 475V / mm, or 500V / mm, etc.
[0059] In the chip varistor 100 disclosed in this application, a large potential gradient difference between two adjacent first material layers 11 and second material layers 12 is required to ensure a large surge protection range. On the one hand, if ΔE < 100V / mm, the potential gradient difference between two adjacent first material layers 11 and second material layers 12 is small. When two potential gradients are formed between the two first material layers 11 and the two second material layers 12, although the surge protection range is larger than that of existing chip varistors, its surge protection capability is still relatively weak in some application scenarios with high surge protection requirements, such as industrial power supplies and new energy vehicles. On the other hand, an excessively large potential gradient between adjacent first material layers 11 and second material layers 12 should also be avoided. If ΔE > 500V / mm, it may cause excessive differences in electrical performance between adjacent first material layers 11 and second material layers 12, affecting the current carrying capacity, leakage current, and other electrical performance parameters between the material layers, and thus potentially affecting the overall electrical performance of the chip varistor 100.
[0060] Therefore, when setting the potential gradient difference between two adjacent material layers, it is necessary to consider not only the effectiveness of the surge protection range formed by the potential gradient difference between the material layers in different application scenarios, but also the electrical performance between the material layers. In other words, the chip varistor 100 disclosed in this application can not only achieve surge protection over a wide range, but also maintain good current carrying capacity, leakage current and other electrical performance.
[0061] It is understandable that when setting the first material layer 11 and the second material layer 12, the potential gradient of the first material layer 11 may be greater than the potential gradient of the second material layer 12, or the potential gradient of the second material layer 12 may be greater than the potential gradient of the first material layer 11.
[0062] In some embodiments, the dielectric constant of the first material layer 11 is ε1 and the dielectric constant of the second material layer 12 is ε2, satisfying: ε1 / ε2≥1.5, or ε2 / ε1≥1.5.
[0063] It is understandable that when ε1 / ε2≥1.5, that is, the dielectric constant of the first material layer 11 is greater than the dielectric constant of the second material layer 12, and when ε2 / ε1≥1.5, that is, the dielectric constant of the second material layer 12 is greater than the dielectric constant of the first material layer 11.
[0064] It should be noted that the dielectric constants of the first material layer 11 and the second material layer 12 are related to their potential gradients.
[0065] When the ratio of the dielectric constants of the first material layer 11 and the second material layer 12 increases, the potential gradient difference between the first material layer 11 and the second material layer 12 increases accordingly. In other words, the larger the ratio between the first material layer 11 and the second material layer 12, the larger the potential gradient difference between the first material layer 11 and the second material layer 12.
[0066] Therefore, when ε1 / ε2≥1.5, or ε2 / ε1≥1.5, the potential gradient difference between adjacent first material layer 11 and second material layer 12 is relatively large. As a result, when multiple potential gradients are formed within the chip varistor 100, the surge protection range created by the multi-layer potential gradient difference is larger, which is beneficial for improving the surge protection range of the chip varistor 100.
[0067] In some embodiments, the bismuth content of the first material layer 11 is a1, and the bismuth content of the second material layer 12 adjacent to the first material layer 11 is a2. The difference between a1 and a2 is Δa, and Δa satisfies: Δa≥1wt%.
[0068] For example, the main material components of the first material layer 11 may include bismuth oxide, manganese carbonate, chromium oxide, silver nitrate, magnesium oxide, etc., and the main material components of the second material layer 12 may include bismuth oxide, cobalt trioxide, chromium oxide, antimony oxide, etc.
[0069] It is understandable that bismuth, as an important dopant element in varistors, can easily affect the electrical properties of the material layer in the varistor.
[0070] For example, when the bismuth content in the first material layer 11 and the bismuth content in the second material layer 12 differs by a value Δa, it affects the potential gradient difference between the first material layer 11 and the second material layer 12. When Δa ≥ 1wt%, the potential gradient difference between the first material layer 11 and the second material layer 12 can be 100V / mm or higher. In other words, when the first material layer 11 and the second material layer 12 are doped with different amounts of bismuth, such that the bismuth content difference Δa ≥ 1wt%, a large potential gradient difference can be formed between the first material layer 11 and the second material layer 12. Furthermore, when multiple potential gradients are formed within the chip varistor 100, it is beneficial to increase the surge protection range of the chip varistor 100.
[0071] Conversely, if Δa < 1wt%, the potential gradient difference between adjacent first material layer 11 and second material layer 12 is small. When multiple potential gradients are formed within the chip varistor 100, it is difficult to form a large surge protection range.
[0072] In some embodiments, the adjacent first material layer 11 and second material layer 12 each contain a variety of additives. The number of different types of additives in the first material layer 11 is S1, and the number of different types of additives in the second material layer 12 is S2. The difference between S1 and S2 is ΔS, and ΔS satisfies: ΔS≥2.
[0073] When forming the first material layer 11 and the second material layer 12, the electrical properties of the first material layer 11 and the second material layer 12 are changed by controlling the types and quantities of additives added to the first material layer 11 and the second material layer 12, respectively. For example, electrical performance parameters such as potential gradient and dielectric constant can be adjusted so that an effective potential gradient difference is formed between adjacent first material layers 11 and second material layers 12. When multiple layers of first material layers 11 and second material layers 12 form a chip varistor 100, the multiple potential gradients are superimposed to form a larger surge protection range.
[0074] It is understandable that the number of types of additives in the first material layer 11 may be greater than the number of types of additives in the second material layer 12, or the number of types of additives in the second material layer 12 may be greater than the number of types in the first material layer 11.
[0075] Optionally, the additives may include one or more of the following: bismuth oxide, manganese oxide, cadmium oxide, antimony oxide, nickel oxide, silicon oxide, aluminum oxide, gallium oxide, titanium oxide, zirconium oxide, boron oxide, titanium trioxide, indium oxide, yttrium oxide, silver trioxide, praseodymium oxide, etc., without specific limitation herein.
[0076] For example, when the additives in the first material layer 11 are bismuth oxide, manganese oxide, cadmium oxide, antimony oxide, nickel oxide, silicon oxide, aluminum oxide, gallium oxide, and titanium oxide, the additives in the second material layer 12 can be bismuth oxide, manganese oxide, cadmium oxide, antimony oxide, gallium oxide, and titanium oxide.
[0077] In some embodiments, the thickness of the first material layer 11 is not equal to the thickness of the adjacent second material layer 12.
[0078] Understandably, the unit of potential gradient can be V / mm.
[0079] Taking the first material layer 11 and the second material layer 12 under the same electric field as an example, if the potential gradients between the first material layer 11 and the second material layer 12 are different when the voltages are the same, the thicknesses of the first material layer 11 and the second material layer 12 will be unequal. In other words, controlling the thickness difference between the first material layer 11 and the second material layer 12 also helps to control the potential gradient difference between the first material layer 11 and the second material layer 12, thereby increasing the surge protection range of the chip varistor 100.
[0080] In some embodiments, please refer to Figure 4 The upper cover plate 41 may be made of ceramic material, and the ceramic material of the upper cover plate 41 may be the same as or different from that of the first material layer 11 and / or the second material layer 12.
[0081] It is understandable that when multiple first material layers 11 and multiple second material layers 12 are alternately arranged in sequence, the material layer located on the upper side of the pressure-sensitive ceramic body 1 in the thickness direction of the pressure-sensitive ceramic body 1 can be either the first material layer 11 or the second material layer 12.
[0082] In one example, when the first material layer 11 is located on the upper side of the varistor ceramic body 1, the upper cover plate 41 is made of the same ceramic material as the first material layer 11. In this case, the upper cover plate 41 is made of a different ceramic material than the second material layer 12. Alternatively, when the second material layer 12 is located on the upper side of the varistor ceramic body 1, the upper cover plate 41 is made of the same ceramic material as the second material layer 12. In this case, the upper cover plate 41 is made of a different ceramic material than the first material layer 11. The upper cover plate 41 can only serve as a protective function to protect the upper side of the varistor ceramic body 1, thereby protecting the structure of the chip varistor 100.
[0083] In another example, when the first material layer 11 is located above the varistor ceramic body 1, if the ceramic material of the upper cover plate 41 is different from that of the first material layer 11, then the ceramic material of the upper cover plate 41 is the same as that of the second material layer 12. Alternatively, if the second material layer 12 is located above the varistor ceramic body 1, and the ceramic material of the upper cover plate 41 is different from that of the second material layer 12, then the ceramic material of the upper cover plate 41 is the same as that of the first material layer 11. That is, when the upper cover plate 41 is different from its adjacent first material layer 11 or second material layer 12, a potential gradient difference can be formed between the upper cover plate 41 and the first material layer 11 or the second material layer 12. In this way, the number of potential gradient layers within the chip varistor 100 can be increased, which is beneficial for expanding the surge protection range of the chip varistor 100.
[0084] In another example, the ceramic materials of the upper cover plate 41 are different from those of the first material layer 11 and the second material layer 12. When the upper cover plate 41 is arranged adjacent to the first material layer 11 or the second material layer 12, a potential gradient difference can be formed between the upper cover plate 41 and the first material layer 11 or the second material layer 12. In this way, the number of potential gradient layers in the chip varistor 100 can be increased, which is beneficial to expanding the surge protection range of the chip varistor 100.
[0085] Optionally, please see Figure 4 The lower cover plate 42 may be made of ceramic material, and the ceramic material of the lower cover plate 42 may be the same as or different from that of the first material layer 11 and / or the second material layer 12.
[0086] It is understandable that when multiple first material layers 11 and multiple second material layers 12 are alternately arranged in sequence, the material layer located on the lower side of the pressure-sensitive ceramic body 1 in the thickness direction of the pressure-sensitive ceramic body 1 can be either the first material layer 11 or the second material layer 12.
[0087] In one example, when the first material layer 11 is located below the varistor ceramic body 1, the lower cover plate 42 is made of the same ceramic material as the first material layer 11, and the lower cover plate 42 is made of a different ceramic material than the second material layer 12. Alternatively, when the second material layer 12 is located below the varistor ceramic body 1, the lower cover plate 42 is made of the same ceramic material as the second material layer 12, and the lower cover plate 42 is made of a different ceramic material than the first material layer 11. The lower cover plate 42 can serve as a protective function to protect the lower side of the varistor ceramic body 1, thereby protecting the structure of the chip varistor 100.
[0088] In another example, when the first material layer 11 is located below the varistor ceramic body 1, if the ceramic material of the lower cover plate 42 is different from that of the first material layer 11, then the ceramic material of the lower cover plate 42 is the same as that of the second material layer 12. Alternatively, if the second material layer 12 is located below the varistor ceramic body 1, and the ceramic material of the lower cover plate 42 is different from that of the second material layer 12, then the ceramic material of the lower cover plate 42 is the same as that of the first material layer 11. That is, when the material of the lower cover plate 42 is different from that of its adjacent first material layer 11 or second material layer 12, a potential gradient difference can be formed between the lower cover plate 42 and the first material layer 11 or the second material layer 12. In this way, the number of potential gradient layers within the chip varistor 100 can be increased, which is beneficial for expanding the surge protection range of the chip varistor 100.
[0089] In another example, the ceramic materials of the lower cover plate 42 are different from those of the first material layer 11 and the second material layer 12. When the lower cover plate 42 is arranged adjacent to the first material layer 11 or the second material layer 12, a potential gradient difference can be formed between the lower cover plate 42 and the first material layer 11 or the second material layer 12. In this way, the number of potential gradient layers in the chip varistor 100 can be increased, which is beneficial to expanding the surge protection range of the chip varistor 100.
[0090] Optionally, when the ceramic material of the upper cover plate 41 is different from that of the first material layer 11 and / or the second material layer 12, an inner electrode 3 is provided between the upper cover plate 41 and the pressure-sensitive ceramic body 1 along the thickness direction of the pressure-sensitive ceramic body 1.
[0091] For example, the upper cover plate 41, lower cover plate 42, first material layer 11, and second material layer 12 can be arranged such that, along the thickness direction of the varistor ceramic body 1, from top to bottom, they are respectively the upper cover plate 41, the first material layer 11, the second material layer 12, the first material layer 11, the second material layer 12, and the lower cover plate 42. The ceramic material of the upper cover plate 41 is different from that of the first material layer 11, and an internal electrode 3 can be provided between the upper cover plate 41 and the adjacent first material layer 11. In this way, at least four internal electrodes 3 are provided in the chip varistor 100, and a potential gradient is formed between each pair of internal electrodes 3, forming three layers of potential gradients in the chip varistor 100. Therefore, when the ceramic material of the upper cover plate 41 is different from that of the adjacent first material layer 11 or second material layer 12, by placing the inner electrode 3 between the upper cover plate 41 and the first material layer 11 or second material layer 12, an additional potential gradient difference can be formed inside the chip varistor 100 to expand the surge protection range of the chip varistor 100.
[0092] Optionally, when the ceramic material of the lower cover plate 42 is different from that of the first material layer 11 and / or the second material layer 12, an internal electrode 3 is provided between the lower cover plate 42 and the piezoresistive ceramic body 1 along the thickness direction of the piezoresistive ceramic body 1.
[0093] In one example, the upper cover plate 41, lower cover plate 42, first material layer 11, and second material layer 12 can be arranged as follows: along the thickness direction of the varistor ceramic body 1, from top to bottom, they can be the upper cover plate 41, the first material layer 11, the second material layer 12, the first material layer 11, the second material layer 12, and the lower cover plate 42, respectively. The ceramic material of the lower cover plate 42 is different from that of the first material layer 11, and an internal electrode 3 can be provided between the lower cover plate 42 and the adjacent first material layer 11. In this way, the chip varistor 100 has at least four internal electrodes 3, and a potential gradient is formed between each pair of internal electrodes 3, forming three potential gradients within the chip varistor 100. Therefore, when the ceramic material of the lower cover plate 42 is different from that of its adjacent first material layer 11 or second material layer 12, by placing the inner electrode 3 between the upper cover plate 41 and the first material layer 11 or second material layer 12, an additional potential gradient can be formed inside the chip varistor 100 to expand the surge protection range of the chip varistor 100.
[0094] In another example, along the thickness direction of the varistor ceramic body 1, from top to bottom, there can be an upper cover plate 41, a first material layer 11, a second material layer 12, a first material layer 11, a second material layer 12, and a lower cover plate 42. When the ceramic materials of the upper cover plate 41 and the first material layer 11, and the lower cover plate 42 and the second material layer 12 are different, an inner electrode 3 is provided between the upper cover plate 41 and the first material layer 11, and an inner electrode 3 is provided between the lower cover plate 42 and the second material layer 12. An inner electrode 3 is also provided between adjacent first material layers 11 and second material layers 12. At least four potential gradients are formed between the five inner electrodes 3, which helps to increase the surge protection range of the chip varistor 100.
[0095] In some embodiments, the pressure-sensitive ceramic body 1 further includes at least two first material layers 11, at least two second material layers 12 and at least two third material layers 13. Along the thickness direction of the pressure-sensitive ceramic body 1, the first material layers 11, the second material layers 12 and the third material layers 13 are sequentially arranged to construct a combined material layer 1a, and the two combined material layers 1a are stacked.
[0096] For example, please see Figure 5 When the two combined material layers 1a are stacked, that is, along the thickness direction of the varistor ceramic body 1, the first material layer 11, the second material layer 12, the third material layer 13, the first material layer 11, the second material layer 12, and the third material layer 13 can be sequentially arranged. In this way, by placing internal electrodes 3 between the layers, at least four potential gradients can be formed. It can be seen that by setting the third material layer 13 to increase the number of potential gradient layers, the surge protection range of the chip varistor 100 can be increased.
[0097] It is understandable that, along the thickness direction of the pressure-sensitive ceramic body 1, the outermost sides of the two combined material layers 1a can be respectively provided with an upper cover plate 41 and a lower cover plate 42.
[0098] In other embodiments, please refer to Figure 6 Along the thickness direction of the pressure-sensitive ceramic body 1, the two third material layers 13 are located on the outermost side of the pressure-sensitive ceramic body 1.
[0099] In other words, the material layers within the surface-mount varistor 100 can be arranged as follows: third material layer 13, first material layer 11, second material layer 12, first material layer 11, second material layer 12, and third material layer 13. By then adding internal electrodes 3 between the layers, at least four potential gradients can be formed. Therefore, by adding the third material layer 13 to increase the number of potential gradient layers, the surge protection range of the surface-mount varistor 100 can be increased.
[0100] In some embodiments, when the first material layer 11, the second material layer 12, and the third material layer 13 are sequentially disposed along the thickness direction of the varistor ceramic body 1, the potential gradients of the first material layer 11, the second material layer 12, and the third material layer 13 change sequentially, or the dielectric constants of the first material layer 11, the second material layer 12, and the third material layer 13 change sequentially.
[0101] For example, when the first material layer 11, the second material layer 12, and the third material layer 13 form a combined material layer 1a and the two combined material layers 1a are stacked, the potential gradient from the first material layer 11 to the third material layer 13 can decrease or increase sequentially. When the chip varistor 100 receives a surge from low to high, the first material layer 11 to the third material layer 13 can respond step by step according to the sequential change of the potential gradient, and the absorbed surge energy can be released step by step from the third material layer 13 to the first material layer 11. In this way, it is beneficial to expand the surge protection range of the chip varistor 100.
[0102] It should be noted that the dielectric constant of the material layer is generally negatively correlated with its potential gradient. That is, when the potential gradient of the material layer increases, its dielectric constant generally decreases. When the potential gradients of the first material layer 11, the second material layer 12, and the third material layer 13 increase in sequence, their dielectric constants generally decrease in sequence. Conversely, when the potential gradients of the first material layer 11, the second material layer 12, and the third material layer 13 decrease in sequence, their dielectric constants generally increase in sequence.
[0103] To facilitate a better understanding of the solutions in this application, two embodiments and related experimental data are described below.
[0104] Example 1:
[0105] The first material layer 11 is indicated by A, the second material layer 12 by B, the third material layer 13 by C, and the upper cover plate 41 and the lower cover plate 42 are both indicated by D.
[0106] Please see Figure 7 Two first material layers 11, two second material layers 12, and two third material layers 13 are sequentially arranged to form an ABCABC stacked combination. Then, a top cover plate 41 and a bottom cover plate 42 are respectively placed on both sides of this stacked combination to form a DABCABCD stacked combination. Considering that the electrical performance of the chip varistor 100 needs to be adjusted in actual products to achieve the desired application function, another first material layer 11 can be placed between CD to form a DABCABCAD stacked combination. The corresponding parameters of each material layer are shown in Table 1 below:
[0107] Table 1
[0108] Material Potential gradient V / mm Dielectric constant A 800 500 B 500 800 C 200 1200
[0109] The structure of homogeneous zinc oxide (ZnO) using the scheme of this application is compared with that of related technologies in Table 2 below:
[0110] Table 2
[0111] Test Items Example 1: Multilayer Heterogeneous Material Structure Comparative Example 1: Homogeneous Structure Varistor voltage V1mA 10V-100V (adjustable) Fixed values (e.g., 50V, 80V) Throughput Capability IP 1000A 500A Leakage current IL 0.1μA 0.5μA
[0112] As can be seen from Tables 1 and 2 above, by forming a multilayer heterogeneous material structure within the chip varistor 100, a multilayer potential gradient difference is sequentially formed within the chip varistor 100, which enables the varistor voltage of the chip varistor 100 to be adjustable within the range of 10V-100V. Its current carrying capacity is increased by 500A compared to the homogeneous structure in Comparative Example 1, and the leakage current is reduced by 0.4μA.
[0113] Example 2:
[0114] The first material layer 11 is indicated by A, the second material layer 12 is indicated by B, and the third material layer 13 is indicated by C.
[0115] Please see Figure 8 When the first material layer 11, the second material layer 12, and the third material layer 13 are sequentially arranged to form a composite material layer 1a, and two composite material layers 1a are stacked together, the two composite material layers 1a can share the third material layer 13, that is, a layered combination of ABCBA can be formed. The corresponding parameters of each material layer are shown in Table 3 below:
[0116] Table 3
[0117] Material Potential gradient V / mm Dielectric constant A 120 1000 B 300 600 C 600 300
[0118] The structure of homogeneous zinc oxide (ZnO) using the scheme of this application is compared with that of related technologies in Table 4 below:
[0119] Table 4
[0120] Test Items Example 2: Multilayer Heterogeneous Material Structure Comparative Example 2: Homogeneous Structure Varistor voltage V1mA 10V-50V (adjustable) Fixed values (e.g., 20V, 30V) Throughput Capability IP 500A 200A
[0121] As can be seen from Tables 1 and 2 above, the solution of this application forms a multilayer heterogeneous material structure within the chip varistor 100, thereby sequentially forming multiple potential gradient differences within the chip varistor 100. This enables the varistor voltage of the chip varistor 100 to be adjustable within the range of 10V to 50V, and its current carrying capacity is increased by 300A compared to the homogeneous structure in Comparative Example 2.
[0122] Therefore, it can be seen that the chip varistor 100 disclosed in this application can absorb small surges by setting multiple potential gradient differences, and absorb large surges by using low potential gradient differences and high potential gradient differences, so that the surge protection range of the chip varistor 100 can be extended to 10V-3KV.
[0123] In different application scenarios, the potential gradients of the first material layer 11, the second material layer 12, the third material layer 13, the upper cover plate 41, and the lower cover plate 42 can be controlled to form a multi-layer potential gradient structure that changes sequentially, in order to meet the surge protection requirements of different application scenarios, as shown in Table 5 below:
[0124] Table 5
[0125]
[0126] The chip varistor 100 disclosed in this application improves the effect of reducing local heat accumulation in the chip varistor 100 by dispersing the current path, as shown in Table 6 below:
[0127] Table 6
[0128]
[0129] As can be seen, the current-carrying capacity of the chip varistor 100 disclosed in this application is improved by 50%-100%. The homogeneous structure of the comparative example broke down and was damaged at a current of 10kA, while the heterogeneous stacked structure in the chip varistor of the embodiment did not fail at a current of 20kA. Moreover, compared with the failure mode of the comparative example, the electrode edge at the center of the comparative example was burned out when it failed, while the embodiment can uniformly distribute energy from the low potential gradient layer to the high potential gradient layer, thus avoiding failure of the chip varistor of the embodiment at high current. The heat dissipation effect is also improved, reducing the probability of damage to the chip varistor 100 and helping to extend the service life of the product.
[0130] Secondly, this application also discloses an electronic device 200, including the chip varistor 100 disclosed in the first aspect.
[0131] That is, when the chip varistor 100 is installed in the electronic device 200 as an electronic component, the chip varistor 100 has a good protection effect against surges over a large range, which allows the electronic device to be installed in scenarios where surge impacts may occur over a large range, thus expanding the application scenarios of the electronic device.
[0132] Understandably, please see Figure 9 Taking a mobile phone as an example, when a chip varistor 100 is set inside the electronic device 200, the chip varistor 100 can be set on the circuit board 201 of the electronic device 200.
[0133] Optionally, the electronic device 200 may be a mobile phone, tablet computer, industrial power supply, vehicle system of new energy vehicle, etc., and this application does not make specific limitations.
[0134] The chip varistor and electronic device disclosed in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the chip varistor and electronic device and its core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A chip varistor, characterized in that, include: A varistor ceramic body includes a first material layer and a second material layer, which are stacked along the thickness direction of the varistor ceramic body. The ceramic materials of the first material layer and the second material layer are different, so that a potential gradient difference is formed between adjacent first material layers and second material layers. The cover plate structure includes an upper cover plate and a lower cover plate. Along the thickness direction of the pressure-sensitive ceramic body, the upper cover plate is located on the upper side of the first material layer, and the lower cover plate is located on the lower side of the second material layer. Two external electrodes are respectively disposed at both ends of the piezoresistive ceramic body and the cover plate structure along the length direction of the piezoresistive ceramic body. The inner electrode, which is at least three in number, is provided between the upper cover plate and the first material layer, between the lower cover plate and the second material layer, and between the first material layer and the second material layer, along the thickness direction of the pressure-sensitive ceramic body. Each inner electrode extends along the length direction of the pressure-sensitive ceramic body, so that one end of each inner electrode is alternately connected to the outer electrode.
2. The chip varistor according to claim 1, characterized in that, The potential gradient difference between adjacent first material layers and second material layers is ΔE, and ΔE satisfies: 100V / mm≤ΔE≤500V / mm.
3. The chip varistor according to claim 1, characterized in that, The dielectric constant of the first material layer is ε1, and the dielectric constant of the second material layer is ε2, satisfying either ε1 / ε2≥1.5 or ε2 / ε1≥1.
5.
4. The chip varistor according to claim 1, characterized in that, The bismuth content of the first material layer is a1, and the bismuth content of the second material layer adjacent to the first material layer is a2. The difference between a1 and a2 is Δa, and Δa satisfies: Δa≥1wt%.
5. The chip varistor according to claim 1, characterized in that, Both the first material layer and the second material layer contain a variety of additives. The number of different types of additives in the first material layer is S1, and the number of different types of additives in the second material layer is S2. The difference between S1 and S2 is ΔS, and ΔS satisfies: ΔS≥2.
6. The chip varistor according to any one of claims 1-5, characterized in that, The thickness of the first material layer is not equal to the thickness of the adjacent second material layer.
7. The chip varistor according to any one of claims 1-5, characterized in that, The upper cover plate is made of ceramic material, and the ceramic material of the upper cover plate may be the same as or different from that of the first material layer and / or the second material layer; and / or... The lower cover plate is made of ceramic material, and the ceramic material of the lower cover plate may be the same as or different from that of the first material layer and / or the second material layer.
8. The chip varistor according to claim 7, characterized in that, When the ceramic material of the upper cover plate is different from that of the first material layer and / or the second material layer, the inner electrode is provided between the upper cover plate and the pressure-sensitive ceramic body along the thickness direction of the pressure-sensitive ceramic body; and / or, When the ceramic material of the lower cover plate is different from that of the first material layer and / or the second material layer, the inner electrode is provided between the lower cover plate and the pressure-sensitive ceramic body.
9. The chip varistor according to any one of claims 1-5, characterized in that, The pressure-sensitive ceramic body includes at least two first material layers, at least two second material layers, and at least two third material layers; Along the thickness direction of the pressure-sensitive ceramic body, the first material layer, the second material layer, and the third material layer are sequentially disposed to construct a composite material layer, with two of the composite material layers stacked on top of each other; or, Along the thickness direction of the pressure-sensitive ceramic body, two first material layers and two second material layers are alternately arranged, and two third material layers are respectively located on the outermost side of the pressure-sensitive ceramic body.
10. The chip varistor according to claim 9, characterized in that, When the first material layer, the second material layer, and the third material layer are arranged sequentially along the thickness direction of the varistor ceramic body, the potential gradients of the first material layer, the second material layer, and the third material layer change sequentially, and / or the dielectric constants of the first material layer, the second material layer, and the third material layer change sequentially.
11. An electronic device, characterized in that, include: The chip varistor as described in any one of claims 1-10.