Overvoltage protection circuit, chip and electronic equipment

Abstract

The invention provides an overvoltage protection circuit, a chip and electronic equipment. A switch assembly 201 is used for connecting or disconnecting a path between a first data transmission interface 302 of a chip 30 and a second data transmission interface 401 of an access assembly 40. When the switch assembly 201 is switched on, the control circuit 203 detects whether the voltage of the first data transmission interface 302 is greater than the withstand voltage limit value of the chip 30; and when the voltage exceeds a withstand voltage limit value, the switch assembly 201 is controlled to be switched off through the control interface 301. When the switch assembly 201 is switched off, the control circuit 203 can detect whether the voltage of the first data transmission interface 302 is smaller than or equal to a withstand voltage limit value; when the voltage is smaller than or equal to the withstand voltage limit value, the control interface 301 controls the switch assembly to be switched on, and overvoltage protection of the chip 30 is achieved. According to the overvoltage protection circuit, an extra detection interface does not need to be led out from the chip end to detect the voltage of the interface of the access component end, overvoltage protection of the chip end is achieved, and the complexity of integrating an OVP circuit at the chip end is reduced.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to an overvoltage protection circuit, chip, and electronic device. Background Art

[0002] Universal Serial Bus (USB) Type-C is widely used in electronic devices. In most scenarios, the USB Type-C interface needs to connect to the system-on-chip (SoC) in the electronic device for data transmission or headphone applications. However, when the USB Type-C interface experiences a short circuit, such as an accidental power failure, a voltage of 5V-20V is generated at the USB Type-C interface, causing most SoCs to overvoltage and damage.

[0003] In related technologies, an overvoltage protection (OVP) circuit can be integrated into the SOC to implement overvoltage protection. However, the SOC requires an additional port to detect the voltage on the USB Type-C port to implement overvoltage protection. Typically, a USB Type-C interface includes multiple signal interfaces, each of which requires independent overvoltage protection control. This requires the SOC to provide more detection ports to detect the voltage of each signal interface, making the SOC circuit design more complex. Summary of the Invention

[0004] The present application provides an overvoltage protection circuit, chip and electronic device to solve the problem in the related art that an additional SOC lead-out port is required to detect the voltage of the USB Type-C end in order to achieve overvoltage protection.

[0005] In a first aspect, the present application provides an overvoltage protection circuit, comprising:

[0006] a switch component, connected to the control interface of the chip, the first data transmission interface of the chip, and the second data transmission interface of the access component, respectively, and configured to open or close a path between the first data transmission interface and the second data transmission interface;

[0007] a first resistor connected in parallel with the switch component;

[0008] A control circuit is connected to the control interface and the first data transmission interface respectively, and the control circuit is used to:

[0009] When the switch component is turned on, detecting whether the voltage of the first data transmission interface is greater than the withstand voltage limit of the chip; and when the voltage exceeds the withstand voltage limit, controlling the switch component to be disconnected through the control interface;

[0010] When the switch component is disconnected, it is detected whether the voltage of the first data transmission interface is less than or equal to the withstand voltage limit value; and when the voltage is less than or equal to the withstand voltage limit value, the switch component is controlled to be turned on through the control interface.

[0011] In a possible implementation, the control circuit includes: a second resistor, a third resistor, a high-voltage end circuit, a low-voltage end circuit, and a logic circuit;

[0012] Wherein, the first end of the second resistor is connected to the first data transmission interface, the second end of the second resistor is connected to the first end of the third resistor through a first connecting line; the second end of the third resistor is grounded through a second connecting line;

[0013] The high-voltage end circuit is connected to the first connecting line, and the low-voltage end circuit is connected to the first end of the second resistor and the second connecting line respectively;

[0014] The logic circuit is connected to the high-voltage end circuit, the low-voltage end circuit and the control interface respectively.

[0015] In a possible implementation, the logic circuit includes: a NOR gate circuit, a first inverter, a buffer, a second inverter, a NAND gate circuit, and a third inverter;

[0016] The input end of the NOR gate circuit is connected to the output end of the high-voltage end circuit and the output end of the low-voltage end circuit, and the output end of the NOR gate circuit is connected to the input end of the first inverter;

[0017] The output end of the first inverter is connected to the input end of the buffer through a fourth connection line; the output end of the buffer is connected to the control interface;

[0018] The input end of the second inverter is connected to the output end of the high-voltage end circuit, and the input end of the NAND gate circuit is connected to the output end of the second inverter and the output end of the low-voltage end circuit;

[0019] The output end of the NAND gate circuit is connected to the input end of the third inverter through a fifth connecting line, and the output end of the third inverter is connected to the low-voltage end circuit.

[0020] In a possible implementation, the high-voltage side circuit includes a first NMOS, a PMOS, and a first comparator;

[0021] The source of the first NMOS is connected to the first connecting line, the drain of the first NMOS is connected to the negative terminal of the first comparator, and the gate of the first NMOS is connected to the logic circuit; the output terminal of the first comparator is the output terminal of the high-voltage circuit;

[0022] The drain of the PMOS is connected to the negative terminal of the first comparator, the source of the PMOS is connected to the power supply voltage of the chip, and the gate of the PMOS is connected to the logic circuit.

[0023] In a possible implementation, the threshold voltage of the first comparator is equal to a first voltage, and the first voltage is a voltage obtained by dividing the withstand voltage limit value by the second resistor and the third resistor.

[0024] In a possible implementation, the low-voltage side circuit includes a fourth resistor, a fifth resistor, a second NMOS, a third NMOS, a fourth NMOS, and a second comparator;

[0025] The first end of the fourth resistor is connected to the first end of the second resistor, the second end of the fourth resistor is connected to the first end of the fifth resistor through a third connecting line, and the second end of the fifth resistor is connected to the drain of the fourth NMOS;

[0026] The gate of the second NMOS is connected to the fifth connection line, the source of the second NMOS is connected to the third connection line, and the drain of the second NMOS is connected to the negative terminal of the second comparator;

[0027] The gate of the third NMOS is connected to the fourth connecting line, the drain of the third NMOS is connected to the negative end of the second comparator, and the source of the third NMOS is connected to the second connecting line; the source of the fourth NMOS is connected to the second connecting line, and the gate of the fourth NMOS is connected to the output end of the third inverter.

[0028] In one possible implementation, the ratio of the resistance of the first resistor to the first resistance is equal to the ratio of the maximum overvoltage of the second data transmission interface to the withstand voltage limit, and the first resistance is the sum of the resistance of the fourth resistor and the resistance of the fifth resistor.

[0029] In a possible implementation, the threshold voltage of the second comparator is less than a second voltage, and the second voltage is a voltage obtained by dividing the operating voltage of the first data transmission interface by the fourth resistor and the fifth resistor when the chip is in a normal working state.

[0030] In a second aspect, the present application provides a chip, comprising:

[0031] Control interface;

[0032] A first data transmission interface, used for transmitting data;

[0033] The overvoltage protection circuit as described in the first aspect is used to perform overvoltage protection on the chip through the control interface.

[0034] In a third aspect, the present application provides an electronic device, comprising: an access component for accessing an external device;

[0035] A chip as described in the second aspect.

[0036] The present application provides an overvoltage protection circuit, chip, and electronic device, in which the switch component 201 can be used to turn on or off the path between the first data transmission interface 302 of the chip 30 and the second data transmission interface 401 of the access component 40. When the switch component 201 is turned on, the control circuit 203 can detect whether the voltage of the first data transmission interface 302 is greater than the withstand voltage limit of the chip 30; and when the voltage exceeds the withstand voltage limit, the switch component 201 is controlled to be disconnected through the control interface 301. When the switch component 201 is disconnected, the control circuit 203 can detect whether the voltage of the first data transmission interface 302 is less than or equal to the withstand voltage limit; and when the voltage is less than or equal to the withstand voltage limit, the switch component is controlled to be turned on through the control interface 301, thereby achieving overvoltage protection for the chip 30. The overvoltage protection circuit of the present application does not require the chip end to lead out an additional detection interface to detect the voltage of the interface at the access component end, thereby achieving overvoltage protection for the chip end and reducing the complexity of integrating the OVP circuit at the chip end. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0038] Figure 1 This is a schematic structural diagram of a SOC with an integrated OVP circuit in a related technology exemplified in this application;

[0039] Figure 2 A schematic diagram of the structure of an overvoltage protection circuit provided in an embodiment of the present application;

[0040] Figure 3 A schematic diagram of the structure of an overvoltage protection circuit provided in an embodiment of the present application;

[0041] Figure 4 A schematic diagram of the structure of a logic circuit 208 provided in an embodiment of the present application;

[0042] Figure 5A schematic structural diagram of a high-voltage end circuit 206 provided in an embodiment of the present application;

[0043] Figure 6 A schematic structural diagram of a high-voltage end circuit 206 provided in an embodiment of the present application;

[0044] Figure 7 A schematic diagram of the structure of an overvoltage protection circuit provided in an embodiment of the present application;

[0045] Figure 8 This is a voltage waveform diagram of an example of this application.

[0046] Description of reference numerals:

[0047] 101-MOSFET switch; 102-SOC end data transmission interface;

[0048] 103-Type-C data transmission interface; 104-control signal interface;

[0049] 105- detection interface; 106- SOC processor;

[0050] 107-comparator; 108-sixth resistor;

[0051] 109-seventh resistor; 20-overvoltage protection circuit;

[0052] 30-chip; 40-access component;

[0053] 301-control interface; 302-first data transmission interface;

[0054] 401-second data transmission interface; 201-switch component;

[0055] 202-first resistor; 203-control circuit;

[0056] 204 - second resistor; 205 - third resistor;

[0057] 206-high voltage end circuit; 207-low voltage end circuit;

[0058] 208-Logic circuit; 209-NOR gate circuit;

[0059] 210 - first inverter; 211 - buffer;

[0060] 212-second inverter; 213-NAND gate circuit;

[0061] 214 - a third inverter; 215 - a first NMOS;

[0062] 216-PMOS; 217-first comparator;

[0063] 218 - fourth resistor; 219 - fifth resistor;

[0064] 220 - second NMOS; 221 - third NMOS;

[0065] 222 - a fourth NMOS; 223 - a second comparator.

[0066] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0067] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0068] The OVP circuit automatically triggers a signal when a short circuit occurs in the USB Type-C port, switching the path between the USB Type-C port and the SoC to prevent overvoltage from reaching the SoC, thus providing overvoltage protection. When the voltage returns to normal, the OVP circuit automatically restores the path, returning the SoC and USB Type-C port to normal operation. Conventional OVP circuit designs typically require an additional port on the SoC to detect the voltage at the USB Type-C port in order to implement overvoltage protection.

[0069] It should be noted that the USB Type-C interface includes multiple signal interfaces, and the SOC includes multiple data transmission interfaces. When the USB Type-C interface is connected to the SOC, each signal interface of the USB Type-C interface is connected to the data transmission interface of its corresponding SOC. An OVP circuit can be set between each signal interface and its corresponding data transmission interface to achieve overvoltage protection for the data transmission interface.

[0070] For ease of description, the USB Type-C interface is described as Type-C below.

[0071] Figure 1 This is a structural diagram of a SOC with an integrated OVP circuit in a related technology exemplified in this application, such as Figure 1As shown, a board-level metal-oxide-semiconductor field-effect transistor (MOSFET) switch is required between the SOC and Type-C terminals. This allows the OVP circuit to detect overvoltage conditions when the Type-C terminal is overvoltage, quickly respond, and shut off the MOSFET. In other words, the OVP circuit provides a shutdown or restart signal to the MOSFET. When the voltage on the Type-C terminal returns to normal, the OVP circuit can restart the MOSFET, restoring the entire system to normal operation.

[0072] Specifically, if Figure 1 As shown, the OVP circuit between the data transmission interface 102 on the SOC end and the data transmission interface 103 on the Type-C end is used as an example to illustrate the OVP circuit. The data transmission interface 102 on the SOC end and the data transmission interface 103 on the Type-C end are connected by a MOSFET switch 101 to form a channel path for data transmission between the two parties. During normal operation (i.e., when in a non-overvoltage state), the MOSFET switch 101 is in the on state, and the USB data will be transmitted to the SOC processor 106 through the channel path. Similarly, the data of the SOC processor 106 can also be sent to the Type-C end by the channel path.

[0073] The OVP circuit includes a comparator 107, a sixth resistor 108, and a seventh resistor 109. The OVP circuit detects the voltage of the Type-C data transmission interface 103 through the detection interface 105, and controls the MOSFET switch 101 to turn on or off through the control signal interface 104.

[0074] The voltage from the Type-C data transmission interface 103 is input into the OVP circuit via the detection interface 105. This voltage is then divided by the sixth resistor 108 and the seventh resistor 109. One end of the seventh resistor 109 is grounded, and the other end is connected to the sixth resistor 108. One end of the sixth resistor 108 is connected to the seventh resistor 109, and the other end is connected to the detection interface 105. This voltage-dividing structure ensures that the voltage input to the SOC components is lower than the withstand voltage of the SOC components.

[0075] The divided voltage is connected to the negative terminal of the comparator 107. A reference voltage VREF111 is generated in the SOC and connected to the positive terminal of the comparator 107. The comparator 107 determines the control signal state of the OVP circuit based on the two voltages at the negative and positive terminals, and controls the MOSFET switch 101 through the control signal interface 104.

[0076] Figure 1 The working process of the OVP circuit is as follows:

[0077] When Type-C and SOC are in normal working state, the voltage of Type-C data transmission interface 103 is normal working voltage. The voltage after voltage division input to the sixth resistor 108 and the seventh resistor 109 through the detection interface 105 is low and lower than VREF voltage 111. After comparison by comparator 107, comparator 107 can output a high-level signal, and control the MOSFET switch 101 to be normally turned on through the control signal interface 104, that is, it is in the on state.

[0078] When a short circuit occurs on the Type-C terminal, the voltage of the Type-C data transmission interface 103 is high. The voltage divided by the sixth resistor 108 and the seventh resistor 109 through the detection interface 105 is high and higher than the VREF voltage 111. After comparison by the comparator 107, the comparator 107 can output a low-level signal, and the MOSFET switch 101 is turned off through the control signal interface 104. At this time, the overvoltage protection function is implemented, and the channel path between the Type-C terminal and the SOC terminal is cut off.

[0079] When the Type-C end recovers from a short circuit to a normal working state, the voltage of the Type-C data transmission interface 103 is a normal working voltage. The voltage after the voltage division input to the sixth resistor 108 and the seventh resistor 109 through the detection interface 105 is low and lower than the VREF voltage 111. After comparison by the comparator 107, the comparator 107 can output a high-level signal, and the MOSFET switch 101 is controlled to return to the on state through the control signal interface 104.

[0080] Among them, the detection interface 105 on the SOC end is an additional interface for realizing overvoltage protection. However, since the Type-C end usually includes multiple signal interfaces, these signal interfaces require independent OVP circuits to realize overvoltage protection. This will cause the SOC end to need to bring out more detection interfaces to detect the voltage of each signal interface, making the circuit design of the SOC more complex and increasing the cost of the SOC chip.

[0081] Therefore, the present application provides an overvoltage protection circuit, which connects the SOC end and the Type-C end through a switch component, and can directly detect the voltage of the interface of the SOC end. When the voltage of the interface is overvoltage, the path between the SOC end and the Type-C end can be cut off. When the voltage of the interface returns to normal, the new signal path can be restored by connecting the resistor in parallel to the switch component and the control circuit in the overvoltage protection circuit. The overvoltage protection circuit of the present application does not require the SOC end to lead out an additional detection interface to detect the voltage of the interface of the Type-C end, thereby realizing overvoltage protection of the SOC end and reducing the complexity of integrating the OVP circuit at the SOC end.

[0082] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can exist independently or in combination with each other. For the same or similar concepts or processes, they may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0083] Figure 2 This is a schematic diagram of the structure of an overvoltage protection circuit provided in an embodiment of the present application, with reference to Figure 2 , the overvoltage protection circuit 20 includes:

[0084] The switch component 201 is respectively connected to the control interface 301 of the chip 30, the first data transmission interface 302 of the chip 30 and the second data transmission interface 401 of the access component 40. The switch component 201 is used to open or close the path between the first data transmission interface 302 and the second data transmission interface 401.

[0085] The first resistor 202 is connected in parallel with the switch component 201 .

[0086] The control circuit 203 is connected to the control interface 301 and the first data transmission interface 302 respectively. The control circuit 203 is used to:

[0087] When the switch component 201 is turned on, it detects whether the voltage of the first data transmission interface 302 is greater than the withstand voltage limit of the chip 30; and when the voltage exceeds the withstand voltage limit, the switch component 201 is controlled to be disconnected through the control interface 301.

[0088] When the switch component 201 is disconnected, it detects whether the voltage of the first data transmission interface 302 is less than or equal to the withstand voltage limit value; and when the voltage is less than or equal to the withstand voltage limit value, the switch component is controlled to be turned on through the control interface 301.

[0089] It can be understood that since the impedance of the switch component 201 is low when it is turned on, the impedance after being connected in parallel with the first resistor 202 is equivalent to 0, so the voltage of the first data transmission interface 302 is equal to the voltage of the second data transmission interface 401.

[0090] When the switch component 201 is disconnected, the first resistor 202 is connected to the control circuit 203, for example, it can be connected to the voltage divider circuit of the control circuit 203, so that the voltage of the first data transmission interface 302 does not exceed the voltage limit of the chip 30, thereby achieving overvoltage protection.

[0091] In a possible implementation, the switch component 201 may be a MOSFET switch.

[0092] In a possible implementation, the chip 30 may be a SOC, wherein the first data transmission interface 302 may be connected to the SOC processor 106 in the chip 30 , so that the first data transmission interface 302 can implement data transmission for the SOC processor 106 .

[0093] In one possible implementation, the access component 40 may be Type-C.

[0094] In this embodiment, the switch component 201 can be used to turn on or off the path between the first data transmission interface 302 of the chip 30 and the second data transmission interface 401 of the access component 40. When the switch component 201 is turned on, the control circuit 203 can detect whether the voltage of the first data transmission interface 302 is greater than the withstand voltage limit of the chip 30; and when the voltage exceeds the withstand voltage limit, the switch component 201 is controlled to be disconnected through the control interface 301. When the switch component 201 is disconnected, the control circuit 203 can detect whether the voltage of the first data transmission interface 302 is less than or equal to the withstand voltage limit; and when the voltage is less than or equal to the withstand voltage limit, the switch component is controlled to be turned on through the control interface 301, thereby realizing overvoltage protection for the chip 30. The overvoltage protection circuit of the present application does not require the chip end to lead out an additional detection interface to detect the voltage of the interface at the access component end, thereby realizing overvoltage protection for the chip end and reducing the complexity of integrating the OVP circuit at the chip end.

[0095] It should be noted that, taking the chip 30 as a SOC and the access component 40 as a Type-C as an example, Type-C has multiple signal interfaces. For each signal interface, an overvoltage protection circuit can be integrated in the SOC. This overvoltage protection circuit is used to determine whether the voltage of the signal interface is overvoltage based on the voltage of the first data transmission interface 302 of the SOC. If so, the path between the first data transmission interface of the SOC and the signal interface of the Type-C can be cut off. Among them, the second data transmission interface 401 is one of the multiple signal interfaces.

[0096] Since each signal interface of Type-C has an independent data transmission interface of SOC, for example, the first data transmission interface 302 of SOC is a dedicated interface for the second data transmission interface 401 of Type-C. SOC can integrate overvoltage protection circuits corresponding to multiple signal interfaces, and each overvoltage protection circuit can determine whether the voltage of the signal interface connected to the overvoltage protection circuit is overvoltage through the voltage of the corresponding SOC data transmission interface. If so, the path between the data transmission interface and the signal interface connected to the overvoltage protection circuit can be cut off, thereby achieving overvoltage protection. It can be seen from this that the present application does not require the chip end to introduce an additional detection interface to detect the voltage of the interface connected to the component end, and can achieve overvoltage protection on the chip end.

[0097] Next, the structure of the control circuit 203 will be described.

[0098] Figure 3 This is a schematic diagram of the structure of an overvoltage protection circuit provided in an embodiment of the present application, with reference to Figure 3 The control circuit 203 includes: a second resistor 204 , a third resistor 205 , a high-voltage end circuit 206 , a low-voltage end circuit 207 and a logic circuit 208 .

[0099] The first end of the second resistor 204 is connected to the first data transmission interface 302 , the second end of the second resistor 204 is connected to the first end of the third resistor 205 via a first connection line, and the second end of the third resistor 205 is grounded via a second connection line.

[0100] The high-voltage end circuit 206 is connected to the first connection line, and the low-voltage end circuit 207 is connected to the first end of the second resistor 204 and the second connection line respectively.

[0101] The logic circuit 208 is connected to the high-voltage end circuit 206 , the low-voltage end circuit 207 and the control interface 301 respectively.

[0102] The second resistor 204 and the third resistor 205 constitute a voltage divider circuit in the control circuit 203 .

[0103] In a possible implementation, the logic circuit 208 includes: a NOR gate circuit 209 , a first inverter 210 , a buffer 211 , a second inverter 212 , a NAND gate circuit 213 , and a third inverter 214 .

[0104] For example, Figure 4 This is a schematic diagram of the structure of a logic circuit 208 provided in an embodiment of the present application, refer to Figure 4 The input end of the NOR gate circuit 209 is connected to the output end of the high-voltage end circuit 206 and the output end of the low-voltage end circuit 207 , and the output end of the NOR gate circuit 209 is connected to the input end of the first inverter 210 .

[0105] The output terminal of the first inverter 210 is connected to the input terminal of the buffer 211 via a fourth connection line. The output terminal of the buffer 211 is connected to the control interface 301 .

[0106] An input end of the second inverter 212 is connected to the output end of the high-voltage circuit 206 , and an input end of the NAND gate circuit 213 is connected to the output end of the second inverter 212 and the output end of the low-voltage circuit 207 .

[0107] The output end of the NAND gate circuit 213 is connected to the input end of the third inverter 214 through a fifth connection line, and the output end of the third inverter 214 is connected to the low-voltage end circuit 207 .

[0108] In a possible implementation, the high-voltage side circuit 206 includes a first NMOS 215 , a PMOS 216 , and a first comparator 217 .

[0109] For example, Figure 5 This is a schematic diagram of the structure of a high-voltage end circuit 206 provided in an embodiment of the present application, with reference to Figure 5 The source S of the first NMOS 215 is connected to the first connection line, the drain D of the first NMOS 215 is connected to the negative terminal of the first comparator 217, and the gate G of the first NMOS is connected to the logic circuit 208; the output terminal of the first comparator 217 is the output terminal of the high-voltage circuit 206.

[0110] A drain D of the PMOS 216 is connected to the negative terminal of the first comparator 217 , a source S of the PMOS 216 is connected to the power supply voltage of the chip 30 , and a gate G of the PMOS 216 is connected to the logic circuit 208 .

[0111] Specifically, the gate G of the first NMOS is connected to the fourth connection line in the logic circuit 208 , and the gate G of the PMOS 216 is connected to the fourth connection line in the logic circuit 208 .

[0112] In a possible implementation, the low-voltage side circuit 207 includes a fourth resistor 218 , a fifth resistor 219 , a second NMOS 220 , a third NMOS 221 , a fourth NMOS 222 , and a second comparator 223 .

[0113] For example, Figure 6 This is a schematic diagram of the structure of a high-voltage end circuit 206 provided in an embodiment of the present application, with reference to Figure 6 The first end of the fourth resistor 218 is connected to the first end of the second resistor 204 , the second end of the fourth resistor 218 is connected to the first end of the fifth resistor 219 through the third connection line, and the second end of the fifth resistor 219 is connected to the drain D of the fourth NMOS 222 .

[0114] A gate G of the second NMOS 220 is connected to the fifth connection line, a source S of the second NMOS 220 is connected to the third connection line, and a drain D of the second NMOS 220 is connected to the negative terminal of the second comparator 223 .

[0115] The gate G of the third NMOS 221 is connected to the fourth connection line, the drain D of the third NMOS 221 is connected to the negative terminal of the second comparator 223, and the source S of the third NMOS 221 is connected to the second connection line for grounding. The source S of the fourth NMOS 222 is connected to the second connection line for grounding. The gate G of the fourth NMOS 222 is connected to the output terminal of the third inverter 214.

[0116] Based on the above circuit structure, Figure 7 A schematic diagram of the structure of an overvoltage protection circuit provided in an embodiment of the present application is shown in FIG. Figure 7 As shown:

[0117] When switch component 201 is turned on, its impedance is low. When connected in parallel with first resistor 202, its impedance is equivalent to zero, making the voltages at second data transmission interface 401 and first data transmission interface 302 equal. Second resistor 204 and third resistor 205 can divide this voltage and compare the divided voltage with the threshold voltage (VREF_H) of first comparator 217. If the divided voltage is greater than the threshold voltage of first comparator 217, indicating that the voltage at first data transmission interface 302 is greater than the withstand voltage limit of chip 30, first comparator 217 can initiate an overvoltage protection process, the specific process of which will be described in detail later.

[0118] When the switch component 201 is disconnected, the first resistor 202 is effectively connected in series to the channel path. The second NMOS 220 and the fourth NMOS 222 are turned on, and the third NMOS 221 is turned off. This forms a series equivalent resistance of the fourth resistor 218 and the fifth resistor 219, which is connected in parallel with the series equivalent resistance of the second resistor 204 and the third resistor 205. These two series equivalent resistances are then connected in parallel to the first resistor 202. The series equivalent resistance of the fourth resistor 218 and the fifth resistor 219 is smaller than the series equivalent resistance of the second resistor 204 and the third resistor 205. This makes the impedance of the entire detection path equivalent to the series impedance of the first resistor 202, the fourth resistor 218, and the fifth resistor 219. As a result, the voltage entering the negative terminal of the second comparator 223 is actually the voltage of the second data transmission interface 401, which is divided by the voltage of the fifth resistor 219 after passing through the series resistance of the first resistor 202 and the fourth resistor 218. If the voltage at the negative terminal of the second comparator 223 is less than or equal to the threshold voltage (VREF_L) of the second comparator 223, it means that when the voltage of the second data transmission interface 401 drops below the withstand voltage limit of the chip 30, the second comparator 223 can respond to the recovery process, and the specific process will be explained in detail later.

[0119] In one possible implementation, the threshold voltage (VREF_L) of the second comparator 223 can be equal to the first voltage, which is the voltage value after the voltage limit value of the chip 30 is divided by the series equivalent resistance of the first resistor 202 and the fourth resistor 218 and the fifth resistor 219. When the voltage of the second data transmission interface 401 is reduced to the voltage limit value of the SOC, the recovery process can be triggered.

[0120] In one possible implementation, the threshold voltage (VREF_L) of the second comparator is less than the second voltage, which is the voltage obtained by dividing the operating voltage of the first data transmission interface 302 by the fourth resistor 218 and the fifth resistor 219 when the chip 30 is in normal working condition. In this way, when the voltage of the second data transmission interface 401 drops to the withstand voltage limit of the chip 30, the second comparator 223 can respond to the recovery process.

[0121] It should be noted that the threshold voltage of the second comparator is a relatively low voltage, even much lower than the voltage divided by the fourth resistor 218 and the fifth resistor 219 when the chip 30 is operating normally. Thus, when the chip 30 is operating normally, the recovery process will not be abnormally triggered, resulting in repeated triggering of the overvoltage shutdown process and the recovery process.

[0122] In one possible implementation, if the voltage of the first data transmission interface 302 of the chip 30 is maintained less than or equal to the withstand voltage limit of the chip 30, the ratio of the resistance of the first resistor 202 to the first resistance is equal to the ratio of the maximum overvoltage of the second data transmission interface to the withstand voltage limit of the chip 30, where the first resistance is the sum of the resistance of the fourth resistor 218 and the resistance of the fifth resistor 219 (typically, the maximum overvoltage of the second data transmission interface can reach 20V, while the terminal withstand voltage limit of the chip 30 is less than 3.6V, so the resistance of the fourth resistor 218 and the resistance of the fifth resistor 219 are less than the resistance of the first resistor 202). In this way, even if the voltage of the second data transmission interface 401 reaches the maximum overvoltage, the first data transmission interface 302 of the chip 30 can still be equal to the withstand voltage limit of the chip 30, ensuring that the internal structure of the chip 30 is not damaged.

[0123] Below, taking the chip 30 as SOC, the access component 40 as Type-C, and the switch component 201 as a MOSFET switch as an example, based on the voltage of the second data transmission interface 401, the process from Type-C startup to normal working state, then to overvoltage state, and finally back to normal working state over time, combined with Figure 7 The circuit structure, and Figure 8 The voltage waveform diagram is used to illustrate the above overvoltage protection process and recovery process:

[0124] At time t0, the SOC is in its initial state. The second data transmission interface 401 does not transmit any signals, and its voltage is 0V. The first data transmission interface 302 of the SOC also does not transmit any signals, and its voltage is also 0V. Therefore, the voltage after the voltage division between the second resistor 204 and the third resistor 205 is also 0V. The output signal (OVP_H) of the first comparator 217, i.e., the output of the high-voltage circuit 206, is a high-level signal by default. At this point, the output signal (OVP_L) of the second comparator 223, i.e., the output of the low-voltage circuit 207, is either a high-level signal or a low-level signal. After the output signal (OVP_H) of the first comparator 217 and the output signal (OVP_L) of the second comparator 223 pass through the NOR gate 209 and the first inverter 210, the output signal S1 is both a high-level signal. Output signal S1 is connected to the control interface 301 via the buffer 211 and then transmitted to the MOSFET switch. At this point, the MOSFET switch receives a high-level signal and is therefore in the on state. Simultaneously, the output signal S1 is transmitted to the PMOS 216 and the first NMOS 215, turning on the first NMOS 215 and turning off the PMOS 216. The voltage 0V obtained by dividing the voltage between the second resistor 204 and the third resistor 205 is transmitted to the first comparator 217 via the first NMOS 215. The threshold voltage (VREF_H) of the first comparator 217 is much greater than 0V, so the output signal of the first comparator 217 is a high-level signal, and the MOSFET switch is in a stable on state.

[0125] To facilitate the subsequent process description, the operating state of the second comparator 223 at time t0 is described here: At time t0, the output signal (OVP_H) of the first comparator 217 is converted to a low-level signal after being output by the second inverter 212. It then enters the NAND gate 213 along with the output signal (OVP_L) of the second comparator 223. Regardless of whether the output signal (OVP_L) of the second comparator 223 is a high-level signal or a low-level signal, the output signal (S2_N) of the NOT gate 213 is a high-level signal, and the output signal (S2) of the third inverter 214 is a low-level signal. The output signal (S2_N) of the NOT gate 213 is transmitted to the second NMOS 220 and the fourth NMOS 222, turning them on. The output signal (S2) of the third inverter 214 is transmitted to the third NMOS 221, turning it off. At this time, the fourth resistor 218 and the fifth resistor 219 can divide the voltage 0V of the first data transmission interface 302 of the SOC, and the divided voltage value is transmitted to the negative terminal of the second comparator 223 and compared with the threshold voltage (VREF_L) of the second comparator 223. The threshold voltage (VREF_L) is much greater than 0V, so the output signal of the second comparator 223 (i.e., the output terminal of the low-voltage terminal circuit 207) is a high-level signal at time t0.

[0126] During the time period between time t0 and time t0_1, the Type-C end starts transmitting signals, the second data transmission interface 401 starts to be powered on, and the SOC end and the Type-C end maintain the state described at time t0.

[0127] At time t0_1, the voltage of the SOC's first data transmission interface 302, after being divided by the fourth resistor 218 and the fifth resistor 219, exceeds the threshold voltage (VREF_L) of the second comparator 223, causing the output signal (OVP_L) of the second comparator 223 to be converted to a low-level signal. Furthermore, the output signal (OVP_L) of the second comparator 223 passes through the NAND gate 213, causing the output signal (S2_N) of the NAND gate 213 to remain high, and the output signal (S2) of the third inverter 214 also remains low. Because the output signal (OVP_L) of the second comparator 223 passes through the NOR gate 209, and the output signal (OVP_H) of the first comparator 217 remains high, the output signal (S1) of the first inverter 210 remains high, and the MOSFET switch remains on. Clearly, the power-up process of the second data transmission interface 401 does not cause the overvoltage protection to be falsely triggered.

[0128] During the time period from time t0_1 to time t1, the SOC end and the Type-C end maintain the state described at time t0_1 above.

[0129] From time t1, Type-C enters normal operation. The following explanation uses the example of Type-C operating normally, continuously sending high-level signals, with a normal operating voltage of V1 and a SOC voltage limit of V2. At this point, the voltage of the second data transmission interface 401 is V1, the MOSFET switch is on, and the voltage of the first data transmission interface 302 is also V1. V1 is divided by the fourth resistor 218 and the fifth resistor 219, and then compared with the threshold voltage (VREF_H) of the first comparator 217. At this point, V1 is less than the SOC voltage limit V2. Therefore, the voltage of V1 divided by the fourth resistor 218 and the fifth resistor 219 is also less than the threshold voltage (VREF_H) of the first comparator 217. The output signal (OVP_H) of the first comparator 217 is a high-level signal, causing the output signal (S1) of the first inverter 210 to remain high, and the MOSFET switch remains on.

[0130] During the time period between t1 and t2, the SOC end and the Type-C end maintain the state described in the time period from t0_1 to t1. At this time, the voltage of the second data transmission interface 401 remains at V1, and V1 is less than the withstand voltage limit value V2 of the SOC. Therefore, the voltage of V1 after being divided by the fourth resistor 218 and the fifth resistor 219 is also less than the threshold voltage (VREF_H) of the first comparator 217. The output signal (OVP_H) of the first comparator 217 is a high-level signal, so that the output signal (S1) of the first inverter 210 maintains a high-level signal, and the MOSFET switch remains in the on state.

[0131] Between t2 and t3, the Type-C terminal begins to enter an overvoltage state, and the voltage on the second data transmission interface 401 begins to rise due to an abnormality such as a power short circuit. At t3, the voltage on the second data transmission interface 401 reaches the SOC's withstand voltage limit, V2. Prior to t3, the voltage on the second data transmission interface 401 remains below the SOC's withstand voltage limit, V2. Therefore, the MOSFET switch remains on, as it did between t1 and t2.

[0132] Starting at time t3, the Type-C terminal officially enters an overvoltage state. At time t3, the voltage of the second data transmission interface 401 reaches the SOC's withstand voltage limit value V2. At this time, the overvoltage protection function of the overvoltage protection circuit has not yet taken effect. That is, the MOSFET switch is still in the on state, and the voltage of the first data transmission interface 302 is also V2. After V2 is divided by the fourth resistor 218 and the fifth resistor 219, the divided voltage is compared with the threshold voltage (VREF_H) of the first comparator 217. The output signal (OVP_H) of the first comparator 217 will soon become a low signal.

[0133] Due to the operational delay of the first comparator 217, the output signal (OVP_H) of the first comparator 217 does not reach a low level until time t4. After the output signal (OVP_H) of the first comparator 217 passes through the second inverter 212, the second inverter 212 outputs a high-level signal. This signal, along with the output signal (low-level signal) of the second comparator 223, simultaneously enters the NAND gate 213. The output signal (S2_N) of the NAND gate 213 remains high, and the output signal (S2) of the third inverter 214 remains low. The second NMOS transistor 220 and the second NMOS transistor 220 remain on. The output signal (OVP_H) of the first comparator 217 and the output signal (OVP_L) of the second comparator 223 simultaneously enter the NOR gate 209. After passing through the first inverter 210, the output signal (S1) of the first inverter 210 becomes a low-level signal. This turns on the PMOS 216 and turns off the first NMOS 215, allowing the power supply voltage VDD (maximum voltage) of the SOC to enter the negative terminal of the first comparator 217, so that the output signal (OVP_H) of the first comparator 217 is stabilized as a low-level signal and is no longer affected by the voltage in the path. This can effectively avoid repeatedly triggering the overvoltage protection process and the recovery process.

[0134] At this point, the output signal (S1) of the first inverter 210 is a low-level signal. After passing through the buffer 211, due to the delay of the buffer 211, at time t5, the control interface 301 transmits the output signal (S1) of the first inverter 210 to the MOSFET switch, causing it to disconnect the channel path between the first data transmission interface 302 and the second data transmission interface 401. The first resistor 202 is connected in series with the channel path, so that the first resistor 202, the fourth resistor 218, and the fifth resistor 219 form a voltage divider circuit, reducing the voltage of the first data transmission interface 302 to less than the terminal withstand voltage limit V2 of the SOC, thus achieving overvoltage protection. Because the MOSFET switch is disconnected at time t5, the voltage of the second data transmission interface 401 remains equal to the voltage of the first data transmission interface 302 during the time period from time t2 to t5. The period from time t3 to time t5 is the overvoltage period, and the first comparator 217 can be a low-latency comparator to shorten the duration of this period.

[0135] During the period between time t5 and time t6, the first resistor 202, the fourth resistor 218, and the fifth resistor 219 form a voltage divider circuit, so that the voltage of the first data transmission interface 302 changes synchronously with the voltage of the second data transmission interface 401 in a fixed ratio and is always less than the withstand voltage limit value V2 of the SOC, and the MOSFET switch remains off. Figure 3 In the example, the voltage near time t6 is a straight line because the fixed ratio is large, resulting in a low voltage at the first data transmission interface 302 when the voltage at the second data transmission interface 401 is low, so Figure 3 In the simplified graph, these lower voltages are approximated as a straight line.

[0136] Starting at time t6, the voltage of the second data transmission interface 401 has begun to fall below the SOC withstand voltage limit V2. As can be seen from the above embodiment, the threshold voltage (VREF_L) of the second comparator 223 can be equal to the voltage value obtained by dividing the SOC withstand voltage limit by the series equivalent resistance of the first resistor 202 and the fourth resistor 218, and the voltage of the fifth resistor 219. Therefore, at this time, the negative terminal of the second comparator 223 is less than the threshold voltage (VREF_L) of the second comparator 223.

[0137] Due to the response delay of the second comparator 223, the output signal (OVP_L) of the second comparator 223 does not transition to a high level until time t7. At this time, the output signal (OVP_H) of the first comparator 217 is a low level. Therefore, after passing through the NOR gate 209 and the first inverter 210, the output signal (S1) of the first inverter 210 transitions to a high level. After passing through the second inverter 212, the NAND gate 213, and the third inverter 214, the output signal (S2_N) of the NAND gate 213 transitions to a low level, and the output signal (S2) of the third inverter 214 transitions to a high level. Since the output signal (S1) of the first inverter 210 is high, the PMOS 216 is turned off, the first NMOS 215 is turned on, and the negative terminal of the first comparator 217 is connected to the voltage divided by the second resistor 204 and the third resistor 205. However, since the voltage of the first data transmission interface 302 is always less than the SOC withstand voltage limit V2, the voltage at the negative terminal of the first comparator 217 is always less than the threshold voltage (VREF_H) of the first comparator 217, so the output signal (OVP_H) of the first comparator 217 is about to become high. The output signal (S2_N) of the NAND gate 213 is low, and the output signal (S2) of the third inverter 214 is high, turning off the second NMOS 220 and the fourth NMOS 222, turning on the third NMOS 221, and grounding the negative terminal of the second comparator 223, so that the output signal (OVP_L) of the second comparator 223 remains high. This effectively prevents repeated triggering of the overvoltage protection and recovery processes.

[0138] Due to the response delay of buffer 211, control interface 301 transmits a high-level signal to the MOSFET switch only at time t8, turning the MOSFET switch on. The first resistor 202 is then connected in parallel with the MOSFET switch again. The voltage of the first data transmission interface 302 is once again equal to the voltage of the second data transmission interface 401, and normal data transmission resumes.

[0139] However, the recovery process is not complete at this point. Because the delay of the first comparator 217 is greater than that of the buffer 211, the output signal (OVP_H) of the first comparator 217 does not transition to a high level until time t9. The output signal (OVP_H) of the first comparator 217 and the output signal (OVP_L, a high level signal) of the second comparator 223 enter the NOR circuit 209 and the first inverter 210. The output signal (S1) of the first inverter 210 remains high. After the output signal (OVP_H) of the first comparator 217 enters the second inverter 212, the output signal of the second inverter 212 becomes a low level signal. This low level signal and the output signal (OVP_L) of the second comparator 223 enter the NAND circuit 213. The output signal (S2_N) of the NAND circuit 213 transitions to a high level signal, and the output signal (S2) of the third inverter 214 transitions to a low level signal. The second NMOS 220 and the fourth NMOS 222 are turned on, and the third NMOS 221 is turned off. Referring to the above description, it can be seen that the output signal (OVP_L) of the second comparator 223 will become a low level signal at time t9.

[0140] Due to the delay of the second comparator 223, the output signal (OVP_L) of the second comparator 223 turns low at time t10. At this time, the SOC and Type-C return to the same state as between time t1 and time t2. The Type-C data is transmitted normally, and the SOC operates normally.

[0141] It can be understood that when the next overvoltage state occurs, all the above processes will be repeated.

[0142] In the embodiment of the present application, for example, the first NMOS and the second NMOS are all N-type metal-oxide-semiconductor field-effect transistors (N-Metal-Oxide-Semiconductor Field-Effect Transistors).

[0143] In the embodiment of the present application, PMOS is a P-type metal-oxide-semiconductor field-effect transistor (P-Metal-Oxide-Semiconductor Field-Effect Transistor).

[0144] In the embodiment of the present application, GND represents ground, and VDD represents power supply voltage.

[0145] In the embodiments of the present application, “connection” refers to electrical connection.

[0146] An embodiment of the present application provides a chip, including:

[0147] Control interface;

[0148] A first data transmission interface, used for transmitting data;

[0149] For example, the overvoltage protection circuit in the above embodiment is used to perform overvoltage protection on the chip through the control interface.

[0150] The specific implementation method and technical effects of the electronic device of this embodiment are similar and will not be repeated here.

[0151] An embodiment of the present application provides an electronic device, including:

[0152] Access component, used to access external devices;

[0153] A chip as in the above embodiment.

[0154] The specific implementation method and technical effects of the electronic device of this embodiment are similar and will not be repeated here.

[0155] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0156] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. An overvoltage protection circuit, characterized in that: include: a switch component, connected to the control interface of the chip, the first data transmission interface of the chip, and the second data transmission interface of the access component, respectively, and configured to open or close a path between the first data transmission interface and the second data transmission interface; a first resistor connected in parallel with the switch component; A control circuit is connected to the control interface and the first data transmission interface respectively, and the control circuit is used to: When the switch component is turned on, detecting whether the voltage of the first data transmission interface is greater than the withstand voltage limit of the chip; and when the voltage exceeds the withstand voltage limit, controlling the switch component to be disconnected through the control interface; When the switch component is disconnected, it is detected whether the voltage of the first data transmission interface is less than or equal to the withstand voltage limit value; and when the voltage is less than or equal to the withstand voltage limit value, the switch component is controlled to be turned on through the control interface.

2. The overvoltage protection circuit according to claim 1, wherein: The control circuit includes: a second resistor, a third resistor, a high-voltage end circuit, a low-voltage end circuit and a logic circuit; Wherein, the first end of the second resistor is connected to the first data transmission interface, the second end of the second resistor is connected to the first end of the third resistor through a first connecting line; the second end of the third resistor is grounded through a second connecting line; The high-voltage end circuit is connected to the first connecting line, and the low-voltage end circuit is connected to the first end of the second resistor and the second connecting line respectively; The logic circuit is connected to the high-voltage end circuit, the low-voltage end circuit and the control interface respectively.

3. The overvoltage protection circuit according to claim 2, characterized in that: The logic circuit includes: a NOR gate circuit, a first inverter, a buffer, a second inverter, a NAND gate circuit and a third inverter; The input end of the NOR gate circuit is connected to the output end of the high-voltage end circuit and the output end of the low-voltage end circuit, and the output end of the NOR gate circuit is connected to the input end of the first inverter; The output end of the first inverter is connected to the input end of the buffer through a fourth connection line; the output end of the buffer is connected to the control interface; The input end of the second inverter is connected to the output end of the high-voltage end circuit, and the input end of the NAND gate circuit is connected to the output end of the second inverter and the output end of the low-voltage end circuit; The output end of the NAND gate circuit is connected to the input end of the third inverter through a fifth connecting line, and the output end of the third inverter is connected to the low-voltage end circuit.

4. The overvoltage protection circuit according to claim 3, characterized in that: The high-voltage end circuit includes a first NMOS, a PMOS and a first comparator; The source of the first NMOS is connected to the first connecting line, the drain of the first NMOS is connected to the negative terminal of the first comparator, and the gate of the first NMOS is connected to the logic circuit; the output terminal of the first comparator is the output terminal of the high-voltage circuit; The drain of the PMOS is connected to the negative terminal of the first comparator, the source of the PMOS is connected to the power supply voltage of the chip, and the gate of the PMOS is connected to the logic circuit.

5. The overvoltage protection circuit according to claim 4, characterized in that: The threshold voltage of the first comparator is equal to a first voltage, and the first voltage is a voltage obtained by dividing the withstand voltage limit value by the second resistor and the third resistor.

6. The overvoltage protection circuit according to any one of claims 3 to 5, characterized in that: The low-voltage end circuit includes a fourth resistor, a fifth resistor, a second NMOS, a third NMOS, a fourth NMOS and a second comparator; The first end of the fourth resistor is connected to the first end of the second resistor, the second end of the fourth resistor is connected to the first end of the fifth resistor through a third connecting line, and the second end of the fifth resistor is connected to the drain of the fourth NMOS; The gate of the second NMOS is connected to the fifth connection line, the source of the second NMOS is connected to the third connection line, and the drain of the second NMOS is connected to the negative terminal of the second comparator; The gate of the third NMOS is connected to the fourth connecting line, the drain of the third NMOS is connected to the negative end of the second comparator, and the source of the third NMOS is connected to the second connecting line; the source of the fourth NMOS is connected to the second connecting line, and the gate of the fourth NMOS is connected to the output end of the third inverter.

7. The overvoltage protection circuit according to claim 6, characterized in that: The ratio of the resistance of the first resistor to the first resistance is equal to the ratio of the maximum overvoltage of the second data transmission interface to the withstand voltage limit value, and the first resistance is the sum of the resistance of the fourth resistor and the resistance of the fifth resistor.

8. The overvoltage protection circuit according to claim 6 or 7, characterized in that: The threshold voltage of the second comparator is less than a second voltage, and the second voltage is a voltage obtained by dividing the operating voltage of the first data transmission interface by the fourth resistor and the fifth resistor when the chip is in a normal working state.

9. A chip, characterized in that: include: Control interface; A first data transmission interface, used for transmitting data; The overvoltage protection circuit according to any one of claims 1 to 8, configured to perform overvoltage protection on the chip through the control interface.

10. An electronic device, characterized in that: include: Access component, used to access external devices; The chip as claimed in claim 9.

Images