Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a first panel pad area in a non-display area of a substrate. The display device includes: first panel pads on a first panel pad area and spaced apart from each other along a first direction; a second panel pad spaced apart from the first panel pad in the second direction and spaced apart from each other along the first direction; a planarization layer on the first panel pads and the second panel pads and including contact holes exposing corresponding ones of the first panel pads; an upper pad electrode on the planarization layer and electrically connected to a corresponding one of the first panel pads via a corresponding one of the contact holes; a circuit board overlapping the first panel pad area in the third direction and including a circuit pad; and an anisotropic conductive film on the first panel pad area and electrically connecting the upper pad electrode to a corresponding one of the circuit pads.

Description

Technical Field

[0001] The disclosure generally relates to a display device and a method of manufacturing the display device. Background Art

[0002] With the development of the information society, the demand for display devices for displaying images in various forms is increasing. For example, display devices can be applied to (or associated with) various electronic devices such as smartphones, digital cameras, notebook computers, navigation devices, smart TVs, billboards, and household appliances.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. The light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, and a micro-light-emitting display device including a micro-light-emitting element.

[0004] Head-mounted displays (HMDs) including light-emitting display devices have been developed. These HMDs may be glasses-type monitor devices for virtual reality (VR), augmented reality (AR), or mixed reality (MR). These glasses-type monitor devices can be worn as glasses, goggles, or a helmet and can focus at a relatively short distance in front of the user's eyes. High-resolution micro-LED display panels including micro-LED elements can be applied to HMDs.

[0005] The background technology provided herein is for the purpose of presenting the content of the disclosure in general. To the extent described in this background technology section, the work of the presently named inventors and aspects of the description that may not qualify as prior art at the time of filing are neither intended nor implied to be an admission that they are prior art in violation of the disclosure. Summary of the Invention

[0006] Some aspects provide a display device that can increase the degree of freedom of a process of connecting a display panel and a circuit board together and can be used to implement a relatively high-resolution display device.

[0007] Some aspects provide a method of manufacturing a display device that can increase the degree of freedom of a process of connecting a display panel and a circuit board and realize a relatively high-resolution display device.

[0008] Additional aspects will be set forth in the detailed description which follows, and in part will be apparent from the disclosure, or may be learned by practice of the disclosed embodiments and / or claimed subject matter.

[0009] According to one aspect, a display device includes a substrate, a first panel pad region, a first panel pad, a second panel pad, a planarization layer, an upper pad electrode, a circuit board, and an anisotropic conductive film. The substrate includes a display region and a non-display region. The first panel pad region is disposed in the non-display region. The first panel pad is disposed on the first panel pad region. The first panel pads are spaced apart from each other along a first direction. The second panel pads are spaced apart from the first panel pad in a second direction intersecting the first direction. The second panel pads are spaced apart from each other along the first direction. The planarization layer is disposed on the first and second panel pads. The planarization layer includes contact holes. Each contact hole exposes a corresponding first panel pad among the first panel pads. Upper pad electrodes are disposed on the planarization layer. Each of the upper pad electrodes is electrically connected to a corresponding first panel pad among the first panel pads via a corresponding contact hole among the contact holes. The circuit board overlaps the first panel pad region in a third direction perpendicular to the first and second directions. The circuit board includes a circuit pad. The anisotropic conductive film is disposed on the first panel pad region and electrically connects each of the upper pad electrodes to a corresponding circuit pad among the circuit pads.

[0010] In an embodiment, the upper pad electrode may include a first upper pad electrode and a second upper pad electrode spaced apart from the first upper pad electrode in the first direction.

[0011] In an embodiment, the first upper pad electrode may overlap one of the first panel pads in the third direction, and the second upper pad electrode may overlap another of the first panel pads in the third direction. The another first panel pad may be adjacent to the one first panel pad.

[0012] In an embodiment, the first upper pad electrode may overlap two second panel pads among the second panel pads in the third direction. The two second panel pads may be adjacent to the one first panel pad. The second upper pad electrode may not overlap the second panel pad in the third direction.

[0013] In an embodiment, the first upper pad electrode may be disposed closer to the display area than the second upper pad electrode.

[0014] In an embodiment, a corresponding width of the upper pad electrode may be greater than a corresponding width of the first panel pad or a corresponding width of the second panel pad.

[0015] In an embodiment, the first panel pads and the upper pad electrodes may be arranged in a one-to-one correspondence with each other.

[0016] In an embodiment, each of the upper pad electrodes may include a first portion having a first width and a second portion having a second width. The first width may be smaller than the second width.

[0017] In an embodiment, the upper pad electrode may include a first upper pad electrode and a second upper pad electrode. A direction in which the first portion of the first upper pad electrode protrudes from the second portion of the first upper pad electrode may be opposite to a direction in which the first portion of the second upper pad electrode protrudes from the second portion of the second upper pad electrode.

[0018] In an embodiment, the direction along which the first portion of the first upper pad electrode protrudes from the second portion of the first upper pad electrode may be a direction extending toward an adjacent side of the substrate. The direction along which the first portion of the second upper pad electrode protrudes from the second portion of the second upper pad electrode may be a direction extending toward the display area.

[0019] In an embodiment, the first upper pad electrode may overlap one of the first panel pads in the third direction. The first upper pad electrode may overlap two of the second panel pads in the third direction. The two second panel pads may be adjacent to the one first panel pad. The second upper pad electrode may not overlap the second panel pad in the third direction.

[0020] According to one aspect, a display device includes a substrate, a first panel pad region, a first panel pad, a second panel pad, a planarization layer, an upper pad electrode, a circuit board, and an anisotropic conductive film. The substrate includes a display region and a non-display region. The first panel pad region is disposed in the non-display region. The first panel pad is disposed on the first panel pad region. The first panel pads are spaced apart from each other along a first direction. The second panel pads are spaced apart from the first panel pad in a second direction intersecting the first direction. The second panel pads are spaced apart from each other along the first direction. The planarization layer is disposed on the second panel pad. The upper pad electrode is disposed on the first panel pad. The circuit board overlaps the first panel pad region in a third direction perpendicular to the first and second directions. The circuit board includes a circuit pad. The anisotropic conductive film is disposed on the first panel pad region and electrically connects each of the upper pad electrodes to a corresponding circuit pad among the circuit pads.

[0021] In an embodiment, the planarization layer may overlap the second panel pad in the third direction and may not overlap the first panel pad in the third direction.

[0022] In an embodiment, each of the upper pad electrodes may directly contact a corresponding first panel pad among the first panel pads.

[0023] In an embodiment, the upper pad electrode may include a first upper pad electrode and a second upper pad electrode spaced apart from the first upper pad electrode in the first direction.

[0024] In an embodiment, the first upper pad electrode may overlap the planarization layer in the third direction, and the second upper pad electrode may not overlap the planarization layer in the third direction.

[0025] According to one aspect, a method for manufacturing a display device includes forming a first panel pad and a second panel pad on a substrate, the first panel pads being spaced apart from each other along a first direction, and the second panel pads being spaced apart from the first panel pad in a second direction intersecting the first direction. The second panel pads are spaced apart from each other along the first direction. The method also includes forming a planarization layer on the second panel pad or both the first panel pad and the second panel pad; forming upper pad electrodes on at least the planarization layer, each of the upper pad electrodes being electrically connected to a corresponding first panel pad among the first panel pads. The method also includes aligning a circuit pad of a circuit board with the upper pad electrodes; and pressing an anisotropic conductive film between the circuit board and the substrate to bond the circuit board and the substrate together and form corresponding electrical connections between the upper pad electrodes and the circuit pads.

[0026] In an embodiment, a planarization layer may be formed on both the first panel pad and the second panel pad. The method may further include forming contact holes in the planarization layer. Each of the contact holes may expose a corresponding first panel pad among the first panel pads. The method may further include forming connecting electrodes in the contact holes. Each connecting electrode may be formed in a corresponding contact hole among the contact holes. Each of the upper pad electrodes may be electrically connected to a corresponding first panel pad among the first panel pads via a corresponding connecting electrode among the connecting electrodes.

[0027] In an embodiment, the planarization layer may not overlap the first panel pad in a view in a third direction perpendicular to the first and second directions. Each of the upper pad electrodes may also be directly formed on a portion of a corresponding first panel pad among the first panel pads to form an electrical connection between the upper pad electrode and the corresponding first panel pad.

[0028] In an embodiment, the method may further include forming test pads on the substrate from the same layer of material used to form the first panel pads. Each test pad may be electrically connected to a corresponding first panel pad among the first panel pads. The method may further include forming test electrodes on the test pads from the same layer of material used to form the upper pad electrodes; and cutting the substrate into at least one unit. Cutting the substrate into at least one unit may separate the test pads and the test electrodes from the display device.

[0029] According to various embodiments, by increasing the adhesion area between the anisotropic conductive film and the upper pad electrode, the adhesion reliability between the circuit board and the substrate can be improved. In some implementations, a relatively high-resolution display device can be realized in which the pad area and the circuit board are bonded together using the anisotropic conductive film.

[0030] According to some embodiments, at least because the planarization layer can be formed not to overlap with the first panel pad and to overlap with the second panel pad, it may be feasible to omit one or more contact holes in the planarization layer, thereby simplifying the structure and omitting one or more manufacturing processes.

[0031] The foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Various embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals and / or characters refer to similar elements.

[0033] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0034] Figure 2 According to the embodiment of the invention Figure 1 A schematic cross-sectional view taken along the section line Q1-Q1'.

[0035] Figure 3 is a schematic cross-sectional view of a light emitting element according to an embodiment.

[0036] Figure 4 According to the embodiment Figure 1 An enlarged schematic plan view of a portion P1 of FIG.

[0037] Figure 5 According to the embodiment of the invention Figure 4 A schematic cross-sectional view taken along the section line Q2-Q2'.

[0038] Figure 6 According to the embodiment of the invention Figure 4 A schematic cross-sectional view taken along the section line Q3-Q3'.

[0039] Figure 7 According to the embodiment Figure 1 An enlarged schematic plan view of an example of a portion P1.

[0040] Figure 8 is a diagram showing a method according to an embodiment of the present invention. Figure 7 Schematic plan view of a first upper pad electrode and a second upper pad electrode.

[0041] Figure 9 According to the embodiment Figure 1 An enlarged schematic plan view of an example of a portion P1.

[0042] Figure 10 According to the embodiment of the invention Figure 9 A schematic cross-sectional view taken along the section line Q4-Q4'.

[0043] Figure 11 According to the embodiment of the invention Figure 9 A schematic cross-sectional view taken along the section line Q5-Q5'.

[0044] Figures 12 to 18 are schematic cross-sectional views of a display device at various stages of manufacture according to an embodiment.

[0045] Figure 19 is a schematic perspective view of a virtual reality (VR) device including a display device according to an embodiment.

[0046] Figure 20 is a schematic perspective view of a smart device including a display device according to an embodiment.

[0047] Figure 21 is a schematic perspective view of a vehicle including a display device according to an embodiment.

[0048] Figure 22 is a schematic perspective view of a transparent display device including a display device according to an embodiment. DETAILED DESCRIPTION

[0049] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various embodiments or implementations. The terms "embodiment" and "implementation" can be used interchangeably to describe one or more non-limiting examples of the systems, devices, methods, etc. described herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various embodiments. In addition, the various embodiments may be different, but are not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the embodiment may be used or implemented in another embodiment without departing from the disclosed teachings.

[0050] Unless otherwise noted, the illustrated embodiments are to be understood as providing exemplary features of varying details of some embodiments. Therefore, unless otherwise noted, the various illustrated features, components, modules, layers, films, regions, aspects, structures, etc. (hereinafter individually or collectively referred to as "elements" or "elements") may be combined, separated, interchanged, and / or rearranged in other ways without departing from the teachings of the disclosure.

[0051] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross hatching or shading is not intended to convey or indicate any preference or requirement for the material, material properties, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the sizes and relative sizes of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the sizes and relative sizes of the various elements are not necessarily limited to the sizes and relative sizes shown in the drawings. In the case where the embodiments can be implemented differently, a specific process sequence can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously, or can be performed in an order opposite to the described order. In addition, the same reference numerals and / or figure characters represent the same elements.

[0052] When an element (such as a layer) is referred to as being “on,” “over,” “connected to” (or “connected to”), or “bound to” (or “bound to”) another element, it may be directly on, directly on, directly connected to (or directly connected to), or directly bound to (or directly bound to) the other element, or there may be at least one intervening element. However, when an element is referred to as being “directly on,” “directly on,” “directly connected to” (or “directly connected to”), or “directly bound to” (or “directly bound to”) another element, there are no intervening elements. Other terms and / or phrases used herein to describe relationships between elements should be interpreted in a similar manner, such as “between” versus “directly between,” “adjacent” versus “directly adjacent to,” “on” versus “directly on,” “in contact with” versus “directly in contact with,” “touching” versus “directly touching,” etc. Additionally, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection. For this reason, for purposes of this disclosure, similar to how the phrase "electrically connected" is used with respect to components that are connected to form an electrical connection, the phrase "fluidically connected" may be used with respect to volumes, plenums, holes, openings, etc. that may be connected to one another to form a fluid connection, either directly or via one or more intervening components or volumes.

[0053] For the purposes of this disclosure, the first axis extending along the first direction DR1, the second axis extending along the second direction DR2, and the third axis extending along the third direction DR3 are not limited to the three axes of a rectangular coordinate system (such as the x-axis, y-axis, and z-axis of a Cartesian coordinate system) and can be interpreted in a broader sense. For example, the first axis, the second axis, and the third axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. In addition, as used herein, the phrases "at least one of X, Y, ..., and Z" and "at least one selected from the group consisting of X, Y, ..., and Z" can be interpreted as only X, only Y, ..., only Z, or any combination of two or more of X, Y, ..., and Z (such as XYZ, XYY, YZ, and ZZ as examples). In addition, as used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0054] Although the terms "first," "second," and "third" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the disclosed teachings, the first element discussed below may be referred to as the second element. For this reason, the use of such identifiers (e.g., "first element") should not be interpreted as implicitly or inherently suggesting that another instance (e.g., "second element") must exist.

[0055] For descriptive purposes, spatially relative terms such as "below," "beneath," "beneath," "lower," "above," "upper," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein to describe the spatial relationship of one element to at least another element as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the drawings is turned over, an element described as "below" or "beneath" other elements or features would then be oriented "above" or "on" the other elements or features. Thus, the term "below" can encompass both above and below orientations. Moreover, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and, as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0056] The terminology used herein is for the purpose of describing some embodiments and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a," "an," and "the," as used herein, are intended to include the plural forms as well. It will be understood that phrases such as "for each of one or more <items>" and / or "each of one or more <items>" as used herein include both single and multiple groups of items. That is, the phrase "for each" is used in a programming language to refer to each item in any group of items being referenced. For example, if the group of items being referenced is a single item, then "each" will refer only to that single item (although dictionary definitions of "each" often define the term to mean "each of two or more things") and will not imply that at least two of those items must be present. Similarly, the terms "set" or "subset" should not be construed as necessarily encompassing a plurality of items by themselves; it will be understood that a set or subset can encompass only one component or multiple components (unless the context indicates otherwise).

[0057] When the terms "comprises" and variations thereof, "includes" and variations thereof, and / or "having" and variations thereof are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It is also noted that the terms "substantially," "about," "approximately," and other similar terms as used herein are used as approximate terms rather than terms of degree, and as such, are used to account for the inherent deviations in measured, calculated, and / or provided values ​​that will be recognized by those of ordinary skill in the art. Thus, unless otherwise indicated, the term "substantially" as used herein can mean within 5% of the reference value. For example, substantially perpendicular can mean within ±5% of a parallel state. Furthermore, unless otherwise indicated, the term "between" as used herein in connection with a numerical range should be understood to include the starting and ending values ​​of the range. For example, between 1 and 5 should be understood to include the numbers 1, 2, 3, 4, and 5, rather than just the numbers 2, 3, and 4.

[0058] Various embodiments are described herein with reference to cross-sectional, isometric, perspective, orthogonal, and / or exploded views that are schematic illustrations of idealized embodiments and / or intermediate structures. As such, variations from the illustrated shapes due, for example, to manufacturing techniques and / or tolerances, are to be expected. Thus, the embodiments disclosed herein should not be construed as limited to the illustrated shapes of regions but are to include deviations in shapes that result, for example, from manufacturing. To this end, the regions illustrated in the figures may be schematic in nature, and the shapes of such regions may not reflect the actual shapes of regions of the device and, as such, are not intended to be limiting.

[0059] According to common practice in the art, some embodiments may be described and illustrated in the accompanying drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.), and that these blocks, units, and / or modules may be formed using semiconductor-based or other manufacturing technologies. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein and may optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module may be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) that performs other functions. Furthermore, each block, unit, and / or module of some embodiments may be physically separated into two or more interacting and discrete blocks, units, and / or modules without departing from the scope of this disclosure. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the disclosure.

[0060] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and not in an idealized or overly formal sense, unless expressly defined herein.

[0061] Hereinafter, various embodiments will be described with reference to the accompanying drawings.

[0062] Figure 1 is a schematic plan view of a display device 10 according to the embodiment. Figure 2 According to the embodiment of the invention Figure 1 A schematic cross-sectional view taken along the section line Q1-Q1'.

[0063] Figure 1 and Figure 2An embodiment is schematically shown in which the display device 10 is a light-emitting diode on silicon (LEDoS) display device, in which a light-emitting diode as a light-emitting element LE is provided on a semiconductor circuit board formed by a semiconductor process using a silicon wafer (for example, on a substrate 110 (for example, a backplane substrate) of the display panel 100 in which the pixel circuit PXC and the like are formed on the silicon wafer). However, the device including the light-emitting element LE is not limited to the above example. For example, the light-emitting element LE can be applied to (or associated with) display devices of different types and / or structures, or can be applied to devices of different types and / or structures, such as lighting devices such as light bulbs. Hereinafter, the substrate 110 will be referred to as the backplane substrate 110.

[0064] exist Figure 1 and Figure 2 , the first direction DR1 may refer to the horizontal direction of the display panel 100, and the second direction DR2 may refer to the vertical direction of the display panel 100. The third direction DR3 may refer to the thickness direction of the display panel 100. In this manner, the “plan view” may be a view of the display panel 100 in the third direction DR3.

[0065] The display device 10 according to the embodiment may include a display panel 100. The display panel 100 may include a display area DA and a non-display area NDA.

[0066] The display panel 100 may have a quadrilateral planar shape having long sides in the first direction DR1 and short sides in the second direction DR2. However, the planar shape of the display panel 100 is not limited to this example, and the display panel 100 may have a polygonal, circular, oval, elliptical, or irregular planar shape other than (or in addition to) a quadrilateral planar shape. As used herein, "planar shape" may refer to the shape of an element in a view (e.g., a plan view) of the element in the third direction DR3.

[0067] The display area DA may be an area where an image may be displayed, and the non-display area NDA may be an area where no image is displayed. In an embodiment, the planar shape of the display area DA may follow (or correspond to) the planar shape of the display panel 100, but the embodiment is not limited to this example. For example, the planar shape of the display area DA may be different from the planar shape of the display panel 100. Figure 1As shown in , the planar shape of the display area DA is a quadrilateral planar shape. The display area DA can be set in the central area (or central zone) of the display panel 100. The non-display area NDA can be set outside the display area DA (for example, around the display area DA). For example, the non-display area NDA can surround the display area DA in the view on the third direction DR3. For example, the inner boundary of the non-display area NDA can surround (or surround) the outer boundary of the display area DA in the view on the third direction DR3. As used herein, the terms "surround" and "surrounding" are not limited to a first feature that forms a circle around a second feature, and as such, may include a first feature that forms any suitable two-dimensional geometric figure around the second feature in the view on the third direction DR3, for example. To this end, the first feature that surrounds or surrounds the second feature (unless otherwise specified) may include the inner boundary of the first feature that contacts one or more points of the outer boundary of the second feature, or the inner boundary of the first feature may be spaced apart from the outer boundary of the second feature.

[0068] The display area DA of the display panel 100 may include pixels PX. Each of the pixels PX may be defined as (or formed into) a minimum light-emitting unit (or structure) that can display color light (such as white light). In some embodiments, a single pixel PX may be configured to display white light, thereby forming a minimum light-emitting unit. In some embodiments, two or more sub-pixels may be grouped together to form a single pixel PX configured to display white light, thereby forming a minimum light-emitting unit.

[0069] In an embodiment, each pixel PX may include three light-emitting elements LE. For example, each pixel PX may include a first light-emitting element LE1 disposed in a first emission area EA1, a second light-emitting element LE2 disposed in a second emission area EA2, and a third light-emitting element LE3 disposed in a third emission area EA3. Hereinafter, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may be collectively (or individually) referred to as light-emitting elements LE. The number and / or type of light-emitting elements LE disposed in each (or as part of) pixel PX may vary depending on the embodiment.

[0070] In an embodiment, each of the pixels PX may include a light emitting element LE that emits light of different colors from each other. For example, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may emit light of different colors from each other.

[0071] The first light emitting element LE1 may emit first light. The first light may be red light. For example, a peak wavelength (R-peak) of the first light may be in the range of about 600 nm to about 750 nm, but the embodiment is not limited to this example.

[0072] The second light emitting element LE2 may emit a second light different from the first light. The second light may be green light. For example, the peak wavelength (G-peak) of the second light may be in the range of about 480 nm to about 560 nm, but the embodiment is not limited to this example.

[0073] The third light emitting element LE3 may emit a third light that may be different from both the first light and the second light. The third light may be blue light. For example, the peak wavelength (B-peak) of the third light may be in the range of about 370 nm to about 460 nm, but the embodiment is not limited to this example.

[0074] In an embodiment, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 can emit light of the same color. In some embodiments, a light conversion layer including a light conversion element (e.g., quantum dots and / or quantum rods, etc.) for converting the color (or wavelength band corresponding to the color) of light emitted from at least one light-emitting element LE into light of another color (or wavelength band corresponding to another color) can be disposed on (or overlapped with) at least one light-emitting element LE among the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3, for example, in the third direction DR3.

[0075] In an embodiment, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 of each pixel PX may be sequentially arranged in the first direction DR1 (or sequentially arranged along the first direction DR1). In an embodiment, the first light-emitting element LE1 may be arranged in the second direction DR2 (or arranged along the second direction DR2). The second light-emitting element LE2 may be arranged in the second direction DR2 (or arranged along the second direction DR2). The third light-emitting element LE3 may be arranged in the second direction DR2 (or arranged along the second direction DR2). For example, the first light-emitting element LE1, the second light-emitting element LE2, or the third light-emitting element LE3 may be arranged in each pixel column extending along the second direction DR2 (or arranged along each pixel column extending along the second direction DR2). The arrangement structure of the pixel PX and the light-emitting elements LE provided in the pixel PX (or included as part of the pixel PX) may vary depending on the embodiment.

[0076] In the embodiment, the light emitting elements LE may be arranged at substantially equal intervals in the display area DA in the first direction DR1 and the second direction DR2. However, the embodiment is not limited to this example. For example, the position and / or arrangement interval of the light emitting elements LE may vary according to the embodiment.

[0077] In embodiments, the sizes (e.g., areas) of the light-emitting elements LE may be substantially equal. For example, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may have substantially the same size. For example, the size of the light-emitting element LE may refer to the planar surface area of ​​the light-emitting element LE when viewed in the third direction DR3, or one or more dimensions (e.g., length, width, etc.) of the light-emitting element LE. However, embodiments are not limited to this example. For example, the respective sizes of the light-emitting elements LE and / or the areas of the emission regions corresponding to the light-emitting elements LE may vary depending on the embodiment.

[0078] In an embodiment, each light-emitting element LE may have a circular planar shape when viewed in the third direction DR3, but the embodiment is not limited to this example. For example, each light-emitting element LE may have a quadrilateral planar shape or other polygonal planar shape, an oval planar shape, an elliptical planar shape, or an irregular shape. The light-emitting elements LE may have substantially the same planar shape, or may have one or more different planar shapes. In some embodiments, the planar shapes of light-emitting elements LE in different groups may have the same planar shape or different planar shapes.

[0079] The non-display area NDA may include a first panel pad area PDA1 and a second panel pad area PDA3 .

[0080] The first panel pad area PDA1 may be disposed in (or overlap with) the non-display area NDA. The first panel pad area PDA1 may be disposed on a first side (e.g., an upper side) of the display panel 100. A first panel pad PD1 and a second panel pad PD2, which will be described later, may be disposed in the first panel pad area PDA1.

[0081] The first panel pad area PDA1 may be electrically connected to the first circuit board CB1 through at least one conductive connection member. For example, the first panel pad PD1 may be electrically connected to the circuit pad CPD disposed on the first circuit board CB1 through an anisotropic conductive film ACF.

[0082] The second panel pad area PDA3 may be disposed in (or overlapped with) the non-display area NDA. The second panel pad area PDA3 may be disposed on a second side (e.g., a lower side) of the backplane substrate 110 or the display panel 100. A third panel pad may be disposed in the second panel pad area PDA3.

[0083] The second panel pad area PDA3 and the third panel pad may be substantially the same as or similar to the first panel pad area PDA1, the first panel pad PD1, and the second panel pad PD2, respectively. However, the embodiment is not limited to this example. In some embodiments, the second panel pad area PDA3 and the third panel pad may be omitted.

[0084] The non-display area NDA may include the common electrode connection portion CVA1 surrounding (or encircling) the display area DA in a view in the third direction DR3 . In some embodiments, the common electrode connection portion CVA1 may not completely surround the display area DA.

[0085] The common electrode connection portion CVA1 may be provided in the non-display area NDA and may be provided between the first panel pad area PDA1 and the display area DA, and between the second panel pad area PDA3 and the display area DA. The common electrode connection portion CVA1 may be provided on one side (or first side) and the other side (or second side) of the display area DA that are opposite to each other in the first direction DR1 (or along the first direction DR1), and may be provided on one side (or third side) and the other side (or fourth side) of the display area DA that are opposite to each other in the second direction DR2 (or along the second direction DR2). The common electrode connection portion CVA1 may include a plurality of common electrode connectors CVS for providing one or more electrical connections to the backplane substrate 110.

[0086] The common electrode connection portion CVA1 may surround (or encircle) at least a portion of the display area DA in a plan view. Figure 1 As shown in FIG, the common electrode connection portion CVA1 may completely surround the display area DA. However, embodiments are not limited to this example. For example, the common electrode connection portion CVA1 may be provided on one side (or side edge), two opposite sides, two non-opposite sides, or at least three sides of the display area DA.

[0087] The common electrode connection portion CVA1 may include a portion electrically connected to a common electrode (eg, Figure 2 The common electrode CE in the display area DA may be connected to a plurality of common electrode connectors CVS. For example, the common electrode CE may extend from the display area DA to the common electrode connection portion CVA1 and may be electrically connected to the common electrode connectors CVS. A common voltage may be supplied to the common electrode CE through the common electrode connectors CVS.

[0088] The common electrode connection member CVS may be provided in the common voltage supply area (eg, the common electrode connection portion CVA1 ) of the non-display area NDA. The common electrode connection member CVS may include a conductive material (eg, a metal material such as aluminum (Al)). Figure 1 and Figure 2 , a display device 10 is shown in which the common electrode connector CVS is located in the non-display area NDA, but embodiments are not limited to this structure or arrangement. For example, the common electrode connector CVS may be additionally or alternatively located in the display area DA. For example, the common electrode connector CVS may be located in a pixel PX or in an area between pixels PX (or overlap with a pixel PX or an area between pixels PX).

[0089] The common electrode connection part CVS of the common electrode connection part CVA1 can be electrically connected to any one of the first panel pad PD1 and the second panel pad PD2 of the first panel pad area PDA1. For example, the common electrode connection part CVS of the common electrode connection part CVA1 can receive a common voltage from any one of the first panel pads PD1 of the first panel pad area PDA1.

[0090] The display device 10 may further include a first circuit board CB1 and a second circuit board CB2 .

[0091] Each of the first and second circuit boards CB1 and CB2 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), a flexible printed circuit (FPC), or a flexible film such as a chip on film (COF). However, embodiments are not limited to these examples.

[0092] The first circuit board CB1 and the second circuit board CB2 may respectively overlap edges of the display panel 100. In a view in the third direction DR3, the display panel 100 may be disposed between the first circuit board CB1 and the second circuit board CB2.

[0093] For example, in a plan view, the first circuit board CB1 may face a first side of the display panel 100 extending in a first direction DR1, and the second circuit board CB2 may face a second side of the display panel 100 that may be opposite to the first side of the display panel 100 along, for example, the second direction DR2. Figure 1 As shown in FIG, the first circuit board CB1, the display panel 100, and the second circuit board CB2 may be sequentially arranged in (or along) the second direction DR2 in a plan view.

[0094] However, embodiments are not limited to the above arrangement. For example, either the first circuit board CB1 or the second circuit board CB2 may face a first side of the display panel 100 extending in the first direction DR1, and the other of the first circuit board CB1 and the second circuit board CB2 may face a second side of the display panel 100 extending in, for example, the second direction DR2. In some embodiments, the second circuit board CB2 may be omitted.

[0095] Reference Figure 2 The display panel 100 may include a backplane substrate 110 and a light emitting element layer 120. In an embodiment, the display panel 100 may further include an optical structure (and / or light output structure) provided (or disposed) on the light emitting element layer 120, for example, one or more (e.g., multiple) lens-type optical structures LS.

[0096] The display panel 100 may further include one or more additional components according to embodiments. For example, the display panel 100 may further include a light conversion layer for converting the color and / or wavelength of light emitted from at least some of the light emitting elements LE and / or a color filter layer for controlling the specific (or determined) color of light to be emitted from each emission area EA.

[0097] The display panel 100 may include emission areas EA located (or arranged) within the display area DA. Each of the emission areas EA may include at least one light-emitting element LE. For example, the emission areas EA may include first emission areas EA1, each including at least one first light-emitting element LE1; second emission areas EA2, each including at least one second light-emitting element LE2; and third emission areas EA3, each including at least one third light-emitting element LE3. In an embodiment, first light, second light, and third light may be emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively.

[0098] The backplane substrate 110 may include a display area DA (or may include a portion within or overlapping the display area DA), and the display area DA may include an emission area EA. In embodiments, the backplane substrate 110 may be a semiconductor circuit board formed using a wafer (such as a silicon wafer) through a semiconductor process. For example, a silicon wafer may be used as a base member for forming the display panel 100.

[0099] The backplane substrate 110 may include a pixel circuit PXC and a pixel electrode PXE disposed on a portion of the backplane substrate 110 and in the display area DA. For example, at least one light emitting element LE may be disposed in each emission area EA of the display panel 100, and the backplane substrate 110 may include a pixel electrode PXE and a pixel circuit PXC connected (e.g., electrically connected) to the light emitting elements LE disposed in the emission areas EA, respectively.

[0100] In an embodiment, the backplane substrate 110 may further include a first insulating layer INS1 disposed around the pixel electrode PXE (or between the pixel electrodes PXE). For example, in a view along the third direction DR3, the first insulating layer INS1 may surround the pixel electrode PXE, or may be at least disposed between adjacent pixel electrodes PXE.

[0101] Pixel circuits PXC may be disposed in the display area DA to correspond to regions in which pixels PX and / or emission areas EA are respectively formed. In an embodiment, each of the pixel circuits PXC may include a complementary metal oxide semiconductor (CMOS) circuit formed using a semiconductor process.

[0102] Each of the pixel circuits PXC may include at least one transistor formed by a semiconductor process. In addition, each of the pixel circuits PXC may further include at least one capacitor formed by a semiconductor process.

[0103] The pixel circuits PXC may be electrically connected to the pixel electrodes PXE, respectively. For example, the pixel circuits PXC and the pixel electrodes PXE may be electrically connected to each other in a one-to-one correspondence. Each of the pixel circuits PXC may apply a pixel voltage to the corresponding pixel electrode PXE electrically connected to the pixel circuit PXC.

[0104] The pixel electrodes PXE may be electrically connected to the pixel circuits PXC, respectively. The pixel electrodes PXE may be individually disposed in the emission areas EA and electrically connected to the light-emitting elements LE, respectively disposed in the emission areas EA. The light-emitting elements LE, respectively disposed in the emission areas EA, may be controlled individually and / or independently of one another.

[0105] Each pixel electrode PXE may be disposed on a corresponding pixel circuit PXC. For example, each pixel electrode PXE may overlap a portion of the corresponding pixel circuit PXC in the third direction DR3. In embodiments, each pixel electrode PXE may be formed integrally with (and / or integral with) the pixel circuit PXC and exposed from the pixel circuit PXC. For example, each pixel electrode PXE may protrude from a surface (e.g., an upper surface) of the pixel circuit PXC. Each pixel electrode PXE may receive a pixel voltage from the corresponding pixel circuit PXC. The pixel electrode PXE may include a conductive material (e.g., a metal material such as aluminum (Al)), but embodiments are not limited to this example.

[0106] In an embodiment, the first insulating layer INS1 may be provided around the pixel electrode PXE, for example, when viewed in the third direction DR3. The first insulating layer INS1 may be provided on a surface (e.g., an upper surface) of the semiconductor circuit board in which (or on which) the pixel circuit PXC is formed. In an embodiment, the first insulating layer INS1 may be provided between the pixel electrodes PXE to surround (or encircle) the pixel electrodes PXE.

[0107] The first insulating layer INS1 may expose at least a portion of each of the pixel electrodes PXE. For example, the first insulating layer INS1 may include an opening corresponding to the pixel electrode PXE, and the surface (eg, upper surface) of the pixel electrode PXE may be exposed through the opening. The first insulating layer INS1 may include an inorganic insulating material (such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Alx O y ) and at least one of aluminum nitride (AlN) and / or any other suitable insulating material.

[0108] The backplane substrate 110 may also include Figure 1 and Figure 2 . In an embodiment, the backplane substrate 110 may further include a common electrode connector CVS, a first panel pad PD1, a second panel pad PD2, and the like, which are provided on a portion of the backplane substrate 110 and in the non-display area NDA.

[0109] In an embodiment, the common electrode connection member CVS may be provided in (or as part of) the common electrode connection portion CVA1 of the non-display area NDA. For example, the common electrode connection member CVS may be provided on opposite sides of the display area DA.

[0110] In an embodiment, each of the common electrode connections CVS may include a first common connection electrode CCE1, a second common connection electrode CCE2, and a third common connection electrode CCE3. The first common connection electrode CCE1 may include the same material as the pixel electrode PXE. In some embodiments, the first common connection electrode CCE1 and the pixel electrode PXE may be formed using the same process and / or from the same initial layer of material. The first common connection electrode CCE1 and the pixel electrode PXE may be formed to have the same thickness in the third direction DR3.

[0111] The second common connection electrode CCE2 may be disposed on the first common connection electrode CCE1. The second common connection electrode CCE2 may include the same material as the bonding electrode BOE. In some embodiments, the second common connection electrode CCE2 and the bonding electrode BOE may be formed using the same process and / or from the same initial layer of material. However, in some embodiments, the second common connection electrode CCE2 may have a thickness smaller than that of the bonding electrode BOE in the third direction DR3.

[0112] The third common connection electrode CCE3 may be disposed on the second common connection electrode CCE2 and may transmit a common voltage signal from the second common connection electrode CCE2 to the light-emitting element LE. The third common connection electrode CCE3 may be made of the same material as the bonding electrode BOE, but the embodiment is not limited thereto. The third common connection electrode CCE3 may be relatively thick in the third direction DR3 to electrically connect the second common connection electrode CCE2 and the light-emitting element LE.

[0113] The first panel pad PD1 may be electrically connected to the circuit pad CPD of the first circuit board CB1 through the anisotropic conductive film ACF. For example, the first panel pad PD1 and the circuit pad CPD of the first circuit board CB1 may be electrically connected to each other in a one-to-one correspondence.

[0114] In an embodiment, each of the first panel pads PD1 may include a first pad electrode PDE1 and a second pad electrode PDE2. The first pad electrode PDE1 may include the same material as the first common connection electrode CCE1. In some embodiments, the first pad electrode PDE1 and the first common connection electrode CCE1 may be formed by the same process and / or from the same initial layer of material. The first pad electrode PDE1 and the first common connection electrode CCE1 may be formed to have the same thickness as each other in the third direction DR3.

[0115] The second pad electrode PDE2 may be disposed on the first pad electrode PDE1. The second pad electrode PDE2 may include the same material as the second common connection electrode CCE2. In some embodiments, the second pad electrode PDE2 may be formed using the same process and / or from the same initial layer of material as the second common connection electrode CCE2 and the bonding electrode BOE. The second pad electrode PDE2 may be formed to have the same thickness as the second common connection electrode CCE2 in the third direction DR3. However, the second pad electrode PDE2 may be thinner than the bonding electrode BOE in the third direction DR3.

[0116] Like the first panel pad PD1, the second panel pad PD2 may include a first pad electrode PDE1 and a second pad electrode PDE2. The second panel pad PD2 may be used as a pad for test driving (or testing) the display panel 100, or as a dummy pad. For ease of description, an embodiment in which the second panel pad PD2 is a dummy pad will be described as an example.

[0117] According to an embodiment, the first panel pad area PDA1 may further include a planarization layer PLL, a connection electrode CNE, and an upper pad electrode PCE.

[0118] The planarization layer PLL may be provided in the first panel pad area PDA1 and may insulate and planarize a surface covering the first and second panel pads PD1 and PD2. The planarization layer PLL may be made of an organic material that may perform a planarization function, but the embodiment is not limited to this example.

[0119] The connection electrode CNE may electrically connect the second pad electrode PDE2 of the first panel pad PD1 to the upper pad electrode PCE. The connection electrode CNE may fill a contact hole CNT of a planarization layer PLL as will be described later (see, for example, Figure 4 ). The connection electrode CNE may be made of a metal material having a relatively low resistance.

[0120] The upper pad electrode PCE may be provided on both the planarization layer PLL and the connection electrode CNE. The upper pad electrode PCE may be electrically connected to the second pad electrode PDE2 of the first panel pad PD1 through the connection electrode CNE. The upper pad electrode PCE may be electrically connected to the circuit pad CPD of the first circuit board CB1 through the anisotropic conductive film ACF.

[0121] The light emitting element layer 120 may include a bonding electrode BOE, a light emitting element LE, and a common electrode CE. In an embodiment, the light emitting element layer 120 may further include an organic layer ORL disposed around or at least adjacent to the light emitting element LE in a view in the third direction DR3 and / or a second insulating layer INS2 disposed on the common electrode CE.

[0122] In an embodiment, the light emitting element layer 120 may further include one or more additional components. For example, the light emitting element layer 120 may further include a reflective layer and / or a light blocking layer disposed between the light emitting elements LE and / or on side surfaces (eg, lateral side surfaces) of the light emitting elements LE.

[0123] The bonding electrodes BOE may be provided at positions corresponding to the pixel electrodes PXE, and may be electrically connected to the pixel electrodes PXE. For example, the bonding electrodes BOE may be provided on the pixel electrodes PXE. The bonding electrodes BOE may be individually patterned into shapes corresponding to the shapes of the pixel electrodes PXE. For example, the bonding electrodes BOE may be individually patterned into sizes and / or planar shapes corresponding to the sizes and / or planar shapes of the pixel electrodes PXE, and thus the bonding electrodes BOE may be separated from each other.

[0124] Each of the bonding electrodes BOE may include a first bonding electrode and a second bonding electrode. The second bonding electrode may be provided on the first bonding electrode, and the first bonding electrode and the second bonding electrode may have sizes and planar shapes corresponding to each other.

[0125] The first bonding electrode and the second bonding electrode may include a conductive bonding material suitable for bonding or attaching the light-emitting element LE to the pixel electrode PXE. For example, each of the second bonding electrodes may be a single-layer or multi-layer electrode including at least one of gold (Au), copper (Cu), aluminum (Al), and tin (Sn), and / or any other suitable metal material (e.g., a bonding metal).

[0126] The light emitting elements LE may be respectively disposed on the bonding electrodes BOE, and each of the light emitting elements LE may be electrically connected between a corresponding pixel electrode PXE among the pixel electrodes PXE and the common electrode CE.

[0127] The light emitting element LE may include a semiconductor layer grown on a semiconductor substrate (e.g., a wafer substrate) by epitaxial growth, but any other suitable method of forming a semiconductor layer may be used. For example, each of the light emitting elements LE may include a first semiconductor layer doped with a first conductive type dopant, a second semiconductor layer doped with a second conductive type dopant, and an active layer disposed between the first semiconductor layer and the second semiconductor layer. Figure 3 An example structure of the light emitting element LE is described in more detail.

[0128] The light-emitting elements LE may be formed from one or more epitaxial thin films grown on a semiconductor wafer, which may be segmented or cut into a plurality of dies corresponding to the light-emitting elements LE. The light-emitting elements LE may be patterned or arranged in unit regions of the display panel 100 and may be formed in the emission areas EA, respectively. Some example structures and manufacturing methods of the light-emitting elements LE according to some embodiments will be described in more detail later.

[0129] In the third direction DR3, the organic layer ORL may be disposed around (or adjacent to) each light-emitting element LE. For example, in the third direction DR3, the organic layer ORL may be disposed between the emission areas EA to surround (or encircle) the emission areas EA in which the light-emitting elements LE are disposed, and may also surround (or encircle) the light-emitting elements LE and the second bonding electrode. In embodiments, the organic layer ORL may be a filler that fills one or more gaps between the light-emitting elements LE. The organic layer ORL may expose a portion (e.g., the upper surface) of each light-emitting element LE.

[0130] The organic layer ORL may include an insulating material. For example, the organic layer ORL may be a single layer or multiple layers of organic insulating material including at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin and / or any other suitable organic insulating material.

[0131] The common electrode CE may be disposed on portions of the light-emitting element LE not covered by the organic layer ORL. For example, the common electrode CE may be disposed on the upper surface of the light-emitting element LE exposed by an opening in the organic layer ORL. In embodiments, the common electrode CE may be disposed entirely (substantially entirely) in the display area DA to cover (overlap with) the light-emitting element LE and the organic layer ORL in, for example, the third direction DR3. The common electrode CE may be a common layer formed and / or electrically connected to the light-emitting elements LE of the display area DA and the pixels PX including the light-emitting elements LE. In some embodiments, multiple common electrodes CE may be utilized, and the multiple common electrodes CE may be formed in association with one or more light-emitting elements LE. When multiple common electrodes CE are utilized, the multiple common electrodes CE may be electrically connected to each other and / or to the same voltage source to receive a common voltage. Hereinafter, it will be assumed that the common electrode CE is formed in common with respect to the light-emitting elements LE of the display area DA of the display panel 100.

[0132] The common electrode CE may be electrically connected to a device provided at, for example, Figure 1 and Figure 2 The common electrode CE may receive a common voltage through the common electrode connector CVS in the common electrode connection portion CVA1 described in FIG.

[0133] The common electrode CE may include a transparent conductive material that transmits light. For example, the common electrode CE may be made of at least one of indium tin oxide (ITO) and indium zinc oxide (IZO) and / or any other suitable transparent conductive material (such as a transparent conductive polymer, which may be a derivative of at least one of polyacetylene, polyaniline, polypyrrole, and polythiophene). In embodiments, the common electrode CE may serve as the cathode (or anode) of each light-emitting element LE.

[0134] The second insulating layer INS2 may be provided on the common electrode CE. For example, the second insulating layer INS2 may be a covering layer provided in the entire (or substantially the entire) display area DA to cover (or overlap) the common electrode CE in, for example, the third direction DR3. The second insulating layer INS2 may include an inorganic insulating material (such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ) and at least one of aluminum nitride (AlN) and / or any other suitable insulating material.

[0135] In an embodiment, the display panel 100 may include a lens type optical structure LS disposed on the light emitting element layer 120. The display panel 100 may further include a protection layer PRL covering (or overlapping) the lens type optical structure LS in, for example, the third direction DR3.

[0136] The lens-type optical structure LS can be respectively arranged in the emission area EA to overlap with the light-emitting element LE. In an embodiment, the lens-type optical structure LS can be a convex lens-type optical structure arranged on the light-emitting element LE. The convex surface of the lens-type optical structure LS can be defined relative to the surface of the light-emitting element layer 120 on which the lens-type optical structure LS can be arranged. However, the type and / or shape of the optical structure is not limited to the above example. The lens-type optical structure LS arranged on the light-emitting element LE can adjust and / or improve the light output characteristics of the pixel PX.

[0137] The lens-type optical structure LS may be made of a transparent material to allow light incident from the light-emitting element LE to transmit therethrough. For example, the lens-type optical structure LS may be made of at least one of glass, plastic, and ceramic and / or any other suitable material, and may be made of an optical material having a relatively high refractive index.

[0138] The protective layer PRL may be provided on the lens-type optical structure LS to cover the lens-type optical structure LS (or to overlap with the lens-type optical structure LS). The protective layer PRL may be made of a transparent and durable material (e.g., plastic or at least one of organic glass, optical glass, and ceramics, and / or any other suitable material). The material of the protective layer PRL is not limited as long as the material is suitable for protecting the lens-type optical structure LS and is relatively transparent to allow light to propagate through the protective layer PRL. Although Figure 2 While an embodiment is described in which the surface (e.g., upper surface) of the protective layer PRL has multiple curved surfaces corresponding to the shape of the lens-type optical structure LS, the embodiment is not limited to this example structure. For example, the protective layer PRL may be formed to have a shape that flattens the upper surface of the display panel 100 that overlaps the lens-type optical structure LS.

[0139] Figure 3 is a schematic cross-sectional view of a light emitting element LE according to the embodiment.

[0140] Reference Figure 3The light-emitting element LE may include a first semiconductor layer SEM1, an active layer MQW, and a second semiconductor layer SEM2 sequentially arranged and / or stacked along a third direction DR3. In embodiments, the light-emitting element LE may further include a contact electrode CTE disposed at one end (or one end) of the light-emitting element LE. For example, the light-emitting element LE may further include a contact electrode CTE disposed at the end where the first semiconductor layer SEM1 is located. For example, the first semiconductor layer SEM1 may be disposed on the contact electrode CTE such that the first semiconductor layer SEM1 is positioned between the active layer MQW and the contact electrode CTE.

[0141] The light emitting element LE may further include one or more additional layers according to embodiments. For example, the light emitting element LE may include an electron blocking layer disposed between the first semiconductor layer SEM1 and the active layer MQW and / or a superlattice disposed between the active layer MQW and the second semiconductor layer SEM2.

[0142] In an embodiment, the light emitting element LE may be an inorganic light emitting element made of an inorganic material. For example, the light emitting element LE may be an inorganic light emitting diode made of at least one nitride-based semiconductor material (such as at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN) and at least one phosphide-based semiconductor material (such as at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP) and / or any other suitable inorganic material.

[0143] A contact electrode (CTE) may be disposed and / or formed at one end (or one side) of the light-emitting element LE where the first semiconductor layer SEM1 is disposed. For example, the contact electrode (CTE) may be disposed and / or formed on the surface of the first semiconductor layer SEM1. The contact electrode (CTE) may be an electrode used to protect the first semiconductor layer SEM1 and electrically connect the first semiconductor layer SEM1 to at least one circuit element, electrode, line, and / or conductive layer. The contact electrode (CTE) may include at least one of a metal and a metal oxide, and / or any other suitable conductive material.

[0144] The first semiconductor layer SEM1 may be disposed on the contact electrode CTE. In embodiments, the first semiconductor layer SEM1 may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the first semiconductor layer SEM1 may include a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide-based semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The first semiconductor layer SEM1 may additionally or alternatively include other materials.

[0145] The first semiconductor layer SEM1 may include a semiconductor material doped with a first conductive type dopant. For example, the first semiconductor layer SEM1 may be made of GaN (e.g., p-GaN) doped with a first conductive type dopant (e.g., p-type dopant) such as Mg, Zn, Ca, Sr, and / or Ba.

[0146] The active layer MQW may be disposed on the first semiconductor layer SEM1. The active layer MQW may emit light by recombining electron-hole pairs according to an electrical signal received through the first and second semiconductor layers SEM1 and SEM2. For example, the active layer MQW may be a light emitting layer of the light emitting element LE.

[0147] The active layer MQW may include a material having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, the active layer MQW may have a structure in which multiple well layers and multiple barrier layers are alternately stacked. Depending on the wavelength band of light that the active layer MQW is configured to emit, the active layer MQW may include different Group 3 to Group 5 semiconductor materials.

[0148] In embodiments, the active layer MQW may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the active layer MQW may include a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, InN, and AlInN, or a phosphide-based semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. For example, the well layer may be made of InGaN, and the barrier layer may be made of GaN or AlGaN, but embodiments are not limited to this example. When the active layer MQW includes InGaN, the color of light emitted from the light-emitting element LE can be controlled by adjusting the indium (In) content in the active layer MQW. The active layer MQW may additionally or alternatively include other materials.

[0149] In an embodiment, Figure 2 The active layers MQW of the first, second, and third light-emitting elements LE1, LE2, and LE3 shown in FIG may emit light of the same color (e.g., blue light). In an embodiment, the active layers MQW of the first, second, and third light-emitting elements LE1, LE2, and LE3 may emit light of different colors (e.g., red light, green light, and blue light, respectively).

[0150] The second semiconductor layer SEM2 may be disposed on the active layer MQW. In embodiments, the second semiconductor layer SEM2 may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the second semiconductor layer SEM2 may include a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide-based semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The second semiconductor layer SEM2 may additionally or alternatively include other materials.

[0151] The second semiconductor layer SEM2 may include a semiconductor material doped with a second conductivity type dopant. For example, the second semiconductor layer SEM2 may be made of GaN (e.g., n-GaN) doped with a second conductivity type dopant (e.g., n-type dopant) such as Si, Ge, Se, and / or Sn.

[0152] In embodiments, the first semiconductor layer SEM1 and the second semiconductor layer SEM2 may have different thicknesses in the thickness direction (e.g., third direction DR3) of the light emitting element LE. For example, the second semiconductor layer SEM2 may be thicker than the first semiconductor layer SEM1 in the thickness direction of the light emitting element LE. The active layer MQW may be positioned closer to the first end (e.g., p-type end) of the light emitting element LE, where the first semiconductor layer SEM1 is provided (or disposed), than to the second end (e.g., n-type end) of the light emitting element LE, where the second semiconductor layer SEM2 is provided (or disposed).

[0153] In embodiments, the light-emitting element LE may be a vertical micro-LED that extends and / or is stacked in the third direction DR3. For example, the light-emitting element LE may be a micro-LED having a length in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3, all ranging from approximately several micrometers (µm) to approximately several hundred µm. In embodiments, the length of the light-emitting element LE in the first direction DR1, the length of the light-emitting element LE in the second direction DR2, and the length of the light-emitting element LE in the third direction DR3 may all range from greater than 0 µm to approximately 100 µm.

[0154] In an embodiment, the light emitting element LE may include Figure 3 . For example, the light emitting element LE may be patterned by vertical etching and may have a rectangular or square cross-sectional shape in a plane parallel to (or substantially parallel to) the DR1-DR3 plane, such that the upper surface and the lower surface of the light emitting element LE have substantially the same width in a plane parallel to (or substantially parallel to) the DR1-DR2 plane.

[0155] The shape of the light-emitting element LE may vary depending on the embodiment. For example, the light-emitting element LE may have a cross-sectional shape in a plane parallel to (or substantially parallel to) the DR1-DR3 plane, such that the upper and lower surfaces of the light-emitting element LE have different widths in a plane parallel to (or substantially parallel to) the DR1-DR2 plane. However, the embodiments are not limited to this example. For example, the light-emitting element LE may have an inverted tapered cross-sectional shape in a plane parallel to (or substantially parallel to) the DR1-DR3 plane. For example, the light-emitting element LE may have an inverted trapezoidal cross-sectional shape in a plane parallel to (or substantially parallel to) the DR1-DR3 plane, such that the upper surface of the light-emitting element LE is wider than the lower surface of the light-emitting element LE in a plane parallel to (or substantially parallel to) the DR1-DR2 plane.

[0156] In an embodiment, the light emitting element LE may be disposed on the backplane substrate 110 such that Figure 3 As shown in FIG, the first semiconductor layer SEM1 is located below the active layer MQW (e.g., close to the backplane substrate 110), and the second semiconductor layer SEM2 is located above the active layer MQW (e.g., away from the backplane substrate 110). For example, the light emitting element LE can be provided in each emission area EA so that the contact electrode CTE (or the first semiconductor layer SEM1) contacts the bonding electrode BOE (such as Figure 2 ), and the second semiconductor layer SEM2 (or another contact electrode provided on the second semiconductor layer SEM2 ) contacts the common electrode CE which may serve as a cathode of the light emitting element LE.

[0157] The structure, material, size and / or shape of the light emitting element LE are not limited to the above-described embodiments. For example, the structure, material, size and / or shape of the light emitting element LE may vary according to the embodiments.

[0158] Figure 4 According to the embodiment Figure 1 An enlarged schematic plan view of a portion P1 of FIG. Figure 5 According to the embodiment of the invention Figure 4 A schematic cross-sectional view taken along the section line Q2-Q2'. Figure 6 According to the embodiment of the invention Figure 4 A schematic cross-sectional view taken along the section line Q3-Q3'.

[0159] Reference Figures 4 to 6 , the first panel pad area PDA1 may include a plurality of first panel pads PD1 and a plurality of second panel pads PD2 .

[0160] The first panel pad PD1 and the second panel pad PD2 may be disposed in the first panel pad area PDA1 . The first panel pad PD1 may be disposed on the backplane substrate 110 .

[0161] The first panel pads PD1 may extend in the second direction DR2 in a plan view and may be arranged to form a row in which the first panel pads PD1 are spaced apart from each other in the first direction DR1. The second panel pads PD2 may extend in the second direction DR2 in a plan view and may be arranged to form a row in which the second panel pads PD2 are spaced apart from each other in the first direction DR1. The first panel pads PD1 and the second panel pads PD2 may be spaced apart from each other in at least the second direction DR2. For example, Figure 4 As shown in FIG, the first panel pads PD1 may be arranged to form a first row R1 extending in a first direction DR1, and the second panel pads PD2 may be arranged to form a second row R2 extending in the first direction DR1. However, embodiments are not limited to this example. For example, the first panel pads PD1 and the second panel pads PD2 may be respectively provided or arranged to form two or more rows.

[0162] The first panel pad PD1 may be disposed closer to an edge of the backplane substrate 110 or an edge of the first panel pad area PDA1 than the second panel pad PD2. The second panel pad PD2 may be disposed closer to the display area DA or the common electrode connection portion CVA1 of the display panel 100 than the first panel pad PD1.

[0163] The first panel pad PD1 and the second panel pad PD2 may be disposed or arranged to form a zigzag pattern in a plan view. Figure 4 As shown in , the first panel pads PD1 in the first row R1 may be arranged at a first pitch in the first direction DR1, and the second panel pads PD2 in the second row R2 may be arranged at a second pitch in the first direction DR1. The first pitch and the second pitch may be equal, but the embodiment is not limited to this example. The first panel pads PD1 may be offset from the second panel pads PD2 in the second direction DR2 in a plan view. The space between the first panel pads PD1 of the first row R1 may not overlap with the second panel pads PD2 of the second row R2 in a third direction DR3 in a plan view. The first pitch and the second pitch may be substantially equal to the pitch at which a plurality of emission areas (e.g., the first emission area EA1, the second emission area EA2, and the third emission area EA3) are arranged. However, the embodiment is not limited to this example.

[0164] The first panel pads PD1 in the first row R1 and the second panel pads PD2 in the second row R2 may be arranged at a third interval in the second direction DR2. For example, the first panel pads PD1 and the second panel pads PD2 may be spaced apart from each other by a third interval in the second direction DR2.

[0165] The first panel pad PD1 in the first row R1 may be located in an oblique direction with respect to the second panel pad PD2 in the second row R2 closest to the first row R1 , and the oblique direction may cross both the first direction DR1 and the second direction DR2 in a plan view.

[0166] The first panel pad PD1 and the second panel pad PD2 may have a rectangular planar shape in a plan view. The total number of first panel pads PD1 and the total number of second panel pads PD2 may be equal, but the embodiment is not limited to this example. In addition, any suitable number of first panel pads PD1 and second panel pads PD2 may be utilized, provided that sufficient space is available for the first panel pad PD1 and the second panel pad PD2. However, the embodiment is not limited to these examples. For example, the first panel pad PD1 and the second panel pad PD2 may have any suitable geometric planar shape, such as a circular planar shape, a square planar shape, an oval planar shape, an elliptical planar shape, a diamond planar shape, an arbitrary (or irregular) planar shape, etc.

[0167] The planarization layer PLL may be disposed on the first panel pad PD1 and the second panel pad PD2 in the first panel pad area PDA1. The planarization layer PLL may cover the first panel pad PD1 and the second panel pad PD2 (or overlap the first panel pad PD1 and the second panel pad PD2) and may be aligned with the side (e.g., the lateral side) of the backplane substrate 110. The planarization layer PLL may insulate the first panel pad PD1 and the second panel pad PD2 from each other and may flatten steps that may otherwise be formed in the surface covering the first panel pad PD1 and the second panel pad PD2. The planarization layer PLL may be disposed in a portion of the first panel pad area PDA1. For example, in a view in the third direction DR3, the planar surface area of ​​the planarization layer PLL may be smaller than the planar surface area of ​​the first panel pad area PDA1.

[0168] The planarization layer PLL may include a plurality of contact holes CNT. The contact holes CNT may overlap with the first panel pad PD1 and expose a surface (e.g., an upper surface) of the first panel pad PD1. The contact holes CNT may be arranged corresponding to the first panel pad PD1. For example, the contact holes CNT may correspond one-to-one with the first panel pad PD1. One (or one) contact hole CNT may be arranged on one (or one) side surface of the first panel pad PD1. For example, the contact hole CNT may be arranged on the first panel pad PD1 and may be adjacent to one or more second panel pads PD2 (e.g., two second panel pads PD2).

[0169] A plurality of connection electrodes CNE may be provided in the first panel pad area PDA1. The connection electrodes CNE may overlap and correspond to the first panel pads PD1, respectively. For example, the connection electrodes CNE may correspond to the first panel pads PD1 one by one and overlap the first panel pads PD1 in the third direction DR3.

[0170] The connection electrodes CNE may be disposed in the contact holes CNT in the planarization layer PLL. The connection electrodes CNE may fill the contact holes CNT. The connection electrodes CNE may not protrude from the planarization layer PLL (e.g., above the planarization layer PLL) and may be disposed so that a surface (e.g., an upper surface) of the planarization layer PLL is flush with a corresponding surface (e.g., a corresponding upper surface) of the connection electrodes CNE. A polishing process (such as a chemical mechanical polishing (CMP) process) performed after forming the connection electrodes CNE in the contact holes CNT may cause the surface of the connection electrodes CNE to be coplanar with the corresponding surface of the planarization layer PLL. The connection electrodes CNE may be made of a metal having relatively low contact resistance with the first panel pad PD1. For example, the connection electrodes CNE may include at least one of gold (Au), copper (Cu), aluminum (Al), and tin (Sn), but embodiments are not limited to these materials.

[0171] A plurality of upper pad electrodes (e.g., a first upper pad electrode PCE1 and a second upper pad electrode PCE2) may be disposed on the planarization layer PLL. Hereinafter, the first upper pad electrode PCE1 and the second upper pad electrode PCE2 may be collectively referred to as "upper pad electrodes PCE1 and PCE2." The upper pad electrodes PCE1 and PCE2 may include a plurality of first upper pad electrodes PCE1 and a plurality of second upper pad electrodes PCE2.

[0172] The first upper pad electrodes PCE1 and the second upper pad electrodes PCE2 may be arranged to form a zigzag pattern in a plan view. The first upper pad electrodes PCE1 and the second upper pad electrodes PCE2 may be arranged alternately with each other in (or along) the first direction DR1. The first upper pad electrodes PCE1 and the second upper pad electrodes PCE2 may be arranged alternately with each other to overlap with the first panel pad PD1 in the third direction DR3. For example, the first upper pad electrode PCE1 of the first type may overlap with one side of the first panel pad PD1 of the first type, and the second upper pad electrode PCE2 of the first type may overlap with the first panel pad PD1 of the second type, with the first panel pad PD1 of the second type being adjacent to the first panel pad PD1 of the first type.

[0173] Each of the first upper pad electrodes PCE1 may overlap with a corresponding one of the first panel pads PD1 in the third direction DR3 and may also overlap with one or more of the second panel pads PD2 in the third direction DR3. For example, the first upper pad electrode PCE1 of the first type may overlap with the first panel pad PD1 of the first type in the third direction DR3 and may also overlap with two second panel pads PD2 in the third direction DR3, the two second panel pads PD2 being adjacent to the first panel pad PD1 of the first type in an oblique direction intersecting both the first direction DR1 and the second direction DR2.

[0174] The second upper pad electrode PCE2 may overlap with the first panel pad PD1 in the third direction DR3, and may not overlap with the second panel pad PD2 in the third direction DR3. For example, the second upper pad electrode PCE2 of the first type may overlap with the first panel pad PD1 of the second type, and in a view in the third direction DR3, the second upper pad electrode PCE2 of the first type may be spaced apart from two second panel pads PD2 that are adjacent to the first panel pad PD1 of the second type in an oblique direction intersecting both the first direction DR1 and the second direction DR2.

[0175] The first upper pad electrode PCE1 may be disposed closer to the common electrode connection portion CVA1 or the display area DA than the second upper pad electrode PCE2 . The second upper pad electrode PCE2 may be disposed closer to an edge of the backplane substrate 110 than the first upper pad electrode PCE1 .

[0176] The first upper pad electrodes PCE1 may be spaced apart from each other by a first interval in the first direction DR1, and the second upper pad electrodes PCE2 may be spaced apart from each other by a second interval in the first direction DR1. The first interval may be equal to (or substantially equal to) the second interval, but the embodiment is not limited to this example.

[0177] The first and second upper pad electrodes PCE1 and PCE2 may be disposed on the planarization layer PLL to overlap the connection electrode CNE in the third direction DR3. The first and second upper pad electrodes PCE1 and PCE2 may contact (e.g., directly contact) a surface (e.g., an upper surface) of the connection electrode CNE. The first and second upper pad electrodes PCE1 and PCE2 may be electrically connected to the first panel pad PD1 via the connection electrode CNE.

[0178] Each of the first upper pad electrode PCE1 and the second upper pad electrode PCE2 may have a width greater than a corresponding width of the first panel pad PD1 and / or a corresponding width of the second panel pad PD2. When the first upper pad electrode PCE1 and the second upper pad electrode PCE2 are wider than the first panel pad PD1 (which may be arranged at a relatively fine pitch), the contact area between the first upper pad electrode PCE1 and the second upper pad electrode PCE2 and the conductive balls CDB of the anisotropic conductive film ACF may be increased, which in turn may improve adhesion reliability.

[0179] The display device 10 may include an anisotropic conductive film ACF that may electrically connect the first panel pad PD1 and the circuit pad CPD of the first circuit board CB1 .

[0180] The anisotropic conductive film ACF may be provided in the first panel pad area PDA1. For example, the anisotropic conductive film ACF may be provided on the planarization layer PLL. The anisotropic conductive film ACF may overlap the first panel pad PD1 and the second panel pad PD2 in the third direction DR3.

[0181] The anisotropic conductive film ACF may include an adhesive layer, and may also include a plurality of conductive balls CDB dispersed in the adhesive layer.

[0182] The adhesive layer may include a resin and may be melted by the application of external heat, or may be hardened in a natural state (or without the application of external heat). Each of the conductive balls CDB may include an elastic core and a conductive layer covering (or surrounding) the core. The core may include an elastic polymer material, for example, a styrene polymer (such as acrylonitrile-butadiene-styrene (ABS), polystyrene (PS), styrene-acrylonitrile (SAN), or acrylonitrile-styrene-acrylate (ASA)) or an acrylic polymer (such as poly(methacrylate) (PMA), poly(methyl methacrylate) (PMMA), poly(ethyl methacrylate) (PEMA), or poly(2-hydroxyethyl methacrylate) (polyHEMA)).

[0183] As part of manufacturing the display device 10, an anisotropic conductive film (ACF) may be applied to the first panel pad area (PDA1), the first circuit board (CB1) may be aligned relative to the first and second upper pad electrodes (PCE1 and PCE2), and the first circuit board (CB1) may be bonded to (or with) the first panel pad area (PDA1) through a press process, for example, using heat. Circuit pads (CPD) of the first circuit board (CB1) may be electrically connected to the first upper pad electrode (PCE1) via conductive balls (CDB).

[0184] As described above, in the display device 10 according to some embodiments, the first and second panel pads PD1 and PD2 may be insulated by the planarization layer PLL in the first panel pad area PDA1, and the upper pad electrodes PCE1 and PCE2 (which may be wider than the first panel pad PD1) may be disposed on the planarization layer PLL. In some embodiments, the contact area between the anisotropic conductive film ACF and the upper pad electrodes PCE1 and PCE2 may be increased, thereby improving adhesion reliability.

[0185] Figure 7 According to the embodiment Figure 1 An enlarged schematic plan view of an example of a portion P1. Figure 8 is a diagram showing a method according to an embodiment of the present invention. Figure 7 Schematic plan view of a first upper pad electrode PCE1 and a second upper pad electrode PCE2.

[0186] Reference Figure 7 and Figure 8 The first upper pad electrode PCE1_1 and the second upper pad electrode PCE2_1 have a combination with Figures 4 to 6 The first upper pad electrode PCE1 and the second upper pad electrode PCE2 are described as having different planar shapes. Except for the difference in planar shape between the first upper pad electrode PCE1_1 and the second upper pad electrode PCE2_1, the first upper pad electrode PCE1_1 and the second upper pad electrode PCE2_1 may be similar to the first upper pad electrode PCE1 and the second upper pad electrode PCE2. Therefore, repeated descriptions will be omitted, and the differences will be described below.

[0187] Each of the upper pad electrodes PCE1_1 and PCE2_1 may include portions having different widths. For example, each of the first upper pad electrode PCE1_1 and the second upper pad electrode PCE2_1 may include portions having different widths. Aside from differences in orientation, the first and second upper pad electrodes PCE1_1 and PCE2_1 may have the same shape. Thus, the first upper pad electrode PCE1_1 will be described as a representative example.

[0188] Each of the first upper pad electrodes PCE1_1 may include a first portion PA1 and a second portion PA2. The first portion PA1 may be a region having a smaller width than the second portion PA2 in, for example, the first direction DR1. The first portion PA1 may be a region overlapping the first panel pad PD1 in the third direction DR3. The first portion PA1 may be formed to have a quadrilateral planar shape when viewed in the third direction DR3 and may have a first width W1 extending in the first direction DR1. The second portion PA2 may be a region extending from the first portion PA1. The second portion PA2 may be formed to have a quadrilateral planar shape when viewed in the third direction DR3 and may have a second width W2 extending in the first direction DR1. The first width W1 of the first portion PA1 may be smaller than the second width W2 of the second portion PA2.

[0189] The first portion PA1 of each of the first upper pad electrodes PCE1_1 may overlap the first panel pad PD1 and the contact hole CNT in the third direction DR3. The second portion PA2 of each of the first upper pad electrodes PCE1_1 may not overlap the first panel pad PD1 in the third direction DR3, and may overlap one or more (e.g., two) second panel pads PD2 in the third direction DR3, the one or more (e.g., two) second panel pads PD2 being adjacent to the first panel pad PD1 in an oblique direction intersecting both the first direction DR1 and the second direction DR2.

[0190] The first portion PA1 of each of the second upper pad electrodes PCE2_1 may overlap the first panel pad PD1 and the contact hole CNT in the third direction DR3. The second portion PA2 of each of the second upper pad electrodes PCE2_1 may include a portion overlapping the first panel pad PD1 in the third direction DR3 and one or more other portions that may not overlap either the first panel pad PD1 or the second panel pad PD2 in the third direction DR3, the second panel pad PD2 being adjacent to the first panel pad PD1 in an oblique direction intersecting both the first direction DR1 and the second direction DR2. The second portion PA2 of each of the second upper pad electrodes PCE2_1 may not overlap the contact hole CNT.

[0191] The first portion PA1 of the first upper pad electrode PCE1_1 and the second portion PA1 of the second upper pad electrode PCE2_1 may overlap with the imaginary line extending in the first direction DR1 in a plan view. The second portion PA2 of the first upper pad electrode PCE1_1 and the second portion PA2 of the second upper pad electrode PCE2_1 may not overlap with the imaginary line extending in the first direction DR1 in a plan view.

[0192] The first upper pad electrode PCE1_1 and the second upper pad electrode PCE2_1 may be arranged in a zigzag pattern in a plan view. The direction in which the first portion PA1 of each first upper pad electrode PCE1_1 protrudes from the second portion PA2 of the corresponding first upper pad electrode PCE1_1 may be opposite to the direction in which the first portion PA1 of each second upper pad electrode PCE2_1 protrudes from the second portion PA2 of the corresponding second upper pad electrode PCE2_1. For example, the direction in which the first portion PA1 of each first upper pad electrode PCE1_1 protrudes from the second portion PA2 of the corresponding first upper pad electrode PCE1_1 may be the second direction DR2, and the direction in which the first portion PA1 of each second upper pad electrode PCE2_1 protrudes from the second portion PA2 of the corresponding second upper pad electrode PCE2_1 may be the opposite direction to the second direction DR2. The direction along which the first portion PA1 of each first upper pad electrode PCE1_1 protrudes from the second portion PA2 of the corresponding first upper pad electrode PCE1_1 can be toward the adjacent side (or edge) of the backplane substrate 110, and the direction along which the first portion PA1 of each second upper pad electrode PCE2_1 protrudes from the second portion PA2 of the corresponding second upper pad electrode PCE2_1 can be toward the display area DA.

[0193] In the case where the direction in which the first portion PA1 of each first upper pad electrode PCE1_1 protrudes from the second portion PA2 of the corresponding first upper pad electrode PCE1_1 is opposite to the direction in which the first portion PA1 of each second upper pad electrode PCE2_1 protrudes from the second portion PA2 of the corresponding second upper pad electrode PCE2_1, the first upper pad electrode PCE1_1 and the second upper pad electrode PCE2_1 can have an increased surface area without contacting each other. In some embodiments, the adhesion area between the anisotropic conductive film ACF and the upper pad electrodes PCE1_1 and PCE2_1 can be increased, thereby improving adhesion reliability.

[0194] Figure 9 According to the embodiment Figure 1 An enlarged schematic plan view of an example of a portion P1. Figure 10 According to the embodiment of the invention Figure 9 A schematic cross-sectional view taken along the section line Q4-Q4'. Figure 11 According to the embodiment of the invention Figure 9 A schematic cross-sectional view taken along the section line Q5-Q5'.

[0195] Reference Figures 9 to 11 , the planarization layer PLL_1 is different from the combined Figures 4 to 8 The planarization layer PLL described. Figures 9 to 11As shown in FIG, the planarization layer PLL_1 overlaps the second panel pad PD2 in the third direction DR3 and does not overlap the first panel pad PD1 in the third direction DR3. Repeated descriptions will be omitted and differences will be described below.

[0196] The planarization layer PLL_1 may be disposed in the first panel pad area PDA1. The planarization layer PLL_1 may be disposed on the second panel pad PD2. For example, the planarization layer PLL_1 may cover the second panel pad PD2. The planarization layer PLL_1 may be spaced apart from the first panel pad PD1 when viewed in the third direction DR3. For example, the planarization layer PLL_1 may not overlap with the first panel pad PD1 in the third direction DR3 and may not cover the first panel pad PD1.

[0197] At least because the planarization layer PLL_1 does not cover the first panel pad PD1 , the contact hole CNT in the planarization layer PLL_1 may be omitted.

[0198] For example, the first and second upper pad electrodes PCE1_1 and PCE2_1 may be disposed on the first panel pad PD1 and the planarization layer PLL_1 to contact (eg, directly contact) the first panel pad PD1.

[0199] The first upper pad electrode PCE1_1 may extend from the first panel pad PD1 onto the planarization layer PLL_1. In some embodiments, the first upper pad electrode PCE1_1 may be disposed on (e.g., directly disposed on) the first panel pad PD1, the first insulating layer INS1, and the planarization layer PLL_1. In this manner, the contact hole CNT may be omitted from the planarization layer PLL_1, thereby simplifying the structure and omitting one or more manufacturing processes.

[0200] The anisotropic conductive film ACF may be formed along the stepped portion of the first upper pad electrode PCE1_1 and may be bent by a press process of bonding the anisotropic conductive film ACF to the first circuit board CB1. The first circuit board CB1 may also be bent along the stepped portion of the first upper pad electrode PCE1_1.

[0201] The second upper pad electrode PCE2_1 may be disposed on the first panel pad PD1 and may not overlap the second panel pad PD2 in the third direction DR3. The second upper pad electrode PCE2_1 may be disposed (e.g., directly disposed) on the first panel pad PD1 and the first insulating layer INS1. The second upper pad electrode PCE2_1 may not overlap the planarization layer PLL_1 in the third direction DR3.

[0202] As described above, at least because the planarization layer PLL_1 is formed not to overlap with the first panel pad PD1 in the third direction DR3 and to overlap with the second panel pad PD2 in the third direction DR3, the contact hole CNT in the planarization layer PL1_1 can be omitted, thereby simplifying the structure and omitting one or more manufacturing processes.

[0203] A method of manufacturing the display device 10 will now be described. The following description will focus on the method of manufacturing the display device 10 in combination with Figure 5 The described structure corresponds to the first panel pad area PDA1.

[0204] Figures 12 to 18 1 are schematic cross-sectional views of the display device 10 at various stages of manufacture according to the embodiment, and will be used to describe a method of manufacturing the display device 10 according to the embodiment.

[0205] Reference Figure 12 , a first panel pad PD1 , a second panel pad PD2 , and a test pad TPD may be formed on the backplane substrate 110 .

[0206] Each of the first panel pad PD1, the second panel pad PD2, and the test pad TPD may be formed to include a first pad electrode PDE1 and a second pad electrode PDE2. For example, the first common connection electrode CCE1 (see FIG. Figure 2 ) The first pad electrode PDE1 is formed through the same process. However, embodiments are not limited to this example, and the first pad electrode PDE1 may be formed through a separate (or different) process from the process of forming the first common connection electrode CCE1. A first insulating layer INS1 may be formed on the backplane substrate 110, and the first insulating layer INS1 may expose the first pad electrode PDE1. The process of exposing the first pad electrode PDE1 may be performed through a CMP process.

[0207] can be connected to the second common electrode CCE2 (see Figure 2 ) The second pad electrode PDE2 is formed by the same process. However, the embodiment is not limited to this example, and the second pad electrode PDE2 may be formed by a process separate from (or different from) the process of forming the second common connection electrode CCE2. The second panel pad PD2 may be electrically connected to the first panel pad PD1, but as Figure 12 As shown in FIG, the second panel pad PD2 may be used as a dummy panel pad and may be spaced apart from the first panel pad PD1 in a view in the third direction DR3. In some embodiments, the test pad TPD may extend from the first panel pad PD1.

[0208] Reference Figure 13, a planarization layer PLL may be formed on the first panel pad PD1 and the second panel pad PD2. The planarization layer PLL may be made of an organic material. However, the embodiment is not limited to this example, and the planarization layer PLL may be made of an inorganic material additionally or alternatively.

[0209] A contact hole CNT exposing a portion of the first panel pad PD1 may be formed in the planarization layer PLL. The contact hole CNT may be formed by an optical process (eg, a photolithography process). Due to the formation of the contact hole CNT, a portion of the second pad electrode PDE2 of the first panel pad PD1 may be exposed.

[0210] Reference Figure 14 A connection electrode CNE may be formed on the planarization layer PLL. The connection electrode CNE may be formed by depositing a connection electrode material on the planarization layer PLL and in the contact hole CNT and polishing the connection electrode material using a CMP process. The connection electrode CNE may be formed to fill the contact hole CNT, and a surface (e.g., upper surface) of the connection electrode CNE may be flush (or substantially flush or coplanar) with a corresponding surface (e.g., corresponding upper surface) of the planarization layer PLL. The connection electrode CNE may be electrically connected to the first panel pad PD1 through the contact hole CNT.

[0211] Reference Figure 15 , a first upper pad electrode PCE1 may be formed on the planarization layer PLL, and a test electrode TD may be formed on the test pad TPD. The first upper pad electrode PCE1 and the test electrode TD may be formed by depositing a metal layer on the backplane substrate 110 and patterning the metal layer using an optical process, such as a photolithography process.

[0212] The first upper pad electrode PCE1 may be formed on (e.g., directly on) the connection electrode CNE and may be electrically connected to the first panel pad PD1 through the connection electrode CNE. The test electrode TD may be formed on (e.g., directly on) the test pad TPD and may be electrically connected to the test pad TPD. A test of the display panel 100 (see FIG. 1 ) may be performed using the test pad TPD and a test jig. Figure 1 ). The test pad TPD may be directly electrically and physically connected to the first panel pad PD1 to perform a drive test of the display panel 100, but the embodiment is not limited to this example. For example, an indirect electrical connection may be used between the test pad TPD and the first panel pad PD1.

[0213] Reference Figure 16 After the driving test is completed, the backplane substrate 110 can be cut into units. As part of the cutting process, the test pads TPD and the test electrodes TD can be cut and removed.

[0214] Reference Figure 17and Figure 18 , an anisotropic conductive film ACF including conductive balls CDB may be applied on the first upper pad electrode PCE1 and the planarization layer PLL. Figure 17 and Figure 18 As shown in FIG, an anisotropic conductive film ACF is applied to the structure on the backplane substrate 110. However, the embodiment is not limited to this example. For example, the anisotropic conductive film ACF may be applied to the first circuit board CB1.

[0215] The first circuit board CB1, having the circuit pads CPD formed thereon, can be aligned relative to the backplane substrate 110. For example, the circuit pads CPD of the first circuit board CB1 and the first upper pad electrode PCE1 can be aligned facing each other in the third direction DR3. The first circuit board CB1 and the backplane substrate 110 can be pressed together using a hot pressing process to bond the first circuit board CB1 to the structures formed on the backplane substrate 110 (e.g., to the first upper pad electrode PCE1). The first upper pad electrode PCE1 and the circuit pads CPD of the first circuit board CB1 can be electrically connected via conductive balls CDB of an anisotropic conductive film (ACF).

[0216] According to various embodiments, a display device 10 (see FIG. Figure 1 The method of bonding the backplane substrate 110 and the first circuit board CB1 together using an anisotropic conductive film (ACF) including conductive balls (CDB) can be used. At least because the bonding method using the anisotropic conductive film (ACF) can be applied in conjunction with forming a relatively high-resolution display device 10 rather than a wire bonding method, the degree of process freedom can be increased.

[0217] Although the case where the test pad TPD and the test electrode TD are formed is shown and described, the embodiment is not limited to this example. For example, the formation of the test pad TPD and the test electrode TD may be omitted.

[0218] The bonding may be fabricated by forming a planarization layer PLL_1 on the second panel pad PD2 instead of on the first panel pad PD1. Figures 9 to 11 The display device 10 described above can thus omit the process of manufacturing the contact hole CNT, which not only reduces the number of manufacturing processes and the associated manufacturing time, but also reduces the cost and complexity of forming the related display device.

[0219] Figure 19 is a schematic perspective view of a virtual reality (VR) device 1 including a display device 10_1 according to an embodiment.

[0220] Figure 19 A VR device 1 is shown, and a display device 10_1 according to an embodiment has been applied as a part of or incorporated into the VR device 1 .

[0221] Reference Figure 19 The VR device 1 according to the embodiment may be a device in the form of glasses. The VR device 1 according to the embodiment may include a display device 10_1, a first lens (e.g., a left lens) 10a, a second lens (e.g., a right lens) 10b, a support frame 20, glasses frame legs 30a and 30b, a reflective member (or structure) 40, and a display device housing 50.

[0222] exist Figure 19 , the VR device 1 including the glasses frame legs 30a and 30b is shown as an example. However, the VR device 1 according to some embodiments may be formed as a head-mounted display including a headband that can be mounted on the user's head instead of the glasses frame legs 30a and 30b. The VR device 1 is not limited to Figure 19 The structure shown in FIG can be applied to various other electronic devices in various forms.

[0223] The display device housing 50 may include a display device 10_1 and a reflective member 40. An image displayed on or via the display device 10_1 may be reflected by the reflective member 40 and provided to the user's right eye through the right lens 10b. The user may view the VR image displayed on the display device 10_1 through their right eye.

[0224] Despite Figure 19 The display device housing 50 is provided at the right end of the support frame 20, but the embodiment is not limited to this structure. For example, the display device housing 50 can be provided at the left end of the support frame 20. The image displayed on the display device 10_1 can be reflected by the reflective member 40 and provided to the user's left eye through the left lens 10a. The user can view the VR image displayed on the display device 10_1 through their left eye. As another example, the display device housing 50 can be provided at both the right end and the left end of the support frame 20. The user can view the VR image displayed on the display device 10_1 through both their left eye and right eye.

[0225] Figure 20 is a schematic perspective view of a smart device 2 including a display device 10_2 according to an embodiment.

[0226] Reference Figure 20 The display device 10_2 according to the embodiment may be applied to a smart watch as a type of smart device 2 or incorporated as a part of the smart watch.

[0227] Figure 21 is a schematic perspective view of a vehicle including a display device according to an embodiment.

[0228] Figure 21A vehicle to which the display device according to the embodiment has been applied or otherwise incorporated is shown.

[0229] Reference Figure 21 According to some embodiments, the display device may be applied to a vehicle instrument cluster 10_a, a vehicle center instrument panel 10_b, or central information displays (CIDs) 10_c, 10_d, and 10_e disposed on and / or incorporated into the vehicle instrument panel. In some embodiments, the display device may be applied to one or more interior (or cabin) mirror displays that replace the vehicle's sideview mirrors and / or rearview mirrors.

[0230] Figure 22 is a schematic perspective view of a transparent display device including a display device 10_3 according to an embodiment.

[0231] Reference Figure 22 The display device 10_3 according to the embodiment can be applied to or form a transparent display device. The transparent display device can transmit light while displaying an image IM. A user located in front of the transparent display device can not only view the image IM displayed on the display device 10_3, but also view an object RS or background located behind the transparent display device. In the case where the display device 10_3 is applied to a transparent display device, a combination of the display device 10_3 and the transparent display device 10_3 is formed. Figure 2 At least one layer (or member) of the described display panel 100 may include a light-transmitting portion that may transmit light or may be made of a material that may transmit light.

[0232] According to various embodiments, by increasing the adhesion area between an anisotropic conductive film and an upper pad electrode forming part of a display device, adhesion reliability can be improved. Using one or more embodiments, a relatively high-resolution display device can be realized in which a pad area and a circuit board are bonded together using an anisotropic conductive film.

[0233] According to some embodiments, at least because the planarization layer can be formed not to overlap the first panel pad and to overlap the second panel pad, one or more contact holes can be omitted, thereby simplifying the structure of the display device and omitting one or more manufacturing processes.

[0234] Although the above embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the disclosed embodiments. Accordingly, the embodiments are to be considered as illustrative rather than restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. A display device, comprising: The substrate comprises a display area and a non-display area, wherein a first panel pad area is provided in the non-display area; first panel pads disposed on the first panel pad area, the first panel pads being spaced apart from each other along a first direction; second panel pads spaced apart from the first panel pads in a second direction intersecting the first direction, the second panel pads being spaced apart from each other along the first direction; a planarization layer disposed on the first panel pad and the second panel pad, the planarization layer comprising contact holes, each contact hole exposing a corresponding first panel pad among the first panel pads; an upper pad electrode disposed on the planarization layer, each of the upper pad electrodes being electrically connected to a corresponding first panel pad among the first panel pads via a corresponding contact hole among the contact holes; a circuit board overlapping the first panel pad area in a third direction perpendicular to the first direction and the second direction, the circuit board including a circuit pad; as well as An anisotropic conductive film is disposed on the first panel pad region and electrically connects each of the upper pad electrodes to a corresponding circuit pad among the circuit pads.

2. The display device according to claim 1, wherein The upper pad electrode includes a first upper pad electrode and a second upper pad electrode spaced apart from the first upper pad electrode in the first direction.

3. The display device according to claim 2, wherein: The first upper pad electrode overlaps one of the first panel pads in the third direction, and The second upper pad electrode overlaps another first panel pad among the first panel pads in the third direction, and the another first panel pad is adjacent to the one first panel pad.

4. The display device according to claim 3, wherein The first upper pad electrode overlaps two second panel pads among the second panel pads in the third direction, and the two second panel pads are adjacent to the one first panel pad, and The second upper pad electrode does not overlap the second panel pad in the third direction.

5. The display device according to claim 2, wherein The first upper pad electrode is disposed closer to the display area than the second upper pad electrode. The display device according to claim 1 , wherein: A corresponding width of the upper pad electrode is greater than a corresponding width of the first panel pad or a corresponding width of the second panel pad.

7. The display device according to claim 1, wherein The first panel pads and the upper pad electrodes are arranged in one-to-one correspondence with each other.

8. The display device according to claim 1, wherein Each of the upper pad electrodes includes a first portion having a first width and a second portion having a second width, the first width being smaller than the second width.

9. The display device according to claim 8, wherein The upper pad electrode includes a first upper pad electrode and a second upper pad electrode, and A direction in which the first portion of the first upper pad electrode protrudes from the second portion of the first upper pad electrode is opposite to a direction in which the first portion of the second upper pad electrode protrudes from the second portion of the second upper pad electrode.

10. The display device according to claim 9, wherein The direction in which the first portion of the first upper pad electrode protrudes from the second portion of the first upper pad electrode is a direction extending toward an adjacent side of the substrate, and A direction along which the first portion of the second upper pad electrode protrudes from the second portion of the second upper pad electrode is a direction extending toward the display area.

11. The display device according to claim 9, wherein The first upper pad electrode overlaps one of the first panel pads in the third direction, The first upper pad electrode overlaps two second panel pads among the second panel pads in the third direction, and the two second panel pads are adjacent to the one first panel pad, and The second upper pad electrode does not overlap the second panel pad in the third direction.

12. A display device, comprising: The substrate comprises a display area and a non-display area, wherein a first panel pad area is provided in the non-display area; first panel pads disposed on the first panel pad area, the first panel pads being spaced apart from each other along a first direction; second panel pads spaced apart from the first panel pads in a second direction intersecting the first direction, the second panel pads being spaced apart from each other along the first direction; a planarization layer, disposed on the second panel pad; an upper pad electrode, disposed on the first panel pad; a circuit board overlapping the first panel pad area in a third direction perpendicular to the first direction and the second direction, the circuit board including a circuit pad; as well as An anisotropic conductive film is disposed on the first panel pad region and electrically connects each of the upper pad electrodes to a corresponding circuit pad among the circuit pads.

13. The display device according to claim 12, wherein: The planarization layer overlaps the second panel pad in the third direction and does not overlap the first panel pad in the third direction.

14. The display device according to claim 12, wherein: Each of the upper pad electrodes directly contacts a corresponding first panel pad among the first panel pads.

15. The display device according to claim 12, wherein: The upper pad electrode includes a first upper pad electrode and a second upper pad electrode spaced apart from the first upper pad electrode in the first direction.

16. The display device according to claim 15, wherein The first upper pad electrode overlaps the planarization layer in the third direction, and The second upper pad electrode does not overlap the planarization layer in the third direction.

17. A method for manufacturing a display device, the method comprising the following steps: forming a first panel pad and a second panel pad on a substrate, the first panel pads being spaced apart from each other along a first direction, the second panel pads being spaced apart from the first panel pad in a second direction intersecting the first direction, and the second panel pads being spaced apart from each other along the first direction; forming a planarization layer on the second panel pad or both the first panel pad and the second panel pad; forming upper pad electrodes on at least the planarization layer, each of the upper pad electrodes being electrically connected to a corresponding first panel pad among the first panel pads; aligning the circuit pads of the circuit board with the upper pad electrodes; as well as An anisotropic conductive film is pressed between the circuit board and the substrate to bond the circuit board and the substrate together and to form corresponding electrical connections between the upper pad electrodes and the circuit pads.

18. The method according to claim 17, wherein forming the planarization layer on both the first panel pad and the second panel pad, The method further includes: forming contact holes in the planarization layer, each of the contact holes exposing a corresponding first panel pad among the first panel pads; and forming connection electrodes in the contact holes, each of the connection electrodes being formed in a corresponding contact hole among the contact holes, and Each of the upper pad electrodes is electrically connected to a corresponding first panel pad among the first panel pads through a corresponding connection electrode among the connection electrodes.

19. The method according to claim 17, wherein In a view in a third direction perpendicular to the first direction and the second direction, the planarization layer does not overlap with the first panel pad, Each of the upper pad electrodes is further formed directly on a portion of a corresponding first panel pad among the first panel pads to form an electrical connection between the upper pad electrode and the corresponding first panel pad.

20. The method according to claim 17, further comprising: forming test pads on the substrate from a same layer of material as that used to form the first panel pads, each test pad being electrically connected to a corresponding first panel pad among the first panel pads; forming a test electrode on the test pad from the same layer of material as that used to form the upper pad electrode; as well as cutting the substrate into at least one unit, The step of cutting the substrate into the at least one unit separates the test pad and the test electrode from the display device.

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