Tunneling over universal serial bus (USB)

Abstract

Some aspects of the present disclosure provide various techniques for tunneling universal serial bus (USB) packets using pass-through techniques in a USB 4 system. The disclosed shoot-through techniques may avoid the use of store-and-forward (SAF) operations to tunnel USB3 packets (e.g., USB 3.2 packets) over a USB4 link, such that latency of the tunneled USB3 packets may be reduced. Further, when tunneling USB3 packets using SAF operations, the disclosed pass-through techniques may reduce the need for a big data buffer in a USB controller / adapter.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to pending U.S. non-provisional application No. 18 / 169,764, filed on February 15, 2023, which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] The technology discussed below relates generally to data communication buses, and more particularly to tunneling data using a communication bus such as a Universal Serial Bus (USB). Background Art

[0004] Computing devices can use various communication protocols and standards to communicate with each other for different applications and functions. Some examples of computing devices include desktop computers, servers, laptops, network entities (e.g., converged or disaggregated base stations), and mobile devices (e.g., smartphones, smartwatches, and tablets). Among them, the Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors, and protocols used for connections and communications between computing devices, peripherals, and other devices.

[0005] USB 4.0 (also known as USB4) is the latest generation of USB standards. USB4 functionally replaces the older USB 3.2 while maintaining parallel operation of the USB 2.0 bus. Enhanced SuperSpeed ​​(SS) USB, as defined in the USB 3.2 specification, remains the architecture for USB data transfer on USB4 connections. In some aspects, a USB4 connection can support multiple high-speed interface protocols, including USB3, DisplayPort, and PCI Express, for efficient data transfer and simultaneous delivery of data, power, and high-resolution video over a single USB Type-C cable. USB4 has a tunneling architecture designed to combine multiple protocols onto a single physical interface (e.g., USB Type-C) so that the total speed and performance of a USB4 connection can be dynamically shared between the protocols. In some aspects, a USB4 connection can tunnel USB 3.2 communications (USB3).

[0006] USB4 introduces the ability to dynamically control bandwidth allocation between various protocols and double the maximum available bandwidth. The USB4 structure is based on Intel's Thunderbolt 3 standard (Thunderbolt TMis a registered trademark of Intel Corporation). The Thunderbolt 3 protocol is USB4's primary method of moving data across its connection, and a USB4 connection can serve as a tunnel for USB3, DisplayPort, and PCIe (Peripheral Component Interconnect Express) signals over the same physical cable. Summary of the Invention

[0007] The following presents an overview of one or more aspects of the present disclosure to provide a basic understanding of these aspects. This overview is not an extensive review of all anticipated features of the present disclosure and is neither intended to identify key or important elements of all aspects of the present disclosure nor to delineate the scope of any or all aspects of the present disclosure. Its sole purpose is to present some concepts of one or more aspects of the present disclosure in a form that serves as a prelude to the more detailed description presented later.

[0008] Various method, system, device, and apparatus embodiments may also include additional features. Some aspects of the present disclosure provide various techniques for tunneling Universal Serial Bus (USB) packets using pass-through techniques in a USB4 system. The disclosed pass-through techniques can avoid using store-and-forward (SAF) operations to tunnel USB3 packets (e.g., USB 3.2 packets) through a USB4 link, such that the latency of the tunneled USB3 packets can be reduced. Furthermore, when using SAF operations to tunnel USB3 packets, the disclosed pass-through techniques can reduce the need for large data buffers in a USB controller / adapter.

[0009] One aspect of the present disclosure provides a device for data communication. The device includes a memory and a universal serial bus (USB) component. The USB component is configured to sequentially receive a plurality of first data packets from a USB link, wherein the plurality of first data packets conform to a first communication protocol and is configured to tunnel second data packets conforming to a second communication protocol different from the first communication protocol. The USB component is further configured to decapsulate a subset of the plurality of first data packets to retrieve a partial payload of the second data packet. The USB host is further configured to store the partial payload of the second data packet decapsulated from the subset of the plurality of first data packets in the memory before receiving all of the first data packets in the plurality of first data packets.

[0010] One aspect of the present disclosure provides a method for performing data communication at a device. The method includes sequentially receiving a plurality of first data packets from a universal serial bus (USB) link. The plurality of first data packets conform to a first communication protocol and are configured to tunnel second data packets conforming to a second communication protocol different from the first communication protocol. The method also includes decapsulating a subset of the plurality of first data packets to retrieve a portion of a payload of the second data packets. The method also includes storing, in a memory, the portion of the payload of the second data packets decapsulated from the subset of the plurality of first data packets before receiving all of the first data packets in the plurality of first data packets.

[0011] One aspect of the present disclosure provides a device for data communication. The device includes a memory and a universal serial bus (USB) component coupled to the memory. A USB host is configured to extract data from the memory to construct a first data packet that complies with a first communication protocol. The USB host is further configured to form one or more second data packets that comply with a second communication protocol different from the first communication protocol. Each of the one or more second data packets includes a payload for tunneling a portion of the first data packet. The USB host is further configured to transmit the one or more second data packets using a USB link before completing the construction of the first data packet.

[0012] These and other aspects of the present disclosure will be more fully understood upon reading the following detailed description. After reading the following description of specific exemplary embodiments in conjunction with the accompanying drawings, other aspects, features, and embodiments will become apparent to those of ordinary skill in the art. Although each feature may be discussed below with respect to certain examples and drawings, all embodiments may include one or more of the advantageous features discussed herein. In other words, although one or more embodiments may be discussed as having certain advantageous features, one or more of such features may also be used according to the various examples discussed herein. In a similar manner, although each example may be discussed below as a device, system, or method embodiment, it should be understood that such examples may be implemented in various devices, systems, and methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic diagram illustrating an exemplary Universal Serial Bus (USB) system according to some aspects of the present disclosure.

[0014] Figure 2 、 Figure 3 and Figure 4 is a schematic diagram illustrating further details of an exemplary USB device according to some aspects of the present disclosure.

[0015] Figure 5is a diagram illustrating an exemplary USB protocol stack according to some aspects of the present disclosure.

[0016] Figure 6 is a diagram conceptually illustrating a USB3 packet being tunneled using multiple USB4 packets in accordance with aspects of the present disclosure.

[0017] Figure 7 is a block diagram of a USB device configured to implement various pass-through techniques to tunnel USB3 packets using USB4 packets, in accordance with aspects of the present disclosure.

[0018] Figure 8 is a diagram illustrating a process of receiving a tunneled USB3 packet using pass-through technology according to some aspects of the present disclosure.

[0019] Figure 9 is a conceptual illustration of some aspects of the present disclosure. Figure 7 An illustration of the memory space of a USB device.

[0020] Figure 10 is a diagram illustrating a process of transmitting tunneled USB3 packets using pass-through technology according to some aspects of the present disclosure.

[0021] Figure 11 is a flow chart illustrating an exemplary method for receiving tunneled data packets according to some aspects of the present disclosure.

[0022] Figure 12 is a flow chart illustrating an exemplary method for transmitting tunneled data packets according to some aspects of the present disclosure. DETAILED DESCRIPTION

[0023] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0024] Although various aspects and specific implementations are described in this application by way of illustration of some examples, it will be understood by those skilled in the art that additional specific implementations and use cases may be generated in many other arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and packaging arrangements. For example, specific implementations and / or uses may occur via integrated chips and other devices based on non-module components (e.g., end-user devices, vehicles, communication equipment, computing equipment, industrial equipment, retail / purchase equipment, medical equipment, AI-enabled devices, etc.). Although some examples may or may not specifically point to use cases or applications, the applicability of various types of the described innovations may occur. Specific implementations may range from chip-level or modular components to non-modular, non-chip-level specific implementations, and further to aggregated, distributed, or OEM devices or systems incorporating one or more aspects of the described innovations. In some actual settings, the devices incorporating the described aspects and features may also necessarily include additional components and features for the implementation and implementation of the claimed and described examples. For example, the transmission and reception of wireless signals necessarily include multiple components for analog and digital purposes (e.g., hardware components including antennas, RF chains, power amplifiers, modulators, buffers, processors, interleavers, adders / summers, etc.). The innovations described herein are intended to be practiced in a variety of devices of different sizes, shapes, and configurations, chip-level components, systems, distributed arrangements, disaggregated arrangements (e.g., base stations and UEs), end-user devices, etc.

[0025] Some aspects of the present disclosure provide various techniques for tunneling Universal Serial Bus (USB) packets using pass-through technology in a USB4 system. The disclosed pass-through technology can avoid using store-and-forward (SAF) operations to tunnel USB3 packets (e.g., USB 3.2 packets) through a USB4 link, so that the latency of the tunneled USB3 packets can be reduced. In addition, when using store-and-forward (SAF) operations to tunnel USB3 packets, the disclosed pass-through technology can reduce the need for large data buffers in the USB controller / adapter.

[0026] Figure 1 1 is a schematic diagram of an exemplary universal serial bus (USB) system 100 according to some aspects of the present disclosure. In some aspects, USB system 100 has a bus architecture that uses the USB4 communication protocol. In some aspects, USB system 100 is a USB4 system that is backward compatible with older USB generations (e.g., USB 2.0 to USB 3.2).

[0027] The USB system 100 may include a USB host 102 connected to a USB hub 104 via a USB link 106. In some aspects, the USB host 102 may be a USB4 host, which may be included in or connected to a processing device or subsystem (e.g., a computer, server, motherboard, controller, mobile phone, etc.). In some aspects, the USB hub 104 may be a USB host connected to one or more USB devices (e.g., a Figure 1 108). The USB hub 104 may also be connected to other types of devices, such as a display or other peripheral devices. The USB hub 104 may be a standalone device or included in another device (e.g., a USB docking station). The USB device 108 may include one or more USB endpoints or functionality. In some aspects, the USB device 108 may be a peripheral device, a memory, or any device connected to the USB host 102 directly or via the USB4 hub 104. In some aspects, the USB host 102 may be a USB4 host capable of supporting 20 or higher Gbps (gigabits per second) USB4 operations (e.g., Gen 2×2, Gen 3×2).

[0028] In some aspects, the USB host 102 may include a USB host router 112, the USB hub 104 may include a USB hub router 114, and the USB device 108 may include a USB device router 116. In a USB4 system, the router may convert tunneled protocol traffic (e.g., USB3 packets) into USB4 packets and route the packets through the USB4 system 100 (e.g., a USB4 fabric including links 106 and 110). Tunneled protocol traffic is tunneled through the USB4 fabric as USB4 packets. An example of tunneled protocol traffic is USB3 traffic (e.g., USB 3.2 traffic). In some aspects, each of the USB host 102, USB hub 104, and USB device 108 may include one or more USB connector ports 118, 120, 122, 124, 126, and 128, respectively. In one example, the USB connector ports may be implemented using USB Type-C connectors for connecting USB-compliant components and for transmitting information and power between the components.

[0029] Figure 2 、 Figure 3 and Figure 41 is a schematic diagram illustrating more details of a USB host 102, a USB hub 104, and a USB device 108, respectively, according to some aspects of the present disclosure. Each of the USB host 102, the USB hub 104, and the USB device 108 has a router (e.g., routers 112, 114, and 116) for routing USB traffic. The routers can distribute and synchronize time throughout the USB system 100 via a time management unit (TMU). For example, the USB host 102 has a TMU 202 ( Figure 2 ), the USB hub 104 has a TMU 302 ( Figure 3 ), and the USB device 108 has a TMU 402 ( Figure 4 The USB host 102 has a host interface adapter 204 that can perform functions related to discovery and configuration of the routers. Each router provides a flat point-to-point configurable switch for routing traffic between various adapters or ports (e.g., between USB3 and USB4 ports or adapters).

[0030] In some aspects, the USB host 102 may include a PCIe (Peripheral Component Interconnect Express) controller 210 ( Figure 2 ). The PCIe controller 210 may include (or be connected to) a PCIe root complex or a PCIe switch complex for controlling PCIe-based routing to one or more peripheral devices. The PCIe controller 210 may be connected to the USB host router 112 via a PCIe adapter 212. In some aspects, the USB hub 104 includes (or is connected to) a PCIe switch 304 via a PCIe adapter 306 (e.g., a PCIe downstream or upstream facing adapter). In some aspects, the USB device 108 may include a PCIe function 404 that is connected to the PCIe controller 210 (see Figure 2 The USB device router 116 may include a PCIe upstream adapter 406 to couple the PCIe function 404 with upstream connected components (such as the PCIe switch 304 of the USB hub 104 and the PCIe controller 210 of the USB host 102).

[0031] In some aspects, the USB host 102 includes an internal enhanced SuperSpeed ​​(SS) host 214 that can provide one or more downstream USB3 ports that can be connected to downstream USB3 protocol adapters (e.g., USB3 adapters 308 and 310). The USB hub 104 includes an internal enhanced SuperSpeed ​​hub (e.g., SS hub 320) that provides one or more upstream USB3 ports and downstream USB3 ports. The upstream USB3 port can be connected to an upstream USB3 protocol adapter (e.g., USB3 adapter 308), which forwards packets to the upstream-facing port of the USB4 hub. The downstream USB3 port can be connected to a downstream USB3 protocol adapter (e.g., USB3 adapter 310), which forwards packets to the downstream-facing port of the USB4 hub.

[0032] Each router (e.g., routers 112, 114, and 116) may include one or more adapters (e.g., PCIe adapters, DisplayPort (DP) adapters, USB3 adapters, etc.). The adapters may provide interfaces between routers (e.g., routers 112, 114, and 116) and external entities or functionality. The USB system 100 may support three types of adapters: protocol adapters, channel adapters, and control adapters. Protocol adapters are used to convert communications or traffic between different protocols to support tunneling. In some aspects, a router may include one or more types of protocol adapters. In one example, the USB host 102 includes two USB3 adapters 216 and 218, a host interface 204, and a PCIe adapter 212. In one example, the USB hub 104 includes two USB3 adapters 308 and 310 and a PCIe adapter 306. In one example, the USB device 108 includes a USB3 adapter 408 and a PCIe adapter 406. In some aspects, the host interface 204 may be a processing device (e.g., Figure 7 The processor 702 provides an interface to access the USB host 102 or the host router 112.

[0033] In some aspects, each router of the USB host 102, USB hub 104, and USB device 108 may include one or more USB4 ports. The USB4 port (an entity in the router) provides a USB4 functional interface residing on each end of a USB4 link or connection (e.g., USB links 106 and 110). The USB4 link includes a USB4 data bus and a two-wire sideband (SB) channel. The USB4 data bus includes a transmit and receive channel. The USB4 link operates as a single-channel link or a dual-channel link (e.g., channel 0 and channel 1). When operating as a single-channel link, one channel of the USB4 port (e.g., channel 1) is disabled. When operating as a dual-channel link, both channels (e.g., channels 0 and 1) are enabled and logically bound together to provide a single data channel. In one example, the host router 112 may include two USB4 ports 220 and 222 ( Figure 2 In one example, the device router 116 may include a USB4 port 410. In some aspects, the hub router 114 may include one or more downstream-facing USB4 ports (e.g., USB4 ports 312 and 314) and an upstream-facing USB4 port (e.g., USB4 port 316). The hub router 114 enables one or more downstream-facing USB4 ports to be serviced by one upstream-facing USB4 port (e.g., for port expansion).

[0034] In the USB system 100, a USB4 link can be the primary communication channel interconnecting two USB4 ports. In some aspects, the USB4 link can transmit data packets for both tunneled protocol traffic and bus management traffic between routers. The sideband channel of the USB4 port can be used to initialize and manage the USB4 link between connected USB4 ports. In one example, a USB4-enabled USB Type-C port includes a USB4 port, a USB 2.0 data bus, and a USB Type-C configuration channel (CC), as well as power and ground.

[0035] In some aspects, the USB hub 104 (e.g., the router 114) can support earlier USB generations or functionality. For example, the downstream-facing ports of the USB hub 104 (e.g., the USB4 ports 312 and 314) can be backward compatible with USB 3.2 devices and USB 2.0 devices. In one example, the USB host 102 can include USB 2.0 functionality provided via a USB 2.0 host 224, which can be connected to a USB 2.0 hub 318 (included in the USB hub 104) and / or USB 2.0 functionality 412 (included in the USB device 108). In some aspects, the USB host 102, the USB hub 104, and the USB device 108 can support 20G (20Gbit / s) USB4 operation (Gen 2×2) or 40G (40Gbit / s) USB4 operation (Gen 3×2). However, it is contemplated that in other aspects, the USB system 100 may achieve higher throughput than 40G (eg, 80G in USB Gen 4).

[0036] Figure 5 5 is a diagram of an exemplary USB protocol stack 500 according to some aspects of the present disclosure. In one aspect, the USB protocol stack 500 may be a USB4 protocol stack including a physical layer 502, which includes an electrical layer 504 and a logical layer 506. The USB protocol stack 500 also includes a protocol adapter layer 510 and a configuration layer 512 located above the transport layer 508.

[0037] The electrical layer 504 defines various electrical signaling characteristics of the USB link, such as scrambling, encoding, jitter, and voltage. The logic layer 506 is responsible for establishing a USB4 link between two routers (e.g., routers 112, 114, and 116) and providing services to send and receive data traffic between the routers. The logic layer 506 further handles traffic to and from the transport layer 508 as a byte stream. The logic layer 506 provides services for establishing and maintaining a USB4 link with a link partner (e.g., another USB-enabled device or peer). Other services provided by the logic layer 506 include, for example, performance scalability (e.g., different data communication speeds and widths), error detection and recovery mechanisms, data scrambling, forward error correction codes, power management, and the like.

[0038] In some aspects, the transport layer 508 forwards tunneled packets (e.g., USB3 packets, DP packets, PCIe packets) and control packets over USB links (e.g., USB links 106 and 110). For example, the transport layer 508 can define packet formats, routing, quality of service (QoS) support, flow control, and time synchronization. Protocol multiplexing (e.g., multiplexing of USB4 and USB3 services) can be further performed at the transport layer 508. The configuration layer 512 performs router configuration tasks and handles incoming control packets. The configuration layer 512 provides an addressing scheme for control packets within the domain, processes control packets, and delivers a reliable transport mechanism for control packets. Control packets provide the connection manager with access to the router's configuration space. The protocol adapter layer 510 performs mapping / conversion between tunneled protocol services (e.g., USB3 services) and USB4 transport layer packets. The protocol adapter layer 510 is defined by the type of tunneled protocol services it transmits and receives, such as a USB3 adapter layer.

[0039] USB4 tunneling

[0040] In some aspects, the USB host 102, USB hub 104, and / or USB device 108 may support tunneling for various protocols, such as USB3 tunneling, PCIe tunneling, and the like. The aforementioned USB3 controllers and adapters may support USB3 Gen T or Gen X tunneling. USB3 Gen T is a USB3 tunneling architecture. A USB3 Gen T path tunnels USB3 traffic between two USB3 Gen T adapters. A USB Gen T port is a port on an internal USB3 Gen T component that supports USB3 Gen T operation. USB3 Gen X is a USB3 tunneling architecture that uses the existing USB 3.2 Enhanced SuperSpeed ​​protocol. A USB3 Gen X path tunnels USB3 traffic between two USB3 Gen X adapters. A USB3 Gen X port is a port on an internal USB3 component that supports USB3 Gen X operation. A USB3 path is a path that tunnels USB3 traffic. This USB3 path may refer to both a USB3 Gen T path and a USB3 Gen X path.

[0041] In some aspects, USB3 packets can be tunneled over a USB4 link between a USB host 102 and a USB device 108 with or without the use of a USB hub 104. A USB3 adapter within each router (e.g., USB3 adapters 216, 218, 308, 310, 408) enables USB3 packets to be tunneled over a USB4 link (e.g., USB link 106 and / or USB link 110). For example, USB3 packets can be tunneled between an enhanced SS host 214 ( Figure 2 USB host 102) and enhanced SS function 414 ( Figure 4 The SS host 214, SS hub 320, and SS function 414 may be referred to as internal USB3 devices in this disclosure. Each internal USB3 device interfaces with the USB3 adapter layer after the link layer. The USB3 adapter encapsulates the local USB3 protocol packets into one or more USB4 transport layer packets (tunneled packets). Each USB4 packet may carry the payload of a tunneled USB3 packet (e.g., a portion of a USB3 packet).

[0042] In some aspects, the tunneling of USB3 traffic (e.g., USB3 packets) over a USB4 link (as payload in one or more USB4 packets) may operate on a USB3 protocol layer (e.g., a USB 3.2 Gen T or Gen X adapter layer) that defines the tunneling and processing of USB3 traffic over a USB4 link. In some examples, store-and-forward techniques may be used to tunnel a USB3 packet as one or more USB4 packets that are forwarded to a destination (e.g., Figure 7 The processor 702, or processing subsystem) is previously reassembled by the downstream USB3 adapter. The USB3 protocol layer may provide specific rules for bandwidth allocation and division for periodic and non-periodic traffic types. In one example, periodic traffic may be limited to approximately 70% of the link bandwidth (BW) for USB Gen T traffic. In one example, periodic traffic may be limited to approximately 90% of the link BW for USB Gen X traffic. In one example, the maximum BW of each periodic endpoint (EP) may be defined in the corresponding endpoint descriptor and its companion. The endpoint descriptor and its companion may contain attributes of the endpoint. Based on these attributes, the maximum BW of the periodic endpoint may be calculated.

[0043] Figure 6 This is a conceptual example of how multiple USB4 packets can be used (e.g. Figure 6, 604-n) is shown. In one example, USB3 packet 600 may be 1024 bytes in size, and each USB4 packet may include a portion of USB3 packet 602 (e.g., a payload of 256 bytes or less) as a payload. The USB4 packets may be sent over a USB4 link and verified for proper reception at a receiver. In some aspects, USB3 tunneling (e.g., USB3 Gen X or Gen T tunneling) may be performed using a multi-port USB3 adapter port capable of concurrently tunneling traffic to and from several USB3 devices. In such cases, to prevent congestion between tunneled USB3 packets to and from different USB3 devices, the USB3 adapter may need to provide a large data buffer to achieve high overall throughput (e.g., 80 Gbps). However, when using store-and-forward (SAF) operation, using a larger buffer may result in increased hardware cost and increased latency for tunneled USB3 traffic.

[0044] Some aspects of the present disclosure provide various techniques for tunneling USB3 packets through a USB4 link using pass-through technology. The disclosed pass-through technology can avoid using store-and-forward (SAF) operations to tunnel USB3 packets through USB4 lines, so that the latency of the tunneled USB3 packets can be reduced. For example, when using SAF, a USB3 controller and / or adapter needs to receive (and store) all USB4 packets carrying the payload of the tunneled USB3 packets before the USB3 packets can be forwarded to the next target (e.g., a processing device or another USB device). In addition, compared to SAF operations, pass-through operations can reduce the need for large data buffers for reducing congestion between USB3 packets of different devices and the costs associated with the large data buffers.

[0045] Figure 7 7 is a block diagram of a USB component 700 that can implement various pass-through techniques to tunnel USB3 packets using USB4 packets according to some aspects. In some aspects, the USB component 700 can be a USB host or a USB device. In one example, the USB component 700 includes a processor 702 that can be coupled to other devices via a system interface 704. In some aspects, the system interface 704 can be a data bus that conforms to an Advanced eXtensible Interface (AXI) bus. It is contemplated that the system interface 704 can be implemented using other bus architectures or parallel / serial interfaces (e.g., PCIe). The processor 702 is coupled to a memory 706 (e.g., Figure 2The USB system 708 enables the USB component 700 to communicate with other devices using a USB link (e.g., a USB4 link). The USB system 708 can be used to implement Figures 1 to 4 Any of the illustrated USB components (eg, USB host 102, USB hub 104, or USB device 108) or any suitable USB-enabled device.

[0046] The processor 702 can transmit data to and receive data from the memory 706 and the USB system 708 via the system interface 704. For example, each device (e.g., the processor 702 or the USB system 708) can communicate with the other device (e.g., the memory 706) by exchanging address, control, and data information over the system interface 704. The USB system 708 may include a data buffer 710 that can be used to buffer and store USB packets received from the USB link.

[0047] In one aspect, the USB system 708 can provide USB3 functionality and USB4 functionality to enable tunneling of USB3 packets (e.g., USB 3.2 packets) using one or more USB4 packets using the pass-through technology described herein. In one example, the USB system 708 can be implemented to include the functionality of a USB3 host and a USB3 adapter (e.g., SS host 214 and USB3 adapter port 216 / 218). In one example, when multiple USB4 packets are used to tunnel USB3 packets, the USB system 708 can receive the USB4 packets sequentially. Using the pass-through technology, the USB system 708 can retrieve the payload of each received USB4 packet (partial USB3 packet) and store it in the memory 706 before all USB4 packets in the USB4 packet used to tunnel the USB3 packet are received or processed. This is different from SAF operation, in which the USB system 708 stores the USB4 packets in the buffer 710 and reconstructs the complete USB3 packet after receiving all tunneled USB4 packets. Using the SAF method, the USB system 708 may forward the complete USB3 packet to the memory 706 / processor 702 .

[0048] Figure 8 8 is a diagram illustrating a process 800 for receiving a tunneled USB3 packet using a pass-through technique according to some aspects of the present disclosure. In one example, the process 800 can be performed using the USB component 700 or any USB-enabled device (e.g., the USB host 102, the USB device 108, etc.).

[0049] At block 802, the USB component 700 may receive a USB4 packet from a USB link (e.g., USB link 106 and / or USB link 110). The USB4 packet may include a payload for tunneling a USB3 packet. When the packet size of the tunneled USB3 packet is no greater than a payload threshold for the USB4 packet (e.g., 252 bytes or less), the USB3 packet may be tunneled using a single USB4 packet. When the size of the USB3 packet is greater than the payload threshold for the USB4 packet, the USB3 packet may be tunneled using two or more USB4 packets (e.g., USB4 packets 604-a, 604-b, 604-c, ..., and 604-n). In this case, each USB4 packet carries a payload corresponding to a portion of the USB3 packet.

[0050] At block 804, the USB component 700 may decapsulate or deconstruct the USB4 packet to retrieve the USB3 packet payload. For example, the USB component may decapsulate the header of the USB4 packet and use this information to obtain the USB3 packet payload encapsulated in the USB4 packet.

[0051] At block 806, the USB component 700 may store the USB3 payload (e.g., the partial USB3 packet) in a memory (e.g., memory 706) that is accessible by a processor (e.g., processor 702) for storing the decapsulated USB3 payload (e.g., the partial USB3 packet) before all tunneled USB4 packets are received. For example, the USB component 700 may store the decapsulated USB3 payload (e.g., the partial USB3 packet) at the USB protocol layer (e.g., Figure 5 The USB3 payload is further processed at an upper layer (e.g., a user application layer or software) above the protocol adapter layer 510. In some aspects, once the USB3 payload is retrieved from the received USB4 packet, the USB system 708 stores the USB3 payload in the memory 706 without buffering the USB4 packet at the USB system. In some aspects, the USB system 708 may temporarily buffer or store some USB4 packets in the buffer 710, but the USB system releases the USB4 packet from the buffer before the complete USB3 packet is received via tunneling.

[0052] In some aspects, the USB component 700 can maintain receipt information for the USB3 payload. For example, the receipt information can indicate the length of the USB3 packet, the location of the portion of the USB3 payload stored in memory, a memory offset for locating the USB3 payload data in memory, and / or a cyclic redundancy check (CRC) for the second data packet. In some aspects, the USB3 payload may not be stored in memory on packet boundaries. Therefore, the USB component 700 can maintain a memory offset for locating the USB3 payload in memory. In some examples, the memory offset can be a page offset of a memory page storing the USB3 payload.

[0053] In some aspects, the CRC can span the entire USB3 packet. In a pass-through approach, when a USB4 packet is received, the CRC is calculated over the portion of the USB3 payload contained in the USB4 packet, and the USB system 708 can maintain intermediate states between packets. When the last USB4 packet arrives, using the intermediate CRC states, the entire CRC can be verified against the entire USB3 payload in the USB3 payload, and the result can be processed and reported as if it were calculated immediately on the complete USB3 packet. Similarly, in the transmit direction, the CRC can be calculated as the USB4 packet is sent, with the intermediate CRC states retained between packets, and then appended to the end of the last tunneled USB4 packet of the USB3 packet.

[0054] In some aspects, the USB system 708 can wait for one or more USB4 packets of the tunneled USB3 payload to complete before storing the decapsulated USB3 payload in the memory 706 in order to align the bus width with the amount of data being sent across the system interface 704. For example, the USB system 708 can decapsulate a number of tunneled USB4 packets so that the amount of decapsulated USB3 payload transmitted across the bus is sized to align with the bus width of the interface. In one example, when the bus width of the system interface 704 is X bytes, the USB system 708 can transmit USB3 payload data via the system interface in multiples of X bytes (e.g., 2X, 3X, ... nX, etc.) in order to align the bus width with each data transfer. Aligning the bus width with the transmitted USB3 payload data can improve the efficiency of the system interface 704 in terms of utilization.

[0055] At box 808, the USB component 700 determines whether all USB4 packets (for tunneling USB3 packets) have been received. If not all expected USB4 packets have been received, the process returns to box 802 to receive more USB4 packets; otherwise, the process goes to box 810. At box 810, after the USB component 700 has received all expected USB4 packets, the USB component 700 (e.g., processor 702) can retrieve and process the complete USB3 packet payload stored in memory 706. For example, the processor 702 can reconstruct the USB3 packet based on the payload data stored in memory 706 by the USB system. Using these pass-through techniques, the USB system 708 can reduce or avoid buffering USB4 packets of tunneled USB3 packets in buffer 710. Instead, partial USB3 packet payloads can be forwarded to memory 706, where the processor 702 can reconstruct the USB3 packet while the USB system continues to receive more USB4 packets. Using pass-through technology, the USB component can start processing (e.g., decapsulating) each received USB4 packet to retrieve the tunneled USB3 payload before all USB4 packets used to tunnel the USB3 packets have been received. In contrast, SAF operation will buffer USB4 packets until all USB4 packets used to tunnel the USB3 packets have been received.

[0056] Figure 9 is a diagram conceptually illustrating a memory space 900 of a USB component 700 according to some aspects. In one example, the memory space 900 may be Figure 7 706, which is different from the buffer memory 710 used to buffer and route USB4 packets at the USB system 708. In some aspects, the memory space 900 can be used by the processor 702 for functions other than USB communication, such as user software or functions above the USB3 protocol layer.

[0057] In some aspects, the USB system 708 can receive USB4 packets to use the above-mentioned Figure 7 and Figure 8The USB3 packets are tunneled using the pass-through operation described above. Without buffering the USB4 packets in a buffer, the USB system 708 can retrieve the USB3 payload from each received USB4 packet and store a portion of the received USB3 payload in the memory space 900. In one example, the USB system 708 can store the first USB3 payload in a first memory location 902, the second USB3 payload in a second memory location 904, the third USB3 payload in a third memory location 906, and the fourth USB3 payload in a fourth memory location 908. Any partitioning can be used to store USB3 payload data in memory locations, regardless of USB4 packet boundaries. For example, the payload of a single USB4 packet can be transferred to several memory locations, or the payloads of several USB4 packets can be transferred to the same contiguous memory location. The USB system 708 can store the USB3 payloads in the memory space 900 without first buffering some or all of the corresponding USB4 packets at the buffer 710. In one example, the memory space 900 can be implemented in a dynamic random access memory (DRAM) or the like.

[0058] The USB component can strategically store USB3 payloads (e.g., portions of USB3 packets) in the memory space 900 for faster access. For example, the USB component 700 can store USB3 payloads in the memory space 900 using a technique that enables the USB component 700 to retrieve the USB3 payloads from the memory 900 using fewer memory access cycles (e.g., read accesses). In one example, the USB3 payloads can be stored in memory locations corresponding to the same row of memory read accesses. As another example, the USB3 payloads can be stored in the memory space 900 using a scatter and gather technique that facilitates reading the USB3 payload data from the memory using fewer memory read cycles.

[0059] Figure 10 The process 1000 of transmitting a tunneled USB3 packet using pass-through technology according to some aspects of the present disclosure is illustrated. In one example, the process 1000 can be performed using the USB component 700 or any USB-enabled device (eg, USB host 102, USB device 108, etc.).

[0060] At block 1002, a USB component may have data to be transferred to another device using a USB connection (e.g., a USB4 link). For example, the processor 702 may load the data to be transferred into a memory 706 accessible by the USB component or any USB controller / adapter.

[0061] At box 1004, the USB component may extract data from the memory to construct one or more USB3 packets, which may be tunneled as one or more USB4 packets via a USB4 link (e.g., USB link 106). The USB component 700 may encapsulate a USB3 payload (e.g., a portion of a USB3 packet) in a USB4 packet. At box 1006, the USB component may construct or form one or more USB4 packets to tunnel the USB3 packet as the payload of the USB4 packet. When the size of the USB3 packet is greater than the payload size of the USB4 packet, the USB component may use two or more USB4 packets to tunnel the USB3 packet. The process of extracting data (USB3 payload data) from the memory to construct the USB3 packet and the process of forming the USB4 packet for tunneling the USB3 packet may occur concurrently. For example, the USB component may begin to form a USB4 packet while the USB component extracts data from the memory to construct the USB3 packet fragment by fragment.

[0062] At block 1008, the USB component may transmit a USB4 packet with a payload (e.g., a partial USB3 packet) to tunnel the USB3 packet. In some aspects, the USB component may transmit the USB4 packet before a complete USB3 packet is constructed and / or all USB4 packets for tunneling the USB packet are formed. When the size of the USB3 packet is greater than the payload threshold of the USB4 packet, the USB3 packet may be tunneled using two or more USB4 packets (e.g., USB4 packets 604-a, 604-b, 604-c ... and 604-n). Using pass-through technology, the USB component may begin transmitting the USB4 packet before all USB4 packets (for tunneling the USB3 packet) are constructed and ready.

[0063] At decision block 1010, the USB component 700 (eg, the USB subsystem 708) may return ( Figure 10 ) to block 1008 to transmit more USB4 packets for the same USB3 packet when the complete USB3 packet has not yet been transmitted or tunneled. Otherwise ( Figure 10 In the "Yes" path in the USB component 700, the USB component 700 can return to block 1004 / 1006 to prepare another USB3 packet to be tunneled as a USB4 packet. Using these pass-through techniques, the USB component can avoid or reduce the need to buffer the USB4 packet of the tunneled USB3 packet in the buffer 710.

[0064] Figure 11is a flow chart illustrating an exemplary process / method 1100 for receiving tunneled data packets according to some aspects of the present disclosure. As described below, some or all of the illustrated features may be omitted in certain implementations within the scope of the present disclosure, and some illustrated features may not be required for all exemplary implementations. In some examples, process 1100 may be performed by Figure 7 In some examples, process 1100 can be performed by any suitable device or component for performing the functions or algorithms described below.

[0065] At block 1102, a USB component may sequentially receive a plurality of first data packets from a USB link. The plurality of first data packets conform to a first communication protocol and are configured to tunnel a second data packet conforming to a second communication protocol different from the first communication protocol. In one example, the first data packet may be a USB4 data packet, and the second data packet may be a USB3 packet. In one example, the USB system 708( Figure 7 ) may provide a component (e.g., USB system 708) for sequentially receiving a plurality of first data packets (e.g., USB4 packets for tunneling USB3 packets) from a USB4 link (e.g., link 106).

[0066] At block 1104, the USB component may decapsulate a subset of the plurality of first data packets to retrieve a portion of the payload of the second data packet. In one aspect, the USB system 708 ( Figure 7 ) may provide means for decapsulating a first data packet (e.g., one or more USB4 packets) to retrieve data corresponding to a portion of the USB3 packet. For example, the USB system 708 may decapsulate or deconstruct each received USB4 packet to retrieve a payload comprising a portion of the USB3 packet. For example, the USB component may decapsulate a header of the USB4 packet and use this information to obtain a USB3 packet payload encapsulated in the USB4 packet.

[0067] At block 1106, the USB component may store in memory a portion of the payload of the second data packet decapsulated from a subset of the plurality of first data packets before receiving all of the first data packets in the plurality of first data packets. Figure 7) can provide means for storing a portion of a payload of a second data packet (e.g., a USB3 packet) in a memory (e.g., memory 706) before receiving all of the first data packets in a plurality of first data packets (e.g., all USB4 tunneled packets). This differs from SAF, in which the USB3 payload is buffered as a USB4 packet in a buffer (e.g., buffer 710). In the present disclosure, the USB3 payload of each USB4 packet is retrieved and stored without waiting for all USB4 packets.

[0068] In some aspects, wherein the first communication protocol comprises a USB4 compliance protocol and the second communication protocol comprises a USB3 compliance protocol, in some aspects, the USB component may maintain receipt information for the second data packet. For example, the receipt information may indicate at least one of: a length of the second data packet; a location of a portion of the payload stored in memory; a memory offset for locating the second data packet in memory; or a cyclic redundancy check of the second data packet.

[0069] In some aspects, the USB component may store a portion of the payload of the second data packet in a memory (e.g., memory 706) before receiving the entire second data packet. In some aspects, the second data packet comprises a USB3 packet, and the plurality of first data packets comprises a plurality of USB4 packets that respectively include payloads for tunneling the USB3 packets without using a store-and-forward technique.

[0070] In some aspects, the USB component may further use the USB4 port to receive a plurality of USB4 packets and forward a portion of the payload of the USB3 packet before receiving all of the plurality of USB4 packets.

[0071] In some aspects, the USB component may further align the size of the portion of the payload of the second data packet with the bus width of the memory.

[0072] In some aspects, the USB component may further receive, in sequence, a plurality of third data packets from the USB link, the plurality of third data packets conforming to the first communication protocol and configured to tunnel fourth data packets conforming to the second communication protocol; and the USB component may further process the plurality of third data packets and the plurality of first data packets based on respective priorities of the plurality of third data packets and the plurality of first data packets.

[0073] Figure 12is a flow chart illustrating an exemplary process / method 1200 for transmitting tunneled data packets according to some aspects of the present disclosure. As described below, some or all of the illustrated features may be omitted in certain implementations within the scope of the present disclosure, and some illustrated features may not be required for all exemplary implementations. In some examples, process 1200 may be performed by Figure 7 In some examples, process 1200 can be performed by any suitable device or component for performing the functions or algorithms described below.

[0074] At block 1202, the USB component may retrieve data from a memory to construct a first data packet that conforms to a first communication protocol. For example, the first data packet may be a USB3 packet that conforms to the USB 3.2 specification. In one aspect, the processor 702 may store data in the memory 706 for constructing the USB3 packet, and the USB system 708 may provide components for retrieving data from the memory 706 to construct the first data packet.

[0075] At block 1204, the USB component may form one or more second data packets that conform to a second communication protocol different from the first communication protocol. Each of the one or more second data packets includes a payload for tunneling a portion of the first data packet. For example, the second data packet may be a USB4 packet that conforms to the USB4 specification. In one aspect, the USB system 708 may provide components for forming one or more second data packets (e.g., USB4 packets). For example, the USB system 708 may encapsulate a first data packet (e.g., a USB3 packet) in one or more second data packets. Each second data packet carries a payload corresponding to a portion of the first data packet (e.g., a portion of a USB3 packet).

[0076] At block 1206, the USB component may transmit one or more second data packets using the USB link before completing construction of the first data packet. In one aspect, the USB system 708 may provide components for transmitting the one or more second data packets (e.g., USB4 packets) to tunnel the USB3 packets.

[0077] In a first aspect, an apparatus for data communication is provided. The apparatus includes a memory and a universal serial bus (USB) component. The USB component is configured to: sequentially receive a plurality of first data packets from a USB link, the plurality of first data packets conforming to a first communication protocol and configured to tunnel second data packets conforming to a second communication protocol different from the first communication protocol; decapsulate a subset of the plurality of first data packets to retrieve partial payloads of the second data packets; and, before receiving all of the plurality of first data packets, store the partial payloads of the second data packets decapsulated from the subset of the plurality of first data packets in the memory.

[0078] In a second aspect, alone or in combination with the first aspect, the first communication protocol comprises a USB4 compliance protocol, and the second communication protocol comprises a USB3 compliance protocol.

[0079] In a third aspect, alone or in combination with the first aspect, the USB component is configured to maintain reception information for the second data packet, the reception information indicating at least one of: a length of the second data packet; a location of a portion of the payload stored in a memory; a memory offset for locating the second data packet in the memory; or a cyclic redundancy check of the second data packet.

[0080] In a fourth aspect, alone or in combination with any one of the first to third aspects, the second data packet includes a USB3 packet, and the plurality of first data packets include a plurality of USB4 packets, each of the plurality of USB4 packets including a payload for tunneling the USB3 packet without using store-and-forward technology.

[0081] In a fifth aspect, alone or in combination with the fourth aspect, the USB component includes: a USB4 port configured to receive multiple USB4 packets; and a USB controller configured to forward a portion of the payload of the USB3 packet before receiving all of the USB4 packets in the multiple USB4 packets.

[0082] In a sixth aspect, alone or in combination with any one of the first to third aspects, the USB component is configured to: make the size of the partial payload of the second data packet consistent with the bus width of the memory.

[0083] In a seventh aspect, alone or in combination with any one of the first to third aspects, the USB component is further configured to: receive a plurality of third data packets in sequence from the USB link, the plurality of third data packets conforming to the first communication protocol and configured to tunnel transmit a fourth data packet conforming to the second communication protocol; and process the plurality of third data packets and the plurality of first data packets in an order based on the respective priorities of the plurality of third data packets and the plurality of first data packets.

[0084] In an eighth aspect, a method for communicating data at a device is provided. The method includes sequentially receiving a plurality of first data packets from a universal serial bus (USB) link, the plurality of first data packets conforming to a first communication protocol and configured to tunnel second data packets conforming to a second communication protocol different from the first communication protocol; decapsulating a subset of the plurality of first data packets to retrieve a portion of a payload of the second data packets; and storing the portion of the payload of the second data packets decapsulated from the subset of the plurality of first data packets in a memory before receiving all of the first data packets in the plurality of first data packets.

[0085] In a ninth aspect, alone or in combination with the eighth aspect, the first communication protocol comprises a USB4 compliance protocol, and the second communication protocol comprises a USB3 compliance protocol.

[0086] In the tenth aspect, alone or in combination with the eighth aspect, the method further comprises: maintaining reception information of the second data packet, the reception information indicating at least one of: the length of the second data packet; the location of the portion of the payload stored in the memory; a memory offset for locating the second data packet in the memory; or a cyclic redundancy check of the second data packet.

[0087] In the eleventh aspect, alone or in combination with any one of the eighth to tenth aspects, the second data packet includes a USB3 packet, and the plurality of first data packets include a plurality of USB4 packets, each of the plurality of USB4 packets including a payload for tunneling the USB3 packet without using a store-and-forward technology.

[0088] In a twelfth aspect, alone or in combination with the eleventh aspect, the method further comprises forwarding a portion of the payload of the USB3 packet before receiving all of the USB4 packets in the plurality of USB4 packets.

[0089] In a thirteenth aspect, alone or in combination with any one of the eighth to tenth aspects, the method further comprises: aligning the size of the portion of the payload of the second data packet with the bus width of the memory.

[0090] In the fourteenth aspect, alone or in combination with any one of the eighth to tenth aspects, the method further includes: receiving a plurality of third data packets in sequence from the USB link, the plurality of third data packets conforming to the first communication protocol and configured to tunnel transmit a fourth data packet conforming to the second communication protocol; and processing the plurality of third data packets and the plurality of first data packets based on their respective priorities.

[0091] In a fifteenth aspect, a device for data communication is provided. The device includes a memory and a universal serial bus (USB) component coupled to the memory. The USB component is configured to: extract data from the memory to construct a first data packet conforming to a first communication protocol; form one or more second data packets conforming to a second communication protocol different from the first communication protocol, each of the one or more second data packets including a payload for tunneling a portion of the first data packet; and transmit the one or more second data packets using a USB link before completing the construction of the first data packet.

[0092] In a sixteenth aspect, alone or in combination with the fifteenth aspect, the first communication protocol comprises a USB3 compliance protocol, and the second communication protocol comprises a USB4 compliance protocol.

[0093] In a seventeenth aspect, alone or in combination with the fifteenth aspect, the USB component is further configured to: extract an initial portion of the first data packet from the memory; and form one or more second data packets using the initial portion of the first data packet.

[0094] In an eighteenth aspect, alone or in combination with the seventeenth aspect, the USB component is further configured to: make the size of the initial portion of the first data packet extracted from the memory consistent with the bus width of the memory.

[0095] In a nineteenth aspect, alone or in combination with any one of aspects fifteen to seventeen, wherein the first data packet comprises a USB3 packet, and the one or more second data packets comprise one or more USB4 packets, the one or more USB4 packets respectively comprising a payload for tunneling the USB3 packet without using a store-and-forward technique.

[0096] In a twentieth aspect, alone or in combination with the nineteenth aspect, the USB component is further configured to transmit at least one of the one or more USB4 packets before completing construction of the USB3 packet.

[0097] Several aspects of data communication systems have been presented with reference to exemplary implementations. As will be readily appreciated by those skilled in the art, various aspects described throughout this disclosure may be extended to other data communication systems, network architectures, and communication standards.

[0098] Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior or preferred over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact with each other. For example, a first object can be coupled to a second object, even if the first object has never been in direct physical contact with the second object. The term "circuitry" is used broadly, and is intended to include both hardware implementations of electronic devices and conductors (wherein these electronic devices and conductors, when connected and configured, enable the performance of the functions described in this disclosure, without limitation as to the type of electronic circuitry) and software implementations of information and instructions (wherein these information and instructions, when executed by a processor, enable the performance of the functions described in this disclosure).

[0099] Figures 1 to 12 One or more of the components, steps, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, step, feature, or function or embodied in several components, steps, or functions. Additional elements, components, steps, and / or functions may also be added without departing from the novel features disclosed herein. Figures 1 to 12 The apparatus, device and / or components illustrated in the can be configured to perform one or more of the methods, features or steps described herein. The novel algorithms described herein can also be effectively implemented in software and / or embedded in hardware.

[0100] It should be understood that the specific order or hierarchy of steps in the disclosed methods is an illustration of exemplary processes. It should be understood that the specific order or hierarchy of steps in these methods may be rearranged based on design preferences. The accompanying method claims present elements of the various steps in a sample order and are not intended to be limited to the specific order or hierarchy presented unless expressly stated herein.

[0101] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Accordingly, the claims are not intended to be limited to the aspects shown herein, but rather to the full scope consistent with the text of the claims, wherein, unless expressly stated otherwise, reference to an element in the singular is not intended to mean "one and only one," but rather "one or more." Unless otherwise specified, the term "some" refers to one or more. A phrase referring to "at least one" of a list of items refers to any combination of those items, including individual members. As an example, "at least one of a, b, or c" is intended to encompass: a; b; c; a and b; a and c; b and c; and a, b, and c. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are or later become known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is expressly recited in the claims. No claim element is to be construed under 35 USC §112(f) unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the phrase “step for.”

Claims

1. A device for data communication, the device comprising: Memory; and Universal Serial Bus (USB) components, The USB component is configured as follows: sequentially receiving a plurality of first data packets from a USB link, the plurality of first data packets conforming to a first communication protocol and configured to tunnel second data packets conforming to a second communication protocol different from the first communication protocol; decapsulating a subset of the plurality of first data packets to retrieve a portion of the payload of the second data packet; as well as The portion of the payload of the second data packet decapsulated from the subset of the plurality of first data packets is stored in the memory prior to receiving all of the plurality of first data packets.

2. The apparatus of claim 1, wherein the first communication protocol comprises a USB4 compliance protocol, and the second communication protocol comprises a USB3 compliance protocol.

3. The apparatus of claim 1 , wherein the USB component is configured to maintain reception information of the second data packet, the reception information indicating at least one of the following: the length of the second data packet; a location of the portion of the payload stored in the memory; a memory offset for locating the second data packet in the memory; or a cyclic redundancy check of the second data packet.

4. The apparatus of claim 1 , wherein the second data packet comprises a USB3 packet, and the plurality of first data packets comprises a plurality of USB4 packets, the plurality of USB4 packets respectively comprising payloads for tunneling the USB3 packets without using a store-and-forward technique.

5. The apparatus of claim 4, wherein the USB component comprises: a USB4 port configured to receive the plurality of USB4 packets; and A USB controller is configured to forward a portion of the payload of the USB3 packet before receiving all of the USB4 packets in the plurality of USB4 packets.

6. The apparatus of claim 1 , wherein the USB component is configured to: The portion of the payload of the second data packet is sized to conform to a bus width of the memory.

7. The apparatus of claim 1 , wherein the USB component is further configured to: sequentially receiving a plurality of third data packets from the USB link, the plurality of third data packets conforming to the first communication protocol and configured to tunnel a fourth data packet conforming to the second communication protocol; and The plurality of third data packets and the plurality of first data packets are processed in an order based on their respective priorities.

8. A method for communicating data at a device, the method comprising: sequentially receiving a plurality of first data packets from a universal serial bus (USB) link, the plurality of first data packets conforming to a first communication protocol and configured to tunnel second data packets conforming to a second communication protocol different from the first communication protocol; decapsulating a subset of the plurality of first data packets to retrieve a portion of the payload of the second data packet; as well as Prior to receiving all of the plurality of first data packets, the portion of the payload of the second data packet decapsulated from the subset of the plurality of first data packets is stored in a memory.

9. The method of claim 8, wherein the first communication protocol comprises a USB4 compliance protocol and the second communication protocol comprises a USB3 compliance protocol.

10. The method according to claim 8, further comprising: Maintaining reception information of the second data packet, the reception information indicating at least one of the following: the length of the second data packet; a location of the portion of the payload stored in the memory; a memory offset for locating the second data packet in the memory; or a cyclic redundancy check of the second data packet.

11. The method of claim 8, wherein the second data packet comprises a USB3 packet, and the plurality of first data packets comprises a plurality of USB4 packets, the plurality of USB4 packets respectively comprising payloads for tunneling the USB3 packets without using a store-and-forward technique.

12. The method according to claim 11, further comprising: The partial payload of the USB3 packet is forwarded before receiving all of the USB4 packets in the plurality of USB4 packets.

13. The method according to claim 8, further comprising: The portion of the payload of the second data packet is sized to conform to a bus width of the memory.

14. The method according to claim 8, further comprising: sequentially receiving a plurality of third data packets from the USB link, the plurality of third data packets conforming to the first communication protocol and configured to tunnel a fourth data packet conforming to the second communication protocol; as well as The plurality of third data packets and the plurality of first data packets are processed based on their respective priorities.

15. An apparatus for data communication, the apparatus comprising: Memory; and a universal serial bus (USB) component coupled to the memory, The USB component is configured as follows: extracting data from the memory to construct a first data packet conforming to a first communication protocol; forming one or more second data packets conforming to a second communication protocol different from the first communication protocol, each second data packet of the one or more second data packets including a payload for tunneling a portion of the first data packet; as well as The one or more second data packets are transmitted using a USB link before completing the construction of the first data packet.

16. The apparatus of claim 15, wherein the first communication protocol comprises a USB3 compliant protocol, and the second communication protocol comprises a USB4 compliant protocol.

17. The apparatus of claim 15, wherein the USB component is further configured to: extracting an initial portion of the first data packet from the memory; and The one or more second data packets are formed using the initial portion of the first data packet.

18. The apparatus of claim 17, wherein the USB component is further configured to: The initial portion of the first data packet fetched from the memory is sized to a bus width of the memory.

19. The apparatus of claim 15, wherein the first data packet comprises a USB3 packet, and the one or more second data packets comprise one or more USB4 packets, the one or more USB4 packets respectively comprising a payload for tunneling the USB3 packet without using a store-and-forward technique.

20. The apparatus of claim 19, wherein the USB component is further configured to: At least one of the one or more USB4 packets is transmitted before completing the construction of the USB3 packet.

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