Instruction execution method and apparatus, electronic device, and readable storage medium

Abstract

Embodiments of the present application provide an instruction execution method and device, electronic equipment and readable storage medium, and relate to the technical field of computers. In the method, for any operation unit in an operation array, in the case of obtaining first data of a target microinstruction from a first data path, a one-time data operation operation is performed on the first data based on second data input along a second data path each time, and the second data is sent to a next operation unit through the second data path. After the one-time data operation operation, the control unit local to the operation unit updates the number of times the first data has been operated. In the case where the number of times the first data has been operated meets a preset number of times condition, a current result of the data operation operation is determined as an execution result of the target microinstruction. In this way, the second data is sequentially passed down between the operation units based on the second data path, and the data required for processing the microinstruction can be shared. Therefore, the overall performance of the scheme is better and the power consumption is lower.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of computer technology, and particularly relate to an instruction execution method and device, electronic equipment and readable storage medium. BACKGROUND

[0002] In an instruction pipeline, microinstructions are obtained by decoding an instruction, and one instruction may obtain multiple microinstructions after decoding. For microinstructions with data dependency, data interaction is involved when they are executed in an operation array. For example, one instruction is split into multiple microinstructions, and one microinstruction defines part of the operands in the instruction. For one microinstruction, the execution result of the microinstruction can be obtained only after the operands defined in the microinstruction are respectively operated with the operands defined in each of the multiple microinstructions.

[0003] Therefore, how to implement the execution of the multiple microinstructions with higher performance and lower power consumption becomes a technical problem to be solved urgently. SUMMARY

[0004] Embodiments of the present application provide an instruction execution method and device, electronic equipment and readable storage medium, which can solve the problem of how to execute microinstructions with higher performance and lower power consumption.

[0005] To solve the above problem, an instruction execution method is disclosed in embodiments of the present application and applied to an operation array, and the method comprises:

[0006] For any operation unit in the operation array, in the case of obtaining first data of a target microinstruction from a first data path, performing a data operation on the first data based on second data input along a second data path each time, and sending the second data to a next operation unit through the second data path;

[0007] After performing the data operation once, a control unit local to the operation unit updates the number of times of operation of the first data once;

[0008] In the case where the number of times of operation meets a preset number of times condition, determining a current result of the data operation as an execution result of the target microinstruction.

[0009] On the other hand, an instruction execution device is disclosed in embodiments of the present application and applied to an operation array, and the device comprises:

[0010] The first processing module is configured to, for any operation unit in the operation array, in a case where first data of a target micro instruction is obtained from a first data path, perform a data operation operation on the first data based on second data input along a second data path each time, and send the second data to a next operation unit through the second data path.

[0011] The updating module is configured to update, by a control unit local to the operation unit, a number of times of operation on the first data after the data operation operation is performed once.

[0012] The first determining module is configured to determine, in a case where the number of times of operation meets a preset number condition, a current result of the data operation operation as an execution result of the target micro instruction.

[0013] In another aspect, an electronic device is disclosed, which comprises a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is configured to store executable instructions, and the executable instructions make the processor execute the foregoing method.

[0014] The embodiment of the present application also discloses a readable storage medium, which stores executable instructions, and when executed by one or more processors, makes the processor execute the method as described above.

[0015] The embodiment of the present application has the following advantages: for any operation unit in the operation array, in a case where first data of a target micro instruction is obtained from a first data path, a data operation operation is performed on the first data based on second data input along a second data path each time, and the second data is sent to a next operation unit through the second data path. After the data operation operation is performed once, a number of times of operation on the first data is updated by a control unit local to the operation unit. In a case where the number of times of operation meets a preset number condition, a current result of the data operation operation is determined as an execution result of the target micro instruction. In this way, the second data is sequentially passed down based on the second data path between the operation units, and the data required for processing the micro instruction can be shared, so that the operation of one GATHER instruction can be completed by obtaining the required data from the physical register heap only once. Therefore, the overall performance of the scheme is better and the power consumption is lower. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative labor.

[0017] Figure 1 is a data rearrangement diagram in the prior art;

[0018] Figure 2 is a step flow chart of an instruction execution method provided by an embodiment of the present application;

[0019] Figure 3 is a data transfer diagram provided by an embodiment of the present application;

[0020] Figure 4 is another data transfer diagram provided by an embodiment of the present application;

[0021] Figure 5 is an operation array diagram provided by an embodiment of the present application;

[0022] Figure 6 is a processing procedure diagram provided by an embodiment of the present application;

[0023] Figure 7 is another processing procedure diagram provided by an embodiment of the present application;

[0024] Figure 8 is another processing procedure diagram provided by an embodiment of the present application;

[0025] Figure 9 is another processing procedure diagram provided by an embodiment of the present application;

[0026] Figure 10 is another processing procedure diagram provided by an embodiment of the present application;

[0027] Figure 11 is a processing diagram of an operation unit provided by an embodiment of the present application;

[0028] Figure 12 is a generation diagram of a selection signal provided by an embodiment of the present application;

[0029] Figure 13 is a selection diagram provided by an embodiment of the present application;

[0030] Figure 14 is a block diagram of an instruction execution device provided by an embodiment of the present application;

[0031] Figure 15 is a structural diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0032] With reference to the drawings and the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0033] First, the application scenarios involved in the embodiments of the present application are described. Taking a permutation instruction as an example, when the network on chip processes an instruction, the decoding may generate multiple micro instructions (Micro Operation, UOP). Among them, the permutation instruction can also be called a data query instruction, and the permutation instruction is an instruction for rearranging vector data according to rules, for example, a GATHER instruction in a vector instruction extension instruction set (RVV) for performing permutation operation on data in a vector register. The GATHER instruction can include a vrgather.vv instruction and a vrgatherei16.vv instruction, and the instruction formats thereof are vrgather.vv vd, vs2, vs1 and vrgatherei16.vv vd, vs2, vs1 respectively.

[0034] The instructions in the RVV set the vector configuration register (VTYPE CSR) using an independent vector configuration instruction. The vector configuration register is a register defined in the RVV for controlling the vector configuration, and the VTYPE register includes a vector length multiplier (LMUL) field and a selected element width (SEW) field. Among them, LMUL and SEW are both 3 bits, SEW is used to specify the bit width of the operand of the vector instruction, and LMUL is used to specify the number of vector registers of the operand of the vector instruction. The vector register is a user programmable register defined in the RVV, and 32 vector registers are defined in the RVV for user use.

[0035] In the RVV instruction set, the vector register numbers in a vector instruction use LMUL consecutive vector registers. For example, the instruction "vrgather.vv v24, v8, v16" when LMUL = 8, the vs1 register group of the instruction contains 8 vector registers v16~v23, the vs2 register group contains 8 vector registers v8~v15, and the vd register group contains 8 vector registers v24~v31. For the GATHER instruction, the data in the vs1 register group can be regarded as an index vector, the data in the vs2 register group can be regarded as a data table vector, and the data in the vd register group can be regarded as a destination vector. The maximum number of elements represented by a single vector register number that a vector instruction can operate on can be represented as VLMAX. Where VLMAX = VLEN x LMUL / SEW, VLEN represents the vector register length (Vector LENgth) in bits. DLEN represents the data path length (Datapath LENgth) in a specific implementation in bits. DLEN is the maximum bit width of data that an operation unit in a specific implementation obtains from a data path in bits. DLEN can be the same as or different from VLEN, but DLEN is always able to multiply and divide VLEN. If VLEN / DLEN = n, the data of a vector register can be delivered to the operation unit through n data paths. Usually, DLEN determines the number of microinstructions that a vector instruction is split into. In most implementations, DLEN is equal to VLEN.

[0036] Specifically, the vrgather.vv instruction is a data rearrangement instruction in vector extension for batch querying values of an index vector in a data table vector. The bit width of a single index element in the vs1 register group of the vrgather.vv instruction, the bit width of a single data element provided by the vs2 register group, and the bit width of a single destination element provided by the vd register group are specified by SEW in VTYPE. For example, when SEW is 32, the bit widths of the index element, the data element, and the vd register group are all 32 bits, one vector register in the vs1 register group includes VLEN / SEW index elements, the vs1 register group includes VLEN x LMUL / SEW index elements, and all the index elements included in the vs1 register group constitute an index vector. One vector register in the vs2 register group includes VLEN / SEW data elements, the vs2 register group includes VLEN x LMUL / SEW data elements, and all the data elements included in the vs2 register group constitute a data table vector. One vector register in the vd register group includes VLEN / SEW data elements, the vd register group includes VLEN x LMUL / SEW destination elements, and all the destination elements included in the vd register group constitute a destination vector.

[0037] The function of the vrgather.vv instruction is to query the data elements in vs2 using the index elements in vs1, and store the query results in vd corresponding to the positions of vs1. The elements in vd, vs2 and vs1 are divided into a plurality of elements in SEW, and vd[i], vs2[i] and vs1[i] represent the i-th element in the vd register group, the i-th element in the vs2 register group and the i-th element in the vs1 register group respectively, in the case of vs1[i]>=VLMAX, the value of vd[i] is set to 0, otherwise, the value of vd[i] is set to vs2[vs1[i]].

[0038] Taking vrgather.vv v6,v2,v4 as an example, VLEN=128, SEW=32, LMUL=2, Figure 1 is a data rearrangement schematic diagram shown by an embodiment of the present application, as Figure 1 shown, the vs1 register group (v4 and v5) includes 8 index elements: vs1[0]~vs1[7], and the specific values of vs1[0]~vs1[7] are 1, 8, 7, 19, 2, 3, 0 and 5 respectively. The vs2 register group (v2 and v3) includes 8 data elements: vs2[0]~vs2[7], and the specific values of vs2[0]~vs2[7] are 10, 32, 54, 76, 98, BA, DC and FE respectively. Then, when executing the instruction, each index element in v4 and v5 is used to find the element in the corresponding position in the v2 and v3 registers, and in this example, since vs1[1] and vs1[3] satisfy the condition of >=VLMAX, the corresponding elements vd[1] and vd[3] in the destination register group of vs1[1] and vs1[3] are both set to 0. The positions of vd[0], vd[2], vd[4], vd[5], vd[6] and vd[7] are filled with the specific values of vs2[1], vs2[7], vs2[2], vs2[3], vs2[0] and vs2[5] respectively: 32, FE, 54, 76, 10 and BA.

[0039] The vrgatherei16.vv instruction is a special version of the vrgather.vv instruction, which fixes the bit width of the index element in the vs1 register group as 16 bits, and SEW is only used to specify the data bit width in the vs2 and vd register groups. Corresponding to the vrgatherei16.vvv6,v2,v4 instruction when VLEN=128, SEW=32, and LMUL=2, according to the principle that the number of register numbers operated in the RISC-V specification satisfies the principle that the number of elements is equal, the continuous vector register represented by the register number v6 has a total of 8 elements, and the continuous vector register represented by the register number v4 contains 8 elements. In this example, v4 includes 128 / 16=8 elements, and therefore, vs1[0]~vs1[7] are included in v4, that is, only the register group represented by the register number v4 includes the register v4. The execution manner of the vrgatherei16.vv instruction is the same as that of the vrgather.vv instruction, which will not be described herein again.

[0040] As can be known from the above examples, each index vector needs to look up LMUL indexed vs2 registers, and thus the more the LMUL is, the more the lookups are. In the embodiment of the present application, for one GATHER instruction, multiple UOPs can be generated, and the number of index elements, data elements and destination elements defined in one UOP is the same, for example, the number of index elements, data elements and destination elements defined in one UOP is the number of data elements included in a single vs2 register. For example, for the vrgather.vv v6, v2, v4 instruction in the above example, two UOPs 0 and 1 can be generated, and the operands defined in UOP 0 are v4, v2 and v6, and the operands defined in UOP 1 are v5, v3 and v7, that is, the index elements defined in UOP 0 are 4 elements included in v4, and the data elements are 4 elements included in v2, and after the corresponding elements are looked up from the vs2 register group by taking the values of the 4 index elements in v4 as indexes, the values of the 4 destination elements in v6 register are obtained, that is, the execution result is obtained. Correspondingly, the execution result can be written back to complete the execution of the UOP. That is, in the embodiment of the present application, the UOP can be split according to DLEN as granularity, so that the number of UOPs obtained by instruction decoding can be reduced, and thus the UOP counting circuit can be simplified and the execution efficiency can be improved. It should be noted that any UOP split by the instruction only includes one data table vector, one index vector and one result vector. However, each index element needs to query LMUL indexed vs2 registers, or each data element needs to be queried by LMUL indexed vs1 registers. The number of UOPs split by this splitting manner is small, but data transmission between UOPs is needed to complete the operation.

[0041] In the existing implementation method, only one element query is completed per cycle operation, and when SEW is small, for example, SEW=8, in the above example, 32 rounds of operations are needed to obtain all the required elements from the memory storing vs2, and the processing efficiency is low. How to conveniently and efficiently implement the execution of the multiple UOPs becomes the key to affecting the execution efficiency of the GATHER instruction which is a commonly used instruction. For example, in one related technology, multiple operation units that do not transfer data to each other execute the UOPs split by the GATHER instruction. In this way, in the instruction decoding stage, the combination of any index in the vs1 register and any data in the vs2 register needs to be implemented in the operation unit at the same time by splitting multiple UOPs, that is, one UOP is needed between each group of vs1 register and vs2 register. Thus, one GATHER instruction needs to split up to (VLEN / DLEN x LMUL) 2one UOP (LMUL when DLEN = VLEN) 2 Assuming that there are 2 operation pipelines available in a specific implementation, DLEN is equal to VLEN, and LMUL is the maximum value 8, up to 32 UOPs need to be executed by each pipeline to complete the execution of all 64 UOPs, and then complete the execution of one GATHER instruction, so the execution efficiency of this scheme is low. At the same time, in this way, the registers in each vs1 or vs2 register group need to be read by up to 8 UOPs, and repeated reading of the same data also leads to high power consumption of this method.

[0042] Therefore, an embodiment of the present application provides an instruction execution method.

[0043] Referring to Figure 2 , a step flowchart of an instruction execution method provided by an embodiment of the present application is shown, which can be applied to an operation array, as shown in Figure 2 , the method can specifically include the following steps:

[0044] Step 101, for any operation unit in the operation array, in the case of obtaining target micro-instruction first data from a first data path, performing a data operation operation with the first data based on second data input along a second data path each time, and sending the second data to a next operation unit through the second data path.

[0045] Step 102, after performing one data operation operation, updating the number of operations of the first data by a control unit local to the operation unit.

[0046] Step 103, in the case where the number of operations meets a preset number condition, determining the current result of the data operation operation as the execution result of the target micro-instruction.

[0047] Wherein, the method can be specifically applied to an electronic device including the operation array. After the UOP in the instruction pipeline passes through the renaming unit, the dispatch unit, the emission unit, and the physical register heap, it enters the operation array, and the UOP is executed by the operation unit in the operation array. In the embodiment of the present application, the operation array includes a plurality of operation units, and the number of operation units included in the operation array can be set as needed, which is not limited in the embodiment of the present application. Further, the plurality of operation units adopt a preset connection mode, for example, the plurality of operation units can be connected in series, or the plurality of operation units can be interconnected, for example, each operation unit is connected with other operation units, which is not limited in the embodiment of the present application.

[0048] The target microinstruction is a microinstruction obtained by decoding a target instruction, which is the data query instruction described above. When the microinstruction is executed using an operation unit, a source operand defined in the microinstruction, i.e., the first data described above, is input to the operation unit. Specifically, the first data can be actively acquired by the operation unit, or can be issued by a processing unit in the electronic device responsible for providing the operand. For example, the first data can be issued by a control unit located outside the operation unit. Assuming that one GATHER instruction generates four UOPs, each of the four operation units processing the four UOPs obtains the first data defined in one of the four UOPs.

[0049] The first data path is a data transmission path connecting the physical register file and each operation unit in the operation array, which is used to obtain the first data defined in each microinstruction obtained by decoding the target instruction from the physical register file and deliver it only to the operation unit related to the order of the microinstruction entering the operation array split from the same instruction. The second data path is a data transmission path connecting the physical register file and each operation unit in the operation array, which is used to obtain the second data defined in each microinstruction obtained by decoding the target instruction from the physical register file and share it in the operation array in turn through the delivery of the operation units in the operation array. Specifically, the next operation unit and the microinstruction processed by the operation unit are obtained by decoding the same instruction. For the operation unit processing one target microinstruction split from the target instruction, the second data from the second data path is delivered to the next operation unit, so that each operation unit can obtain the second data defined in other UOPs belonging to the same MOP as the microinstruction processed by the operation unit. In this way, each second data used for operation only needs to be obtained from the physical register file once to complete the operation of one instruction, and the data path does not need to send the second data defined in other UOPs to each operation unit multiple times. Therefore, the overall power consumption of the scheme is lower.

[0050] In the method of the present application, only one GATHER instruction needs to be split into VLEN / DLENxLMUL UOPs, without splitting into (VLEN / DLENxLMUL) 2 UOPs, reducing the number of microinstruction splitting. In the case of LMUL being 2, 4 and 8 when DLEN=VLEN is usually the case, compared with the method in the related art, 2, 12 and 56 UOPs are reduced respectively, and the number of UOPs is significantly reduced when LMUL is large, so the overall efficiency of the scheme is higher.

[0051] In the embodiment of the present application, each operation unit is locally provided with a control unit (referred to as a local control unit), which is responsible for recording the number of times of querying the second data by the first data, i.e., the number of times of operation. The local control unit can use an iteration counter to record the number of times of operation. The initial value of the number of times of operation is 0, and updating the number of times of operation can be adding 1 to the current value of the number of times of operation, so as to realize the statistics of the queried second data. Referring to the foregoing example, for the microinstruction generated by the GATHER instruction, the index element of the microinstruction needs to be used to query the data elements defined in the microinstruction and the data elements defined in other microinstructions, i.e., multiple queries are needed to obtain the query results corresponding to the index element of the microinstruction. Compared with the mode in which the data path sends the second data defined in other UOPs to the operation unit multiple times, and then the operation unit writes back the current result as the execution result under the control of the total control unit, in the embodiment of the present application, the number of times of operation is maintained by the local control unit, and whether the current query is completed can be conveniently determined based on the number of times of operation. The execution result is directly obtained and written back when the preset number condition is met, which can further improve the overall execution efficiency to a certain extent.

[0052] Specifically, if the number of times of operation meets the preset number condition, it is determined that the current query is completed, and accordingly, the current result of the data operation operation can be determined as the execution result of the target microinstruction. Conversely, if the number of times of operation does not meet the preset number condition, it is determined that the current query is not completed, and accordingly, the second data transmitted subsequently can be continued to be waited for and used to continue the data operation operation. The data operation operation can be a query operation.

[0053] In summary, in the instruction execution method provided by the embodiment of the present application, for any operation unit in the operation array, in the case that the first data of the target microinstruction is obtained from the first data path, a data operation operation is performed based on the second data input along the second data path each time, and the second data is sent to the next operation unit through the second data path. After the data operation operation is performed once, the number of times of operation of the first data is updated by the control unit locally arranged in the operation unit. In the case that the number of times of operation meets the preset number condition, the current result of the data operation operation is determined as the execution result of the target microinstruction. In this way, the second data is sequentially transmitted downward between the operation units based on the second data path, and the data required for processing the microinstruction can be shared, so that the operation of one GATHER instruction can be completed by obtaining the required data from the physical register heap only once. Therefore, the overall performance of the scheme is better and the power consumption is lower.

[0054] And in the embodiment of the application, the number of operations is maintained by the local control unit, and the data operation is ended directly when the number of operations meets the preset number condition, the execution result is obtained, the result write-back can be performed in time, and the overall execution efficiency can be further improved, thereby improving the overall processing performance.

[0055] Optionally, the embodiment of the application further comprises:

[0056] In step S21, the second data sent by the operand providing unit is received by the entry operation unit; wherein, the operand providing unit sends the second data defined in the microinstruction to the entry operation unit in the case that one data query instruction is received every time, and sends the first data defined in the microinstruction to the operation units in the operation array based on the first data channel according to the order of unit numbers.

[0057] The entry operation unit can be a predefined operation unit. The operand providing unit is directly connected with each operation unit through the first data channel. When the first data is sent in the order of unit numbers from small to large, the entry operation unit is the operation unit with the smallest unit number. When the first data is sent in the order of unit numbers from large to small, the entry operation unit is the operation unit with the largest unit number. That is, in the embodiment of the application, the entry operation unit is the operation unit that starts processing the microinstruction obtained by decoding the target instruction earliest, and the microinstruction obtained by decoding the target instruction that is emitted earliest enters the operation unit for processing first.

[0058] The operand providing unit includes a physical register stack. For the processing scenario of the GATHER instruction, the operand providing unit specifically includes a vector physical register stack, and the operation array is a GATHER array. In this way, the operand providing unit has the ability to provide the first data and the second data. In the embodiment of the application, the target microinstruction is the microinstruction obtained by decoding the data query instruction. Correspondingly, the operand providing unit will allocate the microinstruction to the operation units in the operation array in the order of unit numbers from small to large every time one microinstruction of the data query instruction is received, and input the first data of the allocated microinstruction to the operation units. The microinstruction is the target microinstruction of the operation unit. For the i-th UOP obtained by decoding the target instruction, the first data defined in the i-th UOP is read from the physical register stack and sent to the j-th operation unit. Wherein, j represents the order of receiving the i-th UOP. In the case of sequential emission, j=i. In the case of out-of-order emission, j does not necessarily equal to i. At the same time, the second data of all the microinstructions obtained by decoding the data query instruction is uniformly transmitted from the entry operation unit. That is, the operand providing unit inputs the second data to the entry operation unit first, and transmits the second data from the entry operation unit to the next operation unit inside the operation array.Figure 3 is a data transfer schematic diagram provided by an embodiment of the present application, as shown in Figure 3 The first data of D1 bits defined in the i-th UOP of the target instruction can be read from the vector physical register stack first, and then transferred to the operation unit j. Figure 4 is another data transfer schematic diagram provided by an embodiment of the present application, as shown in Figure 4 The second data of D2 bits defined in the i-th UOP of the target instruction can be read from the vector physical register stack first, and then transferred to the entry operation unit.

[0059] D1 represents the total length of all index elements included in the first data, and D2 represents the total length of all data elements included in the second data, i.e. the data bit width used by each operation unit in each round of operation. For the vrgather.vv instruction, D1=D2=DLEN. For the vrgatherei16.vv instruction, since the element bit width of the index vector of the vrgatherei16.vv instruction and the element bit width of the data table vector can be inconsistent, and the RISC-V specification restricts that the data table vector and the index vector of the vrgatherei16.vv instruction each contain at most 8 vector registers, therefore, the data transfer process can be split according to the longer vector in the data table vector and the index vector, i.e. D1 and D2 can not be equal. Specifically, the division principle of the total size of the index elements and the total size of the data elements carried in a UOP split by the GATHER instruction is: the maximum bit width of the total size of the index elements or the total size of the data elements carried by each UOP reaches DLEN, and the number of index elements carried is equal to the number of data elements.

[0060] For the vrgatherei16.vv instruction, assuming VLEN=DLEN=128, SEW=64, LMUL=8, the data vector length of the vrgatherei16.vv instruction is VLEN*LMUL=1024 bits, and the index vector length is VLEM*LMUL / 64*16=256 bits. Each split UOP carries two data elements (128 bits in total) and two index elements (32 bits in total). For the GATHER instruction, the bit width of the data element is SEW, and the bit width of the index element is EEW. In the vrgatherei16.vv instruction, EEW=16, and in the vrgather.vv instruction, EEW=SEW. Then D1=EEW<SEW?DLEN / (SEW / EEW):DLEN, that is, if EEW is less than SEW, D1 is determined as DLEN / (SEW / EEW). Otherwise, if EEW is not less than SEW, D1 is determined as DLEN. D2=EEW>SEW?DLEN / (EEW / SEW):DLEN, that is, if EEW is greater than SEW, D2 is determined as DLEN / (EEW / SEW). Otherwise, if EEW is not greater than SEW, D2 is determined as DLEN. Assuming SEW=64 and EEW=16, D1=DLEN / (64 / 16)=DLEN / 4, and D2=DLEN.

[0061] For different values of SEW and EEW, the sizes of D1 and D2 can be as shown in Table 1:

[0062]

[0063] Table 1

[0064] Assuming that the operation array includes 8 operation units connected in series: operation unit 0 to operation unit 7. Figure 5 is a schematic diagram of an operation array provided by an embodiment of the present application, as Figure 5 shown, the operation array is connected to the vector physical register file through three independent data paths. Among them, the first data path and the second data path are respectively used to obtain data from the vector physical register file, and the third data path is used to write back data to the vector physical register file. The first data can be stored in the first buffer, the second data is stored in the second buffer, and the current result of the data operation is stored in the third buffer. There is only a second buffer between the operation units that can pass data to the second buffer of the next operation unit, and there is no data path between the other buffers.

[0065] Suppose that a GATHER instruction is decoded to obtain UOP0-UOP1, and UOP0 and UOP1 are successively issued, then UOP0 and UOP1 are successively assigned to operation unit 0 and operation unit 1 for processing. That is, in the embodiment of the present application, for a microinstruction obtained by decoding a target instruction, the operation units in the operation array are successively assigned from the operation unit with the smallest unit number according to the issuing order of the microinstruction. Correspondingly, the operand providing unit inputs the first data defined in UOP0 to operation unit 0 through the first data path, and inputs the second data defined in UOP0 to operation unit 0 through the second data path. After one or several periods (varying due to different operand ready conditions), the operand providing unit inputs the first data defined in UOP1 to operation unit 1 through the first data path, and inputs the second data defined in UOP1 to operation unit 0 (the entry operation unit) through the second data path. The second data defined in UOP0 is input to operation unit 1 from the second buffer of operation unit 0.

[0066] wherein the data path bit width of the first data path, the second data path and the third data path is DLEN. It should be noted that LMUL MAX represents the maximum value of LMUL supported by a specific implementation, and the maximum number of UOPs obtained by decoding a GATHER instruction can be represented as VLEN / DLEN×LMUL MAX Therefore, VLEN / DLEN×LMUL MAX operation units need to be set in the operation array to ensure that the operation array can meet the processing requirements of any GATHER instruction. Exemplarily, LMUL MAX may be 8, and accordingly, the number of operation units can be 8 in the case of DLEN=VLEN.

[0067] By setting two data paths for input and one data path for output, the first data and the second data can arrive in the same clock cycle, and the operation result can be written back using the third data path in the same clock cycle, so that the operation efficiency is higher. Of course, only one data path for reading and writing can be set to transmit data, and one data path for reading and writing is used to complete the reception of the first data, the reception of the second data and the writing of the third data in multiple periods, which is not limited in the embodiment of the present application. By setting DLEN=VLEN, the number of operation units in the operation array can reach the minimum unit number LMUL MAX , and the operation array can reach the maximum throughput of 1 / LMUL MAX GATHER instructions with LMUL MAX , and the operation performance is higher. If LMUL MAX= 8, DLEN is half of VLEN, then 16 operation units are needed, and the throughput of the operation array becomes 1 / 16 GATHER instructions of LMUL = 8 per cycle. In this way, the hardware circuit size cannot be reduced, but the operation efficiency is halved, and the operation performance is lower.

[0068] In the embodiment of the present application, for all micro-instructions split from a data query instruction, the second data that needs to be shared is uniformly sent into the operation array from the entry operation unit, so that the second data of each micro-instruction is sequentially passed down from the entry operation unit. The second data defined by each micro-instruction is always passed to the entry operation unit and then to the next operation unit, ensuring that each operation unit in the operation array can obtain the second data defined by all micro-instructions split from a data query instruction, and further ensuring that the micro-instructions are executed correctly. The second data input along the second data path includes the second data defined in all UOPs obtained by decoding the target instruction.

[0069] Optionally, the embodiment of the present application further includes that a unit state bit is arranged in the operation unit.

[0070] In step S31, the control unit sets the unit state bit to a first value when the first data is received, and restores the unit state bit to a second value after detecting that the number of operations meets the preset number condition; the first value represents that the operation unit is in an activated state, and the second value represents that the operation unit is in an inactivated state.

[0071] Correspondingly, the above sending the second data to the next operation unit through the second data path includes: in the case that the unit state bit is the first value, sending the second data to the next operation unit through the second data path.

[0072] The unit state bit in each operation unit is 1 bit. The first value can be 1 and the second value can be 0. Correspondingly, for any operation unit, if the operation unit obtains the first data, i.e., the UOP enters the operation unit to start execution, the local control unit of the operation unit sets the unit state bit to 1 to represent that the operation unit enters the activated state. The default value of the unit state bit is 0, which represents that no micro-instruction is executed in the operation unit. Further, after updating the number of operations of the first data once, if the number of operations meets the preset number condition, the unit state bit is restored to 0 to represent that the operation unit exits the activated state.

[0073] If the unit status bit is the second value, it means that all the second data defined in the UOPs split from the target instruction have passed through the operation unit, i.e. have been transmitted to the next operation unit by the operation unit. Therefore, each operation unit can transmit the second data to the next operation unit only when the unit status bit is the first value, i.e. in the active state. In this way, unnecessary transmission operations can be avoided.

[0074] Optionally, the operand providing unit directly transmits the second data defined in the micro instruction to the entry operation unit when the micro instruction has the same instruction sequence number as the instruction sequence number carried by the last transmitted micro instruction (i.e. the sequence number used to uniquely indicate the MOP corresponding to the micro instruction), i.e. both carry the instruction sequence number of the target instruction (indicating that the micro instruction and the last transmitted micro instruction are obtained by the same instruction decoding). When the micro instruction has a different instruction sequence number from the last transmitted micro instruction (indicating that the micro instruction and the last transmitted micro instruction are obtained by different instruction decoding), if the unit status bit of the entry operation unit is the second value, the second data defined in the micro instruction is transmitted to the entry operation unit. In this case, if the unit status bit of the entry operation unit is the first value, it means that the entry operation unit has not completed the processing of the UOP in the target instruction. Therefore, the transmission of the second data defined in the UOP obtained by the new instruction decoding can be continued after the unit status bit of the entry operation unit is the second value, i.e. the entry operation unit is idle. In this way, the conflict can be avoided. That is, the micro instruction is received from the entry operation unit when the micro instruction has a different instruction sequence number from the last transmitted micro instruction.

[0075] In the first implementation, the first data is an index element defined by a first source operand of the target micro instruction, and the second data is a data element defined by a second source operand of the target micro instruction. Accordingly, in this mode, the transmission of the second data to the next operation unit through the second data path includes only transmitting the second data to the next operation unit through the second data path. In this implementation, one data element group (i.e. a group of data elements) defined by the second source operand of a micro instruction is stored in the second buffer each time, i.e. the data element group is shared along the second data path each time. In this way, each operation unit processing the UOP obtained by the target instruction decoding obtains the group defined by all the micro instructions obtained by the target instruction decoding. In this mode, the amount of data to be transmitted is smaller.

[0076] In the second implementation, the first data is a data element defined by a second source operand of the target microinstruction, and the second data is an index element defined by a first source operand of the target microinstruction. Accordingly, in this mode, the sending of the second data to the next operation unit through the second data path includes sending the second data, a current operation result of the data operation, and the number of operations to the next operation unit through the second data path.

[0077] In this implementation, the second buffer stores an index element group defined by a first source operand of a microinstruction each time, and each time the second data is shared along the second data path, the current operation result of the data operation and the number of operations maintained by the control unit (which is equivalent to the control signal maintained by the local operation unit) are obtained from the third buffer first. The index element group, the current operation result, and the number of operations are sent to the next operation unit. This ensures that each operation unit can hold the data required for data query in each clock cycle. The next operation unit can be an operation unit with a number one greater than that of the operation unit.

[0078] In actual application scenarios, the index element group, the current operation result, and the number of operations have more than DLENx2 bits of data, while the data vector group has only DLEN bits of data. Therefore, in the first implementation, the amount of data to be transmitted is less, thereby reducing the hardware circuit and power consumption.

[0079] Optionally, the step of performing a data operation on the first data and the second data input along the second data path each time includes:

[0080] In step 1011, for each received second data, a query operation is performed on each data element in the second data based on each index element in the first data to obtain a query result corresponding to each index element.

[0081] In step 1012, the query result corresponding to each index element is written into a destination element corresponding to each index element in a destination buffer.

[0082] Specifically, one index element in the first data can be used to query the plurality of data elements in the second data to obtain a query result corresponding to the index element. Denote the index element as vs1[i], if vs1[i]>=VLMAX, the query result corresponding to the index element is 0, and the final query result corresponding to the index element is obtained by the query operation. If vs1[i] is less than VLMAX, and the second data received this time includes vs2[vs1[i]], the query result this time is the final query result corresponding to the index element. Otherwise, the query result this time is the temporary query result corresponding to the index element. Correspondingly, the query result of vs1[i] can be written into vd[i] in the destination buffer. The destination buffer is the third buffer described above.

[0083] In the embodiment of the present application, the second data defined in each micro instruction obtained by decoding the target instruction is passed through each operation unit processing the micro instruction obtained by decoding the target instruction. Therefore, the query is performed each time to ensure that the second data defined in each micro instruction obtained by decoding the target instruction can be queried, and the correctness of the query is ensured.

[0084] It should be noted that in the embodiment of the present application, after obtaining the final query result corresponding to the index element, the index element is set with a queried identifier. For example, a queried state bit is set for each index element, and after obtaining the final query result corresponding to the index element, the queried state bit of the index element is set to 1 to set the index element with a queried identifier. The queried state bit is 0 by default. Correspondingly, the operation of querying the plurality of data elements in the second data based on the index element is performed when the index element is not set with a queried identifier. In this way, the correct query result is prevented from being covered, and the problem of inaccurate instruction execution result is solved.

[0085] Further, in the second implementation manner, when the index element group is transmitted, the queried state bit of each index element is synchronously transmitted to the next operation unit. The operation unit writes the received current operation result and the number of operations into the third buffer and the local control unit respectively, and writes the queried state bit of each index element into the local control unit. Then, based on the queried state bit of each index element in the second data being 0, a query operation is performed on the plurality of data elements in the first data respectively, to obtain the query result corresponding to each index element; and the query result corresponding to each index element is written into the destination element corresponding to each index element in the third buffer. After that, the number of operations and the queried state bit of each index element are updated. Then, the second data, the destination element (i.e. the current operation result) in the third buffer, the number of operations and the queried state bit of each index element are sent to the next operation unit.

[0086] Optionally, in the case that the number of operations satisfies the preset number condition, the current result of the data operation is determined as the execution result of the target microinstruction, and specifically includes:

[0087] In the case that the number of operations satisfies the preset number condition, each destination element in the destination buffer is read as the execution result of the target microinstruction.

[0088] Correspondingly, the embodiment of the present application further includes: step S41, writing back the execution result to the physical register stack through the third data path.

[0089] In the embodiment of the present application, if the number of operations satisfies the preset number condition, it indicates that all the data elements defined in the microinstructions obtained by decoding the target instruction have been queried, and the value of each destination element in the destination buffer is the final query result. Therefore, each destination element in the destination buffer can be taken as the execution result of the target microinstruction.

[0090] Further, the third data path connects each operation unit and the vector physical register stack. The execution result can be written back through the third data path, i.e. written back to the vector physical register stack, to complete the execution of the target microinstruction.

[0091] In the embodiment of the present application, in the case that the number of operations satisfies the preset number condition, each destination element in the destination buffer is read as the execution result of the target microinstruction. The execution result is written back to the physical register stack through the third data path. In this way, the final query result can be written back to the physical register stack, and the accuracy of the execution result is ensured.

[0092] Optionally, the embodiment of the present application further includes:

[0093] Step S51: Calculate the sum of the number of operations already performed and the data length of the second data to obtain the length already queried.

[0094] Step S52: If the length of the query reaches the total length of the second source operand of the data arrangement instruction, determine that the number of operations performed meets the preset number condition.

[0095] The length of the second data can be the sum of the lengths of the multiple data elements included in the second data. For example, assuming that a second data set includes 4 data elements, and each data element is 32 bits, then the sum of the lengths of the second data sets is 128 bits. It should be noted that when using the second implementation method described above and passing the index element group, the product of the number of operations and the sum of the lengths of the first data set (i.e., the sum of the lengths of the multiple data elements included in the first data set) is used as the length of the query.

[0096] The total length of the second source operand of the data arrangement instruction can be represented as LMUL × VLEN. Let n represent the number of operations performed, and D2 represent the sum of the lengths of the second data. Then, D2 × n represents the length queried. Accordingly, if D2 × n = LMUL × VLEN, then the number of operations performed satisfies the preset number condition, which can be expressed as n = LMUL × VLEN / D2. Further, if D2 × n = LMUL × VLEN, it means that the index elements have been used to query all data elements defined in the microinstructions decoded from the target instruction; therefore, it can be determined that the preset number condition is satisfied.

[0097] In this embodiment of the invention, the length of the query is calculated based on the number of operations already performed, and the current condition of whether the preset number of operations is met can be determined based on the length of the query and the total length of the second source operand. This method has high efficiency.

[0098] In this embodiment of the invention, the index element group in the first buffer of each operation unit only queries the currently stored data element group in the second buffer within that operation unit, and stores the current query result (i.e., the current result of the data operation) in the third buffer. In this embodiment of the invention, the query process in each operation unit can be completed within one clock cycle. The number of operations recorded by the local control unit of each operation unit can characterize how many rounds the index element group in the first buffer within that operation unit has queried the data element group in the second buffer.

[0099] Taking the `vrgather.vv v24,v8,v16` instruction with DLEN=VLEN and LMUL=8 as an example, in this `vrgather.vv` instruction, v24~v31 are the VD register group, v8~v15 are the vs2 register group, and v16~v23 are the vs1 register group. This instruction decodes to obtain UOP0~UOP7. In UOP0, the first data is the index element represented by the data in register v16, the second data is the data element represented by the data in register v8, and the destination element is the element in register v24. In UOP1, the first data is the index element represented by the data in register v17, the second data is the data element represented by the data in register v9, and the destination element is the element in register v25. In UOP2, the first data is the index element represented by the data in register v18, the second data is the data element represented by the data in register v10, and the destination element is the element in register v26. In UOP3, the first data is defined as the index element represented by the data in register v19, the second data is the data element represented by the data in register v11, and the destination element is the element in register v27. In UOP4, the first data is defined as the index element represented by the data in register v20, the second data is the data element represented by the data in register v12, and the destination element is the element in register v28, and so on. In UOP7, the first data is defined as the index element represented by the data in register v23, the second data is the data element represented by the data in register v15, and the destination element is the element in register v31. That is, the vs1 and vs2 register groups of this instruction are passed sequentially to the arithmetic array in eight rounds. And since DLEN=VLEN, each round passes exactly one element from each of the vector registers in the vs1 and vs register groups into the arithmetic array.

[0100] Figure 6 This is a schematic diagram of a processing procedure provided by an embodiment of the present invention, such as... Figure 6 As shown, in the first round, the data in register v8 of the vs2 register group is used as the second data of UOP0 and stored in the second buffer of operation unit 0. The data in register v16 of the vs1 register group is used as the first data of UOP0 and stored in the first buffer of operation unit 0. Operation unit 0 enters the active state. At the same time, a query operation is performed in operation unit 0 (i.e., using the index element in register v16 to query the data element in register v8). The result of this operation (represented by v24 (v8)) is stored in the third buffer. The content stored in the third buffer can also be called the result vector. The control unit in operation unit 0 updates the number of operations to 1 (not shown in the figure), indicating that the index element of operation unit 0 has completed a query of the data vector. In this example, the result of destination register v24 has completed the query of the data element in v8.

[0101] Figure 7 is another processing procedure schematic diagram provided by the embodiment of the present application, as shown in Figure 7 the second round starts (i.e. reaches the next clock cycle), only the operation unit 0 is in the active state, and the data in the second buffer of the operation unit 0 is sent to the second buffer of the operation unit 1 for storage. The data in the v9 register is stored in the second buffer of the operation unit 0 as the second data of the UOP1, the data in the v17 register is stored in the first buffer of the operation unit 1 as the first data of the UOP1, and the operation unit 1 also enters the active state. In the second round, the two active operation units respectively complete the respective query operations (the query operation is performed on the data elements in the v9 register using the index elements in the v16 register, and the query operation is performed on the data elements in the v8 register using the index elements in the v17 register), and the results are stored in the respective third buffers. At the same time, the control units in the operation units 0 and 1 respectively update the operation times to 2 and 1 (not shown in the figure). The updated operation times indicate that the operation units 0 and 1 have respectively completed the query operations on the data elements in the v8~9 and v8.

[0102] Figure 8 is another processing procedure schematic diagram provided by the embodiment of the present application, as shown in Figure 8 the third round starts (i.e. reaches the next clock cycle), the operation units 0 and 1 are in the active state, and the data in the second buffers of the operation units 0 and 1 is respectively sent to the second buffers of the operation unit 1 and the operation unit 2 for storage. The data in the v10 register is stored in the second buffer of the operation unit 0 as the second data of the UOP2, the data in the v18 register is stored in the first buffer of the operation unit 2 as the first data of the UOP2, and the operation unit 2 also enters the active state. In the third round, the three active operation units respectively complete the respective query operations (the query operation is performed on the data elements in the v10 register using the index elements in the v16 register, the query operation is performed on the data elements in the v9 register using the index elements in the v17 register, and the query operation is performed on the data elements in the v8 register using the index elements in the v18 register), and the results are stored in the respective third buffers. At the same time, the control units in the operation units 0, 1 and 2 respectively update the operation times to 3, 2 and 1 (not shown in the figure). The updated operation times indicate that the operation units 0, 1 and 2 have respectively completed the query operations on the data elements in the v8~10, v8~9 and v8.

[0103] Figure 9 is another processing procedure schematic diagram provided by the embodiment of the present application, as shown in Figure 9As shown, when the eighth round is reached, the data in the v15 register is stored in the second buffer of operation unit 0 as the second data of UOP7, the data in the v23 register is stored in the first buffer of operation unit 7 as the first data of UOP7, and all the eight operation units in the operation array are activated. In the eighth round, operation unit 0 completes its query operation (querying the data elements in the v15 register using the index elements in the v16 register) and stores the result in the third buffer of operation unit 0. At this time, the control unit of operation unit 0 records that the number of operations is 8 (not shown in the figure), i.e., the query of the data elements in the v8~15 registers has been completed, i.e., the number of operations meets the preset number condition. Therefore, the control unit of operation unit 0 restores the unit state bit to 0 and transfers each destination element in the third buffer of operation unit 0 to the vector physical register stack for storage. In the next round, if no new microinstruction enters the operation array, operation unit 0 will exit the activated state.

[0104] Figure 10 is another processing process schematic diagram provided by an embodiment of the present application, as shown in Figure 10 In the ninth round, since no new microinstruction enters the operation array, no data in the data register enters operation unit 0. However, the operation units in the activated state in the last round still transfer the data in the second buffer to the next operation unit. It should be noted that, in this example, operation unit 7 has no next operation unit, and therefore the data in the second buffer in this unit is directly overwritten by the data transferred by operation unit 6. In the case where operation unit 0 that completes the operation in the eighth round exits the activated state, the data in the three buffers becomes invalid, and the data in the first buffer, the second buffer and the third buffer in operation unit 0 can be emptied.

[0105] In the ninth round, operation unit 1 completes its query operation (querying the data elements in the v15 register using the index elements in the v17 register) and stores the result in the third buffer of operation unit 1. At this time, the control unit of operation unit 1 records that the number of operations is 8 (not shown in the figure), i.e., the query of the data elements in the v8~15 registers has been completed, i.e., the number of operations meets the preset number condition. Therefore, the control unit of operation unit 1 restores the unit state bit to 0 and transfers each destination element in the third buffer of operation unit 1 to the vector physical register stack for storage. In the next round, if no new microinstruction enters the operation array, operation unit 1 will exit the activated state. In this way, after another six rounds, i.e., after a total of 15 rounds of operation, the operation of one vrgather.vv instruction can be completed.

[0106] Figure 11Figure 1 is a schematic diagram of a processing unit according to an embodiment of the present application. Figure 11 As shown in Figure 1, the processing unit can first initialize the number of operations to 0. If there is no first data entering the processing unit, the processing unit continues to wait for one clock cycle and then continues to judge. If there is first data entering the processing unit, the processing unit receives second data transmitted on the second data path. The second data can come from a vector physical register stack or from a previous processing unit. The processing unit performs a query operation based on the first data and the second data. Then, the processing unit adds 1 to the number of operations. Then, the processing unit judges whether a preset number condition is met. If the preset number condition is met, the processing unit writes back the destination element in the third buffer to the vector physical register stack and continues to wait for one clock cycle and then continues to judge. If the preset number condition is not met, the processing unit sends the second data in the second buffer to a next processing unit and receives newly entered second data. In the embodiment of the present application, the processing array only needs to read the first data and the second data each once in groups, so as to obtain all the operation numbers required by the UOP. After the UOP operation is completed, the processing array only needs to store the result in the vector physical register stack once in groups. In this way, the number of times of occupying the read-write port of the vector physical register stack is only proportional to LMUL, and thus the influence on the execution of other instructions is smaller. The second data defined in the microinstruction obtained based on the target instruction decoding successively pass through each processing unit. It should be noted that, for one processing unit, the three operations of performing a query operation, sending the second data to a next processing unit, and receiving the second data sent by a previous processing unit can be completed in one clock cycle or in multiple clock cycles, and the embodiment of the present application does not limit this.

[0107] For one vrgatherei16.vv instruction, LMUL / SEW*EEW index vector registers and LMUL data table vector registers are required to participate in operation, and LMUL vector registers are generated as a result. In the embodiment of the present application, D1-bit index elements and D2-bit data elements are transmitted to the processing array in each clock cycle. After LMUL cycles of operation (the number of cycles is equal to the number of UOPs obtained by instruction splitting), D2-bit target elements can be output to the vector physical register stack in each clock cycle, and the operation on the instruction is completed after LMUL cycles of continuous transmission.

[0108] In the embodiment of the present application, the second data of different instructions sent to the first UOP of the operation array all enter from the entry operation unit and participate in the operation. In the embodiment of the present application, the operation array can complete the calculation of the GATHER instruction in linear time complexity proportional to LMUL, which is more efficient. Specifically, a round represents a clock cycle, operation unit 0 receives data and starts operation in the first round, completes operation in the LMULth round, and can receive new microinstructions for operation in the LMUL+1th round. Similarly, operation unit i starts operation in the i+1th round, completes operation in the LMUL+i round, and can receive new microinstructions for operation in the LMUL+i+1th round. That is, the operation array does not need to wait for all microinstructions of the current instruction to complete operation, and can start receiving microinstructions decoded from operation unit 0 for the next instruction when operation unit 0 is in an inactive state. Therefore, the processing efficiency is higher. Moreover, the operation array can start operation when only part of the index vector and part of the data table vector required by one operation unit are received, without waiting for all index vectors and data table vectors to enter the operation unit, or without waiting for all data table vectors to enter the operation unit before operation. Therefore, the processing efficiency can be further improved.

[0109] Exemplarily, assuming that 8 UOPs decoded from the current processing instruction 1 are processed, one UOP decoded from instruction 2 is sent to operation unit 0 to start processing after operation unit 0 exits the active state. In the subsequent period, other operation units will complete the execution of the UOPs decoded from instruction 1 in turn, and exit the active state in turn. Accordingly, in the subsequent period, the second data defined in the UOP decoded from instruction 2 can be directly sent from operation unit 0. That is, in the subsequent period, the UOP decoded from instruction 2 can be directly sent to each operation unit in the order of the unit number for execution by the operation unit. It is ensured that instruction 2 can be normally executed.

[0110] It should be noted that in the case of 4 UOPs decoded from the GATHER instruction, 4 consecutive units can be used, that is, in the embodiment of the present application, the number of units is set to LMUL MAX The number of operation units included in the operation array can ensure that the operation array can adapt to processing any GATHER instruction. In the embodiment of the present application, a plurality of operation arrays can also be set for the number of UOPs generated by decoding the GATHER instruction. Assuming that the GATHER instruction decoding can generate 2, 4, and 8, the operation arrays including 2, 4, and 8 can be set. For any GATHER instruction, the corresponding number of operation arrays is used to start execution from the operation unit with the smallest unit number, which is not limited in the embodiment of the present application.

[0111] Further, in the embodiment of the present application, in order to facilitate display, three buffers are used to store the index vector, the data table vector and the result vector respectively. In actual application, one buffer can be used to meet the requirements of storing the index vector and the operation result, that is, the third buffer is the same as the first buffer. For the index element in the buffer, after obtaining the final query result corresponding to the index element, the final query result (i.e. the queried destination element) of the index element is used to cover the index element, so that the index pair which has obtained the final query result is no longer valid for subsequent operation. In this way, by reusing the buffer storing the index element to store the operation result, the area of the storage unit in the operation unit can be reduced. For example, the size of each buffer is DLEN. In the case of setting three buffers, the storage space requirement of each operation unit is DLEN*3. By reusing, in the case of setting only two buffers, the storage space requirement of each operation unit is reduced to DLEN*2.

[0112] In the embodiment of the present application, a plurality of operation units are connected to form an operation array to accelerate the calculation of the GATHER instruction. The first data of D1 bits and the second data of D2 bits are sequentially and in pairs sent in the operation array through a data path. The first data of D1 bits and the second data of D2 bits in pairs can be simultaneously sent into the operation unit, or can be sent into the operation unit in different clock cycles, which is not limited in the embodiment of the present application. Both D1 and D2 are not greater than DLEN. The first data of D1 bits defined in different UOPs are sequentially sent into the memory of the operation unit in the corresponding order according to the order of receiving the UOP, and at the same time, the operation unit is marked to enter an active state. The second data of D2 bits is stored in the memory of the first operation unit. When new paired data enters the operation array, the operation unit in the active state will transfer the second data in the second buffer thereof to the next operation unit. At the same time, all the operation units in the active state use the index element in the internal thereof to perform a query operation on the data element entering the operation unit, and the operation result is stored in the third buffer in the operation unit as a temporary result. At the same time, each operation unit records and updates the number of operations n, and when the preset number condition D2*n=VLEN*LMUL is met, it is determined that the complete query operation in the operation unit is completed, and the result in the third buffer is written back to the vector physical register stack.

[0113] Optionally, the query operation is performed on the plurality of data elements in the second data based on each index element in the first data respectively to obtain a query result corresponding to each index element, and specifically includes:

[0114] Step 1011a, for any index element in the first data, based on the number of data elements, the index element is divided into a first index component, a second index component and a third index component in the order from low to high;

[0115] Step 1011b, in the case that the third index component is 0 and the second index component is equal to the microinstruction sequence number of the target microinstruction, a selection signal is generated based on the first index component; a target data element is selected from the data elements of the second data based on the selection signal as the query result corresponding to the index element.

[0116] Step 1011c, in the case that the third index component is not 0 and / or the second index component is not equal to the microinstruction sequence number, the query result corresponding to the index element is set to 0.

[0117] Wherein, the microinstruction sequence number is the UOP number of the target microinstruction, indicating that the microinstruction is the first microinstruction in the plurality of microinstructions decoded from the target instruction. The first index component, the second index component and the third index component can be referred to as low index, middle index and high index. That is, for an index element in the first buffer, it includes three parts of high index, middle index and low index.

[0118] Specifically, the step of dividing the index element into a first index component, a second index component and a third index component based on the number of data elements in the order from low to high can be executed in the case that the queried state bit of the index element is not 1. The bit width of the low index is determined by the number of data elements (i.e. the number of data elements included in the second data (second buffer)). Assuming that the total size of the data elements defined in a UOP is DLEN, then the number of data elements is DLEN / SEW. Accordingly, the bit width Width low of the low index is log2(DLEN / SEW). Assuming that DLEN=128 and SEW=32, then the bit width of the low index is log2(128 / 32)=2. Assuming that DLEN=128 and SEW=16, then the bit width of the low index is log2(128 / 16)=3.

[0119] Accordingly, the low Width low of the index element can be taken as the first index component, i.e. the 0th bit to the Width low bit is taken as the first index component. The Width low +1th bit to the Width low +1+rth bit of the index element is taken as the second index component. Wherein, r represents the middle index bit width Width middle=log2(VLEN / DLEN×LMUL MAX The portion of this index element excluding the first and second index components is taken as the third index component. That is, the high-order index width is Width. high =max(EEW-Width low Width middle The value is determined by ,0). The high-order index width may be 0. When the high-order index width is 0, the third index component is considered to always be equal to 0. For example, when VLEN=DLEN=256, SEW=8, EEW=8, Width... low =log2(DLEN / SEW)=4,Width middle =log2(VLEN / DLEN×8)=4, at this time Width high =0.

[0120] For the i-th UOP derived from the target instruction, the first data defined in the i-th UOP is the index element included in the i-th index vector, and the second data defined in the i-th UOP is the data element included in the i-th data table vector. If VLEN=DLEN, the i-th UOP will obtain the i-th VLEN bit data from both the data table vector and the index vector. Accordingly, when the i-th UOP enters the arithmetic array, the i-th index vector and the i-th data table vector are sent into the arithmetic array.

[0121] Assume the middle index and the low-order index are INDEX. MID INDEX LOW According to the index bit width rule, INDEX LOW The value can be 0 to 2^WIDTH LOW -1 corresponds to the index of all elements in a data table vector (i.e., a second set of data). Where 2^WIDTH LOW WIDTH represents 2 LOW The power of 2^WIDTH LOW -1 indicates WIDTH of 2. LOW The power of 1 minus 1. Therefore, the low-order index can be converted into a one-hot code as a selection signal. When the index element is less than VLMAX, the data element corresponding to that index element is at the INDEX position. MID In a data table vector. Therefore, the index element is less than VLMAX and the UOP number and INDEX are... MID If they are equal, it means that the intermediate index component represents the INDEX-1. MID Each data table vector exists in the second buffer. Conversely, when the UOP number and INDEX... MID If they are not equal, it means that the intermediate index component represents the INDEX-1.MID The data table vector does not exist in the second buffer. At this time, the query result corresponding to the index element can be directly set to 0.

[0122] In the case of UOP sequential emission, the queried number of times is equal to the UOP number of the UOP. In the case of UOP out-of-order emission, the queried number of times is not equal to the UOP number of the UOP. Accordingly, the UOP number of the UOP (i.e., the UOP in which the second data is defined) corresponding to the second data can be sent to the next operation unit together with the second data. In the embodiment of the present application, the UOP number (i.e., the above i) in the operation unit always corresponds to the number of the data table vector in the second buffer (i.e., both are i).

[0123] Further, according to the division mode, the high-bit index is used to determine whether the index element is less than VLMAX, i.e., whether the index element is within [0, VLMAX). If the third index component is not 0, it indicates that the index element is not less than VLMAX, and therefore, according to the RVV instruction set specification, the query result corresponding to the index element can be set to 0. The selection signal can be a target one-hot encoding of s bits, where s is the number of data elements included in the second data. The initial one-hot encoding is all 0, and the tth bit in the initial one-hot encoding represents the tth data element included in the second data. Accordingly, assuming that the low-bit index is equal to u, the u th bit in the initial one-hot encoding is set to 1 to obtain the target one-hot encoding. When selecting using the selection signal, the v th bit of each data element in the second buffer forms a bit sequence, and the selection signal is used to perform AND operation with each bit sequence to obtain the v th bit in the query result corresponding to the index element. Assuming that a data element includes 32 bits, 32 bit sequences of each data element are used to perform AND operation to obtain a 32-bit query result. Of course, in the case that the third index component is not 0 and / or the second index component is not equal to the microinstruction sequence number, the selection signal is all 0, and the selected data is also 0. In the embodiment of the present application, in the case that the third index component is 0 and the second index component is equal to the microinstruction sequence number of the target microinstruction, the query result corresponding to the index element is determined as the final query result of the index element.

[0124] Assuming that VLEN=128, DLEN=128, and SEW=32, the second buffer includes 4 32-bit data. Figure 12 is a generation diagram of a selection signal provided by the embodiment of the present application, as Figure 12As shown, index[31:5], index[4:2], index[1:0] represent high index, middle index and low index respectively, and uopIdx[2:0] represents UOP number. In the case that the electronic device adopts sequential transmission, uopIdx[2:0] is the number of iterations iterIdx, that is, the number of iterations also participates in data selection. In the case that the second index component is equal to the microinstruction sequence number of the target microinstruction, 1 is output to indicate that the index completes the query. Accordingly, the query result corresponding to the index element is determined as the final query result. The conversion circuit is used to convert index[1:0] into the target one-hot encoding. The middle index and the UOP number are compared. Assuming that w represents the number of data elements included in one second data, then the data elements included in the iterIdxth second data are: the iterIdxthw data elements~the iterIdxthw+w-1 data elements. Accordingly, if they are equal, it indicates that the element sequence number in the second buffer is in the interval [iterIdxthw, iterIdxthw+w-1], and the AND gate outputs 1. Otherwise, 0 is output. If the third index component is 0, the AND gate outputs 1. Otherwise, 0 is output. Finally, the output of the AND gate is the selection signal. Exemplarily, assuming that index=0x0000_0019 and iterIdx=0x6, index[31:5]=0, index[4:2]=0x6, and index[1:0]=0x1 can be obtained. Since index[4:2]==iterIdx, the AND gate outputs 1, and the conversion circuit converts index[1:0]=0x1 into one-hot code b0010.

[0125] Figure 13 is a selection schematic diagram provided by an embodiment of the present application, as shown in Figure 13 Taking the selection signal 0100 as an example, the selection signal and the value of each element in the bit sequence are used as the input of a plurality of AND gates, and the final output of the one gate connected to the plurality of AND gates is the selection result selected from the bit sequence. In specific implementation, the number of selection circuits corresponding to the number of bit positions of one data element can be set.

[0126] In the embodiment of the present application, by dividing the index element into the first index component, the second index component and the third index component, the query can be conveniently realized based on the division of the index element into the first index component, the second index component and the third index component, and therefore the processing efficiency is higher.

[0127] Referring to Figure 14 , a block diagram of an instruction execution device provided by an embodiment of the present application is shown, as shown in Figure 14 The device can specifically include:

[0128] The first processing module 201 is configured to, for any operation unit in the operation array, in a case where first data of a target micro instruction is obtained through a first data path, perform a data operation operation on the first data based on second data input along a second data path each time, and send the second data to a next operation unit through the second data path.

[0129] The updating module 202 is configured to update, by a control unit local to the operation unit, a number of times of operation of the first data after the data operation operation is performed once.

[0130] The first determining module 203 is configured to determine a current result of the data operation operation as an execution result of the target micro instruction in a case where the number of times of operation satisfies a preset number condition.

[0131] Optionally, the apparatus further includes a receiving module configured to receive, by an entry operation unit, the second data sent by an operand providing unit.

[0132] The operand providing unit is configured to, in a case where a micro instruction of a data query instruction is received each time, send second data defined in the micro instruction to the entry operation unit, and send first data defined in the micro instruction to operation units in the operation array based on a first data path in an order of unit numbers.

[0133] Optionally, a unit state bit is arranged in the operation unit, and the apparatus further includes:

[0134] A second processing module in the control unit is configured to set the unit state bit to a first value in a case where the first data is received, and restore the unit state bit to a second value after detecting that the number of times of operation satisfies the preset number condition; the first value represents that the operation unit is in an activated state, and the second value represents that the operation unit is in an inactivated state.

[0135] The first processing module 201 is specifically configured to, in a case where the unit state bit is the first value, send the second data to the next operation unit through the second data path.

[0136] Optionally, the target micro instruction is a micro instruction obtained by decoding a data query instruction; the first data is an index element defined by a first source operand of the target micro instruction, and the second data is a data element defined by a second source operand of the target micro instruction.

[0137] Optionally, the first processing module 201 is specifically configured to:

[0138] For each received second data, based on each index element in the first data, a query operation is performed on a plurality of data elements in the second data respectively, to obtain a query result corresponding to each index element;

[0139] The query result corresponding to each index element is written into a destination element in a destination buffer corresponding to each index element.

[0140] Optionally, the first determining module 203 is specifically configured to:

[0141] In a case where the number of operations satisfies the preset number condition, each destination element in the destination buffer is read as an execution result of the target microinstruction;

[0142] The apparatus further includes a write-back module configured to write back the execution result to a physical register file through a third data path.

[0143] Optionally, the apparatus further includes:

[0144] A calculating module configured to calculate a sum of the number of operations and a data length of the second data to obtain a queried length;

[0145] A second determining module configured to determine that the number of operations satisfies the preset number condition in a case where the queried length reaches a total length of a second source operand of a data query instruction.

[0146] Optionally, the first processing module 201 is specifically configured to:

[0147] For each index element in the first data, based on the number of data elements, the index element is divided into a first index component, a second index component and a third index component in a low-to-high order;

[0148] In a case where the third index component is 0 and the second index component is equal to a microinstruction serial number of the target microinstruction, a selection signal is generated based on the first index component; a target data element is selected from data elements of the second data based on the selection signal as a query result corresponding to the index element;

[0149] In a case where the third index component is not 0 and / or the second index component is not equal to the microinstruction serial number, the query result corresponding to the index element is set to 0.

[0150] Optionally, the target microinstruction is a microinstruction obtained by decoding a data query instruction; the first data is a data element defined by a second source operand of the target microinstruction, and the second data is an index element defined by a first source operand of the target microinstruction.

[0151] The first processing module 201 is specifically configured to send the second data, the current operation result of the data operation operation and the operation times to the next operation unit through the second data channel.

[0152] To sum up, in the instruction execution device provided by the embodiment of the application, for any operation unit in the operation array, in the case that the first data of the target microinstruction is obtained, a data operation operation is performed on the first data based on the second data input along the second data channel each time, and the second data is sent to the next operation unit through the second data channel. After the data operation operation is performed once, the control unit local to the operation unit updates the operation times of the first data. In the case that the operation times meet the preset number of times condition, the current result of the data operation operation is determined as the execution result of the target microinstruction. In this way, the second data is sequentially passed down between the operation units based on the second data channel, and the data required for processing the microinstruction can be shared, so that the required data is obtained from the physical register stack only once to complete the operation of one GATHER instruction. Therefore, the overall performance of the scheme is better and the power consumption is lower.

[0153] Reference Figure 15 is a structural schematic diagram of an electronic device provided by the embodiment of the application. As shown in Figure 15 The electronic device includes a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete mutual communication through the communication bus; the memory is used to store executable instructions, and the executable instructions make the processor execute the instruction execution method of the foregoing embodiment. The executable instructions can constitute a program.

[0154] The embodiment of the application provides a readable storage medium, which stores executable instructions, and when the executable instructions are executed by one or more processors, the processors execute the instruction execution method of the foregoing embodiment.

[0155] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same and similar parts between each embodiment can be referred to.

[0156] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, apparatus, or computer program product. Accordingly, embodiments of the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, and the like) embodying computer program instructions. It is to be understood that all actions to obtain signals, information, or data in this application are performed in compliance with the corresponding data protection regulations of the country where the data is obtained, and with the authorization of the owner of the corresponding device. Embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to embodiments of the present application. It is to be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, a special purpose computer, an embedded processor, or other programmable data processing terminal devices to produce a machine, such that the instructions, which are executed via the processor of the computer or other programmable data processing terminal devices, create means for implementing the functions specified in the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to embodiments of the present application. Figure 1 one or more flows and / or blocks Figure 1 an apparatus to perform the functions specified in the flowchart

[0157] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal devices to work in a predictive manner, such that the instructions stored in the computer-readable memory produce a manufactured product including instruction means that implement the functions specified in the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to embodiments of the present application. Figure 1 one or more flows and / or blocks Figure 1 an apparatus to perform the functions specified in the flowchart

[0158] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, such that a series of operational steps are performed on the computer or other programmable terminal device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to embodiments of the present application. Figure 1 one or more flows and / or blocks Figure 1 an apparatus to perform the functions specified in the flowchart

[0159] Although preferred embodiments of the present application have been described, those skilled in the art will appreciate that additional modifications and changes can be made thereto without departing from the scope of the present application. Accordingly, the appended claims are intended to cover all such modifications and changes as fall within the scope of the present application.

[0160] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between such entities or operations. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0161] The above provides a detailed description of the instruction execution method, the instruction execution device, the electronic device and the readable storage medium. The principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the method and the core idea of the present application. For those skilled in the art, according to the idea of the present application, the specific implementation manners and application scopes can be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A method for executing instructions, characterized in that, Applied to a computation array, the method includes: For any arithmetic unit in the arithmetic array, when the first data of the target microinstruction is obtained from the first data path, a data operation is performed with the first data based on the second data input along the second data path each time, and the second data is sent to the next arithmetic unit through the second data path. After each data operation is performed, the local control unit of the processing unit updates the number of times the first data has been processed. If the number of operations already performed meets a preset number of conditions, the current result of the data operation is determined as the execution result of the target microinstruction.

2. The method according to claim 1, characterized in that, The method further includes: receiving the second data sent by the operand providing unit from the entry operation unit; Specifically, upon receiving a microinstruction for a data query instruction, the operand providing unit sends the second data defined in the microinstruction to the entry operation unit, and sends the first data defined in the microinstruction to the operation units in the operation array according to the unit number order, based on the first data path.

3. The method according to claim 1, characterized in that, The arithmetic unit is equipped with a unit status bit; the method further includes: Upon receiving the first data, the control unit sets the unit status bit to a first value, and after detecting that the number of operations has met the preset number condition, restores the unit status bit to a second value; the first value indicates that the operation unit is in an active state, and the second value indicates that the operation unit is in an inactive state; Sending the second data to the next processing unit through the second data path includes: when the unit status bit is the first value, sending the second data to the next processing unit through the second data path.

4. The method according to any one of claims 1-3, characterized in that, The target microinstruction is a microinstruction obtained by decoding a data query instruction; The first data is an index element defined by the first source operand of the target microinstruction, and the second data is a data element defined by the second source operand of the target microinstruction.

5. The method according to claim 4, characterized in that, The step of performing a data operation with the first data based on the second data input along the second data path each time includes: For any given second data received, based on each index element in the first data, query operations are performed on multiple data elements in the second data to obtain query results corresponding to each index element; Write the query results corresponding to each index element into the destination buffer corresponding to each index element.

6. The method according to claim 5, characterized in that, The step of determining the current result of the data operation as the execution result of the target microinstruction when the number of operations meets a preset number condition includes: If the number of operations meets the preset number condition, each destination element in the destination buffer is read as the execution result of the target microinstruction; The method further includes writing the execution result back to the physical register file via a third data path.

7. The method according to claim 1, characterized in that, The method further includes: Calculate the sum of the number of operations already performed and the length of the second data to obtain the length of the query. If the length of the query reaches the total length of the second source operand of the data query instruction, it is determined that the number of operations performed satisfies the preset number condition.

8. The method according to claim 5, characterized in that, The step of performing query operations on multiple data elements in the second data based on each index element in the first data to obtain query results corresponding to each index element includes: For any index element in the first data, based on the number of data elements, the index element is divided into a first index component, a second index component, and a third index component in ascending order; When the third index component is 0 and the second index component is equal to the microinstruction number of the target microinstruction, a selection signal is generated based on the first index component; a target data element is selected from the data elements of the second data based on the selection signal, which serves as the query result corresponding to the index element. If the third index component is not 0, and / or the second index component is not equal to the microinstruction number, the query result corresponding to the index element is set to 0.

9. The method according to any one of claims 1-3, characterized in that, The target microinstruction is a microinstruction obtained by decoding a data query instruction; the first data is a data element defined by the second source operand of the target microinstruction, and the second data is an index element defined by the first source operand of the target microinstruction; Sending the second data to the next processing unit through the second data path includes: sending the second data, the current result of the data operation, and the number of operations performed to the next processing unit through the second data path.

10. An instruction execution device, characterized in that, Applied to a computation array, the device includes: The first processing module is configured to, for any arithmetic unit in the arithmetic array, upon obtaining the first data of the target microinstruction from the first data path, perform a data operation operation with the first data based on the second data input along the second data path each time, and send the second data to the next arithmetic unit through the second data path; An update module is used to update the number of times the first data has been processed by the local control unit of the processing unit after each data processing operation. The first determining module is used to determine the current result of the data operation as the execution result of the target microinstruction when the number of operations meets the preset number condition.

11. An electronic device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store executable instructions that cause the processor to perform the method as described in any one of claims 1 to 9.

12. A readable storage medium, characterized in that, It stores executable instructions that, when executed by one or more processors, cause the processors to perform the method as described in any one of claims 1 to 9.

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