Wafer defect and chip failure position matching method and system

Abstract

The invention discloses a wafer defect and chip failure position matching method and system. The matching method comprises the following steps: acquiring a first position coordinate of a wafer defect in a to-be-detected wafer; obtaining a second position coordinate of chip failure in each to-be-detected chip; converting the second position coordinates into corresponding third position coordinates in a wafer coordinate system; and traversing combinations of all wafer defects and all chip failures, and judging whether the positions of the wafer defects and the chip failures in each combination can be matched or not based on the first position coordinates and the third position coordinates. The second position coordinates are converted into the corresponding third position coordinates in the wafer coordinate system, so that the first position coordinates and the third position coordinates are data in the same coordinate system, and a data basis is provided for subsequent judgment processing. Through programmed traversal combination and then matching judgment, traditional manual comparison is replaced, the working efficiency can be remarkably improved, the working time can be shortened, and the reliability of data processing can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method and system for matching wafer defects and chip failure positions. Background Art

[0002] With the rapid development of semiconductor technology, chips are increasingly used in various fields, and their reliability and performance requirements are constantly increasing. The correlation between wafer defects and chip failure locations has become an important topic in semiconductor manufacturing and failure analysis.

[0003] During the semiconductor manufacturing process, wafers undergo multiple complex process steps, such as photolithography, etching, and thin film deposition. Various defects are inevitable during these steps. For example, uneven photoresist coating can cause circuit line widths to not meet design requirements, thereby affecting the chip's electrical performance. Furthermore, particle contamination, residual impurities, or process deviations on the wafer surface can also lead to wafer defects. These defects can be amplified during subsequent chip manufacturing, ultimately affecting chip performance and reliability.

[0004] Chip failures arise from a variety of factors, including design flaws, manufacturing defects, packaging defects, and environmental factors. Among manufacturing defects, wafer defects are a key factor. Defects on the wafer can gradually manifest during chip use, leading to chip failure. For example, a tiny crack on the wafer can propagate due to thermal stress after chip packaging, ultimately causing circuit breakage. Furthermore, impurities introduced during wafer manufacturing can accelerate chip failure in high-temperature or high-humidity environments.

[0005] To improve chip reliability and yield, it's crucial to study the correlation between wafer defects and chip failure locations. Advanced inspection technologies, such as scanning electron microscopes and focused ion beams, enable precise detection and analysis of wafer defects. Furthermore, failure analysis techniques, such as photon emission microscopy and laser-induced voltage variation, can help pinpoint the specific location of chip failures. Correlating wafer defect data with chip failure locations helps engineers better understand failure mechanisms, thereby optimizing manufacturing processes, reducing defects, and improving overall chip quality and reliability.

[0006] However, the existing technology still has many problems in the process of matching wafer defects and chip failure positions. Summary of the Invention

[0007] The problem solved by the present invention is to provide a method and system for matching wafer defects and chip failure positions, so as to improve matching efficiency and reliability.

[0008] To solve the above problems, the technical solution of the present invention provides a method for matching wafer defects and chip failure positions, including: providing a wafer to be inspected, wherein the wafer to be inspected includes several chips to be inspected; obtaining the first position coordinates of the wafer defect in the wafer to be inspected; obtaining the second position coordinates of the chip failure in each of the chips to be inspected; converting the second position coordinates into the corresponding third position coordinates in the wafer coordinate system; traversing all combinations of the wafer defects and all the chip failures, and judging whether the positions of the wafer defects and the chip failures in each combination can be matched based on the first position coordinates and the third position coordinates.

[0009] Optionally, the method of converting the second position coordinate into a corresponding third position coordinate in the wafer coordinate system includes: determining the global coordinate system of the wafer to be inspected; determining the local coordinate system of each of the chips to be inspected; calculating the coordinates corresponding to the center position of each of the chips to be inspected in the wafer coordinate system based on the row and column offsets of each of the chips to be inspected on the wafer to be inspected; adding the second position coordinates of each of the chips to be inspected with the coordinates corresponding to the chip to be inspected in the wafer coordinate system to obtain the third position coordinates corresponding to the position of the chip failure in the chip to be inspected in the wafer coordinate system.

[0010] Optionally, the method of converting the second position coordinates into corresponding third position coordinates in the wafer coordinate system further includes: detecting whether the converted third position coordinates meet the geometric constraints of the wafer to be inspected by drawing or checking coordinates.

[0011] Optionally, before traversing all combinations of the wafer defects and all chip failures, the method further includes: screening out the wafer defects that are not located in the chip area in the wafer to be inspected.

[0012] Optionally, the method for judging whether the position of the wafer defect and the chip failure in each combination can be matched based on the first position coordinates and the third position coordinates includes: obtaining size information of the wafer defect; based on the size information of the wafer defect and the first position coordinates, constructing a first area graphic corresponding to the wafer defect with the first position coordinates as the center; constructing a second area graphic corresponding to the chip failure with the third position coordinates as the center; when the first area graphic and the second area graphic have an overlapping area, judging that the position of the wafer defect and the chip failure matches.

[0013] Optionally, the first area graphic includes: a circle, a square or an equilateral triangle.

[0014] Optionally, the chip to be detected includes: a memory chip.

[0015] Optionally, the chip failure in the chip to be detected includes: failure of a storage unit in a storage array.

[0016] Optionally, the wafer defect detection equipment includes one or more of: a bright field detection system, a dark field detection system, a broadband plasma pattern wafer defect detection system, an electron beam detection system and a defect review electron microscope.

[0017] Optionally, the chip failure detection equipment includes: a yield testing system.

[0018] Correspondingly, the technical solution of the present invention also provides a matching system for wafer defects and chip failure positions, including: a first acquisition module for acquiring the first position coordinates of the wafer defect in the wafer to be detected; a second acquisition module for acquiring the second position coordinates of the chip failure in each of the chips to be detected in the wafer to be detected; a conversion module for converting the second position coordinates into the corresponding third position coordinates in the wafer coordinate system; a judgment module for traversing all combinations of the wafer defects and all the chip failures, and judging whether the positions of the wafer defects and the chip failures in each combination can be matched based on the first position coordinates and the third position coordinates.

[0019] Optionally, the conversion module includes: a first coordinate system determination unit, used to determine the global coordinate system of the wafer to be inspected; a second coordinate system determination unit, used to determine the local coordinate system of each of the chips to be inspected; a first calculation unit, used to calculate the coordinates corresponding to the center position of each of the chips to be inspected in the wafer coordinate system according to the row and column offsets of each of the chips to be inspected on the wafer to be inspected; a second calculation unit, used to add the second position coordinates of each of the chips to be inspected with the coordinates corresponding to the chip to be inspected in the wafer coordinate system, to obtain the third position coordinates corresponding to the position of the chip failure in the chip to be inspected in the wafer coordinate system.

[0020] Optionally, the conversion module further includes: a detection unit, configured to detect whether the converted third position coordinates conform to the geometric constraints of the wafer to be detected by drawing or checking coordinates.

[0021] Optionally, the method further includes: a screening module for screening out the wafer defects that are not located in the chip area in the wafer to be inspected before traversing all combinations of the wafer defects and all the chip failures.

[0022] Optionally, the judgment module includes: a first construction unit, used to construct a first area graphic corresponding to the wafer defect with the first position coordinate as the center based on the size information of the wafer defect and the first position coordinate; a second construction unit, used to construct a second area graphic corresponding to the chip failure with the third position coordinate as the center; an area overlapping unit, used to detect whether the first area graphic and the second area graphic have an overlapping area, and when the first area graphic and the second area graphic have an overlapping area, it is judged that the positions of the wafer defect and the chip failure match.

[0023] Optionally, the first area graphic includes: a circle, a square or an equilateral triangle.

[0024] Optionally, the chip to be detected includes: a memory chip.

[0025] Optionally, the chip failure in the chip to be detected includes: failure of a storage unit in a storage array.

[0026] Optionally, the wafer defect detection equipment includes one or more of: a bright field detection system, a dark field detection system, a broadband plasma pattern wafer defect detection system, an electron beam detection system and a defect review electron microscope.

[0027] Optionally, the chip failure detection equipment includes: a yield testing system.

[0028] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0029] In the method for matching wafer defects and chip failure positions of the technical solution of the present invention, after obtaining the first position coordinates and the second position coordinates, the second position coordinates are converted into corresponding third position coordinates in the wafer coordinate system, so that the first position coordinates and the third position coordinates are data in the same coordinate system, thereby providing a data basis for subsequent judgment processing. By performing a programmed traversal combination of all the wafer defects and all the chip failures, and then judging whether the positions of the wafer defects and the chip failures in each combination can be matched based on the first position coordinates and the third position coordinates, the traditional manual one-to-one comparison process is replaced, which can significantly improve work efficiency. Moreover, by automating the processing of a large number of repetitive tasks, fatigue and negligence that may occur in manual operations can be effectively avoided, thereby greatly shortening working time and improving the reliability of data processing.

[0030] Furthermore, the method of converting the second position coordinates to corresponding third position coordinates in the wafer coordinate system further includes: testing whether the converted third position coordinates conform to the geometric constraints of the wafer to be inspected by drawing or checking coordinates. By testing the converted third position coordinates, the accuracy and usability of the data are ensured, thereby improving the reliability of the matching.

[0031] Furthermore, before traversing all combinations of wafer defects and chip failures, the method further includes: screening out the wafer defects that are not located in the chip area of ​​the wafer to be inspected. Since the wafer defects located outside the chip area will not cause chip failure of the chip to be inspected, the number of wafer defects is reduced by screening out these defects, thereby reducing the number of combinations of wafer defects and chip failures, thereby reducing the amount of calculation and improving matching efficiency.

[0032] In the wafer defect and chip failure position matching system of the technical solution of the present invention, after obtaining the first position coordinate and the second position coordinate, the second position coordinate is converted into the corresponding third position coordinate in the wafer coordinate system by the conversion module, so that the first position coordinate and the third position coordinate are data in the same coordinate system, thereby providing a data basis for subsequent judgment processing. The judgment module performs a programmed traversal combination of all the wafer defects and all the chip failures, and then judges whether the positions of the wafer defects and the chip failures in each combination can be matched based on the first position coordinate and the third position coordinate, thereby replacing the traditional manual one-to-one comparison process, which can significantly improve work efficiency. Moreover, by automating the processing of a large number of repetitive tasks, fatigue and negligence that may occur in manual operations can be effectively avoided, thereby greatly shortening working time and improving the reliability of data processing.

[0033] Furthermore, the conversion module further includes a detection unit configured to detect whether the converted third position coordinates conform to the geometric constraints of the wafer to be inspected by drawing or checking coordinates. The detection unit detects the converted third position coordinates to ensure data accuracy and usability, thereby improving the reliability of the matching.

[0034] Furthermore, the system further includes: a screening module for screening out the wafer defects that are not located in the chip area of ​​the wafer to be inspected before traversing all combinations of the wafer defects and all the chip failures. Since the wafer defects located outside the chip area will not cause chip failure of the chip to be inspected, the screening module is used to screen out the wafer defects in this part to reduce the number of wafer defects, thereby reducing the combination of wafer defects and chip failures, thereby reducing the amount of calculation and improving matching efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 1 is a flow chart of a method for matching wafer defects and chip failure positions according to an embodiment of the present invention;

[0036] Figures 2 to 5 1 is a schematic structural diagram of each step of a method for matching wafer defects and chip failure positions according to an embodiment of the present invention;

[0037] Figure 6 1 is a schematic structural diagram of a system for matching wafer defects and chip failure positions according to an embodiment of the present invention;

[0038] Figure 7 2 is a schematic structural diagram of a conversion module in a system for matching wafer defects and chip failure positions according to an embodiment of the present invention;

[0039] Figure 8 It is a structural diagram of a judgment module in a system for matching wafer defects and chip failure positions according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] To make the above-mentioned objects, features, and advantages of the present invention more clearly understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0041] In the description of the present invention, it should be understood that the terms "upper," "lower," "top," and "bottom" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the positions or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations of the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0042] As described in the background art, the prior art still has many problems in the process of matching wafer defects and chip failure locations, which will be described in detail below.

[0043] Wafer defects can lead to chip yield loss, but the current defect management system and yield testing system use different reference coordinate systems, and the data volume of both is extremely large. It is not feasible to use manual means to match the defect location with the chip failure location one by one. Therefore, automated program operations are required to complete the matching of wafer defects and chip failure points.

[0044] On this basis, the present invention provides a method and system for matching wafer defects and chip failure positions. After obtaining the first position coordinates and the second position coordinates, the second position coordinates are converted into corresponding third position coordinates in the wafer coordinate system so that the first position coordinates and the third position coordinates are data in the same coordinate system, thereby providing a data basis for subsequent judgment and processing. By performing a programmed traversal combination of all the wafer defects and all the chip failures, and then judging whether the positions of the wafer defects and the chip failures in each combination can be matched based on the first position coordinates and the third position coordinates, the traditional manual one-to-one comparison process is replaced, which can significantly improve work efficiency. Moreover, by automating the processing of a large number of repetitive tasks, fatigue and negligence that may occur in manual operations can be effectively avoided, thereby greatly shortening working time and improving the reliability of data processing.

[0045] Figure 1 1 is a flow chart of a method for matching wafer defects and chip failure positions according to an embodiment of the present invention, comprising:

[0046] Step S101, providing a wafer to be inspected, wherein the wafer to be inspected includes a plurality of chips to be inspected;

[0047] Step S102, obtaining the first position coordinates of a wafer defect in the wafer to be inspected;

[0048] Step S103, obtaining the second position coordinates of the failed chip in each of the chips to be detected;

[0049] Step S104, converting the second position coordinates into corresponding third position coordinates in the wafer coordinate system;

[0050] Step S105 , traversing all combinations of the wafer defects and all chip failures, and determining whether the positions of the wafer defects and the chip failures in each combination can be matched based on the first position coordinates and the third position coordinates.

[0051] The following describes in detail the steps of the method and system for matching wafer defects and chip failure positions with reference to the accompanying drawings.

[0052] Figures 2 to 5 It is a schematic structural diagram of each step of the method for matching wafer defects and chip failure positions according to an embodiment of the present invention.

[0053] Please refer to Figure 2 , providing a wafer 100 to be inspected, wherein the wafer 100 to be inspected includes a plurality of chips 101 to be inspected.

[0054] It should be noted that in this embodiment, the wafer 100 to be inspected can be divided into multiple chips 101 to be inspected. During the semiconductor manufacturing process, the wafer 100 to be inspected is the base material for manufacturing the chips 101 to be inspected. After a series of complex process steps such as photolithography, etching, and doping, many tiny chips 101 to be inspected are formed on the wafer 100 to be inspected. These chips 101 to be inspected are neatly arranged on the wafer 100 to be inspected, with dedicated scribe lines between each chip 101 for subsequent cutting.

[0055] In this embodiment, the chip to be detected 101 is a memory chip, specifically a static random-access memory (SRAM) chip.

[0056] Please refer to Figure 3 , obtaining the first position coordinates of the wafer defect 100a in the wafer 100 to be inspected.

[0057] It should be noted that, in this embodiment, the wafer defect 100a refers to a defect or flaw that does not meet the requirements and appears on the surface or inside of the wafer to be inspected 100 during the semiconductor manufacturing process. According to its location and nature, the wafer defect 100a can be divided into surface defects, structural defects, impurity defects, etc. Among them, surface defects are divided into: particle defects, particle defects are particle contamination on the surface of the wafer to be inspected 100, which may come from impurities in the production environment, equipment wear or process residues. These particles can cause circuit short circuits or open circuits; scratch defects, scratch defects are usually caused by mechanical damage, such as handling, cutting and other operations. Scratches will affect the flatness of the wafer surface, and thus affect subsequent processes; pattern defects, pattern defects are usually caused by problems in the photolithography process, such as insufficient exposure or inaccurate focus, which may cause uneven circuit line width; oxide film defects, oxide film defects are uneven or defective oxide films, which may affect the insulation performance of the wafer. Structural defects are categorized as follows: lattice defects, which include point defects (such as vacancies and interstitial atoms), line defects (such as dislocations), and surface defects (such as grain boundary defects). These defects can affect the structural stability and electrical properties of the wafer; crystal defects, which are incomplete crystal structures and are typically caused by temperature gradients or uneven growth rates during wafer growth. Impurity defects include: metallic impurities, which are excessive levels of metal elements within the inspected wafer 100 and can affect electrical properties and thermal stability; organic impurities, which are excessive levels of organic substances and can affect insulation performance; and gaseous impurities, which are excessive levels of gases and can affect electrical and optical properties.

[0058] Figure 3 Only one wafer defect 100 a is shown for exemplary description.

[0059] In this embodiment, the wafer defect 100a detection equipment includes one or more of a brightfield inspection system, a darkfield inspection system, a broadband plasma patterned wafer defect 100a detection system, an electron beam inspection system, and a defect review electron microscope. The brightfield inspection system utilizes a high-brightness light source to illuminate the wafer surface and uses an optical imaging system to capture reflected or transmitted light to detect surface defects. It is suitable for detecting defects on patterned wafers and can quickly identify particles, scratches, opens, and shorts. The darkfield inspection system utilizes a specialized optical design to illuminate the wafer surface at a specific angle, collecting only light scattered from defects. Darkfield inspection systems are highly sensitive to minute defects and are suitable for rapid inspection of large wafers. The Broadband Plasma Inspection System (BPI) combines multiple wavelength light sources to detect a variety of defects on patterned wafers. The E-beam Inspection System (EBI) uses an electron beam to scan the wafer surface, identifying defects by detecting signals from secondary electrons and backscattered electrons. E-beam inspection offers high resolution and is suitable for detecting defects in high-aspect-ratio structures and ultra-thin films. The Review SEM (Review Electron Microscope) is used to review and analyze defects detected by optical inspection systems. It provides high-resolution defect images, helping engineers more accurately locate and analyze defects.

[0060] In this embodiment, the first position coordinate is obtained based on the wafer coordinate system, and the first position coordinate is the center point of the wafer defect 100a. The wafer coordinate system usually takes the center of the wafer to be inspected 100 as the origin and the diameter of the wafer to be inspected 100 as the reference to establish a global coordinate system.

[0061] Please refer to Figure 4 , obtaining the second position coordinates of the failed chip 101a in each of the chips to be detected 101.

[0062] In this embodiment, the chip failure 101a in the chip to be detected 101 is a failure of a storage unit in a storage array.

[0063] In this embodiment, the device for detecting chip failure 101a includes a yield testing system. The yield testing system performs read and write testing on the chip memory array of the chip to be tested 101 to identify failed memory cells, including: data writing, in which the testing system writes specific data into each memory cell of the memory array; data reading and comparison, in which after writing, the testing system reads the data from the memory cell and compares it with the written data. If the read data matches the written data, the memory cell is functioning properly; if not, the memory cell is deemed failed; and failed cell location, in which the testing system records the address information of the failed cell, typically expressed as a row address and a column address.

[0064] After obtaining the specific storage unit failure, a regional graphic occupied by the failed storage unit is obtained through product information, and the center point of the regional graphic is used as the second position coordinate.

[0065] In this embodiment, the second position coordinates are obtained based on the local coordinate system of each chip under test 101. The second position coordinates are the center point of the failed chip 101a. The local coordinate system of each chip under test 101 is typically established with the lower left corner (or center point) of the chip under test 101 as the origin. Therefore, the first and second position coordinates are obtained based on different coordinate systems and cannot be processed mutually.

[0066] Figure 4 Only the location of one chip failure 101 a is shown for exemplary description.

[0067] The second position coordinates are converted into corresponding third position coordinates in the wafer coordinate system.

[0068] The method for converting the second position coordinate into the corresponding third position coordinate in the wafer coordinate system includes: determining the global coordinate system of the wafer 100 to be inspected; determining the local coordinate system of each chip to be inspected 101; calculating the coordinates corresponding to the center position of each chip to be inspected 101 in the wafer coordinate system based on the row and column offset of each chip to be inspected 101 on the wafer 100 to be inspected; adding the second position coordinates of each chip to be inspected 101 to the coordinates corresponding to the chip to be inspected 101 in the wafer coordinate system to obtain the third position coordinates corresponding to the position of the chip failure 101a in the chip to be inspected 101 in the wafer coordinate system.

[0069] In a specific embodiment, the specific process of converting the second position coordinate into the corresponding third position coordinate in the wafer coordinate system includes: determining the wafer coordinate system, establishing a global coordinate system with the center of the wafer 100 to be detected as the origin and the diameter of the wafer 100 to be detected as the reference; determining the chip coordinate system, establishing a local coordinate system with the origin of the lower left corner of each chip 101 to be detected; determining the arrangement of the chips, the chips 101 to be detected are usually arranged in a grid form on the wafer 100 to be detected, starting from the center of the wafer 100 to be detected and extending to the surrounding areas; calculating the global coordinates of the chip center, assuming that the width of the chip 101 to be detected is w, the height is h, and the effective radius of the wafer 100 to be detected is Reff (the radius of the wafer 100 to be detected minus the edge discard size), then the center coordinates of each chip 101 to be detected can be calculated by the following formula: center =i×w,y center =j×h; where i and j are integers representing the row and column offsets of the chip in the grid; for determining the effective area, the four corners of the chip to be inspected 101 must be completely within the effective circle of the wafer to be inspected 100. center ,y center The coordinates of the four corners of the chip to be tested 101 are: (x center -w / 2,y center r -h / 2)、(x center +w / 2,y center r -h / 2)、(x center +w / 2,y center r +h / 2), (x center -w / 2,y center r +h / 2); the coordinates of each angle must satisfy x 2 +y 2 ≤Reff 2 ; Coordinate conversion formula, converting the local coordinates of each chip to be detected 101 into the global coordinates of the wafer to be detected 100. Assume that the local coordinates of the chip to be detected 101 (ie, the second position coordinates) are (x local ,y local ), then its coordinate in the wafer coordinate system (ie, the third position coordinate) is: global =x center +x local ,y global =y center +y local ; Among them, (x center ,y center ) is the coordinate of the center of the chip to be detected 101 in the wafer coordinate system.

[0070] In this embodiment, the method of converting the second position coordinates into corresponding third position coordinates in the wafer coordinate system further includes: testing whether the converted third position coordinates conform to the geometric constraints of the wafer 100 to be inspected by drawing or checking coordinates. By testing the converted third position coordinates, the accuracy and usability of the data are ensured, thereby improving the reliability of the matching.

[0071] Please refer to Figure 5 , traverse all combinations of the wafer defects 100a and all combinations of the chip failures 101a, and determine whether the positions of the wafer defects 100a and the chip failures 101a in each combination can be matched based on the first position coordinates and the third position coordinates.

[0072] After obtaining the first position coordinates and the second position coordinates, the second position coordinates are converted into the corresponding third position coordinates in the wafer coordinate system so that the first position coordinates and the third position coordinates are data in the same coordinate system, thereby providing a data basis for subsequent judgment processing. By programmatically traversing and combining all the wafer defects 100a and all the chip failures 101a, and then judging whether the positions of the wafer defects 100a and the chip failures 101a in each combination can be matched based on the first position coordinates and the third position coordinates, this replaces the traditional manual one-to-one comparison process, which can significantly improve work efficiency. Moreover, by automating the processing of a large number of repetitive tasks, fatigue and negligence that may occur in manual operations can be effectively avoided, thereby greatly shortening working time and improving the reliability of data processing.

[0073] In this embodiment, before traversing all combinations of the wafer defects 100a and all chip failures 101a, the process further includes: screening out the wafer defects 100a that are not located in the chip region of the wafer 100 to be inspected. Since the wafer defects 100a located outside the chip region will not cause chip failures 101a of the chip 101 to be inspected, screening out these wafer defects 100a reduces the number of wafer defects 100a, thereby reducing the number of combinations of wafer defects 100a and chip failures 101a, thereby reducing the amount of computation and improving matching efficiency.

[0074] Please continue to refer to Figure 5The method for determining whether the positions of the wafer defect 100a and the chip failure 101a in each combination can be matched based on the first position coordinates and the third position coordinates includes: obtaining size information of the wafer defect 100a; constructing a first region graphic 1001 corresponding to the wafer defect 100a with the first position coordinates as the center based on the size information of the wafer defect 100a and the first position coordinates; constructing a second region graphic 1011 corresponding to the chip failure 101a with the third position coordinates as the center; and determining that the positions of the wafer defect 100a and the chip failure 101a match when the first region graphic 1001 and the second region graphic 1011 have an overlapping area. The first region graphic 1001 includes a circle, a square, or an equilateral triangle.

[0075] In one specific embodiment, the size information of the wafer defect 100a is the maximum diameter of the wafer defect 100a. A circular region with the size information as the diameter is established with the first position coordinate as the center point. This region serves as the first regional graphic 1001 of the wafer defect 100a. Since the topography and area of ​​the storage unit corresponding to the chip failure 101a can be directly obtained based on the product information, measurement is not required. Instead, a second regional graphic 1011 corresponding to the chip failure 101a is directly constructed with the third position coordinate as the center point. The topography and area of ​​the second regional graphic 1011 are the topography and area of ​​the corresponding storage unit recorded in the product information.

[0076] It should be noted that, in this embodiment, the wafer defects 100a obtained are all small-sized defects, so the graphics of the wafer defects 100a can be regarded as a regular-shaped graphic (such as a circle, a square or an equilateral triangle), and there is no need to obtain the outline graphics of the wafer defects 100a in detail, thereby sacrificing some graphic accuracy to improve processing efficiency.

[0077] Figure 5 As an example, the first area graphic 1001 and the second area graphic 1011 have an overlapping area.

[0078] In this embodiment, after determining that the positions of the wafer defect 100a and the chip failure 101a match, it can help engineers better understand the failure mechanism, thereby optimizing the manufacturing process, reducing the generation of the wafer defect 100a, and improving the overall quality and reliability of the chip 101 to be tested.

[0079] Figure 6 1 is a schematic structural diagram of a system for matching wafer defects and chip failure positions according to an embodiment of the present invention; Figure 72 is a schematic structural diagram of a conversion module in a system for matching wafer defects and chip failure positions according to an embodiment of the present invention; Figure 8 It is a structural diagram of a judgment module in a system for matching wafer defects and chip failure positions according to an embodiment of the present invention.

[0080] Correspondingly, the technical solution of the present invention also provides a matching system for the positions of wafer defects 100a and chip failures 101a, please refer to Figure 6 And continue to combine reference Figures 2 to 5 , including: a first acquisition module 200, used to obtain the first position coordinates of the wafer defect 100a in the wafer to be inspected 100; a second acquisition module 201, used to obtain the second position coordinates of the chip failure 101a in each of the chips to be inspected in the wafer 100 to be inspected; a conversion module 202, used to convert the second position coordinates into corresponding third position coordinates in the wafer coordinate system; a judgment module 203, used to traverse all combinations of the wafer defects 100a and all the chip failures 101a, and judge whether the positions of the wafer defects 100a and the chip failures 101a in each combination can be matched based on the first position coordinates and the third position coordinates.

[0081] After obtaining the first position coordinates and the second position coordinates, the second position coordinates are converted into corresponding third position coordinates in the wafer coordinate system by the conversion module 202, so that the first position coordinates and the third position coordinates are data in the same coordinate system, thereby providing a data basis for subsequent judgment processing. The judgment module 203 performs a programmed traversal combination of all the wafer defects 100a and all the chip failures 101a, and then judges whether the positions of the wafer defects 100a and the chip failures 101a in each combination can be matched based on the first position coordinates and the third position coordinates, thereby replacing the traditional manual one-to-one comparison process, which can significantly improve work efficiency. Moreover, by automating the processing of a large number of repetitive tasks, fatigue and negligence that may occur in manual operations can be effectively avoided, thereby greatly shortening working time and improving the reliability of data processing.

[0082] Please refer to Figure 7In this embodiment, the conversion module 202 includes: a first coordinate system determination unit 2021, used to determine the global coordinate system of the wafer to be detected 100; a second coordinate system determination unit 2022, used to determine the local coordinate system of each chip to be detected 101; a first calculation unit 2023, used to calculate the coordinates corresponding to the center position of each chip to be detected 101 in the wafer coordinate system according to the row and column offset of each chip to be detected 101 on the wafer to be detected 100; a second calculation unit 2024, used to add the second position coordinates of each chip to be detected 101 with the coordinates corresponding to the chip to be detected 101 in the wafer coordinate system, and obtain the third position coordinates corresponding to the position of the chip failure 101a in the chip to be detected 101 in the wafer coordinate system.

[0083] Please continue to refer to Figure 7 In this embodiment, the conversion module 202 further includes a detection unit 2025 for detecting whether the converted third position coordinates conform to the geometric constraints of the wafer 100 to be inspected by drawing or checking coordinates. The detection unit 2025 detects the converted third position coordinates to ensure data accuracy and usability, thereby improving the reliability of the matching.

[0084] Please continue to refer to Figure 6 In this embodiment, the system further includes a screening module 204 for screening out wafer defects 100a that are not located in the chip region of the wafer 100 to be inspected before traversing all combinations of the wafer defects 100a and all chip failures 101a. Since wafer defects 100a located outside the chip region will not cause chip failures 101a of the chip 101 to be inspected, the screening module 204 screens out these wafer defects 100a to reduce the number of wafer defects 100a, thereby reducing the number of combinations of wafer defects 100a and chip failures 101a, thereby reducing the amount of computation and improving matching efficiency.

[0085] Please refer to Figure 8In this embodiment, the judgment module 203 includes: a first construction unit 2031, used to construct a first area graphic 1001 corresponding to the wafer defect 100a with the first position coordinate as the center based on the size information of the wafer defect 100a and the first position coordinate; a second construction unit 2032, used to construct a second area graphic 1011 corresponding to the chip failure 101a with the third position coordinate as the center; and an area overlapping unit 2033, used to detect whether the first area graphic 1001 and the second area graphic 1011 have an overlapping area. When the first area graphic 1001 and the second area graphic 1011 have an overlapping area, it is determined that the positions of the wafer defect 100a and the chip failure 101a match.

[0086] In this embodiment, the first area graphic 1001 includes: a circle, a square or an equilateral triangle.

[0087] It should be noted that in this embodiment, since the topography and area of ​​the storage unit corresponding to the chip failure 101a can be directly obtained based on the product information, measurement is not required. Instead, a second region graphic 1011 corresponding to the chip failure 101a is directly constructed with the third position coordinate as the center. The topography and area of ​​the second region graphic 1011 are identical to the topography and area of ​​the corresponding storage unit recorded in the product information. The acquired wafer defects 100a are all small defects, so the pattern of the wafer defect 100a can be considered a regular shape (such as a circle, square, or equilateral triangle), eliminating the need for a detailed image of the wafer defect 100a's outline. This sacrifices some pattern accuracy in exchange for improved processing efficiency.

[0088] In this embodiment, the chip to be detected 101 is a memory chip, specifically a static random-access memory (SRAM) chip.

[0089] In this embodiment, the chip failure 101a in the chip to be detected 101 is a failure of a storage unit in a storage array.

[0090] In this embodiment, the wafer defect 100a detection equipment includes: one or more of: a bright field detection system, a dark field detection system, a broadband plasma pattern wafer defect 100a detection system, an electron beam detection system, and a defect review electron microscope.

[0091] In this embodiment, the chip failure detection device 101a utilizes a yield test system. The yield test system performs read and write testing on the chip memory array of the chip to be tested 101 to identify failed memory cells, including: data writing, where the test system writes specific data into each memory cell of the memory array; data reading and comparison, where after writing, the test system reads the data from the memory cell and compares it with the written data. If the read data matches the written data, the memory cell is functioning properly; if not, the memory cell is deemed failed; and failed cell location, where the test system records the address information of the failed cell, typically expressed as a row address and a column address.

[0092] It should be understood that the examples and embodiments herein are merely illustrative and that those skilled in the art may make various modifications and corrections without departing from the spirit and scope of the present invention as defined in this application and the appended claims.

Claims

1. A method for matching wafer defects and chip failure locations, characterized in that: include: Providing a wafer to be inspected, wherein the wafer to be inspected includes a plurality of chips to be inspected; Obtaining a first position coordinate of a wafer defect in the wafer to be inspected; Obtaining the second position coordinates of a failed chip in each of the chips to be detected; Converting the second position coordinates into corresponding third position coordinates in a wafer coordinate system; All combinations of the wafer defects and all chip failures are traversed, and based on the first position coordinates and the third position coordinates, it is determined whether the positions of the wafer defects and the chip failures in each combination can be matched.

2. The method for matching wafer defects and chip failure positions according to claim 1, wherein: The method for converting the second position coordinate into the corresponding third position coordinate in the wafer coordinate system includes: determining the global coordinate system of the wafer to be inspected; determining the local coordinate system of each chip to be inspected; calculating the coordinates corresponding to the center position of each chip to be inspected in the wafer coordinate system based on the row and column offset of each chip to be inspected on the wafer to be inspected; adding the second position coordinates of each chip to be inspected with the coordinates corresponding to the chip to be inspected in the wafer coordinate system to obtain the third position coordinates corresponding to the position of the chip failure in the chip to be inspected in the wafer coordinate system.

3. The method for matching wafer defects and chip failure positions according to claim 2, wherein: The method of converting the second position coordinates into corresponding third position coordinates in the wafer coordinate system further includes: detecting whether the converted third position coordinates meet the geometric constraints of the wafer to be inspected by drawing or checking coordinates.

4. The method for matching wafer defects and chip failure positions according to claim 1, wherein: Before traversing all combinations of the wafer defects and all chip failures, the method further includes: screening out the wafer defects that are not located in the chip area in the wafer to be inspected.

5. The method for matching wafer defects and chip failure positions according to claim 1, wherein: The method for judging whether the positions of the wafer defect and the chip failure in each combination can be matched based on the first position coordinates and the third position coordinates includes: obtaining size information of the wafer defect; constructing a first area graphic corresponding to the wafer defect with the first position coordinates as the center based on the size information of the wafer defect and the first position coordinates; constructing a second area graphic corresponding to the chip failure with the third position coordinates as the center; when the first area graphic and the second area graphic have an overlapping area, judging that the positions of the wafer defect and the chip failure match.

6. The method for matching wafer defects and chip failure positions according to claim 5, wherein: The first area graphic includes: a circle, a square or an equilateral triangle.

7. The method for matching wafer defects and chip failure positions according to claim 1, wherein: The chip to be detected includes: a memory chip.

8. The method for matching wafer defects and chip failure positions according to claim 7, wherein: The chip failure in the chip to be detected includes: a failure of a storage unit in a storage array.

9. The method for matching wafer defects and chip failure positions according to claim 1, wherein: The wafer defect detection equipment includes: one or more of a bright field detection system, a dark field detection system, a broadband plasma pattern wafer defect detection system, an electron beam detection system, and a defect review electron microscope.

10. The method for matching wafer defects and chip failure positions according to claim 1, wherein: The chip failure detection equipment includes: a yield test system.

11. A system for matching wafer defects and chip failure locations, characterized in that: include: A first acquisition module is used to obtain the first position coordinates of a wafer defect in a wafer to be inspected; A second acquisition module is used to obtain the second position coordinates of the failed chip in each of the chips to be inspected in the wafer to be inspected; a conversion module, configured to convert the second position coordinates into corresponding third position coordinates in a wafer coordinate system; A judgment module is used to traverse all combinations of the wafer defects and all the chip failures, and judge whether the positions of the wafer defects and the chip failures in each combination can be matched based on the first position coordinates and the third position coordinates.

12. The wafer defect and chip failure location matching system according to claim 11, wherein: The conversion module includes: a first coordinate system determination unit, used to determine the global coordinate system of the wafer to be inspected; a second coordinate system determination unit, used to determine the local coordinate system of each chip to be inspected; a first calculation unit, used to calculate the coordinates corresponding to the center position of each chip to be inspected in the wafer coordinate system according to the row and column offset of each chip to be inspected on the wafer to be inspected; a second calculation unit, used to add the second position coordinates of each chip to be inspected with the coordinates corresponding to the chip to be inspected in the wafer coordinate system, to obtain the third position coordinates corresponding to the position of the chip failure in the chip to be inspected in the wafer coordinate system.

13. The wafer defect and chip failure location matching system according to claim 12, wherein: The conversion module further includes: a detection unit, configured to detect whether the converted third position coordinates conform to the geometric constraints of the wafer to be detected by drawing or checking coordinates.

14. The wafer defect and chip failure location matching system according to claim 11, wherein: Also includes: The screening module is used to screen out the wafer defects that are not located in the chip area in the wafer to be inspected before traversing all combinations of the wafer defects and all the chip failures.

15. The wafer defect and chip failure location matching system according to claim 11, wherein: The judgment module includes: a first construction unit, used to construct a first area graphic corresponding to the wafer defect with the first position coordinate as the center based on the size information of the wafer defect and the first position coordinate; a second construction unit, used to construct a second area graphic corresponding to the chip failure with the third position coordinate as the center; and an area overlapping unit, used to detect whether the first area graphic and the second area graphic have an overlapping area. When the first area graphic and the second area graphic have an overlapping area, it is judged that the positions of the wafer defect and the chip failure match.

16. The wafer defect and chip failure location matching system according to claim 15, wherein: The first area graphic includes: a circle, a square or an equilateral triangle.

17. The wafer defect and chip failure location matching system according to claim 11, wherein: The chip to be detected includes: a memory chip.

18. The wafer defect and chip failure location matching system according to claim 17, wherein: The chip failure in the chip to be detected includes: a failure of a storage unit in a storage array.

19. The wafer defect and chip failure location matching system according to claim 11, wherein: The wafer defect detection equipment includes: one or more of a bright field detection system, a dark field detection system, a broadband plasma pattern wafer defect detection system, an electron beam detection system, and a defect review electron microscope.

20. The wafer defect and chip failure location matching system according to claim 11, wherein: The chip failure detection equipment includes: a yield test system.

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