Wafer defect classification method, model training method, system, equipment and medium

Abstract

The embodiment of the invention provides a wafer defect classification method, a model training method, a system, equipment and a medium. According to the wafer defect classification scheme provided by the invention, the multi-modal test information of the wafer can be acquired, so that a plurality of test maps generated based on the multi-modal test information of the wafer are used as the basis of wafer defect classification, and the test information of different modals (namely, different dimensions) is considered during wafer defect classification; therefore, the accuracy of the classification result can be improved, and an actual manual wafer defect analysis mode can be met. Wherein the plurality of test maps comprise at least two types of maps, and one type of map is generated based on one type of modal test information.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a wafer defect classification method, model training method, system, equipment and medium. Background Art

[0002] Wafers are the silicon wafers used to produce semiconductor integrated circuits. Any process in the manufacturing process can introduce defects. To prevent defective wafers from entering the subsequent packaging process, wafer defects must be identified and classified to analyze their causes and improve the manufacturing process.

[0003] Existing wafer defect classification technology solutions mostly use deep learning methods to identify and analyze wafer images formed by optical scanning equipment during the wafer manufacturing process. However, this method can only identify wafer surface defects (such as mechanical damage, surface redundancy, etc.) and cannot effectively identify wafer electrical performance defects. Summary of the Invention

[0004] In view of the above problems mentioned in the background technology, the present application provides a wafer defect classification method, model training method, system, device and medium that solve the above problems or at least partially solve the above problems. Specifically,

[0005] In a first embodiment, the present application provides a wafer defect classification method. The method includes:

[0006] Obtain multimodal test information of wafers;

[0007] Based on the multimodal test information of the wafer, a plurality of test patterns are generated; wherein the plurality of test patterns include at least two types of patterns, and one type of pattern is generated based on one type of modal test information;

[0008] Determine a defect classification result of the wafer based on the multiple test patterns.

[0009] In a second embodiment, the present application provides a model training method. The method includes:

[0010] Obtaining a training sample set; wherein the training sample set includes training sample data corresponding to multiple wafer defect types, the training sample data including: multiple sample maps and sample attention maps; the multiple sample maps have at least two types of sample maps, one type of sample map is generated based on a modal sample test information of the sample wafer;

[0011] Using the training sample set, training a machine learning model to obtain a multi-classification model for wafer defect classification;

[0012] Selecting test sample data of various wafer defect types from training sample data of various wafer defect types;

[0013] The multi-classification model is tested using test sample data of various wafer defect types.

[0014] In a third embodiment, the present application provides a wafer defect classification system. The system includes:

[0015] A testing device is used to test a wafer to obtain multimodal test information of the wafer; and send the multimodal test information to a processing device;

[0016] A processing device is connected to the testing device and is used to generate a plurality of test patterns based on the multimodal test information; wherein the plurality of test patterns have at least two types of patterns, and one type of pattern is generated based on one modal test information; and a defect classification result of the wafer is determined based on the plurality of test patterns.

[0017] In a fourth embodiment, the present application provides an electronic device. The electronic device includes a memory and a processor, wherein the memory is configured to store a program; and the processor is coupled to the memory and configured to execute the program stored in the memory to implement the steps of each method embodiment provided in the present application.

[0018] In a fifth embodiment, the present application provides a computer-readable storage medium having a computer program stored therein; when the computer program is executed by a processor, the steps of each method embodiment provided in the present application can be implemented.

[0019] The technical solutions provided in the embodiments of the present application use multiple test maps generated based on the multimodal test information of the wafer as the basis for wafer defect classification when performing wafer defect classification, thereby taking into account test information of different modes (i.e., different dimensions) when classifying wafer defects. This is conducive to improving the accuracy of the classification results and is more in line with the actual method of artificial wafer defect analysis; wherein, the above-mentioned multiple test maps have at least two types of maps, and one type of map is generated based on one modal test information. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1A schematic diagram of a wafer provided in one embodiment of the present application;

[0022] Figure 2 A schematic diagram of a process flow of a wafer defect classification method provided in one embodiment of the present application;

[0023] Figure 3A An example schematic diagram of a wafer test provided in one embodiment of the present application;

[0024] Figure 3B A schematic diagram of the wafer defect classification principle provided in one embodiment of the present application;

[0025] Figure 4 A schematic diagram comparing the processing of standard convolution and depthwise separable convolution provided in one embodiment of the present application;

[0026] Figure 5 A schematic diagram of the partitioning of a test map provided in an embodiment of the present application;

[0027] Figure 6 A schematic flow chart of a wafer defect classification method provided in another embodiment of the present application;

[0028] Figure 7 A schematic structural diagram of a wafer defect classification device provided in one embodiment of the present application;

[0029] Figure 8 A schematic diagram of the structure of a model training device provided in one embodiment of the present application;

[0030] Figure 9 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0031] After wafer manufacturing is complete, defect analysis is performed to determine whether the wafer has defects and, if so, the corresponding defect classification. This defect analysis can effectively prevent defective wafers from entering the subsequent packaging process, improving the yield of semiconductor devices. Furthermore, wafer defect classification makes it easier to identify the causes of wafer defects, thereby improving the wafer manufacturing process.

[0032] An existing wafer defect classification technology solution is to use deep learning methods to identify and analyze wafer images, where the wafer image is obtained by scanning the wafer with optical equipment during the wafer manufacturing process. However, this method can only identify surface defects of the wafer, such as mechanical damage, surface redundancy, etc., and cannot well identify the electrical performance defects of the wafer. There is also an existing wafer defect classification technology solution that determines the wafer defect classification based on the Bin information in the wafer test data (electrical performance test data). Although this method can identify the electrical performance defects of the wafer to a certain extent, the defect classification is determined based on a single information and has low accuracy.

[0033] To solve the above problems, the design idea of ​​wafer defect classification in this application is: taking into account the actual wafer defect analysis scenario, relevant industry experts (such as yield engineers) will compare and refer to the Bin map and FSA map to obtain the corresponding wafer defect classification results, among which the Bin map and FSA map are test maps drawn according to the Bin information and FSA information in the wafer test data respectively; based on this, this application will realize wafer defect classification by integrating multiple modal test information (such as Bin information and FSA information) in the wafer test data, and at the same time, it will combine the prior knowledge of industry experts when analyzing wafer defect problems, so that the final wafer defect classification effect can achieve relatively good results.

[0034] The detailed description of the above-mentioned wafer testing, Bin information, and FSA information will be provided in the relevant content of the glossary below and will not be repeated here.

[0035] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0036] Some processes described in the specification, claims, and figures of this application include multiple operations that appear in a specific order. These operations may be executed in a different order than the order in which they appear in this document, or in parallel. Operation numbers, such as 101 and 102, are simply used to distinguish between different operations and do not imply any order of execution. Furthermore, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that terms such as "first" and "second" are used herein to distinguish between different messages, devices, modules, etc., and do not imply a sequential order, nor do they limit "first" and "second" to different types. The term "or / and" in this application simply describes an association relationship between associated objects, indicating that three possible relationships can exist. For example, "A or / and B" indicates that A can exist alone, A and B can exist simultaneously, or B can exist alone. The character " / " in this application generally indicates that the associated objects are in an "or" relationship. It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a product or system comprising a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements that are inherent to such product or system. In the absence of further restrictions, an element defined by the statement "comprising a ..." does not exclude the presence of other identical elements in the product or system comprising the element. In addition, the following embodiments are only some of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0037] Before introducing the technical solutions provided by the embodiments of this application, some terms involved in this application are first explained.

[0038] A wafer is a silicon wafer used to make semiconductor devices. It's made from silicon. A wafer contains multiple unpackaged chips (also called dies). For example, a single wafer can hold over 1,000 chips. Figure 1 An example of a wafer A is shown.

[0039] A chip (die), also often called a grain, is a grid on a wafer. Figure 1 The grid a1 on the wafer A shown in FIG. 1 is one chip.

[0040] Circuit Probing (CP), also known as wafer probe testing, is a process between wafer manufacturing and packaging in the semiconductor device manufacturing process. Specifically, it refers to the use of test equipment to perform electrical performance testing on each chip on the wafer under different test environments (such as temperature environments) after wafer manufacturing is completed and before slicing and packaging, in order to determine whether the electrical performance parameters (such as voltage, current, timing, etc.) of each chip meet the pre-set specifications before the production of the corresponding semiconductor device. The above-mentioned CP testing process involves tests in different dimensions such as DC, function, and margin. DC testing mainly detects DC current and voltage parameters, which are usually performed first to determine whether to continue with other dimensional tests. Specifically, DC testing includes but is not limited to the following test items: connectivity test, open / short circuit test (used to detect whether there is an open circuit or short circuit in the chip pin), input circuit test, leakage current test, power supply current test, and threshold voltage test. Function testing primarily detects whether logical functions operate correctly. Taking memory wafers as an example, Function testing refers to detecting whether the logical functions (such as read, write, and storage) of each memory cell in the memory chip on the wafer can operate normally. Function testing includes scan testing. Scan testing refers to treating the entire chip as a collection of a large number of registers and the combinational logic between registers. By inserting the registers into the scan chain, the fault model established based on physical defects is solved to generate structural test vectors to complete the test of the chip's digital logic. Margin testing primarily detects whether it can operate normally under various boundary parameter conditions, such as maximum voltage, minimum voltage, load range, and ambient temperature range.

[0041] A wafer test map, which can be simply referred to as a test map, refers to an image formed by recording the corresponding test information of the wafer at a spatial position directly related to the wafer.

[0042] Bin map is a wafer test map formed based on the bin information obtained through CP testing, and is a test analysis indicator for wafers. Bin information is a modal test information obtained by testing the chip (die) on the wafer. When forming the corresponding wafer test map, the test results of different chips will be marked at the position of each chip with different colors, shapes or codes (such as letters, numbers or special symbols, etc.). Among them, multiple test items can be tested with the chip (die) as the unit, and each test item is generally defined as a character or special symbol to indicate the failure (fail) of the test item, which is called the chip's Bin information. For example, when performing a Function test, if any chip on the wafer fails to read or write, then the chip will be defined as F. After the Function test is completed, the corresponding Bin information of the chip on the wafer can be obtained, and a Bin map can be formed based on the Bin information. For example, during the open / short test within DC testing, if any chip on the wafer has an open or short pin, that chip will be marked as "!". After the open / short test is complete, the corresponding binning information for each chip on the wafer can be obtained, and a bin map can be generated based on this binning information. As mentioned above, the bin map is a macro representation of the chip's electrical performance test. By defining failed chips with different symbols, the bin map reflects the corresponding electrical performance level of each chip at a macro level.

[0043] FSA (Failure Shape Analysis) map is another type of wafer test map formed based on the FSA information obtained through CP testing. FSA information is another type of modal test information obtained from the microscopic perspective of the chip on the wafer, by testing the failure degree and failure cause of each storage unit in the chip as a unit. The test of memory chips will involve this type of FSA information, but the test of logic chips will not. Memory chips refer to chips mainly used for data storage and reading, including random access memory (RAM), read-only memory (ROM) and flash memory (Flash), among which RAM includes dynamic random access memory (DRAM). Logic chips refer to chips mainly used to implement various logical functions such as calculation, comparison, and control. As can be seen from the above, the FSA map is a microscopic representation of the chip electrical performance test.

[0044] Detractor (defect), in this application, refers to wafer defects, and refers to common problems obtained by analyzing chip failure modes in CP data (including Bin, FSA information, etc.) obtained by CP testing, and is the target of wafer defect classification algorithm identification. Traditionally, yield engineers generally manually summarize chip failure modes by analyzing binary views from different bin level perspectives, bin maps and FSA maps formed after fusion of different bins, and classify the same type of failure modes into a common problem. After confirming this type of common problem through on-site analysis and diagnosis, it is called a Detractor. Manual identification of Detractors will bring a large workload to yield engineers. For this reason, it is necessary to realize automatic identification of Detractors to facilitate the discovery of common problems in batches, thereby guiding on-site equipment personnel to purposefully adjust equipment to improve product yield.

[0045] Figure 2 The flowchart of the wafer defect classification method provided by an embodiment of the present application is shown. The execution subject of the method can be a wafer defect classification device, which can be a hardware with an embedded program integrated in an electronic device, or an application software installed in the electronic device, or a tool software embedded in the device operating system, etc. The embodiment of the present application does not limit this. The electronic device can be Figure 3A The processing device 20 shown in FIG. 2 may be a client device, which may be any terminal device such as a desktop computer, a laptop computer, a tablet computer, a smart phone, etc. Figure 2 As shown, the wafer defect classification method includes the following steps:

[0046] 101. Obtain multimodal test information of the wafer;

[0047] 102. Generate a plurality of test spectra based on multimodal test information of the wafer; wherein the plurality of test spectra include at least two types of spectra, and one type of spectra is generated based on one type of modal test information;

[0048] 103. Determine a defect classification result of the wafer based on the multiple test spectra.

[0049] In the above 101-102, the wafer is a memory wafer, such as a DRAM wafer. Accordingly, each chip on the wafer is a memory chip. A memory chip has multiple logical banks (arrays), and a logical bank contains multiple memory cells (bits). For example, a memory chip contains 8192×8192 bits, where 64 bits can form a logical bank.

[0050] After using test equipment to perform various types of tests on wafers in different test units under different test environments, corresponding CP test data will be obtained. The CP test data is a table-type structured data (see Figure 3B The CP data shown in Figure 1 contains multimodal test information obtained by testing the wafer in different test units. For example, the binning information obtained by testing the wafer using the chips on the wafer as the unit is one type of wafer modal test information; the FSA information obtained by testing the wafer using the memory cells in the chips on the wafer as the unit is another type of wafer modal information, and so on.

[0051] For example, the aforementioned testing equipment often includes a probe machine and a tester. The probe machine includes a probe station and a probe card. The probe station is used to support the wafer and push the probe card so that the probes on the probe card can connect with the pins of the chip on the wafer. The probe card is the connecting medium between the tester and the wafer. The tester applies input signals to the chip on the wafer and collects output signals to determine whether the chip performance and function meet the design specifications under different operating conditions.

[0052] Each type of test performed on wafers using test equipment has multiple test items. Each time a wafer is tested for a test item, test information corresponding to that test item is generated. Therefore, any modal test information in the multimodal test information includes at least one piece of test information, with one piece of test information corresponding to one test item.

[0053] Figure 3A An example of wafer testing is shown. Figure 3A In the embodiment, the test equipment is used to perform three types of tests on the wafers, namely DC, Function, and Margin, under four test environments, namely aging, front-end high temperature, front-end low temperature, and back-end high temperature. Each test type has multiple test items. For example, the DC test type has test items such as short circuit and open circuit. In this embodiment, there are a total of more than 100 test items under these three types of tests. Each time a test item is tested on a pair of wafers, test information corresponding to the test item will be generated. After the wafer test is completed, the test equipment will also obtain the CP test data of the wafer, which contains structured multimodal test information. Each modal test information in the multimodal test information contains test information corresponding to at least one test item. For example, the format of the CP test data is as follows:

[0054]

[0055] The pos(x,y) in the bin map represents the coordinate information of the corresponding chip on the wafer, and the corresponding value represents the test result of the chip. The pos(x,y) in the fas map represents the coordinate information of the storage unit on the corresponding chip, and the corresponding value represents the test result of the storage unit.

[0056] When testing the chip on the wafer as a unit, the definition of the Bin Code (Bin mark) indicator corresponding to the chip under different test items can be shown in the following Table 1:

[0057] Table 1

[0058]

[0059] For example, the symbol "!" is defined for the power short circuit test item to indicate that the chip has failed the test result corresponding to the power short circuit test item. For the meaning of other symbols, please refer to the relevant content of the symbol "!".

[0060] When testing the memory cells in the chip on the wafer as a unit, the corresponding FSA indicator definition can be shown in Table 2 below:

[0061] Table 2

[0062]

[0063] Based on the above content, the above step 101 of “obtaining multimodal test information of a wafer” may include the following steps:

[0064] 1011. Obtain CP test data of the wafer;

[0065] 1012. Obtain the multimodal test information from the CP test data of the wafer; wherein each type of modal test information includes test information corresponding to at least one test item.

[0066] Furthermore, the multimodal test information includes: chip classification information (bin information) obtained by testing chips on a wafer as a unit, and storage unit failure information (FSA information) obtained by testing storage units in a chip as a unit. Of course, other modal test information may also be included in other embodiments based on actual expansion needs.

[0067] Further, see Figure 3BBy reconstructing each piece of multimodal test information and converting it into a graph, corresponding test graphs can be obtained. After the graphing is completed, for example, dozens of test graphs can be obtained. These dozens of test graphs have at least two types of graphs, such as Bin-type test graphs and FSA-type test graphs. Each type of test graph is generated based on a type of modal test information, and each type of test graph contains at least one test graph belonging to that type of test graph. For example, a Bin-type test graph contains multiple Bin maps, and a corresponding Bin map can be generated based on each sub-Bin information in the Bin modal test information.

[0068] The above-mentioned multiple test maps are subsequently used to analyze the defect classification of the wafer, so that the defect classification takes into account the test information of multiple dimensions of the wafer, which is conducive to improving the accuracy of the classification results. In order to further improve the accuracy of the classification results, the present embodiment also converts the prior knowledge formed in the process of analyzing the wafer defect problem by relevant industry experts (such as yield engineers) into a data form that can be used by the algorithm (i.e., attention map, Attention map), as part of the input of the wafer defect classification analysis of this application. During the conversion, the type of map of concern, the area in the spectrum, and other attention rule information can be defined for various wafer defect types based on prior knowledge. Based on this content, between the above-mentioned steps 102 and 103, the following steps may also be included:

[0069] G1. Construct attention maps corresponding to various wafer defect types.

[0070] Accordingly, the above step 103 of “determining defect classification results of the wafer according to the multiple test patterns” may specifically include:

[0071] 1031. Determine a defect classification result of the wafer based on the multiple test patterns and the attention maps corresponding to the multiple wafer defect types.

[0072] In one feasible technical solution, the above-mentioned G1 "constructs attention maps corresponding to various wafer defect types", which may specifically include:

[0073] G11. Obtain attention rules defined for various wafer defect types; the attention rules include the spectrum type, attention area information in the spectrum, and area requirements for the attention area; the attention area information includes at least one attention area and value information of each attention area.

[0074] G12. Select a target test pattern that meets the corresponding focus rule for each defect type from the multiple test patterns.

[0075] G13. Based on the target test maps and the focus areas corresponding to the various wafer defect types, construct attention maps corresponding to the various defect types.

[0076] In the above G11, the wafer defect types include but are not limited to the following: edge failure (generally refers to the failure of the chip in the center area of ​​the wafer), center failure (generally refers to the failure of the chip in the center area of ​​the wafer), random failure (the failed chips on the wafer are irregular), local concentrated failure (generally refers to the failed chips on the wafer being in a relatively concentrated area), strip failure (generally refers to the failed chips on the wafer being in a strip shape), etc.

[0077] The attention rules corresponding to various wafer defect types are defined based on the prior knowledge of manual analysis of wafer defects. Specifically, if the first wafer defect type is one of multiple wafer defect types, the attention rules defined for the first wafer defect type may include: the atlas type of attention, the attention area information in the atlas under the atlas type. The above-mentioned attention area information refers to the area information that needs to be paid attention to in the atlas, which may specifically include: the attention area, the area value defined for the attention area, and the area requirements. The area value reflects: the importance of the area characteristics of the attention area in the corresponding atlas when analyzing whether the wafer belongs to the first wafer defect type. The area values ​​defined for different attention areas may be the same or different, and this embodiment does not limit this. For example, the area values ​​defined for different attention areas may all be 1. The area requirements reflect: under what requirements the attention area in the atlas needs to meet before the atlas can be used as a basic map (which can also be understood as the target test map described below) for generating the attention map corresponding to the first wafer defect type.

[0078] See Figure 5 The Bin map and FSA map shown in the figure take the first wafer defect type EDGEDO4BLC Necking (a type of edge failure) as an example. The corresponding focus rule can be:

[0079] The types of maps of interest include: Bin map, FSA map;

[0080] For the Bin map, the focus area information includes: three focus areas in the Bin map: Area C, Area D, and Area E, as well as the area values ​​and area requirements defined for the focus areas. The area requirements for the focus areas can be: the intersection area accounts for no less than 1.9% of the entire wafer area; the intersection area is the area obtained by intersecting the first and second areas; within the three areas in the Bin map: Area C, Area D, and Area A, the area containing the Bin values ​​of V, W, H, and t is defined as the first area, and the area with the corresponding FSA D04 indicator value greater than 20 is defined as the second area;

[0081] For the FSA map, the focus area information includes the three focus areas (Areas C, D, and E) on the FSA map, as well as the defined area values ​​and requirements for each area. The focus area requirement is that the average FSA DO4 value for Areas C, D, and E on the FSA map be greater than 20 and also greater than the average for Areas A and B.

[0082] It is necessary to add that: Figure 5 In the figure, examples of corresponding Bin information and FSA information are shown on the left side of the Bin map and FSA map, respectively. The bin information and FSA information are both obtained through testing.

[0083] For the attention rules corresponding to other wafer defect types except EDGE DO4 BLC Necking, please refer to the attention rules corresponding to EDGE DO4 BLC Necking given above.

[0084] The present application scheme uses prior knowledge from manual wafer defect analysis to define attention rules corresponding to various wafer defect types. This helps ensure that the attention maps subsequently constructed for various wafer defect types can effectively simulate the allocation of attention resources of the human visual system during manual wafer defect analysis and the targets of focus. In other words, the constructed attention maps are obtained by converting the experience gained by humans (industry experts) in analyzing various wafer defect types into prior inputs that can be used by the algorithm. This effectively ensures that when the corresponding machine learning algorithm model (hereinafter referred to as the machine learning model, such as the multi-classification model described below) is used to automatically analyze wafer defect classification, the machine learning algorithm model can be made sparser and have stronger generalization ability, while also ensuring that the corresponding wafer defect classification results are consistent with the human eye perception mechanism. Generalization ability refers to the ability of the machine learning algorithm model to adapt to fresh data, that is, when encountering data that has not appeared in the training data, the machine learning algorithm model can correctly handle it; sparsity refers to the fact that only a few key features or parameters in the machine learning algorithm model play a decisive role, and the rest can be eliminated or ignored.

[0085] Since there are many types of wafer defects (detractors) and the attention rules corresponding to different types of wafer defects are often different, in order to ensure that a corresponding better attention map can be constructed at a relatively fast speed to provide a good priori input for subsequent wafer defect classification analysis, this embodiment pre-establishes a universal mechanism model (also called an industry model, which is a mathematical model (algorithm model)) based on the knowledge of semiconductor wafer analysis mechanisms. This mechanism model is the attention map model, which can distill and inject information in the attention rules corresponding to different wafer defect types to achieve the generation of attention maps corresponding to different wafer defect types.

[0086] The aforementioned conductor wafer analysis mechanism knowledge includes but is not limited to: the internal mechanism of the wafer production process (such as the production environment, production equipment parameters, etc.), wafer quality indicators, related conservation equations and empirical formulas, etc. In addition, the aforementioned distillation may refer to compressing and condensing the information in the focus rules to streamline the information and retain the core information that is useful for the currently executed task. For example, if the currently executed task is to filter out the target test map from multiple test maps, the core information retained after distilling the focus information may include: the focus map type, the map focus area under the map type, and the area requirements defined for the focus area; injection may refer to injecting the focus area in the focus rule and the area value defined for the focus area into the filtered target test map to generate the corresponding attention map.

[0087] It should be noted that, in order to improve the accuracy of the initially established mechanism model (i.e., the attention model), the initial mechanism model can be trained with corresponding training data to optimize the mechanism model parameters, thereby ultimately obtaining a mechanism model with a preset accuracy. The training data may include, for example, historical internal mechanism data during the wafer production process and historical quality indicators of the wafer.

[0088] From the above, the above attention model can be used to trigger the execution of the above steps G12 to G13.

[0089] Specifically, see Figure 3B , the original generated multiple test maps and the attention rules corresponding to various defect types are input into the attention model. The attention model will then screen the multiple test maps according to the map type, the map attention area under the map type, and the area requirements defined for the attention area in the attention rules corresponding to various wafer defect types, so as to screen out target test maps that meet the corresponding attention rules for various wafer defect types. The target test maps can be one or more. Then, the attention areas contained in the attention rules corresponding to various wafer defect types and the area values ​​defined for the attention areas are injected into the corresponding target test maps. In this way, attention maps corresponding to various wafer defect types can be generated and output. The generated attention maps are binary maps.

[0090] It can be understood that injecting the area of ​​interest corresponding to a certain type of wafer defect and the area value information defined for the area of ​​interest into the corresponding target test map means: determining the target area that matches the area of ​​interest in the target test map, and replacing the value of each unit area in the target area (if the target test map is a Bin map, the value of each unit area on the target test map is the Bin value) with the area value defined in advance for the area of ​​interest. For example, if the area value defined for each area of ​​interest is 1, the value of each unit area in the corresponding target area in the target test map can be replaced with 1. The value of each unit area in other areas of the target test map except the target area can be replaced with 0, for example. Therefore, after the injection is completed, the attention map finally generated is a binary map, which can be seen in Figure 3B An example of an attention map is shown in .

[0091] Based on the above, the first wafer defect type is one of the multiple wafer defect types; and the above step G13 of "determining an attention map corresponding to the first wafer defect type based on the target test map and the focus area corresponding to the first wafer defect type" can be implemented by the following steps:

[0092] G131. Using a pre-established attention model, the attention area corresponding to the first wafer defect type and the area value defined for the attention area are injected into the corresponding target test map to obtain an attention map corresponding to the first wafer defect type.

[0093] It should be noted here that the above step G131 only shows the generation and implementation of the attention map corresponding to the first wafer defect type among multiple wafer defect types. In fact, the attention maps corresponding to various other wafer defect types except the first wafer defect type among multiple wafer defect types can also be generated using the above step G131.

[0094] Continue to see Figure 3B , the attention maps corresponding to the various wafer defect types obtained above and the multiple test maps are used as the input of the pre-trained multi-classification model, and the multi-classification model is executed to obtain the defect type classification results including the probability that the wafer belongs to each wafer defect type. Since the originally generated test maps are generally color maps, in order to reduce the amount of model data processing and improve the model classification and analysis rate, the test maps can be binarized before being input into the multi-classification model. Therefore, in an achievable technical solution, the above 1031 "determine the defect classification results of the wafer based on the multiple test maps and the attention maps corresponding to the multiple wafer defect types" includes:

[0095] 10311. Preprocess the multiple test patterns to obtain the preprocessed multiple test patterns;

[0096] 10312. Obtain a pre-trained multi-classification model;

[0097] 10313. Input the pre-processed multiple test patterns and the attention maps corresponding to the multiple wafer defect types into the multi-classification model, and output the defect classification result of the wafer;

[0098] The preprocessing includes binarization processing, and the defect classification result includes the probability that the wafer belongs to various wafer defect types.

[0099] In the above 10311, each test spectrum can be pre-processed by binarization using a corresponding binarization algorithm, wherein the binarization algorithm can be, but is not limited to, a bimodal histogram method, a threshold segmentation method, an average grayscale method, and an Ostu method.

[0100] In the above 10312, the multi-classification model can be obtained by training the machine learning model using the training sample set. Specifically, the machine learning model can be a neural network model, such as a convolutional neural network model (CNN). The training sample set includes training sample data corresponding to various wafer defect types, and the training sample data includes multiple sample maps and sample attention maps; the multiple sample maps have at least two types of sample maps, and one type of sample map is generated based on a modal sample test information of the sample wafer. For the generation of sample maps and sample attention maps, please refer to the relevant content of the test map and attention map generation described in other embodiments of this application, which will not be repeated here.

[0101] For example, if we take the neural network model for the first wafer defect type among multiple wafer defect types, then:

[0102] The neural network model is trained using training sample data of the first wafer defect type, including:

[0103] S1. Inputting the training sample data of the first wafer defect type into the neural network model, and outputting the defect classification prediction result;

[0104] S2. Optimizing a neural network model based on the defect classification prediction result and the first wafer defect type;

[0105] S3. Selecting test sample data from the training sample data corresponding to the first wafer defect type;

[0106] S4. Using the test sample data, test the optimized neural network model.

[0107] For example, the first wafer defect type is the aforementioned EDGE D04 BLC Necking wafer defect type. The training sample data corresponding to this wafer defect type may include, for example, 417 sample spectra. The training process may be as follows: 1) according to the set parameter batch size (the number of samples selected for a training session), a certain number of sample spectra (including at least two types of sample spectra) are selected from the training sample data corresponding to EDGE D04 BLC Necking, and the sample attention maps are combined to train the neural network model once to obtain the defect classification prediction results obtained from this training; 2) based on the defect classification prediction results obtained from the training and the first wafer defect type, corresponding loss information is determined, thereby optimizing the model parameters of the neural network model based on the loss information; 3) after the optimization is completed, 137 sample spectra and the corresponding sample attention maps selected from the 417 sample spectra can be used as test sample data to test the optimized neural network model and obtain test results; 4) based on the test results, whether to conduct the next training session is required. If so, the process returns to step 1). For example, if the recall rate and precision rate included in the test results are both greater than or equal to the corresponding set thresholds, the training is determined to have converged and the training is stopped; conversely, if at least one of the recall rate and the precision rate is less than the corresponding set threshold, the process returns to step 1) above for a new round of training.

[0108] In a more specific embodiment, the neural network model can be a depthwise separable convolutional model (MobileNet). The reason for selecting MobileNet is that the number of wafers coming off the production line is large and the types of wafer defects to be judged are diverse. Using a lightweight network model such as MobileNet, which has the characteristics of small number of parameters and fast operation speed, can save computational effort, achieve higher computational efficiency, and improve classification speed.

[0109] See Figure 4In standard convolution, if a 12*12*3 feature map is input, convolution with 256 5*5*3 kernels requires a total of 19,200 parameters (256*5*5*3) ​​and 2.7M multiplication-add operations. MobileNet consists of two parts: channel-wise convolution and point-wise convolution. In channel-wise convolution, the number of kernels matches the number of input channels, with each channel being convolved with only one kernel. Point-wise convolution often uses 1×1 convolution to fuse the feature maps obtained in the previous step along the channel dimension. In MobileNet, if a 12*12*3 feature map is input, convolution with three 5*5*1 kernels and 256 1*1*3 kernels requires a total of 843 parameters (3*5*5*1 + 256*1*1*3) and 0.12M multiplication operations.

[0110] In the above 10313, for example, the first wafer defect type is one of multiple wafer defect types. Based on the attention map corresponding to the first wafer defect type, the multi-classification model can determine which regional features in each test pattern require focused analysis and which regional feature information is almost useless and can be ignored. Based on this, the multi-classification model can perform feature analysis on each test pattern to determine the probability that the wafer defect belongs to the first wafer defect type. Similarly, the probability of the wafer defect belonging to other wafer defect types can also be determined.

[0111] See Figure 3B The output defect classification results include the probability that the wafer belongs to various wafer defect types. For example, the probability of belonging to wafer defect type A is a%, the probability of belonging to wafer defect type B is b%, and the probability of belonging to wafer defect type C is c%.

[0112] Furthermore, the method provided in this embodiment may further include the following steps:

[0113] 104. Display the defect classification result of the wafer on the interactive interface.

[0114] By executing step 104, the user-friendly system can be interacted with through callback values ​​or by directly pushing the data to middleware, so that the defect classification results can be displayed on the system's interactive interface. Based on the displayed defect classification results, the user can understand the probability of a wafer belonging to various wafer defect types, thereby making targeted adjustments to the wafer manufacturing equipment to improve product yield.

[0115] The technical solution provided in this embodiment, when performing wafer defect classification, on the one hand, will use multiple test maps generated based on the multimodal test information of the wafer as the basis for wafer defect classification, so that test information of different modes (i.e., different dimensions) is taken into account when classifying wafer defects, which is conducive to improving the accuracy of the classification results and is more in line with the actual method of artificial wafer defect analysis; wherein, there are at least two types of maps in the above-mentioned multiple test maps, and one type of map is generated based on a modal test information. In addition, on the other hand, the attention maps corresponding to the various wafer defect types constructed are also used as the basis for wafer defect classification, which can further improve the effect of wafer defect classification analysis.

[0116] Figure 6 FIG. 1 shows a flow chart of a model training method provided by an embodiment of the present application. Figure 6 As shown, the model training method includes the following steps:

[0117] 201. Obtain a training sample set; wherein the training sample set includes training sample data corresponding to multiple wafer defect types, and the training sample data includes: multiple sample maps and sample attention maps; the multiple sample maps have at least two types of sample maps, and one type of sample map is generated based on a modal sample test information of a sample wafer;

[0118] 202. Using the training sample set, train a machine learning model to obtain a multi-classification model for wafer defect classification and identification;

[0119] 203. Selecting test sample data of various wafer defect types from the training sample data of various wafer defect types;

[0120] 204. Test the multi-classification model using test sample data of various wafer defect types.

[0121] For the specific implementation description of the above steps 201 to 204, please refer to the relevant content in other embodiments of this application.

[0122] The above machine learning model is a neural network model, specifically, a convolutional neural network model, more specifically, MobileNet.

[0123] For the specific implementation description of the above steps in this embodiment, please refer to the relevant content in other embodiments. In addition, in addition to the above steps, the method provided in the embodiment of the present application may also include other steps. For the other steps that may be included and the specific implementation description, please refer to the relevant content in other embodiments, which will not be repeated here.

[0124] Another embodiment of the present application provides a wafer defect classification system. The wafer defect classification system can be seen in Figure 3A , including: testing equipment and processing equipment 20. Among them,

[0125] A testing device, configured to test a wafer to obtain multimodal test information of the wafer; and send the multimodal test information to a processing device 20;

[0126] A processing device 20 is connected to the test device and is used to generate multiple test maps based on the multimodal test information; wherein the multiple test maps have at least two types of maps, and one type of map is generated based on one modal test information; construct attention maps corresponding to multiple wafer defect types; determine the defect classification results of the wafer based on the multiple test maps and the attention maps corresponding to the multiple wafer defect types; and display the defect classification results of the wafer on an interactive interface.

[0127] For a detailed description of the functions of each device in this system, please refer to the relevant content in other embodiments.

[0128] In summary, the present application solution is to combine the original test data of the wafer with the mechanism knowledge to form a priori input, and combine it with deep learning to achieve end-to-end training of the automatic defect classification algorithm. Figure 3A and Figure 3B The training process involves the following Step 0-Step 2, and the final inference process after deployment involves the following Step 0-Step 3. The solution provided in this embodiment can be briefly described as follows:

[0129] Step 0: Connect to IOT (Internet of Things) data and reconstruct the collected CP data. The data of the two modes, Bin and FSA, in the CP data are mainly processed to obtain standard input.

[0130] Step 1: Using the standard input obtained in Step 0 above, combined with knowledge of semiconductor device manufacturing mechanisms, we build a generalized industry model, namely the Attention Map. This model filters the graphs based on the attention needs of different detractors and overlays the region and value information of interest. Since there are many types of detractors, and different detractors focus on different graphs, regions, and other information, we build a generalized industry model (an algorithmic model) to distill and inject the detractor's attention information. This improves the pertinence and simplicity of the data in the subsequent CNN model, greatly enhancing the algorithm's model performance. At the same time, when dealing with small sample detractors, the injected mechanism knowledge can also provide a good prior input for the model, making the model more sparse and more generalizable. In addition to the attention maps of different detractors generated based on mechanism knowledge, the Bin, FSA and other data in the original CP data are also used as inputs to the subsequent CNN model, thus ultimately forming a tensor of (B, N+2, W, H), where B is the batch size, the 2 in N+2 represents the two dimensions of the original data, N is the number of attention maps, and different detractors correspond to different numbers of attention maps. W and H represent the width and height of the wafer data, respectively.

[0131] Step 2. Based on the above Step 0-Step 1, the application can be concluded to be a multi-classification task with a multi-channel two-dimensional tensor as input. For this purpose, a CNN model can be used to perform wafer defect classification processing. Moreover, since the recognition of the Detractor is related to the pattern (failure shape) on the map, this further enhances the adaptability of using convolution to extract deep features. Among many CNN networks, this application solution chose MobileNet. This is because MobileNet uses a depth-separable convolution, which greatly reduces the number of network parameters and computational complexity by splitting the standard convolution into two consecutive steps of depth convolution and point-by-point convolution. In the problem of automatic identification of Detractors, the number of wafers is large and the types of defect problems are many. Using a lightweight network such as MobileNet can achieve higher computational efficiency.

[0132] Step 3: Output the probability that the wafer belongs to each type of Detractor. The probability result can be interacted with the user system through callback values ​​or directly pushed to the middleware.

[0133] As can be seen from the above, the present application solution takes into account the two-dimensional representation of the wafer at the same time, and takes FSA (micro-representation of electrical performance test) and Bin map (macro-representation of electrical performance test) as part of the input and inputs them into the CNN model (such as MobileNet). This method of identifying the Detractor to which the wafer belongs, which integrates multimodal test information, is consistent with the wafer defect analysis method involved in the actual semiconductor device manufacturing process, and is conducive to ensuring the accuracy of Detractor identification. Of course, in other embodiments, according to further expansion based on actual needs, CP data in other different dimensional representation forms can also be input as part of the input into the CNN model. In addition, the present application solution also integrates the empirical knowledge formed by industry experts in the process of analyzing problems, and converts the empirical knowledge into usable priori input (i.e., attention map), which is input into the CNN model, which can further improve the effect of Detractor identification analysis.

[0134] Figure 7 A schematic diagram of the structure of a wafer defect classification device provided in an embodiment of the present application, which is deployed in Figure 3A As shown in the processing device 20. Figure 7 The wafer defect classification device includes: an acquisition module 30, a generation module 31 and a determination module 33.

[0135] An acquisition module 30 is used to acquire multimodal test information of a wafer;

[0136] A generating module 31 is configured to generate a plurality of test patterns based on the multimodal test information of the wafer; wherein the plurality of test patterns include at least two types of patterns, one type of pattern being generated based on one type of modal test information;

[0137] A determination module 33 is configured to determine a defect classification result of the wafer based on the multiple test patterns;

[0138] Furthermore, the device also includes: a construction module 32, used to construct an attention map corresponding to each of the multiple wafer defect types; and a determination module 33, specifically used to: determine the defect classification result of the wafer based on the multiple test patterns and the attention maps corresponding to each of the multiple wafer defect types.

[0139] Furthermore, the chip on the wafer is a memory chip; and the multimodal test information of the wafer includes: chip grading information obtained by testing the chip as a unit, and memory unit failure information obtained by testing the memory unit in the chip as a unit.

[0140] Furthermore, the above-mentioned construction module 32, when used to construct attention maps corresponding to multiple wafer defect types, is specifically used to: obtain attention rules defined for various wafer defect types; wherein the attention rules include the map type and the attention area information in the map under the map type, and the attention area information includes the attention area, the area value defined for the attention area, and the area requirements; from the multiple test maps, select target test maps that meet the attention rules for various wafer defect types; based on the target test maps corresponding to the various wafer defect types and the attention area information, construct attention maps corresponding to the various defect types.

[0141] Furthermore, the first wafer defect type is one of the multiple wafer defect types; and when the above-mentioned construction module 32 is used to construct an attention map corresponding to the first wafer defect type based on the target test map and the focus area information corresponding to the first wafer defect type, it is specifically used to: facilitate the pre-established attention model, inject the focus area corresponding to the first wafer defect type and the area value defined for the focus area into the corresponding target test map, and obtain the attention map corresponding to the first wafer defect type.

[0142] Furthermore, the above-mentioned determination module 33, when used to determine the defect classification result of the wafer based on the multiple test patterns and the attention maps corresponding to the multiple wafer defect types, is specifically used to: preprocess the multiple test patterns to obtain the preprocessed multiple test patterns; obtain a pre-trained multi-classification model; input the preprocessed multiple test patterns and the attention maps corresponding to the multiple wafer defect types into the multi-classification model, and output the defect classification result of the wafer; wherein the preprocessing includes binarization processing, and the defect classification result includes the probability that the wafer belongs to various wafer defect types.

[0143] Furthermore, the multi-classification model is obtained by training a neural network model using a training sample set; the training sample set includes training sample data corresponding to various wafer defect types, and the training sample data includes: multiple sample maps and sample attention maps; the multiple sample maps have at least two types of sample maps, one type of sample map is generated based on a modal sample test information of the sample wafer;

[0144] The first wafer defect type is one of multiple wafer defect types; and the device adopted in this embodiment also includes: a training device, which, when used to train the neural network model using the training sample data of the first wafer defect type, is specifically used to: input the training sample data of the first wafer defect type into the neural network model, and output a defect classification prediction result; optimize the neural network model based on the defect classification prediction result and the first wafer defect type; select test sample data from the training sample data corresponding to the first wafer defect type; and use the test sample data to test the optimized neural network model.

[0145] Furthermore, the neural network model is a depth-separable convolutional model.

[0146] For a detailed description of the functions of each module in the wafer defect classification device provided in this embodiment, please refer to the reference ... Figure 2 Provided method embodiments.

[0147] Figure 8 This is a schematic diagram of the structure of the model training device provided in one embodiment of the present application, which is deployed in Figure 3A As shown in the processing device 20. Figure 8 The model training device includes: an acquisition module 41, a training module 42, a selection module 43 and a testing module 44. The acquisition module 41 is used to acquire a training sample set; wherein the training sample set includes training sample data corresponding to multiple wafer defect types, and the training sample data includes: multiple sample maps and sample attention maps; the multiple sample maps have at least two types of sample maps, and one type of sample map is generated based on a modal sample test information of a sample wafer; the training module 42 is used to use the training sample set to train the machine learning model to obtain a multi-classification model for wafer defect classification; the selection module 43 is used to select test sample data of various wafer defect types from the training sample data of various wafer defect types; the testing module 44 is used to test the multi-classification model using the test sample data of various wafer defect types.

[0148] The above machine learning module is a neural network model.

[0149] For a detailed description of the functions of each module in the model training device provided in this embodiment, please refer to the Figure 6 Provided method embodiments.

[0150] Figure 9 FIG. 1 shows a schematic diagram of the structure of an electronic device provided by an embodiment of the present application. Figure 9As shown, the electronic device includes: a memory 51 and a processor 52. The memory 51 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. Specifically,

[0151] The memory 51 is used to store programs;

[0152] The processor 52 is coupled to the memory 51 and is used to execute the program stored in the memory for performing the steps or functions in the methods provided in the embodiments of the present application.

[0153] Further, if Figure 9 The electronic device also includes other components such as a communication component 53, a display 54, a power component 55 and an audio component 56. Figure 9 Only some components are shown schematically, which does not mean that the electronic device only includes Figure 9 Components shown.

[0154] The electronic equipment is as follows Figure 3A The processing device 20 is shown in FIG.

[0155] Accordingly, an embodiment of the present application further provides a computer-readable storage medium storing a computer program, which, when executed by a computer, can implement the steps or functions of the loan management strategy determination method provided in the above embodiments.

[0156] An embodiment of the present application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the processor is enabled to implement the text processing method steps or functions provided in the above embodiments.

[0157] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by means of hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0158] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A wafer defect classification method, characterized in that: include: Obtain multimodal test information of wafers; Based on the multimodal test information of the wafer, a plurality of test patterns are generated; wherein the plurality of test patterns include at least two types of patterns, and one type of pattern is generated based on one type of modal test information; Determine a defect classification result of the wafer based on the multiple test patterns.

2. The method according to claim 1, characterized in that Also includes: Construct attention maps corresponding to various wafer defect types; And, determining a defect classification result of the wafer according to the plurality of test patterns, comprising: Determine a defect classification result of the wafer based on the multiple test patterns and the attention maps corresponding to the multiple wafer defect types.

3. The method according to claim 1, characterized in that The chip on the wafer is a memory chip; The multimodal test information of the wafer includes: chip classification information obtained by testing on a chip basis, and storage unit failure information obtained by testing on a storage unit in the chip basis.

4. The method according to claim 2, characterized in that Construct attention maps corresponding to various wafer defect types, including: Obtaining attention rules defined for various wafer defect types; wherein the attention rules include a map type and attention area information in the map under the map type, and the attention area information includes an attention area, an area value defined for the attention area, and an area requirement; Selecting, from the plurality of test patterns, target test patterns that meet the focus rule for various wafer defect types; Based on the target test maps and the focus area information corresponding to the various wafer defect types, attention maps corresponding to the various defect types are constructed.

5. The method according to claim 4, characterized in that The first wafer defect type is one of the multiple wafer defect types; as well as Constructing an attention map corresponding to the first wafer defect type based on the target test map and the attention area information corresponding to the first wafer defect type, including: Using a pre-established attention model, the attention area corresponding to the first wafer defect type and the area value defined for the attention area are injected into the corresponding target test map to obtain an attention map corresponding to the first wafer defect type.

6. The method according to any one of claims 2 to 5, characterized in that Determining a defect classification result of the wafer according to the plurality of test patterns and the attention maps corresponding to the plurality of wafer defect types, including: Preprocessing the plurality of test spectra to obtain the plurality of preprocessed test spectra; Get a pre-trained multi-classification model; Inputting the preprocessed multiple test patterns and the attention maps corresponding to the multiple wafer defect types into the multi-classification model, and outputting the defect classification results of the wafer; The preprocessing includes binarization processing, and the defect classification result includes the probability that the wafer belongs to various wafer defect types.

7. The method according to claim 6, characterized in that The multi-classification model is obtained by training the neural network model using the training sample set; The training sample set includes training sample data corresponding to various wafer defect types, and the training sample data includes: multiple sample maps and sample attention maps; the multiple sample maps have at least two types of sample maps, and one type of sample map is generated based on a modal sample test information of the sample wafer; The first wafer defect type is one of a plurality of wafer defect types; and Training the neural network model using training sample data of the first wafer defect type includes: Inputting training sample data of the first wafer defect type into the neural network model, and outputting a defect classification prediction result; Optimizing the neural network model according to the defect classification prediction result and the first wafer defect type; Selecting test sample data from the training sample data corresponding to the first wafer defect type; The optimized neural network model is tested using the test sample data.

8. The method according to claim 7, characterized in that The neural network model is a depth-wise separable convolutional model.

9. A model training method, characterized in that: include: Obtaining a training sample set; wherein the training sample set includes training sample data corresponding to multiple wafer defect types, the training sample data including: multiple sample maps and sample attention maps; the multiple sample maps have at least two types of sample maps, one type of sample map is generated based on a modal sample test information of the sample wafer; Using the training sample set, training a machine learning model to obtain a multi-classification model for wafer defect classification; Selecting test sample data of various wafer defect types from training sample data of various wafer defect types; The multi-classification model is tested using test sample data of various wafer defect types.

10. A wafer defect classification system, characterized in that: include: A testing device, used to test the wafer and obtain multimodal test information of the wafer; sending the multimodal test information to a processing device; A processing device, connected to the test device, for generating a plurality of test patterns based on the multimodal test information; wherein the plurality of test patterns include at least two types of patterns, one type of pattern being generated based on test information of one modality; Determine a defect classification result of the wafer based on the multiple test patterns.

11. An electronic device, characterized in that: include: memory and a processor, wherein The memory is used to store programs; The processor is coupled to the memory and is used to execute the program stored in the memory to implement the steps in the wafer defect classification method described in any one of claims 1 to 7, or to implement the steps in the model training method described in any one of claims 8 to 9.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program; when the computer program is executed by the processor, it can implement the steps in the wafer defect classification method described in any one of claims 1 to 8, or implement the steps in the model training method described in claim 9.

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