Pixel, display device including same, and electronic device

Abstract

According to an embodiment of the present disclosure, a pixel, a display device including the same, and an electronic device are provided. The pixel includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line via a second node, and a second electrode connected to a first electrode of the light emitting element via a third node; a light emitting element configured to output light in response to the driving current supplied from the first transistor, and including a second electrode connected to a second power line; a second transistor connected between the data line and the second node, and including a gate electrode connected to the first scan line; a third transistor including a first sub-transistor and a second sub-transistor connected in series between the first node and a third node; and a first capacitor connected between a first common node between the first sub-transistor and the second sub-transistor and the first electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2024-0037371, filed on March 18, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a pixel, a display device including the pixel, and an electronic device. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information is emerging. In response to this, the use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing.

[0005] Recently, some display devices may require both high-speed driving capabilities, which provide users with images switching at a high frame rate, and low-speed driving capabilities, which provide users with images switching at a low frame rate. To this end, a pixel is needed that can be driven at both high and low speeds and that can stably achieve brightness at both high and low grayscale levels. Summary of the Invention

[0006] The present disclosure provides a pixel that can stably achieve brightness by minimizing leakage current when achieving high grayscale and low grayscale, a display device including the pixel, and an electronic device. In some aspects, when leakage current is minimized when achieving high grayscale and low grayscale, the display device can be stably driven at high and low speeds.

[0007] An object of the present disclosure is to provide a pixel capable of constantly maintaining the direction of leakage current when realizing a high grayscale and a low grayscale, and a display device including the pixel.

[0008] According to an embodiment of the present disclosure, a pixel includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line via a second node, and a second electrode connected to a first electrode of a light-emitting element via a third node; a light-emitting element configured to output light in response to a driving current provided from the first transistor, and including a second electrode connected to the second power line; a second transistor connected between a data line and a second node, and including a gate electrode connected to a first scan line; a third transistor including a first sub-transistor and a second sub-transistor connected in series between the first node and the third node; and a first capacitor connected between a first common node between the first sub-transistor and the second sub-transistor and the first electrode of the light-emitting element.

[0009] According to an embodiment, gate electrodes of the first and second sub-transistors are connected to the second scan line, and turn-on periods of the first and second sub-transistors at least partially overlap with a turn-on period of the second transistor.

[0010] According to an embodiment, gate electrodes of the first sub-transistor and the second sub-transistor are connected to the first scan line.

[0011] According to an embodiment, the pixel also includes: a fourth transistor, which is connected in series between the first node and the third power line and includes a third sub-transistor and a fourth sub-transistor, the third sub-transistor and the fourth sub-transistor include a gate electrode connected to the third scan line; and a fifth transistor, which is connected between the first electrode of the light-emitting element and the fourth power line and includes a gate electrode connected to the fourth scan line.

[0012] According to an embodiment, the pixel further includes a second capacitor connected between the constant power and a second common node between the third sub-transistor and the fourth sub-transistor.

[0013] According to an embodiment, the pixel further includes: a sixth transistor connected between the first power line and the second node and including a gate electrode connected to the emission control line; a seventh transistor connected between the third node and the first electrode of the light-emitting element and including a gate electrode connected to the emission control line; an eighth transistor connected between the second node and the fifth power line and including a gate electrode connected to the fourth scan line; and a storage capacitor connected between the first power line and the first node.

[0014] According to an embodiment, the constant power is one of a first driving power supplied to the first power line, a second driving power supplied to the second power line, a first initialization power supplied to the third power line, a second initialization power supplied to the fourth power line, and a bias power supplied to the fifth power line.

[0015] According to an embodiment of the present disclosure, a pixel includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line via a second node, and a second electrode connected to a first electrode of a light-emitting element via a third node; a light-emitting element outputs light in response to a driving current provided from the first transistor and includes a second electrode connected to the second power line; a second transistor connected between a data line and a third node and including a gate electrode connected to a first scan line; a third transistor including a first sub-transistor and a second sub-transistor connected in series between the first node and the second node; and a first capacitor connected between a first common node between the first sub-transistor and the second sub-transistor and the first electrode of the light-emitting element.

[0016] According to an embodiment, gate electrodes of the first and second sub-transistors are connected to the second scan line, and turn-on periods of the first and second sub-transistors at least partially overlap with a turn-on period of the second transistor.

[0017] According to an embodiment, gate electrodes of the first sub-transistor and the second sub-transistor are connected to the first scan line.

[0018] According to an embodiment, the pixel also includes: a fourth transistor connected in series between the first node and the third power line, and including a third sub-transistor and a fourth sub-transistor, the third sub-transistor and the fourth sub-transistor including a gate electrode connected to the third scan line; and a fifth transistor connected between the first electrode of the light-emitting element and the fourth power line, and including a gate electrode connected to the fourth scan line.

[0019] According to an embodiment, the pixel further includes a second capacitor connected between the constant power and a second common node between the third sub-transistor and the fourth sub-transistor.

[0020] According to an embodiment, the pixel further includes: a sixth transistor connected between the first power line and the second node and including a gate electrode connected to the emission control line; a seventh transistor connected between the third node and the first electrode of the light-emitting element and including a gate electrode connected to the emission control line; an eighth transistor connected between the second node and the fifth power line and including a gate electrode connected to the fourth scan line; and a storage capacitor connected between the first power line and the first node.

[0021] According to an embodiment, the constant power is one of a first driving power supplied to the first power line, a second driving power supplied to the second power line, a first initialization power supplied to the third power line, a second initialization power supplied to the fourth power line, and a bias power supplied to the fifth power line.

[0022] According to an embodiment of the present disclosure, a display device includes pixels connected to scan lines, emission control lines and data lines, and at least one of the pixels includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line via a second node, and a second electrode connected to a first electrode of a light-emitting element via a third node; a light-emitting element configured to output light in response to a driving current provided from the first transistor and including a second electrode connected to the second power line; a second transistor connected between a specific data line in the data lines and a second node or a third node, the second transistor including a gate electrode connected to a first scan line included in the scan lines; a third transistor connected in series between the first node and the second node or the third node, the third transistor including a first sub-transistor and a second sub-transistor, the first sub-transistor and the second sub-transistor each including a gate electrode connected to a second scan line included in the scan lines; and a first capacitor connected between a first common node between the first sub-transistor and the second sub-transistor and the first electrode of the light-emitting element.

[0023] According to an embodiment, the second transistor is connected between a specific data line and a second node, and the third transistor is connected between the first node and a third node, or the second transistor is connected between the specific data line and a third node, and the third transistor is connected between the first node and the second node.

[0024] According to an embodiment, the first scan line and the second scan line are the same scan line.

[0025] According to an embodiment, the pixel further includes: a fourth transistor connected in series between the first node and the third power line, and including a third sub-transistor and a fourth sub-transistor, the third sub-transistor and the fourth sub-transistor including a gate electrode connected to a third scan line among the scan lines; a fifth transistor connected between the first electrode of the light-emitting element and the fourth power line, and including a gate electrode connected to a fourth scan line among the scan lines; and a second capacitor connected between the constant power and a second common node between the third sub-transistor and the fourth sub-transistor.

[0026] According to an embodiment, the pixel further includes: a sixth transistor connected between the first power line and the second node and including a gate electrode connected to the emission control line; a seventh transistor connected between the third node and the first electrode of the light-emitting element and including a gate electrode connected to the emission control line; an eighth transistor connected between the second node and the fifth power line and including a gate electrode connected to the fourth scan line; and a storage capacitor connected between the first power line and the first node.

[0027] According to an embodiment, the constant power is one of a first driving power supplied to the first power line, a second driving power supplied to the second power line, a first initialization power supplied to the third power line, a second initialization power supplied to the fourth power line, and a bias power supplied to the fifth power line.

[0028] According to an embodiment of the present disclosure, an electronic device includes: a display panel including pixels; a display module including a driver for controlling the display panel; and a processor configured to control the display module, and at least one of the pixels includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line via a second node, and a second electrode connected to a first electrode of a light-emitting element via a third node; a light-emitting element configured to output light in response to a driving current provided from the first transistor and including a second electrode connected to a second power line; a second transistor connected between a specific data line included in the data lines and a second node or a third node, the second transistor including a gate electrode connected to a first scan line included in the scan lines; a third transistor connected in series between the first node and the second node or the third node, the third transistor including a first sub-transistor and a second sub-transistor, the first sub-transistor and the second sub-transistor each including a gate electrode connected to a second scan line included in the scan lines; and a first capacitor connected between a first common node between the first sub-transistor and the second sub-transistor and the first electrode of the light-emitting element.

[0029] According to an embodiment, the first scan line and the second scan line are the same scan line.

[0030] The objects of the present disclosure are not limited to those described herein, and other technical objects not described will be clearly understood by those skilled in the art from the following description.

[0031] According to the pixel and the display device including the pixel according to the embodiment of the present disclosure, the leakage current direction of the driving transistor remains constant regardless of the grayscale (high grayscale and low grayscale), and thus display quality can be improved.

[0032] In some aspects, according to the pixel and the display device including the pixel according to the embodiments of the present disclosure, a gate electrode voltage change of the driving transistor due to leakage current may be minimized, and thus display quality may be improved.

[0033] However, the effects of the present disclosure are not limited to the above-described effects, and various extensions can be made within a range that does not depart from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other features of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0035] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure;

[0036] Figure 2 It shows Figure 1 FIGURES of an embodiment of a scan driver and an emission driver shown in FIGURES;

[0037] Figure 3 is a diagram illustrating a pixel according to an embodiment of the present disclosure;

[0038] Figure 4A and Figure 4B is shown driving during the write cycle Figure 3 A waveform diagram of an embodiment of the method for pixels;

[0039] Figure 5A and Figure 5B is shown driving during the hold period Figure 3 A waveform diagram of an embodiment of the method for pixels;

[0040] Figure 6 is a graph showing leakage current corresponding to a gray level supplied to a pixel;

[0041] Figure 7A and Figure 7B are shown respectively with Figure 6 Graphs of the brightness at high and low gray levels corresponding to the leakage current shown in ;

[0042] Figure 8 is a diagram illustrating a pixel according to an embodiment of the present disclosure;

[0043] Figure 9 It shows Figure 8 A graph of the leakage current of the pixel shown in;

[0044] Figure 10A and Figure 10B It is shown that due to Figure 8 A simulation diagram of the voltage change caused by the leakage current of the pixel shown in FIG.

[0045] Figure 11 is a diagram illustrating a pixel according to an embodiment of the present disclosure;

[0046] Figure 12 Is shown driving Figure 11 A waveform diagram of an embodiment of the method for a pixel shown in FIG.

[0047] Figure 13is a diagram illustrating a pixel according to an embodiment of the present disclosure;

[0048] Figure 14A and Figure 14B It is shown that due to Figure 13 A simulation diagram of the voltage change caused by the leakage current of the pixel shown in FIG.

[0049] Figure 15 is a diagram illustrating a pixel according to an embodiment of the present disclosure; and

[0050] Figure 16 is a diagram illustrating an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in various forms and is not limited to the embodiments described herein.

[0052] In order to clearly describe the present disclosure, parts not related to the description are omitted, and the same reference numerals are used throughout the specification to represent the same or similar elements. Therefore, the reference numerals described above may be used in other drawings.

[0053] In some aspects, the phrase "is the same" in the specification may mean "is substantially the same." That is, the phrase "is the same" may be sufficiently similar to allow a person of ordinary skill in the art to understand that it is the same. Other phrases may also be phrases in which "substantially" is omitted.

[0054] For functional blocks, units and / or modules, some embodiments are described in the accompanying drawings. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, line connectors and other electronic circuits. This can be formed using semiconductor-based manufacturing technology or other manufacturing technologies. The blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, optionally driven by firmware and / or software. In some aspects, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented by a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from those functions of the dedicated hardware. In some aspects, in some embodiments, without departing from the scope of the present invention, blocks, units and / or modules can be physically separated into two or more interactive discrete blocks, units and / or modules. In some aspects, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0055] The term "connection" between two configurations may include both electrical and physical connections, but is not limited thereto. For example, "connection" used based on a circuit diagram may mean electrical connection, and "connection" used based on a cross-sectional view or a plan view may mean physical connection.

[0056] As used herein, the terms "about" or "approximately" are inclusive of the stated value and include an appropriate range of deviation from the particular value as determined by one of ordinary skill in the art, in view of the measurements in question and the errors associated with the measurement of a particular quantity. For example, the term "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0057] As used herein, the term "substantially" means approximately or practically. The term "substantially equal" means approximately or practically equal. The term "substantially identical" means approximately or practically identical. The term "substantially perpendicular" means approximately or practically perpendicular. The term "substantially parallel" means approximately or practically parallel.

[0058] Although the terms "first," "second," and the like are used to describe various components, these components are not limited by these terms. These terms are used to distinguish one component from another. Therefore, within the technical spirit of the present disclosure, a first component described herein may be a second component. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0059] In some embodiments, the present disclosure is not limited to the embodiments disclosed below and can be modified and implemented in various forms. In some aspects, each of the embodiments disclosed below can be implemented alone or in combination with at least one of the other embodiments. For example, Figure 3 、 Figure 6 、 Figure 8 、 Figure 11 、 Figure 13 and Figure 15 The connection relationships between the second transistors M2 and M2a and the third transistors M3, M3a and M3b in the illustrated embodiment and other components, signal lines and / or nodes in the pixel can be combined in various ways.

[0060] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure. Figure 2 It shows Figure 1 FIG. 4 is a diagram of an embodiment of a scan driver and an emission driver shown in FIG.

[0061] refer to Figure 1 , a display device 100 according to an embodiment of the present disclosure may include a pixel unit 110 (or a display panel), a timing controller 120 , a scan driver 130 , a data driver 140 , an emission driver 150 , and a power supply 160 .

[0062] The display device 100 can display images at various image refresh rates (driving frequency or screen reproduction rate) depending on the driving conditions. The image refresh rate refers to the frequency at which data signals are written to the driving transistor of the pixel PX. For example, the image refresh rate can be called the screen scan rate or screen reproduction rate and can indicate the frequency at which the display screen is reproduced per second.

[0063] In an embodiment, the output frequency of the data driver 140 for one horizontal line (for example, pixels PX connected to the same scan line may be classified into one horizontal line (or pixel row)) and / or the output frequency of the first scan driver 132 outputting the first scan signal (or write scan signal) may be determined corresponding to the image refresh rate. For example, the image refresh rate for motion image driving may be a frequency of about 60 Hz or higher (for example, 120 Hz, 240 Hz, 360 Hz, etc.).

[0064] For example, the display device 100 may display images corresponding to various image refresh rates from 1 Hz to 360 Hz. However, this is an example, and the display device 100 may display images at an image refresh rate of 360 Hz or higher (eg, 480 Hz).

[0065] The pixel unit 110 may include pixels PX connected to scan lines (e.g., first scan lines SL11, SL12, ..., and SL1n, second scan lines SL21, SL22, ..., and SL2n, third scan lines SL31, SL32, ..., and SL3n, fourth scan lines SL41, SL42, ..., and SL4n), data lines DL1, DL2, ..., and DLm, reflection control lines EL1, EL2, ..., and ELo, and power lines PL1, PL2, PL3, PL4, and PL5 (here, n, m, o are natural numbers equal to or greater than 3).

[0066] For example, the pixel PXij located on the i-th horizontal line (or pixel row) and the j-th vertical line (or pixel column) (refer to Figure 3 ) can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the k-th emission control line ELk and the j-th data line DLj (here, i is a natural number equal to or less than n, j is a natural number equal to or less than m, and k is a natural number equal to or less than o). Here, k can be a number equal to or less than i. In an example in which each of the emission control lines EL1 to ELo is connected to the pixels PX located on one horizontal line, k can be the same number as i. In an example in which each of the emission control lines EL1 to ELo is connected to the pixels PX located on two or more horizontal lines, k can be a number less than i.

[0067] When the first scan line SL11 to SL1n is supplied with an enable first scan signal, pixels PX may be selected in units of horizontal lines, and the pixels PX selected by the enable first scan signal may receive a data signal from a data line connected thereto (one of the data lines DL1 to DLm). The pixels PX receiving the data signal may generate light of predetermined brightness in response to a voltage of the data signal.

[0068] The scan driver 130 may receive a scan driving signal SCS from the timing controller 120. The scan driving signal SCS may include at least one scan start signal and a clock signal associated with driving the scan driver 130. The scan driver 130 may generate a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal in response to the scan start signal and the clock signal.

[0069] The scan signal may have a gate-on voltage (e.g., an enable scan signal) or a gate-off voltage (e.g., a disable scan signal). Hereinafter, enabling the scan signal may refer to the gate-on voltage being supplied to the scan lines SL1, SL2, SL3, and SL4, and disabling the scan signal may refer to the gate-off voltage being supplied to the scan lines SL1, SL2, SL3, and SL4.

[0070] like Figure 2 As shown in FIG, the scan driver 130 may include a first scan driver 132, a second scan driver 134, a third scan driver 136, and a fourth scan driver 138. Depending on the design, at least some of the scan drivers 132, 134, 136, and 138 may be integrated into one driver circuit, module, etc.

[0071] The first scan driver 132 may receive the first scan start signal FLM1 and generate an enable first scan signal by inverting the first scan start signal FLM1 in response to a clock signal. The first scan driver 132 may sequentially provide the enable first scan signal to the first scan lines SL11 to SL1n. In an embodiment, the first scan driver 132 may provide the enable first scan signal during a write period of an effective period of one frame.

[0072] The second scan driver 134 may receive the second scan start signal FLM2 and generate an enable second scan signal by shifting the second scan start signal FLM2 in response to the clock signal. The second scan driver 134 may sequentially provide the enable second scan signal to the second scan lines SL21 to SL2n. In an embodiment, the second scan driver 134 may provide the enable second scan signal during a write period of an effective period of one frame.

[0073] The third scan driver 136 may receive the third scan start signal FLM3 and generate an enabled third scan signal by shifting the third scan start signal FLM3 in response to the clock signal. The third scan driver 136 may sequentially provide the enabled third scan signal to the third scan lines SL31 to SL3n. In an embodiment, the third scan driver 136 may provide the enabled third scan signal during a write period of an effective period of one frame.

[0074] The fourth scan driver 138 may receive the fourth scan start signal FLM4 and generate an enable fourth scan signal by shifting the fourth scan start signal FLM4 in response to a clock signal. The fourth scan driver 138 may sequentially provide the enable fourth scan signal to the fourth scan lines SL41 to SL4n. In an embodiment, the fourth scan driver 138 may provide the enable fourth scan signal during a write period of an effective period of one frame. In an embodiment, the fourth scan driver 138 may provide the enable fourth scan signal during a hold period included in a blanking period of one frame. In an embodiment, when the hold period is included in the effective period of one frame, the fourth scan driver 138 may provide the enable fourth scan signal during the corresponding hold period.

[0075] For example, the fourth scan driver 138 may perform one scan (i.e., provide at least one fourth scan enable signal) during a write period of one frame, and perform at least one scan according to the image refresh rate during a hold period of one frame. Here, when the image refresh rate decreases (i.e., the frame length increases), the number of hold periods included in one frame may increase because the blanking period of one frame increases. That is, when the image refresh rate decreases, the number of repetitions of the operation of providing the fourth scan enable signal may increase.

[0076] For example, Figure 3 As shown in FIG, the enabled first scan signal GW, the enabled second scan signal GC, the enabled third scan signal GI, and the enabled fourth scan signal GB provided to the P-type transistor may be a low level voltage.

[0077] exist Figure 2 , the first scan driver 132, the second scan driver 134, the third scan driver 136, and the fourth scan driver 138 are shown as being connected to the corresponding first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4, respectively, but the embodiments of the present disclosure are not limited thereto. For example, at least two of the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4 (at least two of SL1, SL2, SL3, and SL4) can be driven by one scan driver.

[0078] The data driver 140 may receive output data Dout and a data drive signal DCS from the timing controller 120. The data drive signal DCS may include a sampling signal and / or a timing signal associated with driving the data driver 140. The data driver 140 may generate a data signal based on the data drive signal DCS and the output data Dout. For example, the data driver 140 may generate an analog data signal based on the grayscale of the output data Dout. The data driver 140 may provide the data signal in units of one horizontal period.

[0079] The emission driver 150 may receive an emission driving signal ECS from the timing controller 120. The emission driving signal ECS may include an emission start signal EFLM and a clock signal associated with driving the emission driver 150. The emission driver 150 may generate an emission control signal while shifting the emission start signal EFLM in response to the clock signal.

[0080] The emission control signal may have a gate-on voltage (e.g., enabling the emission control signal) or a gate-off voltage (e.g., disabling the emission control signal). Hereinafter, enabling the emission control signal may refer to the gate-on voltage being provided to the emission control lines EL1 to ELo, and disabling the emission control signal may refer to the gate-off voltage being provided to the emission control lines EL1 to ELo.

[0081] like Figure 2 As shown in , the emission driver 150 may receive the emission start signal EFLM and generate a disable emission control signal while shifting the emission start signal EFLM in response to a clock signal. The emission driver 150 may sequentially provide the disable emission control signal to the emission control lines EL1 to ELo. Figure 3 As shown in , the emission disable control signal EM provided to the P-type transistor may be a high level voltage.

[0082] In an embodiment, the emission driver 150 may provide the emission disable control signal EM during the write period and the hold period of a frame. For example, the emission driver 150 may perform one scan during the write period of a frame and may perform at least one scan during the hold period according to the image refresh rate. Here, when the image refresh rate decreases (i.e., the frame length increases), the number of hold periods included in a frame may increase because the blanking period of a frame increases. In other words, when the image refresh rate decreases, the number of repetitions of the operation of providing the emission disable control signal EM may increase.

[0083] The timing controller 120 may receive input data Din and a control signal CS from the host system through an interface. For example, the timing controller 120 may receive input data Din and a control signal CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. The control signal CS may include various signals including a clock signal.

[0084] The timing controller 120 may generate a scan driving signal SCS, a data driving signal DCS, and an emission driving signal ECS based on the control signal CS. The scan driving signal SCS, the data driving signal DCS, and the emission driving signal ECS may be provided to the scan driver 130, the data driver 140, and the emission driver 150, respectively.

[0085] The timing controller 120 may rearrange the input data Din to fit the specifications of the display device 100. In some aspects, the timing controller 120 may correct the input data Din to generate output data Dout and provide the output data Dout to the data driver 140. In an embodiment, the timing controller 120 may correct the input data Din in response to an optical measurement result measured in a process.

[0086] The power supply 160 may generate various powers for driving the display apparatus 100. For example, the power supply 160 may generate a first driving power VDD, a second driving power VSS, a first initialization power Vint1, a second initialization power Vint2, and a bias power Vbias.

[0087] The first driving power VDD may be power that provides a driving current to the pixel PX. The second driving power VSS may be power that receives a driving current from the pixel PX. During a period in which the pixel PX is set to an emission state, the first driving power VDD may be set to a voltage higher than the voltage of the second driving power VSS.

[0088] The first initialization power Vint1 may be a power source for initializing the gate electrode of the driving transistor included in each of the pixels PX. The first initialization power Vint1 may be set to a voltage lower than the voltage of the data signal. The second initialization power Vint2 may be a power source for initializing the light emitting element LD included in each of the pixels PX (refer to Figure 3 The second initialization power Vint2 can be set to make the light emitting element LD (reference Figure 3 The bias power Vbias may be a power for applying a turn-on bias voltage to a driving transistor included in each of the pixels PX.

[0089] The first driving power VDD generated by the power supply 160 can be supplied to the first power line PL1, the second driving power VSS can be supplied to the second power line PL2, the first initialization power Vint1 can be supplied to the third power line PL3, the second initialization power Vint2 can be supplied to the fourth power line PL4, and the bias power Vbias can be supplied to the fifth power line PL5. The first power line PL1, the second power line PL2, the third power line PL3, the fourth power line PL4, and the fifth power line PL5 are commonly connected to the pixel PX, but the embodiments of the present disclosure are not limited thereto.

[0090] In an embodiment, the first power line PL1 may be included among a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the second power line PL2 may be included among a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the third power line PL3 may be included among a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the fourth power line PL4 may be included among a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the fifth power line PL5 may be included among a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. That is, in an embodiment of the present disclosure, a pixel PX may be connected to one of the first power lines PL1, one of the second power lines PL2, one of the third power lines PL3, one of the fourth power lines PL4, and one of the fifth power line PL5.

[0091] In an embodiment of the present disclosure, the display device 100 may include a flat display device, a curved display device in which a portion of the pixel unit 110 is bent, a flexible display device in which a portion can be folded or bent, and a stretchable display device in which a portion can be expanded and contracted.

[0092] In an embodiment of the present disclosure, the display device 100 may be a device that displays moving images or still images, and may include portable electronic devices such as, for example, mobile phones, smart phones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). In an embodiment of the present disclosure, the display device 100 may include electronic devices such as, for example, televisions, notebook computers, monitors, billboards, or Internet of Things (IoT) devices.

[0093] Figure 3 is a diagram illustrating a pixel according to an embodiment of the present disclosure. Figure 3 Pixels located on the i-th horizontal line and the j-th vertical line are shown.

[0094] refer to Figure 3 , a pixel PXij according to an embodiment of the present disclosure can be connected to corresponding signal lines SL1i, SL2i, SL3i, SL4i, ELk, and DLj. For example, a pixel PXij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the k-th emission control line ELk, and the j-th data line DLj. In an embodiment, the pixel PXij can further be connected to a first power line PL1, a second power line PL2, a third power line PL3, a fourth power line PL4, and a fifth power line PL5.

[0095] The pixel PXij according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit for controlling the amount of driving current supplied to the light emitting element LD.

[0096] The light-emitting element LD may be connected between a first power line PL1 and a second power line PL2. For example, a first electrode (or anode electrode) of the light-emitting element LD may be electrically connected to the first power line PL1 via a seventh transistor M7, a third node N3, a first transistor M1, a second node N2, and a sixth transistor M6, and a second electrode (or cathode electrode) of the light-emitting element LD may be electrically connected to the second power line PL2. The light-emitting element LD may generate light of a predetermined brightness in response to a drive current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0097] The light emitting element LD may be selected as an organic light emitting diode. In some aspects, the light emitting element LD may be selected as an inorganic light emitting diode such as, for example, a micro light emitting diode (LED) or a quantum dot light emitting diode. In some aspects, the light emitting element LD may be an element formed of a composite material of organic and inorganic materials. Figure 3 , the pixel PXij is shown as including a single light emitting element LD. However, in another embodiment, the pixel PXij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD may be connected to each other in series, in parallel, or in series and parallel.

[0098] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a storage capacitor Cst.

[0099] A first electrode of the first transistor M1 (or driving transistor) may be connected to the second node N2, and a second electrode of the first transistor M1 may be connected to the third node N3. In some aspects, a gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may control the amount of driving current provided from the first driving power VDD to the second driving power VSS via the light emitting element LD in response to the voltage of the first node N1.

[0100] The second transistor M2 can be connected between the j-th data line DLj and the second node N2. In some aspects, the gate electrode of the second transistor M2 can be electrically connected to the i-th first scan line SL1i. The second transistor M2 can be turned on when the enable first scan signal GW is provided to the i-th first scan line SL1i and electrically connect the j-th data line DLj and the second node N2.

[0101] The third transistor M3 may be connected between the first node N1 and the third node N3. The third transistor M3 may be a dual-gate transistor including a first sub-transistor M3_1 and a second sub-transistor M3_2. The first sub-transistor M3_1 and the second sub-transistor M3_2 may be connected in series between the first node N1 and the third node N3. In the example where the third transistor M3 is a dual-gate transistor, leakage current between the first node N1 and the third node N3 may be minimized.

[0102] The gate electrode of each of the first sub-transistor M3_1 and the second sub-transistor M3_2 can be electrically connected to the i-th second scan line SL2i. The third transistor M3 (i.e., the first sub-transistor M3_1 and the second sub-transistor M3_2) can be turned on when the enable second scan signal GC is provided to the i-th second scan line SL2i, and can electrically connect the first node N1 and the third node N3. That is, when the third transistor M3 is turned on, the first transistor M1 can be connected in a diode form.

[0103] The fourth transistor M4 may be connected between the first node N1 and the third power line PL3. The fourth transistor M4 may be a dual-gate transistor including a third sub-transistor M4_1 and a fourth sub-transistor M4_2. The third sub-transistor M4_1 and the fourth sub-transistor M4_2 may be connected in series between the first node N1 and the third power line PL3. In the example where the fourth transistor M4 is a dual-gate transistor, leakage current between the first node N1 and the third power line PL3 may be minimized.

[0104] A gate electrode of each of the third sub-transistor M4_1 and the fourth sub-transistor M4_2 may be electrically connected to the i-th third scan line SL3i. The fourth transistor M4 (i.e., the third sub-transistor M4_1 and the fourth sub-transistor M4_2) may be turned on when the enable third scan signal GI is supplied to the i-th third scan line SL3i and provide a voltage of the first initialization power Vint1 to the first node N1.

[0105] A first electrode of the fifth transistor M5 can be connected to the first electrode of the light-emitting element LD, and a second electrode of the fifth transistor M5 can be electrically connected to the fourth power line PL4. In some aspects, a gate electrode of the fifth transistor M5 can be electrically connected to the i-th fourth scan line SL4i. The fifth transistor M5 can be turned on when the enable fourth scan signal GB is provided to the i-th fourth scan line SL4i and provide a voltage of the second initialization power Vint2 to the first electrode of the light-emitting element LD.

[0106] When the voltage of the second initialization power Vint2 is supplied to the first electrode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD can be discharged. As the residual voltage charged in the parasitic capacitor of the light-emitting element LD is discharged (or removed), unintentional micro-emissions can be prevented. Therefore, the black representation capability of the pixel PXij can be improved.

[0107] A first electrode of the sixth transistor M6 can be electrically connected to the first power line PL1, and a second electrode of the sixth transistor M6 can be connected to the second node N2. In some aspects, a gate electrode of the sixth transistor M6 can be electrically connected to the kth emission control line ELk. The sixth transistor M6 can be turned off when the disable emission control signal EM is provided to the kth emission control line ELk, and can be turned on when the enable emission control signal EM is provided.

[0108] The seventh transistor M7 can be connected between the third node N3 and the first electrode of the light emitting element LD. In some aspects, the gate electrode of the seventh transistor M7 can be electrically connected to the kth emission control line ELk. The seventh transistor M7 can be turned off when the disable emission control signal EM is provided to the kth emission control line ELk, and can be turned on when the enable emission control signal EM is provided.

[0109] A first electrode of the eighth transistor M8 (or bias transistor) can be electrically connected to the fifth power line PL5, and a second electrode of the eighth transistor M8 can be connected to the second node N2. In some aspects, a gate electrode of the eighth transistor M8 can be electrically connected to the i-th fourth scan line SL4i. The eighth transistor M8 can be turned on when the enable fourth scan signal GB is provided to the i-th fourth scan line SL4i and electrically connects the fifth power line PL5 and the second node N2.

[0110] The storage capacitor Cst may be connected between the first power line PL1 and the first node N1. The storage capacitor Cst may store a voltage applied to the first node N1.

[0111] exist Figure 3 , the transistors M1 to M8 are shown as P-type transistors, but the embodiments of the present disclosure are not limited thereto. Some of the transistors M1 to M8 (eg, M3 and M4) may be N-type transistors.

[0112] Figure 4A and Figure 4B is shown in Figure 1. During the write cycle WP, the drive Figure 3 The writing period WP may be included in the effective period of the frame.

[0113] refer to Figures 3 to 4BThe write period WP may include a first period P1, a second period P2, a third period P3, and a fourth period P4. The first to third periods P1 to P3 may be set as non-emission periods, and the fourth period P4 may be set as an emission period.

[0114] The emission control signal EM may be provided to the k-th emission control line ELk during the first to third periods P1 to P3. In the example where the emission control signal EM is provided to the k-th emission control line ELk, the sixth transistor M6 and the seventh transistor M7 are turned off. In the example where the sixth transistor M6 and the seventh transistor M7 are turned off, the electrical connection between the first power line PL1 and the light emitting element LD is cut off, and thus the light emitting element LD is set to a non-emission state.

[0115] During the first period P1, the third scan line SL3i is provided with an enable signal GI. In the example where the third scan line SL3i is provided with the enable signal GI, the fourth transistor M4 is turned on. In the example where the fourth transistor M4 is turned on, the voltage of the first initialization power Vint1 of the third power line PL3 can be provided to the first node N1. In the example where the voltage of the first initialization power Vint1 is provided to the first node N1, the gate electrode of the first transistor M1 (i.e., the first node N1) can be initialized to the voltage of the first initialization power Vint1. In some aspects, when the voltage of the first initialization power Vint1 is provided to the first node N1, the first transistor M1 can be set to an on-bias state.

[0116] During the second period P2, the enable second scan signal GC is supplied to the i-th second scan line SL2i, and thus the third transistor M3 is turned on. In the example where the third transistor M3 is turned on, the first transistor M1 may be diode-connected.

[0117] During a write period P_W that overlaps with the second period P2, an enable first scan signal GW is supplied to the i-th first scan line SL1i. In the example where the enable first scan signal GW is supplied to the i-th first scan line SL1i, the second transistor M2 is turned on. In the example where the second transistor M2 is turned on, a data signal can be supplied from the j-th data line DLj to the second node N2. Because the first transistor M1 maintains a diode connection via the turned-on third transistor M3, the first node N1 can have a voltage where the threshold voltage of the first transistor M1 is compensated by the data signal.

[0118] During the third period P3, the fourth scan signal GB is enabled and supplied to the i-th fourth scan line SL4i. When the fourth scan signal GB is enabled and supplied to the i-th fourth scan line SL4i, the fifth transistor M5 and the eighth transistor M8 are turned on. When the fifth transistor M5 is turned on, the voltage of the second initialization power Vint2 can be supplied to the first electrode of the light-emitting element LD, thereby initializing the light-emitting element LD. When the eighth transistor M8 is turned on, the voltage of the bias power Vbias is supplied to the second node N2. When the voltage of the bias power Vbias is supplied to the second node N2, the first transistor M1 can be set to a biased on state.

[0119] In the fourth period P4, the emission enable control signal EM (or a low-level emission control signal) is provided to the k-th emission control line ELk, and thus the sixth transistor M6 and the seventh transistor M7 are turned on. In the example where the sixth transistor M6 and the seventh transistor M7 are turned on, a current flow path is formed that is connected to the second power line PL2 via the first power line PL1, the sixth transistor M6, the first transistor M1, the seventh transistor M7, and the light-emitting element LD. At this time, according to the operation of the first transistor M1, a drive current corresponding to the voltage of the first node N1 can flow through the light-emitting element LD, and the light-emitting element LD can generate light of a predetermined brightness corresponding to the drive current.

[0120] In some aspects, such as Figure 4A As shown in , the widths of the second and third scanning signals GC and GI can be set to be wider than the width of the first scanning signal GW. Figure 4B As shown in , the widths of the second and third scanning signals GC and GI may be substantially the same as the width of the first scanning signal GW. In an embodiment of the present disclosure, the widths of the scanning signals GW, GC, GI, and GB may be set differently so that the display device 100 can be stably driven.

[0121] Figure 5A and Figure 5B It shows that the drive Figure 3 The waveform diagram of an embodiment of the method for displaying a pixel PXij is shown. The hold period MP is a period during which light is emitted while maintaining the voltage of a previously provided data signal, and is a period during which an image is displayed without switching frames. In an embodiment, a frame may include one write period WP during the active period. In an embodiment, a frame may include at least one hold period MP in response to the image refresh rate. In an example in which a frame includes multiple hold periods MP, the multiple hold periods MP may be provided consecutively after the write period WP.

[0122] During the hold period MP, the threshold voltage compensation operation and the data write operation can be omitted compared to the write period WP, ​​and the operation of applying the bias voltage to the first transistor M1 and the operation of initializing the light-emitting element LD can be performed. The hold period MP can be set to a length similar to or the same as the length of the write period WP. The hold period MP can include a first period P1a, a second period P2a, a third period P3a, and a fourth period P4a.

[0123] refer to Figures 3 to 5B , the disable emission control signal EM is supplied to the kth emission control line ELk in the first to third periods P1a to P3a. In the example where the disable emission control signal EM is supplied to the kth emission control line ELk, the sixth transistor M6 and the seventh transistor M7 are turned off, and thus the light emitting element LD is set to a non-emission state.

[0124] The first scan signal GW, the second scan signal GC, and the third scan signal GI are not provided (or the disabled scan signals GW, GC, and GI are provided) during the first to third periods P1a to P3a. Therefore, the second transistor M2, the third transistor M3, and the fourth transistor M4 are set to an off state during the first to third periods P1a to P3a.

[0125] The enabled fourth scan signal GB may be supplied to the i-th fourth scan line SL4i in the third period P3a. In the example where the enabled fourth scan signal GB is supplied to the i-th fourth scan line SL4i, the fifth transistor M5 and the eighth transistor M8 may be turned on.

[0126] When the fifth transistor M5 is turned on, the voltage of the second initialization power Vint2 can be supplied to the first electrode of the light emitting element LD, thereby initializing the light emitting element LD. In the example where the eighth transistor M8 is turned on, the voltage of the bias power Vbias is supplied to the second node N2. In the example where the voltage of the bias power Vbias is supplied to the second node N2, the first transistor M1 can be set to a conductive bias state.

[0127] Since one frame includes the write period WP and the hold period MP, the display device 100 according to the embodiment of the present disclosure described herein can be driven at various image refresh rates. For example, by including the write period WP and the hold period MP in one frame, the display device 100 can emit light at regular cycles or may not emit light at regular cycles regardless of the image refresh rate, and thus can be driven at various image refresh rates.

[0128] Figure 6 is a graph showing leakage current corresponding to the gray level supplied to the pixel PXij. Figure 6In the figure, the solid arrow may indicate the direction of the leakage current associated with the high gray level, and the dotted arrow may indicate the direction of the leakage current associated with the low gray level. Here, the range of the high gray level and the range of the low gray level may be set differently according to the type of the display device 100 (e.g., resolution, size of the display panel, etc.). For example, the high gray level may refer to approximately 100 gray levels or greater, and the low gray level may refer to 30 gray levels or less, but the embodiments of the present disclosure are not limited thereto.

[0129] Figure 7A and Figure 7B are shown respectively with Figure 6 The leakage current corresponding to the brightness of high gray level and low gray level is shown in the figure. Figure 7A and Figure 7B In FIG. 1 , it is assumed that one frame 1F includes 8 hold periods MP.

[0130] refer to Figure 6 When the pixel PXij displays a high grayscale, the voltage of the first node N1 may be set low. Here, since the voltage of the first initialization power Vint1 is set lower than the voltage of the first node N1, leakage current may flow from the first node N1 to the third power line PL3.

[0131] In some aspects, when the voltage of the first node N1 is set to low, a large amount of driving current can be supplied from the first power line PL1 to the first electrode (or third node N3) of the light emitting element LD, and thus the first electrode (or third node N3) of the light emitting element LD can be set to a high voltage. In this case, leakage current may flow in a direction from the third node N3 to the first node N1.

[0132] When the leakage current is supplied in the direction from the third node N3 to the first node N1, the voltage of the first node N1 may increase. Figure 7A As shown in , the brightness of the pixel PXij may gradually decrease over time.

[0133] When the pixel PXij displays a low grayscale, the voltage of the first node N1 may be set high. Here, since the voltage of the first initialization power Vint1 is set lower than the voltage of the first node N1, leakage current may flow from the first node N1 to the third power line PL3.

[0134] In some aspects, when the voltage of the first node N1 is set to high, a small amount of driving current may be supplied from the first power line PL1 to the first electrode (or third node N3) of the light emitting element LD, and thus the first electrode (or third node N3) of the light emitting element LD may be set to a low voltage. In this case, leakage current may flow in a direction from the first node N1 to the third node N3.

[0135] When the leakage current is supplied in the direction from the first node N1 to the third node N3, the voltage of the first node N1 may decrease. Figure 7B As shown in , the brightness of the pixel PXij may gradually increase over time.

[0136] That is to say, in Figure 3 In the case of a pixel PXij, the brightness may gradually decrease during one frame period at a high gray level, and the brightness may gradually increase during one frame period at a low gray level. In the example described herein where the brightness increases or decreases in response to the gray level, it is difficult to tune the display device 100 to have a desired brightness.

[0137] For example, various methods can be proposed to compensate for the reduction in brightness at high gray levels. For example, the width of the emission control signal EM provided in the hold period MP can be controlled so that the brightness gradually increases during one frame period. However, when the width of the emission control signal EM is controlled so that the brightness gradually increases, the brightness may increase rapidly at low gray levels.

[0138] Figure 8 is a diagram showing a pixel according to an embodiment of the present disclosure. Figure 8 In the description of Figure 3 Those configurations are the same configuration, and overlapping descriptions are omitted.

[0139] refer to Figure 8 , a pixel PXija according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit for controlling the amount of driving current supplied to the light emitting element LD.

[0140] The light emitting element LD may generate light of predetermined brightness in response to a driving current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0141] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a storage capacitor Cst, a first capacitor C1, and a second capacitor C2.

[0142] The first capacitor C1 can be connected between a first common node CN1 between the first sub-transistor M3_1 and the second sub-transistor M3_2 and the first electrode of the light-emitting element LD. The first capacitor C1 can be driven as a coupling capacitor. For example, the first capacitor C1 can change the voltage of the first common node CN1 in response to a change in the voltage of the first electrode of the light-emitting element LD. In some aspects, when the first capacitor C1 is formed between the first common node CN1 and the first electrode of the light-emitting element LD, a change in the voltage of the first common node CN1 caused by a change in the voltage of the signal lines (e.g., the scan lines SL1i, SL2i, SL3i, and SL4i and the kth emission control line ELk) can be minimized.

[0143] In some aspects, when the first capacitor C1 is connected to the first common node CN1, the amount of leakage current between the third node N3 and the first node N1 can be controlled. For example, the amount of leakage current between the third node N3 and the first node N1 can be set differently depending on the capacitance of the first capacitor C1. In an example in which the voltage of the first common node CN1 is increased by the first capacitor C1, the amount of leakage current between the third node N3 and the first node N1 can be reduced.

[0144] The second capacitor C2 can be connected between the constant power Vdc and the second common node CN2 between the third sub-transistor M4_1 and the fourth sub-transistor M4_2. Here, the constant power Vdc can be one of the powers provided to the pixel PXija. For example, the constant power Vdc can be one of the first drive power VDD, the second drive power VSS, the first initialization power Vint1, the second initialization power Vint2, and the bias power Vbias.

[0145] In reference Figure 8 In the example described, the second capacitor C2 is connected between the second common node CN2 and the constant power Vdc, which helps minimize the voltage change of the second common node CN2 caused by the voltage change of the signal lines (e.g., the scan lines SL1i, SL2i, SL3i, and SL4i and the kth emission control line ELk). In some aspects, when the second capacitor C2 is connected between the second common node CN2 and the constant power Vdc, the amount of leakage current between the first node N1 and the third power line PL3 can be reduced.

[0146] Figure 9 It shows Figure 8 Figure 2 shows the leakage current of the pixel PXija. Figure 9In the figure, the solid arrow may indicate the direction of the leakage current at a high gray level, and the dotted arrow may indicate the direction of the leakage current at a low gray level. Here, the range of the high gray level and the range of the low gray level may be set differently according to the type of the display device 100 (e.g., resolution, size of the display panel, etc.).

[0147] refer to Figure 9 When the pixel PXija displays a high grayscale, the voltage of the first node N1 may be set low. Here, since the voltage of the first initialization power Vint1 is set lower than the voltage of the first node N1, leakage current may flow from the first node N1 to the third power line PL3.

[0148] In some aspects, when the voltage of the first node N1 is set to low, a large amount of driving current can be supplied from the first power line PL1 to the first electrode (or third node N3) of the light emitting element LD, and thus the first electrode (or third node N3) of the light emitting element LD can be set to a high voltage. In this case, leakage current may flow in a direction from the third node N3 to the first node N1.

[0149] When the pixel PXija displays a low grayscale, the voltage of the first node N1 may be set high. Here, since the voltage of the first initialization power Vint1 is set lower than the voltage of the first node N1, leakage current may flow from the first node N1 to the third power line PL3.

[0150] In some aspects, when the voltage of the first node N1 is set to high, a small amount of driving current can be supplied from the first power line PL1 to the first electrode (or the third node N3) of the light emitting element LD, and thus the first electrode (or the third node N3) of the light emitting element LD can be set to a low voltage. At this time, the first electrode of the light emitting element LD can be increased from the voltage of the second initialization power Vint2 to a predetermined voltage.

[0151] In some aspects, the voltage of the first common node CN1 can increase in response to an increase in the voltage of the first electrode of the light-emitting element LD through coupling of the first capacitor C1. In the example where the voltage of the first common node CN1 increases, leakage current can flow in a direction from the first common node CN1 to the first node N1.

[0152] That is to say, in Figure 8In the pixel PXija according to an embodiment of the present disclosure shown in FIG, leakage current may flow in the same direction at high grayscales and low grayscales. The leakage current flowing in the pixel PXija may flow in the direction from the first common node CN1 to the first node N1 and in the direction from the first node N1 to the third power line PL3 regardless of the grayscale. In this case, the display device 100 can be tuned to have a desired brightness in various ways.

[0153] In some aspects, the pixel PXija may include a path through which leakage current flows into the first node N1 (in the direction from the first common node CN1 to the first node N1) and a path through which leakage current flows out of the first node N1 (in the direction from the first node N1 to the third power line PL3). In this case, the amount of voltage change at the first node N1 caused by the leakage current can be minimized, and thus the display quality can be improved. The amount of current supplied from the first common node CN1 to the first node N1 can be changed by the capacitance of the first capacitor C1. The capacitance of the first capacitor C1 can be determined experimentally to minimize the amount of voltage change at the first node N1.

[0154] Figure 10A and Figure 10B It is shown that due to Figure 8 The simulation diagram of the voltage change caused by the leakage current of the pixel PXija is shown in FIG. Figure 10A and Figure 10B In , N2 refers to the voltage of the second node N2, CN1 refers to the voltage of the first common node CN1, N1 refers to the voltage of the first node N1, CN2 refers to the voltage of the second common node CN2, and Vint1 refers to the voltage of the first initialization power Vint1. Figure 10A and Figure 10B In some aspects, in order to perform Figure 10A and Figure 10B In the simulation, the first driving power VDD is set to 4.6V, the second driving power VSS is set to -4.0V, the first initialization power Vint1 is set to -3.5V, the capacitance of the storage capacitor Cst is set to 70F, the capacitance of the first capacitor C1 is set to 8.7F, and the capacitance of the second capacitor C2 is set to 8.7F.

[0155] Figure 10AThe amount of voltage change at each of the nodes N1, N2, CN1, and CN2 corresponds to the amount of voltage change after the voltage of the data signal corresponding to the high gray level (e.g., white gray level) is applied to the pixel PXija. It can be confirmed that the voltage of the first node N1 remains constant even after a predetermined time has passed after the voltage of the data signal corresponding to the high gray level is applied to the pixel PXija. For example, the amount of voltage change in the gate-source voltage (Vgs) of the first transistor M1 can be set to approximately 0 V, and thus the pixel PXija according to an embodiment of the present disclosure can stably achieve brightness at a high gray level.

[0156] Figure 10B The amount of voltage change corresponding to each of the nodes N1, N2, CN1, and CN2 after the voltage of the data signal corresponding to a low gray level (e.g., a black gray level) is applied to the pixel PXija. In an example where the pixel PXija is driven at a low gray level, the first common node CN1 is set to a voltage higher than the voltage of the first node N1. Therefore, when the pixel PXija is driven at a low gray level, leakage current may flow from the first common node CN1 to the first node N1.

[0157] When the pixel PXija is driven at a low grayscale, the first node N1 may include a current input path (from the first common node CN1 to the first node N1) and a current output path (from the first node N1 to the third power line PL3), and thus the voltage change of the first node N1 may be minimized. For example, the voltage change of the Vgs of the first transistor M1 0.1 seconds after the data signal is provided may be set to approximately -0.01 V, and thus the pixel PXija according to an embodiment of the present disclosure may stably achieve brightness at a low grayscale.

[0158] In some aspects, at low gray levels, the voltage of the first common node CN1 may decrease after a predetermined time has passed. This may be due to leakage current supplied from the first common node CN1 to the first node N1. However, even if the voltage of the first common node CN1 decreases, the first node N1 may maintain a substantially constant voltage for a predetermined time (e.g., 0.1 seconds), and thus, a low gray level may be stably achieved in the pixel PXija.

[0159] Figure 11 is a diagram illustrating a pixel according to an embodiment of the present disclosure. Figure 12 Is shown driving Figure 11 The waveform diagram of the embodiment of the method of the pixel shown in FIG. Figure 11 In the description of Figure 8 The same configurations as those of and repeated descriptions of the same elements are omitted for the sake of brevity.

[0160] refer to Figure 11 , a pixel PXijb according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit for controlling the amount of driving current supplied to the light emitting element LD.

[0161] The light emitting element LD may generate light of predetermined brightness in response to a driving current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0162] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3a, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a storage capacitor Cst, a first capacitor C1, and a second capacitor C2.

[0163] The third transistor M3a may include a first sub-transistor M3_1a and a second sub-transistor M3_2a. The first sub-transistor M3_1a and the second sub-transistor M3_2a may be connected in series between the first node N1 and the third node N3. The gate electrode of the third transistor M3a (i.e., the first sub-transistor M3_1a and the second sub-transistor M3_2a) may be electrically connected to the i-th first scan line SL1i. The third transistor M3a may be turned on when the enable first scan signal GW is provided to the i-th first scan line SL1i, and may electrically connect the first node N1 and the third node N3. In the example where the third transistor M3a is turned on, the first transistor M1 may be connected in a diode manner.

[0164] In reference Figure 11 In the described example, the third transistor M3a is connected to the i-th first scan line SL1i, and the i-th second scan line SL2i may be omitted (or the i-th first scan line SL1i and the i-th second scan line SL2i may be the same scan line). In this case, as Figure 12 As shown in , the enabled second scan signal GC is not provided. That is, the third transistor M3a may be driven by the enabled first scan signal GW, and thus the number of signal lines connected to each of the pixels PX may be minimized.

[0165] In addition to the gate electrode of the third transistor M3a being connected to the i-th first scan line SL1i, Figure 11 The pixel PXijb shown in FIG can have Figure 8 The same configuration of pixels in PXija. Similarly, Figure 12 The method of driving the pixel PXijb shown in FIG can be compared with the reference Figure 4B For example, the basic method may be similar to or the same as that described in reference except that the third transistor M3a is driven in response to the enabling first scan signal GW supplied to the i-th first scan line SL1i. Figure 4B The methods described are similar or identical, and thus repeated descriptions of identical elements are omitted for the sake of brevity.

[0166] Figure 13 is a diagram showing a pixel according to an embodiment of the present disclosure. Figure 13 In the description of Figure 8 The same configurations as those of and repeated descriptions of the same elements are omitted for the sake of brevity.

[0167] refer to Figure 13 , a pixel PXijc according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit for controlling the amount of driving current supplied to the light emitting element LD.

[0168] The light emitting element LD may generate light of predetermined brightness in response to a driving current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0169] The pixel circuit may include a first transistor M1, a second transistor M2a, a third transistor M3b, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a storage capacitor Cst, a first capacitor C1, and a second capacitor C2.

[0170] The second transistor M2a can be connected between the j-th data line DLj and the third node N3. In some aspects, the gate electrode of the second transistor M2a can be electrically connected to the i-th first scan line SL1i. The second transistor M2a can be turned on when the enable first scan signal GW is provided to the i-th first scan line SL1i and electrically connect the j-th data line DLj and the third node N3.

[0171] The third transistor M3b may be connected between the first node N1 and the second node N2. The third transistor M3b may be a dual-gate transistor including a first sub-transistor M3_1b and a second sub-transistor M3_2b. The first sub-transistor M3_1b and the second sub-transistor M3_2b may be connected in series between the first node N1 and the second node N2. In the example where the third transistor M3b is a dual-gate transistor, leakage current between the first node N1 and the second node N2 may be minimized.

[0172] In reference Figure 13In the example described, the third transistor M3b is connected between the first node N1 and the second node N2, which supports the leakage current from the second node N2 to the first node N1 regardless of the gray level. In the example where the pixel PXijc emits light, the second node N2 can be set to the voltage of the first driving power VDD regardless of the gray level, and thus the leakage current can flow in the direction from the second node N2 to the first node N1.

[0173] The first capacitor C1 can be connected between the first common node CN1 between the first sub-transistor M3_1b and the second sub-transistor M3_2b and the first electrode of the light-emitting element LD. The first capacitor C1 can be driven as a coupling capacitor. For example, the first capacitor C1 can change the voltage of the first common node CN1 in response to the amount of change in the voltage of the first electrode of the light-emitting element LD. In this case, the amount of leakage current provided from the first common node CN1 to the first node N1 can be controlled. In the example where the first capacitor C1 is connected between the first common node CN1 and the first electrode of the light-emitting element LD, the voltage change of the first common node CN1 caused by the voltage change of the signal lines (e.g., the scan lines SL1i, SL2i, SL3i, and SL4i and the kth emission control line ELk) can be minimized.

[0174] The second capacitor C2 may be connected between the constant power Vdc and the second common node CN2 between the third sub-transistor M4_1 and the fourth sub-transistor M4_2. In an example in which the second capacitor C2 is connected between the second common node CN2 and the constant power Vdc, a voltage change of the second common node CN2 caused by a voltage change of the signal lines (e.g., the scan lines SL1i, SL2i, SL3i, and SL4i and the kth emission control line ELk) may be minimized.

[0175] In addition to Figure 8 In addition to changing the positions of the second transistor M2a and the third transistor M3b, Figure 13 The basic operation process of the pixel PXijc can be compared with Figure 8 The basic operation process of PXija is similar or the same.

[0176] When combined Figure 4A 、 Figure 4B and Figure 13When describing the operation process, the emission control signal EM can be provided to the k-th emission control line ELk during the first period P1 to the third period P3. In the example where the emission control signal EM is provided to the k-th emission control line ELk, the sixth transistor M6 and the seventh transistor M7 are turned off. In the example where the sixth transistor M6 and the seventh transistor M7 are turned off, the electrical connection between the first power line PL1 and the light emitting element LD is cut off, and thus the light emitting element LD is set to a non-emission state.

[0177] During the first period P1, the third scan line SL3i is supplied with an enable signal GI. When the third scan line SL3i is supplied with the enable signal GI, the fourth transistor M4 is turned on. When the fourth transistor M4 is turned on, the voltage of the first initialization power Vint1 of the third power line PL3 can be supplied to the first node N1. When the voltage of the first initialization power Vint1 is supplied to the first node N1, the gate electrode of the first transistor M1 (i.e., the first node N1) can be initialized to the voltage of the first initialization power Vint1.

[0178] During the second period P2, the enable second scan signal GC is supplied to the i-th second scan line SL2i, and thus the third transistor M3b is turned on. In the example where the third transistor M3b is turned on, the first node N1 and the second node N2 may be electrically connected, and thus the first transistor M1 may be connected in a diode form.

[0179] During a write period P_W that overlaps with the second period P2, an enable first scan signal GW is supplied to the i-th first scan line SL1i. In the example where the enable first scan signal GW is supplied to the i-th first scan line SL1i, the second transistor M2a is turned on. In the example where the second transistor M2a is turned on, a data signal can be supplied from the j-th data line DLj to the third node N3. Since the first transistor M1 maintains a diode connection via the turned-on third transistor M3b, the first node N1 can have a voltage where the threshold voltage of the first transistor M1 is compensated by the data signal.

[0180] During the third period P3, the fourth scan signal GB is enabled and supplied to the i-th fourth scan line SL4i. When the fourth scan signal GB is enabled and supplied to the i-th fourth scan line SL4i, the fifth transistor M5 and the eighth transistor M8 are turned on. When the fifth transistor M5 is turned on, the voltage of the second initialization power Vint2 can be supplied to the first electrode of the light-emitting element LD, thereby initializing the light-emitting element LD. When the eighth transistor M8 is turned on, the voltage of the bias power Vbias is supplied to the second node N2. When the voltage of the bias power Vbias is supplied to the second node N2, the first transistor M1 can be set to a biased on state.

[0181] In the fourth period P4, the emission enable control signal EM (or a low-level emission control signal) is provided to the k-th emission control line ELk, and thus the sixth transistor M6 and the seventh transistor M7 are turned on. In the example where the sixth transistor M6 and the seventh transistor M7 are turned on, a current flow path is formed that is connected to the second power line PL2 via the first power line PL1, the sixth transistor M6, the first transistor M1, the seventh transistor M7, and the light-emitting element LD. At this time, according to the operation of the first transistor M1, a drive current corresponding to the voltage of the first node N1 can flow through the light-emitting element LD, and the light-emitting element LD can generate light of a predetermined brightness corresponding to the drive current.

[0182] In some aspects, while the pixel PXijc emits light, the voltage of the second node N2 can maintain a voltage similar to the first driving power VDD regardless of the grayscale. Therefore, leakage current can flow from the second node N2 to the first node N1 regardless of the grayscale.

[0183] Figure 14A and Figure 14B It is shown that due to Figure 13 The simulation diagram of the voltage change caused by the leakage current of the pixel PXijc shown in FIG. Figure 14A and Figure 14B In , N2 refers to the voltage of the second node N2, CN1 refers to the voltage of the first common node CN1, N1 refers to the voltage of the first node N1, CN2 refers to the voltage of the second common node CN2, and Vint1 refers to the voltage of the first initialization power Vint1. Figure 14A and Figure 14B In some aspects, in order to perform Figure 14A and Figure 14BIn the simulation, the first driving power VDD is set to 4.6V, the second driving power VSS is set to -4.0V, the first initialization power Vint1 is set to -3.5V, the capacitance of the storage capacitor Cst is set to 70F, the capacitance of the first capacitor C1 is set to 8.7F, and the capacitance of the second capacitor C2 is set to 8.7F.

[0184] Figure 14A Corresponding to the voltage change amount at each of the nodes N1, N2, CN1, and CN2 after the voltage of the data signal corresponding to the high gray level (e.g., white gray level) is applied to the pixel PXijc. It can be confirmed that even after a predetermined time has passed after the voltage of the data signal corresponding to the high gray level is applied to the pixel PXijc, the voltage of the first node N1 remains constant. For example, the voltage change amount of Vgs of the first transistor M1 can be set to approximately 0V, and thus the pixel PXijc according to an embodiment of the present disclosure can stably achieve brightness at a high gray level.

[0185] Figure 14B Corresponding to the voltage change amount at each of the nodes N1, N2, CN1, and CN2 after the voltage of the data signal corresponding to the low gray level (e.g., black gray level) is applied to the pixel PXijc. It can be confirmed that even after a predetermined time has passed after the voltage of the data signal corresponding to the low gray level is applied to the pixel PXijc, the voltage of the first node N1 remains constant. For example, the voltage change amount of the Vgs of the first transistor M1 can be set to approximately -0.01V, and thus the pixel PXijc according to an embodiment of the present disclosure can stably achieve brightness at a low gray level.

[0186] Figure 15 is a diagram showing a pixel according to an embodiment of the present disclosure. Figure 15 In the description of Figure 13 The same configurations as those of and repeated descriptions of the same elements are omitted for the sake of brevity.

[0187] refer to Figure 15 , a pixel PXijd according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit for controlling the amount of driving current supplied to the light emitting element LD.

[0188] The light emitting element LD may generate light of predetermined brightness in response to a driving current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0189] The pixel circuit may include a first transistor M1, a second transistor M2a, a third transistor M3c, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a storage capacitor Cst, a first capacitor C1, and a second capacitor C2.

[0190] The third transistor M3c may include a first sub-transistor M3_1c and a second sub-transistor M3_2c. The first sub-transistor M3_1c and the second sub-transistor M3_2c may be connected in series between a first node N1 and a second node N2. The gate electrode of the third transistor M3c (i.e., the first sub-transistor M3_1c and the second sub-transistor M3_2c) may be electrically connected to the i-th first scan line SL1i. The third transistor M3c may be turned on when an enable first scan signal GW is provided to the i-th first scan line SL1i, and may electrically connect the first node N1 to the second node N2. In the example where the third transistor M3c is turned on, the first transistor M1 may be connected in a diode manner.

[0191] In reference Figure 15 In the described example, the third transistor M3c is connected to the i-th first scan line SL1i, and the i-th second scan line SL2i may be omitted (or the i-th first scan line SL1i and the i-th second scan line SL2i may be the same scan line). In addition to the gate electrode of the third transistor M3c being connected to the i-th first scan line SL1i, Figure 15 The pixel PXijd shown in FIG can have Figure 13 The same configuration of pixels PXijc in .

[0192] Figure 16 is a diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0193] refer to Figure 16 , the electronic device 1000 outputs various information through the display module 1140. In an example in which the processor 1110 executes an application stored in the memory 1120, the display module 1140 provides application information to the user through the display panel 1141.

[0194] The processor 1110 obtains external input through the input module 1130 or the sensor module 1161 and executes an application corresponding to the external input. In the example where the user selects a camera icon (or a camera application icon) displayed on the display panel 1141, the processor 1110 obtains the user input through the input sensor 1161-2 and activates the camera module 1171. The processor 1110 transmits image data corresponding to the captured image obtained by the camera module 1171 to the display module 1140. The display module 1140 can display an image corresponding to the captured image through the display panel 1141.

[0195] As another example, when personal information authentication is performed in the display module 1140, the fingerprint sensor 1161-1 obtains input fingerprint information as input data. The processor 1110 compares the input data obtained by the fingerprint sensor 1161-1 with the verification data stored in the memory 1120 and executes the application based on the comparison result. The display module 1140 can display information executed according to the logic of the application through the display panel 1141. The fingerprint sensor 1161-1 can be configured to obtain fingerprint information from the entire area of ​​the display module 1140 (or display panel 1141).

[0196] As yet another example, when a music streaming icon displayed on the display module 1140 is selected, the processor 1110 obtains a user input through the input sensor 1161-2 and activates a music streaming application stored in the memory 1120. In an example in which a music execution command is input into the music streaming application, the processor 1110 activates the sound output module 1163 to provide the user with sound information corresponding to the music execution command.

[0197] In the above, the operation of the electronic device 1000 is briefly described. Hereinafter, the configuration of the electronic device 1000 is described in detail. Some configurations of the electronic device 1000 to be described later may be integrated and provided as one configuration, and one configuration may be separated into two or more configurations and provided.

[0198] The electronic device 1000 can communicate with the external electronic device 2000 through a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to an embodiment, the electronic device 1000 may include a processor 1110, a memory 1120, an input module 1130, a display module 1140, a power module 1150, an internal module 1160, and an external module 1170. According to an embodiment, in the electronic device 1000, at least one of the components described above may be omitted, or one or more other components may be added. According to an embodiment, some of the above components (e.g., the sensor module 1161, the antenna module 1162, or the sound output module 1163) may be integrated into another component (e.g., the display module 1140).

[0199] The processor 1110 may execute software to control at least one other component (e.g., hardware or software component) of the electronic device 1000 connected to the processor 1110 and perform various data processing or operations. Depending on the embodiment, as at least part of the data processing or operation, the processor 1110 may store a command or data received from another component (e.g., the input module 1130, the sensor module 1161, or the communication module 1173) in the volatile memory 1121, process the command or data stored in the volatile memory 1121, and store the resulting data in the non-volatile memory 1122.

[0200] The processor 1110 may include a main processor 1111 and an auxiliary processor 1112. The main processor 1111 may include a central processing unit (CPU) 1111-1. The main processor 1111 may also include any one or more of a graphics processing unit (GPU) 1111-2, a communication processor (CP), and an image signal processor (ISP). The main processor 1111 may also include a neural processing unit (NPU) 1111-3. NPU 1111-3 is a processor specifically configured to process artificial intelligence models, and the artificial intelligence models may be generated through machine learning. The artificial intelligence model may include multiple artificial neural network layers. The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q network, or a combination of two or more of the above artificial neural networks, but is not limited to the above examples. Additionally or alternatively, the artificial intelligence model may include a software structure in addition to the hardware structure. At least two of the above-mentioned processing units and processors may be implemented as one integrated configuration (eg, a single chip), or each may be implemented as an independent configuration (eg, a plurality of chips).

[0201] The auxiliary processor 1112 may include a controller 1112-1. The controller 1112-1 may include an interface conversion circuit and a timing control circuit. For example, the controller 1112-1 may include Figure 1 1. The timing controller 120 shown in FIG. Controller 1112-1 receives an image signal from the main processor 1111, converts the data format of the image signal into a format corresponding to the interface specification of the display module 1140, and outputs the image data. Controller 1112-1 can output various control signals associated with driving the display module 1140.

[0202] The auxiliary processor 1112 may further include a data conversion circuit 1112-2, a gamma correction circuit 1112-3, a rendering circuit 1112-4, a touch control circuit 1112-5, etc. The data conversion circuit 1112-2 may receive image data from the controller 1112-1, and compensate the image data to display an image with desired brightness based on the characteristics of the electronic device 1000, user settings, etc., or convert the image data to reduce power consumption, perform afterimage compensation, etc.

[0203] The gamma correction circuit 1112-3 may convert image data, gamma reference voltage, etc. so that an image displayed on the electronic device 1000 has a desired gamma characteristic. The rendering circuit 1112-4 may receive image data from the controller 1112-1 and render the image data in consideration of the pixel arrangement of the display panel 1141 applied to the electronic device 1000, etc.

[0204] The touch control circuit 1112 - 5 may provide a touch signal to the input sensor 1161 - 2 and receive a sensing signal from the input sensor 1161 - 2 in response to the touch signal.

[0205] At least one of the data conversion circuit 1112-2, the gamma correction circuit 1112-3, the rendering circuit 1112-4, and the touch control circuit 1112-5 may be integrated into another component (e.g., the main processor 1111 or the controller 1112-1). At least one of the data conversion circuit 1112-2, the gamma correction circuit 1112-3, and the rendering circuit 1112-4 may be integrated into a source driver 1143, which will be described later.

[0206] The memory 1120 may store various data used by at least one component of the electronic device 1000 (e.g., the processor 1110 or the sensor module 1161) and input data or output data for commands related thereto. In some aspects, various setting data corresponding to user settings may be stored in the memory 1120. The memory 1120 may include at least one of a volatile memory 1121 and a non-volatile memory 1122.

[0207] The input module 1130 may receive commands or data to be used by components of the electronic device 1000 (eg, the processor 1110, the sensor module 1161, or the sound output module 1163) from outside the electronic device 1000 (eg, a user or an external electronic device 2000).

[0208] The input module 1130 may include a first input module 1131 to which a command or data is input from a user and a second input module 1132 to which a command or data is input from an external electronic device 2000. The first input module 1131 may include a microphone, a mouse, a keyboard, a key (e.g., a button) or a pen (e.g., a passive pen or an active pen). The second input module 1132 may support a specified protocol that can be connected to the external electronic device 2000 by wire or wirelessly. According to an embodiment, the second input module 1132 may include a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface or an audio interface. The second input module 1132 may include a connector that can be physically connected to the external electronic device 2000, for example, an HDMI connector, a USB connector, an SD card connector or an audio connector (e.g., a headphone connector).

[0209] The display module 1140 provides information to the user visually. The display module 1140 may include a display panel 1141, a gate driver 1142, a source driver 1143, and a voltage generating circuit 1144. The display module 1140 may also include a window, a chassis, and a bracket for protecting the display panel 1141. The display module 1140 may include Figure 1 At least a portion of the configuration of the display device 100 shown in FIG.

[0210] The display panel 1141 (or display) may include a liquid crystal display panel, an organic light emitting display panel, or an inorganic light emitting display panel, and the type of the display panel 1141 is not particularly limited. The display panel 1141 may be a rigid type or a flexible type that can be rolled or folded. The display module 1140 may further include a support, a bracket, a heat dissipation member, etc. that supports the display panel 1141. The display panel 1141 may include Figure 1 That is, the display panel 1141 may include Figure 1 The pixels PX shown in FIG, and each of the pixels PX may include Figure 8 、 Figure 11 、 Figure 13 and Figure 15 The pixel circuit and light emitting element LD shown in .

[0211] The gate driver 1142 may be mounted on the display panel 1141 as a driver chip. In some aspects, the gate driver 1142 may be integrated into the display panel 1141. For example, the gate driver 1142 may include an amorphous silicon TFT gate driver circuit (ASG), a low temperature polysilicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate driver circuit (OSG) built into the display panel 1141. The gate driver 1142 receives a control signal from the controller 1112-1 and outputs a scan signal to the display panel 1141 in response to the control signal. The gate driver 1142 may include Figure 1 The scan driver 130 shown in FIG.

[0212] The display module 1140 may further include an emission driver. The emission driver outputs an emission control signal to the display panel 1141 in response to a control signal received from the controller 1112-1. The emission driver may be formed separately from the gate driver 1142 or may be integrated into the gate driver 1142. The emission driver may include Figure 1 The transmit driver 150 shown in FIG.

[0213] The source driver 1143 receives a control signal from the controller 1112-1, converts image data into an analog voltage (eg, a data signal) in response to the control signal, and then outputs the data signal to the display panel 1141. The source driver 1143 may include Figure 1 The data driver 140 is shown in FIG.

[0214] The source driver 1143 may be integrated into another component (e.g., the controller 1112-1). The functions of the interface conversion circuit and the timing control circuit of the controller 1112-1 described herein may be integrated into the source driver 1143. The voltage generating circuit 1144 may output various voltages associated with driving the display panel 1141. As an example, the voltage generating circuit 1144 may include Figure 1 The power supply 160 is shown in FIG.

[0215] In an embodiment, the source driver 1143 may convert data corresponding to red (R), green (G), and blue (B) included in the image data received from the processor 1110 into a red data signal (or data voltage), a green data signal, and a blue data signal, and may provide the red data signal, the green data signal, and the blue data signal to a plurality of pixel columns included in the display panel 1141 during one horizontal period.

[0216] The power module 1150 provides power to the components of the electronic device 1000. The power module 1150 may include a battery that charges the power voltage. The battery may include a non-rechargeable primary battery and a rechargeable secondary battery or fuel cell. The power module 1150 may include a power management integrated circuit (PMIC). The PMIC provides optimized power to each of the modules described above and the modules to be described later. The power module 1150 may include a wireless power transmission / reception component electrically connected to the battery. The wireless power transmission / reception component may include an antenna radiator in the form of multiple coils. In an embodiment, at least part of the configuration of the power module 1150 and the voltage generating circuit 1144 may be integrated into one and provided. As an example, the voltage generating circuit 1144 may be included in the power module 1150.

[0217] The electronic device 1000 may further include an internal module 1160 and an external module 1170. The internal module 1160 may include a sensor module 1161, an antenna module 1162, and a sound output module 1163. The external module 1170 may include a camera module 1171, an optical module 1172, and a communication module 1173.

[0218] The sensor module 1161 can sense input by the user's body or input by the pen in the first input module 1131 and can generate an electrical signal or data value corresponding to the input. The sensor module 1161 can include at least one of a fingerprint sensor 1161-1, an input sensor 1161-2, and a digitizer 1161-3.

[0219] Fingerprint sensor 1161 - 1 may generate a data value corresponding to the user's fingerprint.

[0220] The input sensor 1161-2 can generate data values ​​corresponding to the coordinate information of the input performed by the user's body or pen. The input sensor 1161-2 generates a capacitance change amount as a data value due to the input. The input sensor 1161-2 can sense the input performed by the passive pen, or can transmit and receive data to and from the active pen.

[0221] The input sensor 1161-2 can measure biometric signals such as blood pressure, water, or body fat. For example, when a user touches the sensor layer or sensing panel with a body part and does not move for a certain period of time, the input sensor 1161-2 can sense the biometric signal based on the change in the electric field caused by the body part and output the information desired by the user to the display module 1140.

[0222] The digitizer 1161-3 can generate data values ​​corresponding to the coordinate information of the input performed by the pen. The digitizer 1161-3 generates the amount of electromagnetic change due to the input as a data value. The digitizer 1161-3 can sense the input performed by the passive pen, or can transmit and receive data to and from the active pen.

[0223] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be implemented as a sensor layer formed on the display panel 1141 through a continuous process. At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be provided above the display panel 1141, and any one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 (e.g., the digitizer 1161-3) may be provided below the display panel 1141.

[0224] At least two of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be formed so as to be integrated into a single sensing panel using the same process. In an example where at least two of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 are integrated into a single sensing panel, the sensing panel may be disposed between the display panel 1141 and a window disposed above the display panel 1141. Depending on the embodiment, the sensing panel may be disposed on the window, and the position of the sensing panel is not particularly limited.

[0225] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be embedded in the display panel 1141. That is, at least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be simultaneously formed by a process of forming elements (e.g., light emitting elements, transistors, etc.) included in the display panel 1141.

[0226] In some aspects, the sensor module 1161 may generate electrical signals or data values ​​corresponding to an internal state or an external state of the electronic device 1000. The sensor module 1161 may also include, for example, a gesture sensor, a gyroscope sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illumination sensor.

[0227] The antenna module 1162 may include one or more antennas for transmitting signals or power to the outside or receiving signals or power from the outside. Depending on the embodiment, the communication module 1173 may transmit signals to the external electronic device 2000 or receive signals from the external electronic device 2000 via an antenna suitable for the communication method. The antenna pattern of the antenna module 1162 may be integrated into one configuration of the display module 1140 (e.g., the display panel 1141) or the input sensor 1161-2.

[0228] The sound output module 1163 is a device for outputting sound signals to the outside of the electronic device 1000, and may include, for example, a speaker for general purposes (such as multimedia playback or recording playback) and a receiver specifically for receiving calls. Depending on the embodiment, the receiver may be formed integrally with the speaker or separately from the speaker. The sound output mode of the sound output module 1163 may be integrated into the display module 1140.

[0229] The camera module 1171 can capture still images and moving images. Depending on the embodiment, the camera module 1171 may include one or more lenses, an image sensor, and an image signal processor. The camera module 1171 may also include an infrared camera capable of measuring the presence or absence of a user, the user's position, the user's gaze, etc.

[0230] The light module 1172 may provide light. The light module 1172 may include a light emitting diode or a xenon lamp. The light module 1172 may operate in conjunction with the camera module 1171 or may operate independently.

[0231] The communication module 1173 can support the establishment of a wired communication channel or a wireless communication channel between the electronic device 1000 and the external electronic device 2000 and support communication performance through the established communication channel. The communication module 1173 may include any one or both of a wireless communication module (such as, for example, a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) and a wired communication module (such as, for example, a local area network (LAN) communication module or a power line communication module). The communication module 1173 can communicate with the external electronic device 2000 via a short-range communication network (such as, for example, Bluetooth, WiFi Direct, or Infrared Data Association (IrDA)) or a long-range communication network (such as, for example, a cellular network, the Internet, or a computer network (such as a LAN or WAN)). The various types of communication modules 1173 described above can be implemented as a single chip or separate chips.

[0232] The input module 1130 , the sensor module 1161 , the camera module 1171 , and the like may be used to control the operation of the display module 1140 in conjunction with the processor 1110 .

[0233] The processor 1110 outputs commands or data to the display module 1140, the sound output module 1163, the camera module 1171, or the optical module 1172 based on the input data received from the input module 1130. For example, the processor 1110 may generate image data in response to input data applied through a mouse, an active pen, or the like, and output the image data to the display module 1140, or generate command data in response to the input data and output the command data to the camera module 1171 or the optical module 1172. In an example in which no input data is received from the input module 1130, the processor 1110 may convert the operating mode of the electronic device 1000 into a low power mode or a sleep mode to reduce power consumption in the electronic device 1000.

[0234] The processor 1110 outputs commands or data to the display module 1140, the sound output module 1163, the camera module 1171, or the optical module 1172 based on the sensing data received from the sensor module 1161. For example, the processor 1110 may compare the authentication data applied by the fingerprint sensor 1161-1 with the authentication data stored in the memory 1120 and then execute an application based on the comparison result. The processor 1110 may execute a command or output corresponding image data to the display module 1140 based on the sensing data sensed by the input sensor 1161-2 or the digitizer 1161-3. In an example in which the sensor module 1161 includes a temperature sensor, the processor 1110 may receive temperature data for the measured temperature from the sensor module 1161 and further perform brightness correction, etc. on the image data based on the temperature data.

[0235] The processor 1110 may receive measurement data regarding the user's presence, the user's position, the user's gaze, etc. from the camera module 1171. The processor 1110 may also perform brightness correction, etc. on the image data based on the measurement data. For example, the processor 1110, which determines the presence or absence of the user through input from the camera module 1171, may output image data whose brightness has been corrected through the data conversion circuit 1112-2 or the gamma correction circuit 1112-3 to the display module 1140.

[0236] Some of the components described above may be connected to each other via a communication method between peripheral devices (e.g., a bus, a general-purpose input / output (GPIO), a serial peripheral interface (SPI), a mobile industry processor interface (MIPI), or a Ultra Path Interconnect (UPI) link) to exchange signals (e.g., commands or data) with each other. The processor 1110 may communicate with the display module 1140 via a mutually agreed interface, for example, using any of the communication methods described above, and is not limited to the communication methods described above.

[0237] Although the foregoing has been described with reference to the embodiments of the present disclosure, it will be understood by those skilled in the art that various modifications and changes can be made to the present disclosure without departing from the spirit and scope of the present disclosure described in the claims.

Claims

1. A pixel comprising: a first transistor including a gate electrode connected to the first node, a first electrode connected to the first power line via a second node, and a second electrode connected to the first electrode of the light emitting element via a third node; the light emitting element configured to output light in response to a drive current supplied from the first transistor and including a second electrode connected to a second power line; a second transistor connected between the data line and the second node and including a gate electrode connected to the first scan line; a third transistor including a first sub-transistor and a second sub-transistor connected in series between the first node and the third node; as well as A first capacitor is connected between a first common node between the first sub-transistor and the second sub-transistor and the first electrode of the light emitting element.

2. The pixel according to claim 1, wherein: Gate electrodes of the first sub-transistor and the second sub-transistor are connected to a second scan line, and The conduction periods of the first sub-transistor and the second sub-transistor at least partially overlap with the conduction period of the second transistor.

3. The pixel according to claim 1, wherein Gate electrodes of the first sub-transistor and the second sub-transistor are connected to the first scan line.

4. The pixel according to claim 1, further comprising: a fourth transistor connected in series between the first node and a third power line and including a third sub-transistor and a fourth sub-transistor, the third sub-transistor and the fourth sub-transistor including gate electrodes connected to a third scan line; as well as A fifth transistor is connected between the first electrode of the light emitting element and a fourth power line, and includes a gate electrode connected to a fourth scan line.

5. The pixel according to claim 4, further comprising: A second capacitor is connected between the constant power and a second common node between the third sub-transistor and the fourth sub-transistor.

6. The pixel according to claim 5, further comprising: a sixth transistor connected between the first power line and the second node and including a gate electrode connected to an emission control line; a seventh transistor connected between the third node and the first electrode of the light emitting element and including a gate electrode connected to the emission control line; an eighth transistor connected between the second node and a fifth power line and including a gate electrode connected to the fourth scan line; as well as A storage capacitor is connected between the first power line and the first node.

7. The pixel according to claim 6, wherein: The constant power is one of a first driving power supplied to the first power line, a second driving power supplied to the second power line, a first initialization power supplied to the third power line, a second initialization power supplied to the fourth power line, and a bias power supplied to the fifth power line.

8. A pixel comprising: a first transistor including a gate electrode connected to the first node, a first electrode connected to the first power line via a second node, and a second electrode connected to the first electrode of the light emitting element via a third node; the light emitting element configured to output light in response to a drive current supplied from the first transistor and including a second electrode connected to a second power line; a second transistor connected between the data line and the third node and including a gate electrode connected to the first scan line; a third transistor including a first sub-transistor and a second sub-transistor connected in series between the first node and the second node; as well as A first capacitor is connected between a first common node between the first sub-transistor and the second sub-transistor and the first electrode of the light emitting element.

9. The pixel according to claim 8, wherein Gate electrodes of the first sub-transistor and the second sub-transistor are connected to a second scan line, and The conduction periods of the first sub-transistor and the second sub-transistor at least partially overlap with the conduction period of the second transistor.

10. The pixel according to claim 8, wherein Gate electrodes of the first sub-transistor and the second sub-transistor are connected to the first scan line.

11. The pixel according to claim 8, further comprising: a fourth transistor connected in series between the first node and a third power line and including a third sub-transistor and a fourth sub-transistor, the third sub-transistor and the fourth sub-transistor including gate electrodes connected to a third scan line; as well as A fifth transistor is connected between the first electrode of the light emitting element and a fourth power line, and includes a gate electrode connected to a fourth scan line.

12. The pixel according to claim 11, further comprising: A second capacitor is connected between the constant power and a second common node between the third sub-transistor and the fourth sub-transistor.

13. The pixel according to claim 12, further comprising: a sixth transistor connected between the first power line and the second node and including a gate electrode connected to an emission control line; a seventh transistor connected between the third node and the first electrode of the light emitting element and including a gate electrode connected to the emission control line; an eighth transistor connected between the second node and a fifth power line and including a gate electrode connected to the fourth scan line; as well as A storage capacitor is connected between the first power line and the first node.

14. The pixel according to claim 13, wherein: The constant power is one of a first driving power supplied to the first power line, a second driving power supplied to the second power line, a first initialization power supplied to the third power line, a second initialization power supplied to the fourth power line, and a bias power supplied to the fifth power line.

15. A display device comprising: Pixels, connected to scan lines, emission control lines and data lines, Wherein, at least one of the pixels comprises: a first transistor including a gate electrode connected to the first node, a first electrode connected to the first power line via a second node, and a second electrode connected to the first electrode of the light emitting element via a third node; the light emitting element configured to output light in response to a drive current supplied from the first transistor and including a second electrode connected to a second power line; a second transistor connected between a specific data line among the data lines and the second node or the third node, the second transistor including a gate electrode connected to a first scan line included in the scan lines; a third transistor connected in series between the first node and the second node or the third node, the third transistor including a first sub-transistor and a second sub-transistor, each of the first sub-transistor and the second sub-transistor including a gate electrode connected to a second scan line included in the scan lines; and A first capacitor is connected between a first common node between the first sub-transistor and the second sub-transistor and the first electrode of the light emitting element.

16. The display device according to claim 15, wherein: The second transistor is connected between the specific data line and the second node, and the third transistor is connected between the first node and the third node, or The second transistor is connected between the specific data line and the third node, and the third transistor is connected between the first node and the second node.

17. The display device according to claim 15, wherein: The first scan line and the second scan line are the same scan line.

18. The display device according to claim 15, wherein The at least one of the pixels further comprises: a fourth transistor connected in series between the first node and a third power line, and including a third sub-transistor and a fourth sub-transistor, the third sub-transistor and the fourth sub-transistor including gate electrodes connected to a third scan line among the scan lines; a fifth transistor connected between the first electrode of the light emitting element and a fourth power line and including a gate electrode connected to a fourth scan line among the scan lines; and A second capacitor is connected between the constant power and a second common node between the third sub-transistor and the fourth sub-transistor.

19. The display device according to claim 18, wherein The at least one of the pixels further comprises: a sixth transistor connected between the first power line and the second node and including a gate electrode connected to the emission control line; a seventh transistor connected between the third node and the first electrode of the light emitting element and including a gate electrode connected to the emission control line; an eighth transistor connected between the second node and a fifth power line and including a gate electrode connected to the fourth scan line; and A storage capacitor is connected between the first power line and the first node.

20. The display device according to claim 19, wherein The constant power is one of a first driving power supplied to the first power line, a second driving power supplied to the second power line, a first initialization power supplied to the third power line, a second initialization power supplied to the fourth power line, and a bias power supplied to the fifth power line.

21. An electronic device comprising: a display panel, including pixels; a display module, comprising a driver for controlling the display panel; as well as a processor configured to control the display module, Wherein, at least one of the pixels comprises: a first transistor including a gate electrode connected to the first node, a first electrode connected to the first power line via a second node, and a second electrode connected to the first electrode of the light emitting element via a third node; the light emitting element configured to output light in response to a drive current supplied from the first transistor and including a second electrode connected to a second power line; a second transistor connected between a specific data line included in the data lines and the second node or the third node, the second transistor including a gate electrode connected to a first scan line included in the scan lines; a third transistor connected in series between the first node and the second node or the third node, the third transistor including a first sub-transistor and a second sub-transistor, each of the first sub-transistor and the second sub-transistor including a gate electrode connected to a second scan line included in the scan lines; and A first capacitor is connected between a first common node between the first sub-transistor and the second sub-transistor and the first electrode of the light emitting element.

22. The electronic device according to claim 21, wherein The first scan line and the second scan line are the same scan line.

Images