Display panel, display device and driving method

Abstract

The embodiment of the invention provides a display panel, a display device and a driving method, and the display panel comprises a first control circuit which is configured to respond to signals of M addressing signal ends, and provide positioning signals for N positioning signal ends; wherein M and N are positive integers greater than 0; the gate driving circuit comprises a plurality of gate driving sub-circuits, and each gate driving sub-circuit comprises a plurality of shift register units which are cascaded in sequence; the nth second control circuit is coupled with the nth positioning signal end and the first row of shifting register units in the nth gate driving sub-circuit, and the second control circuit is configured to respond to positioning signals of the positioning signal end and control the first row of shifting register units in the nth gate driving sub-circuit. A signal of a frame start signal end or a signal of an output signal end is provided for a first row shift register unit in the correspondingly coupled gate drive sub-circuit; wherein the output signal end in the nth second control circuit is coupled with the last row of shift register unit in the (n-1) th gate drive sub-circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a display device, and a driving method. Background Art

[0002] Display panels, such as organic light-emitting diode (OLED) and quantum dot light-emitting diode (QLED) panels, typically include multiple pixel units. Each pixel unit can include multiple sub-pixels of different colors. By controlling the brightness of these sub-pixels, the desired color can be mixed to display a color image. Summary of the Invention

[0003] The embodiments of the present disclosure provide:

[0004] A first control circuit is configured to provide positioning signals to N positioning signal terminals in response to signals from M addressing signal terminals, wherein M and N are both positive integers greater than 0;

[0005] A gate driving circuit, comprising a plurality of gate driving sub-circuits, each of the gate driving sub-circuits comprising a plurality of shift register units cascaded in sequence;

[0006] Multiple second control circuits, the nth second control circuit is coupled to the nth positioning signal terminal and the first row shift register unit in the nth gate drive sub-circuit, and the second control circuit is configured to provide the signal of the frame start signal terminal or the signal of the output signal terminal to the first row shift register unit in the corresponding coupled gate drive sub-circuit in response to the positioning signal of the positioning signal terminal; wherein the output signal terminal in the nth second control circuit is coupled to the last row shift register unit in the n-1th gate drive sub-circuit.

[0007] In some possible implementations, the first control circuit includes: M first logic gate circuits and N second logic gate circuits; wherein one first logic gate circuit is coupled to one addressing signal terminal, and one second logic gate circuit is coupled to one positioning signal terminal;

[0008] The first logic gate circuit is configured to generate a first logic signal in response to a signal at the addressing signal terminal;

[0009] The second logic gate circuit is coupled to the first logic gate circuit and / or the addressing signal terminal, and is configured to provide a positioning signal to the positioning signal terminal in response to the first logic signal and / or the signal of the addressing signal terminal.

[0010] In some possible implementations, N=2 M .

[0011] In some possible implementations, M=3, N=8;

[0012] a first end of the first second logic gate circuit coupled to the first positioning signal end, a second end of the first second logic gate circuit coupled to the first end of the first first logic gate circuit, a third end of the first second logic gate circuit coupled to the first end of the second first logic gate circuit, and a fourth end of the first second logic gate circuit coupled to the first end of the third first logic gate circuit;

[0013] a first terminal of a second second logic gate circuit coupled to the second positioning signal terminal, a second terminal of a second second logic gate circuit coupled to the first addressing signal terminal, a third terminal of a second second logic gate circuit coupled to the first terminal of a second first logic gate circuit, and a fourth terminal of a second second logic gate circuit coupled to the first terminal of a third first logic gate circuit;

[0014] a first terminal of the third second logic gate circuit coupled to the third positioning signal terminal, a second terminal of the third second logic gate circuit coupled to the first terminal of the first first logic gate circuit, a third terminal of the third second logic gate circuit coupled to the first terminal of the second first logic gate circuit, and a fourth terminal of the third second logic gate circuit coupled to the third addressing signal terminal;

[0015] a first terminal of a fourth second logic gate circuit coupled to the fourth positioning signal terminal, a second terminal of the fourth second logic gate circuit coupled to the first addressing signal terminal, a third terminal of the fourth second logic gate circuit coupled to the first terminal of the second first logic gate circuit, and a fourth terminal of the fourth second logic gate circuit coupled to the third addressing signal terminal;

[0016] a first terminal of the fifth second logic gate circuit coupled to the fifth positioning signal terminal, a second terminal of the fifth second logic gate circuit coupled to the first terminal of the first first logic gate circuit, a third terminal of the fifth second logic gate circuit coupled to the second addressing signal terminal, and a fourth terminal of the fifth second logic gate circuit coupled to the first terminal of the third first logic gate circuit;

[0017] a first terminal of the sixth second logic gate circuit is coupled to the sixth positioning signal terminal, a second terminal of the sixth second logic gate circuit is coupled to the first addressing signal terminal, a third terminal of the sixth second logic gate circuit is coupled to the second addressing signal terminal, and a fourth terminal of the sixth second logic gate circuit is coupled to the first terminal of the third first logic gate circuit;

[0018] a first terminal of the seventh second logic gate circuit is coupled to the seventh positioning signal terminal, a second terminal of the seventh second logic gate circuit is coupled to the first terminal of the first first logic gate circuit, a third terminal of the seventh second logic gate circuit is coupled to the second addressing signal terminal, and a fourth terminal of the seventh second logic gate circuit is coupled to the third addressing signal terminal;

[0019] a first terminal of the eighth second logic gate circuit is coupled to the eighth positioning signal terminal, a second terminal of the eighth second logic gate circuit is coupled to the first addressing signal terminal, a third terminal of the eighth second logic gate circuit is coupled to the second addressing signal terminal, and a fourth terminal of the eighth second logic gate circuit is coupled to the third addressing signal terminal;

[0020] The second terminal of the first first logic gate circuit is coupled to the first addressing signal terminal;

[0021] The second end of the second first logic gate circuit is coupled to the second addressing signal end;

[0022] The second terminal of the third first logic gate circuit is coupled to the third addressing signal terminal.

[0023] In some possible implementations, the first logic circuit includes: a first transistor and a second transistor;

[0024] The gate of the first transistor is coupled to the addressing signal terminal, the first electrode of the first transistor is coupled to the first power signal terminal, and the second electrode of the first transistor is coupled to the first electrode of the second transistor;

[0025] A gate of the second transistor is coupled to the addressing signal terminal, and a second electrode of the second transistor is coupled to a second power signal terminal.

[0026] In some possible implementations, the effective level signal of the first transistor is different from the effective level signal of the second transistor.

[0027] In some possible implementations, the second logic circuit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0028] The gate of the third transistor is coupled to the gate of the sixth transistor, the first electrode of the third transistor is coupled to the second power signal terminal, and the second electrode of the third transistor is coupled to the positioning signal terminal;

[0029] The gate of the fourth transistor is coupled to the gate of the seventh transistor, the first electrode of the fourth transistor is coupled to the second power signal terminal, and the second electrode of the fourth transistor is coupled to the positioning signal terminal;

[0030] The gate of the fifth transistor is coupled to the gate of the eighth transistor, the first electrode of the fifth transistor is coupled to the second power signal terminal, and the second electrode of the fifth transistor is coupled to the positioning signal terminal;

[0031] A first electrode of the sixth transistor is coupled to the first power signal terminal, a second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor, and a second electrode of the seventh transistor is coupled to the first electrode of the eighth transistor.

[0032] In some possible implementations, the effective level signals of the third transistor, the fourth transistor, and the fifth transistor are the same;

[0033] The effective level signals of the sixth transistor, the seventh transistor and the eighth transistor are the same;

[0034] The third transistor and the sixth transistor have different effective level signals.

[0035] In some possible implementations, the second control circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;

[0036] The gate of the ninth transistor is coupled to the second electrode of the eleventh transistor, the first electrode of the ninth transistor is coupled to the first power signal terminal, and the second electrode of the ninth transistor is coupled to the first electrode of the tenth transistor;

[0037] The gate of the tenth transistor is coupled to the second electrode of the eleventh transistor, and the second electrode of the tenth transistor is coupled to the second power signal terminal;

[0038] The gate of the eleventh transistor is coupled to the positioning signal terminal, the first electrode of the eleventh transistor is coupled to the first power signal terminal, and the second electrode of the eleventh transistor is coupled to the first electrode of the twelfth transistor.

[0039] The gate of the twelfth transistor is coupled to the positioning signal terminal, and the second electrode of the twelfth transistor is coupled to the second power signal terminal;

[0040] The gate of the thirteenth transistor is coupled to the positioning signal terminal, the first electrode of the thirteenth transistor is coupled to the output signal terminal, and the second electrode of the thirteenth transistor is coupled to the first row shift register unit in the gate driving sub-circuit;

[0041] The gate of the fourteenth transistor is coupled to the second electrode of the eleventh transistor, the first electrode of the fourteenth transistor is coupled to the output signal terminal, and the second electrode of the fourteenth transistor is coupled to the first row shift register unit in the gate driving sub-circuit;

[0042] The gate of the fifteenth transistor is coupled to the second electrode of the eleventh transistor, the first electrode of the fifteenth transistor is coupled to the frame start signal terminal, and the second electrode of the fifteenth transistor is coupled to the first row shift register unit in the gate driving sub-circuit;

[0043] The gate of the sixteenth transistor is coupled to the positioning signal terminal, the first electrode of the sixteenth transistor is coupled to the frame start signal terminal, and the second electrode of the sixteenth transistor is coupled to the first row shift register unit in the gate driving subcircuit.

[0044] In some possible implementations, each gate driving sub-circuit includes the same or different numbers of shift register units.

[0045] The display device provided by the embodiment of the present disclosure includes the above-mentioned display panel.

[0046] The driving method of the display panel provided by the embodiment of the present disclosure includes: a first operating mode and a second operating mode;

[0047] In the first operating mode, the first control circuit provides positioning signals to the N positioning signal terminals in response to signals from the M addressing signal terminals; the first control circuit is configured to provide signals from the output signal terminal to the first row shift register unit in the corresponding coupled gate drive sub-circuit in response to the positioning signals from the positioning signal terminals;

[0048] In the second operating mode, the first control circuit provides a positioning signal to N positioning signal terminals in response to the signals of the M addressing signal terminals; the first control circuit is configured to provide the signal of the frame start signal terminal to the first row shift register unit in the corresponding coupled gate drive sub-circuit in response to the positioning signal of the positioning signal terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1Some structural schematic diagrams of display panels provided by embodiments of the present disclosure;

[0050] Figure 2 Some structural schematic diagrams of the first control circuit provided in the embodiments of the present disclosure;

[0051] Figure 3 Some other structural schematic diagrams of the first control circuit provided by the embodiments of the present disclosure;

[0052] Figure 4 Some further structural schematic diagrams of the first control circuit provided in the embodiments of the present disclosure;

[0053] Figure 5 Some structural schematic diagrams of the second control circuit provided in the embodiments of the present disclosure;

[0054] Figure 6 Some signal timing diagrams provided for embodiments of the present disclosure;

[0055] Figure 7 Other structural schematic diagrams of display panels provided by embodiments of the present disclosure;

[0056] Figure 8 Some structural schematic diagrams of pixel circuits provided in embodiments of the present disclosure;

[0057] Figure 9 Some structural schematic diagrams of shift register units provided in embodiments of the present disclosure;

[0058] Figure 10 Other structural schematic diagrams of the shift register unit provided by the embodiments of the present disclosure;

[0059] Figure 11 Some further structural schematic diagrams of the shift register unit provided in the embodiments of the present disclosure;

[0060] Figure 12 Other signal timing diagrams provided for embodiments of the present disclosure;

[0061] Figure 13 Some further signal timing diagrams provided for embodiments of the present disclosure;

[0062] Figure 14 Some further signal timing diagrams are provided for the embodiments of the present disclosure. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0064] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0065] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0066] In an embodiment of the present disclosure, the display panel includes: a plurality of pixel units arranged in an array, each pixel unit including a plurality of sub-pixels. For example, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve a color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve a color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0067] Currently, the application scope of organic light-emitting diode (OLED) display panels has gradually expanded from small and medium-sized watches, mobile phones, tablets and other fields to personal computers, monitors and other fields. To achieve better display effects (for example, reducing the smear effect and improving the screen response speed), the refresh rate of display panels has been gradually increased. However, this increasing refresh rate of display panels also increases power consumption. Therefore, it is necessary to achieve low power consumption while achieving a high refresh rate for display panels.

[0068] Based on the above problems, the display panel provided by the embodiment of the present disclosure is as follows: Figure 1 As shown, including:

[0069] The first control circuit 10 is configured to respond to M addressing signal terminals (eg Figure 1 X1, X2, X3) of the signal, to N positioning signal terminals (such as Figure 1 Y1, Y2, Y3, Y4, Y5, Y6, Y7, and Y8) provide positioning signals; wherein M and N are positive integers greater than 0;

[0070] The gate drive circuit 20 includes a plurality of gate drive sub-circuits 201, each of which includes a plurality of shift register units (eg Figure 1 SR1, SR2, SR3, SR4, SR5, SR6, SR7);

[0071] Multiple second control circuits 30, the nth second control circuit 30 and the nth positioning signal terminal (for example Figure 1 Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 in the n-th gate drive sub-circuit 201), the first row of shift register units (e.g. Figure 1 SR1 in the coupling, the second control circuit 30 is configured to respond to the positioning signal end (eg Figure 1 The positioning signal of Y1, Y2, Y3, Y4, Y5, Y6, Y7, and Y8 in the gate driver sub-circuit 201 is provided to the first row shift register unit (e.g. Figure 1 wherein the output signal terminal OUT of the nth second control circuit 30 is coupled to the last row shift register unit in the n-1th gate drive sub-circuit 201 (eg Figure 1 SR5 in ).

[0072] The embodiment of the present disclosure can realize free selection of a local display area of ​​the display panel for data refresh through the mutual cooperation of the first control circuit, the gate drive circuit and the second control circuit; that is, by adjusting the signals of the M addressing signal terminals, the second control circuit can be controlled to provide the signal of the frame start signal terminal or the signal of the output signal terminal to the first row shift register unit in the corresponding coupled gate drive sub-circuit; in this way, a local area of ​​the display screen can be selected for refresh, and when the local data of the display screen is refreshed, the display panel also only refreshes the selected local area, so that the local area realizes a high-frequency refresh mode, while other partial areas are not refreshed, so that other partial areas realize a low-frequency refresh mode, thereby minimizing the driving power consumption; that is, the display panel can maintain low power consumption while having a high refresh rate.

[0073] In some embodiments of the present disclosure, N=2 M .

[0074] For example, when M=1, N=2; when M=2, N=4; when M=3, N=8; when M=4, N=16.

[0075] For example, the following embodiments of the present disclosure are described using M=3, N=8 as an example. Figure 1 As shown, the display panel includes 8 display areas AA1, AA2, AA3, AA4, AA5, AA6, AA7, and AA8; wherein, the display area AA1 is arranged corresponding to the first gate driving sub-circuit 201_1, the display area AA2 is arranged corresponding to the second gate driving sub-circuit 201_2, the display area AA3 is arranged corresponding to the third gate driving sub-circuit 201_3, the display area AA4 is arranged corresponding to the fourth gate driving sub-circuit 201_4, the display area AA5 is arranged corresponding to the fifth gate driving sub-circuit 201_5, the display area AA6 is arranged corresponding to the sixth gate driving sub-circuit 201_6, the display area AA7 is arranged corresponding to the seventh gate driving sub-circuit 201_7, and the display area AA8 is arranged corresponding to the eighth gate driving sub-circuit 201_8.

[0076] For example, Figure 1 As shown, the first second control circuit 30_1 is coupled to the first positioning signal terminal Y1, the second second control circuit 30_2 is coupled to the second positioning signal terminal Y2, the third second control circuit 30_3 is coupled to the third positioning signal terminal Y3, the fourth second control circuit 30_4 is coupled to the fourth positioning signal terminal Y4, the first second control circuit 30_1 is coupled to the first positioning signal terminal Y1, the sixth second control circuit 30_6 is coupled to the sixth positioning signal terminal Y6, the eighth second control circuit 30_8 is coupled to the eighth positioning signal terminal Y8, and the seventh second control circuit 30_7 is coupled to the seventh positioning signal terminal Y7.

[0077] For example, Figure 1As shown, the first second control circuit 30_1 is coupled to the first row shift register unit SR1 in the first gate driver sub-circuit 201_1, the second second control circuit 30_2 is coupled to the first row shift register unit SR2 in the second gate driver sub-circuit 202_2, the third second control circuit 30_3 is coupled to the first row shift register unit SR3 in the third gate driver sub-circuit 203_3, and the fourth second control circuit 30_4 is coupled to the first row shift register unit SR4 in the fourth gate driver sub-circuit 204_4. Then, the fifth second control circuit 30_5 is coupled to the first row shift register unit SR5 in the fifth gate driver sub-circuit 205_5, the sixth second control circuit 30_6 is coupled to the first row shift register unit SR6 in the sixth gate driver sub-circuit 206_6, the seventh second control circuit 30_7 is coupled to the first row shift register unit SR7 in the seventh gate driver sub-circuit 207_7, and the eighth second control circuit 30_8 is coupled to the first row shift register unit SR8 in the eighth gate driver sub-circuit 208_8.

[0078] For example, Figure 1 As shown, the output signal terminal OUT of the second second control circuit 30_2 is coupled to the last row shift register unit SR5 of the first gate driver sub-circuit 201_1; the output signal terminal OUT of the third second control circuit 30_3 is coupled to the last row shift register unit SR5 of the second gate driver sub-circuit 201_2; the output signal terminal OUT of the fourth second control circuit 30_4 is coupled to the last row shift register unit SR5 of the third gate driver sub-circuit 201_3; the output signal terminal OUT of the fifth second control circuit 30_5 is coupled to the last row shift register unit SR5 of the fourth gate driver sub-circuit 201_4. SR5 is coupled; the output signal terminal OUT in the sixth second control circuit 30_6 is coupled to the last row shift register unit SR5 in the fifth gate driver sub-circuit 201_5; the output signal terminal OUT in the seventh second control circuit 30_7 is coupled to the last row shift register unit SR5 in the sixth gate driver sub-circuit 201_6; the output signal terminal OUT in the eighth second control circuit 30_8 is coupled to the last row shift register unit SR5 in the seventh gate driver sub-circuit 201_7; it should be noted that the output signal terminal OUT in the first second control circuit 30_1 is coupled to the second power signal terminal VGL.

[0079] In some embodiments of the present disclosure, Figure 2 As shown, the first control circuit 10 includes: M first logic gate circuits 101 and N second logic gate circuits 102; wherein, one first logic gate circuit 101 is connected to an addressing signal terminal (eg Figure 2X1, X2, X3 in FIG, a second logic gate circuit 102 is coupled to a positioning signal terminal (eg Figure 2 Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8) are coupled;

[0080] The first logic gate circuit 101 is configured to respond to an addressing signal terminal (eg Figure 2 , generating a first logic signal;

[0081] The second logic gate circuit 102 is connected to the first logic gate circuit 101 and / or the addressing signal terminal (eg Figure 2 The second logic gate circuit 102 is configured to respond to the first logic signal and / or the addressing signal terminal (eg Figure 2 X1, X2, X3) in the signal, to the positioning signal end (such as Figure 2 Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8) provide positioning signals.

[0082] For example, Figure 2 As shown, the first first logic gate circuit 101_1 is coupled to the first addressing signal terminal X1, the second first logic gate circuit 101_2 is coupled to the second addressing signal terminal X2, and the third first logic gate circuit 101_3 is coupled to the first addressing signal terminal X3.

[0083] For example, Figure 2 As shown, the first second logic gate circuit 102_1 is coupled to the first positioning signal terminal Y1, the second second logic gate circuit 102_2 is coupled to the second positioning signal terminal Y2, the third second logic gate circuit 102_3 is coupled to the third positioning signal terminal Y3, the fourth second logic gate circuit 102_4 is coupled to the fourth positioning signal terminal Y4, the fifth second logic gate circuit 102_5 is coupled to the fifth positioning signal terminal Y5, the sixth second logic gate circuit 102_6 is coupled to the sixth positioning signal terminal Y6, the seventh second logic gate circuit 102_7 is coupled to the seventh positioning signal terminal Y7, and the eighth second logic gate circuit 102_8 is coupled to the eighth positioning signal terminal Y8.

[0084] In some embodiments of the present disclosure, Figure 2 As shown, M=3, N=8;

[0085] A first terminal of the first second logic gate circuit 102_1 is coupled to the first positioning signal terminal Y1, a second terminal of the first second logic gate circuit 102_1 is coupled to the first terminal of the first first logic gate circuit 101_1, a third terminal of the first second logic gate circuit 102_1 is coupled to the first terminal of the second first logic gate circuit 101_2, and a fourth terminal of the first second logic gate circuit 102_1 is coupled to the first terminal of the third first logic gate circuit 101_3;

[0086] A first terminal of the second second logic gate circuit 102_2 is coupled to the second positioning signal terminal Y2, a second terminal of the second second logic gate circuit 102_2 is coupled to the first addressing signal terminal X1, a third terminal of the second second logic gate circuit 102_2 is coupled to the first terminal of the second first logic gate circuit 101_2, and a fourth terminal of the second second logic gate circuit 102_2 is coupled to the first terminal of the third first logic gate circuit 101_3;

[0087] A first terminal of the third second logic gate circuit 102_3 is coupled to the third positioning signal terminal Y3, a second terminal of the third second logic gate circuit 102_3 is coupled to the first terminal of the first first logic gate circuit 101_1, a third terminal of the third second logic gate circuit 102_3 is coupled to the first terminal of the second first logic gate circuit 101_2, and a fourth terminal of the third second logic gate circuit 102_3 is coupled to the third addressing signal terminal X3;

[0088] A first terminal of the fourth second logic gate circuit 102_4 is coupled to the fourth positioning signal terminal Y4, a second terminal of the fourth second logic gate circuit 102_4 is coupled to the first addressing signal terminal X1, a third terminal of the fourth second logic gate circuit 102_4 is coupled to the first terminal of the second first logic gate circuit 101_2, and a fourth terminal of the fourth second logic gate circuit 102_4 is coupled to the third addressing signal terminal X3;

[0089] A first terminal of the fifth second logic gate circuit 102_5 is coupled to the fifth positioning signal terminal Y5, a second terminal of the fifth second logic gate circuit 102_5 is coupled to the first terminal of the first first logic gate circuit 101_1, a third terminal of the fifth second logic gate circuit 102_5 is coupled to the second addressing signal terminal X2, and a fourth terminal of the fifth second logic gate circuit 102_5 is coupled to the first terminal of the third first logic gate circuit 101_3;

[0090] A first terminal of the sixth second logic gate circuit 102_6 is coupled to the sixth positioning signal terminal Y6, a second terminal of the sixth second logic gate circuit 102_6 is coupled to the first addressing signal terminal X1, a third terminal of the sixth second logic gate circuit 102_6 is coupled to the second addressing signal terminal X2, and a fourth terminal of the sixth second logic gate circuit 102_6 is coupled to the first terminal of the third first logic gate circuit 101_3;

[0091] A first terminal of the seventh second logic gate circuit 102_7 is coupled to the seventh positioning signal terminal Y7, a second terminal of the seventh second logic gate circuit 102_7 is coupled to the first terminal of the first first logic gate circuit 101_1, a third terminal of the seventh second logic gate circuit 102_7 is coupled to the second addressing signal terminal X2, and a fourth terminal of the seventh second logic gate circuit 102_7 is coupled to the third addressing signal terminal X3;

[0092] A first terminal of the eighth second logic gate circuit 102_8 is coupled to the eighth positioning signal terminal Y8, a second terminal of the eighth second logic gate circuit 102_8 is coupled to the first addressing signal terminal X1, a third terminal of the eighth second logic gate circuit 102_8 is coupled to the second addressing signal terminal X2, and a fourth terminal of the eighth second logic gate circuit 102_8 is coupled to the third addressing signal terminal X3;

[0093] The second terminal of the first first logic gate circuit 101_1 is coupled to the first addressing signal terminal X1;

[0094] The second terminal of the second first logic gate circuit 101_2 is coupled to the second addressing signal terminal X2;

[0095] A second terminal of the third first logic gate circuit 101_3 is coupled to the third addressing signal terminal X3.

[0096] For example, as shown in Table 1 below, when the signal on the addressing signal terminal X1 is "0", the signal on the addressing signal terminal X2 is "0", and the signal on the addressing signal terminal X3 is "0", the positioning signal on the positioning signal terminal Y8 is "1", then the display area AA8 is selected as the refresh area; when the signal on the addressing signal terminal X1 is "1", the signal on the addressing signal terminal X2 is "0", and the signal on the addressing signal terminal X3 is "0", the positioning signal on the positioning signal terminal Y7 is "1", then the display area AA8 is selected as the refresh area. Display area AA7 is the refresh area; when the signal on the addressing signal terminal X1 is "0", the signal on the addressing signal terminal X2 is "0", the signal on the addressing signal terminal X3 is "1", and the positioning signal on the positioning signal terminal Y6 is "1", then the display area AA6 is selected as the refresh area; when the signal on the addressing signal terminal X1 is "1", the signal on the addressing signal terminal X2 is "0", the signal on the addressing signal terminal X3 is "1", and the positioning signal on the positioning signal terminal Y5 is "1", then the display area A is selected. A5 is the refresh area; when the signal on the addressing signal terminal X1 is "0", the signal on the addressing signal terminal X2 is "1", the signal on the addressing signal terminal X3 is "0", the positioning signal on the positioning signal terminal Y4 is "1", then the display area AA4 is selected as the refresh area; when the signal on the addressing signal terminal X1 is "1", the signal on the addressing signal terminal X2 is "1", the signal on the addressing signal terminal X3 is "0", the positioning signal on the positioning signal terminal Y3 is "1", then the display area AA3 is selected as the refresh area. new area; when the signal on the addressing signal terminal X1 is "0", the signal on the addressing signal terminal X2 is "1", the signal on the addressing signal terminal X3 is "1", the positioning signal on the positioning signal terminal Y2 is "1", then the display area AA2 is selected as the refresh area; when the signal on the addressing signal terminal X1 is "1", the signal on the addressing signal terminal X2 is "1", the signal on the addressing signal terminal X3 is "1", the positioning signal on the positioning signal terminal Y1 is "1", then the display area AA1 is selected as the refresh area.

[0097]

[0098]

[0099] Table 1

[0100] It should be noted that, in the embodiment of the present disclosure, “0” represents a low-level signal, and “1” represents a high-level signal.

[0101] For example, Figure 3As shown, when the signal on the addressing signal terminal X1 is "0", the signal on the addressing signal terminal X2 is "0", and the signal on the addressing signal terminal X3 is "0", the first logic signal generated by the first terminal of the first logic gate circuit 101_1 is "1", the first logic signal generated by the first terminal of the first logic gate circuit 101_2 is "1", and the first logic signal generated by the first terminal of the first logic gate circuit 101_3 is "1", then the signals on the second terminal, the third terminal, and the fourth terminal of the second logic gate circuit 102_1 are "1", "1", and "1" respectively, so that the second logic gate circuit The first end of 102_1 provides a positioning signal of "0" to the positioning signal terminal Y1, and the signals of the second end, third end, and fourth end of the second logic gate circuit 102_2 are "0", "1", and "1" respectively, so that the first end of the second logic gate circuit 102_2 provides a positioning signal of "0" to the positioning signal terminal Y2, and the signals of the second end, third end, and fourth end of the second logic gate circuit 102_3 are "1", "1", and "0" respectively, so that the first end of the second logic gate circuit 102_3 provides a positioning signal of "0" to the positioning signal terminal Y3, and the second logic gate circuit The signals at the second, third, and fourth ends of 102_4 are "0", "1", and "0" respectively, so that the first end of the second logic gate circuit 102_4 provides a positioning signal of "0" to the positioning signal end Y4. The signals at the second, third, and fourth ends of the second logic gate circuit 102_5 are "1", "0", and "1" respectively, so that the first end of the second logic gate circuit 102_5 provides a positioning signal of "0" to the positioning signal end Y5. The signals at the second, third, and fourth ends of the second logic gate circuit 102_6 are "0", "0", and "1" respectively. The first end of the second logic gate circuit 102_6 provides a positioning signal of "0" to the positioning signal terminal Y6, and the signals of the second end, third end, and fourth end of the second logic gate circuit 102_7 are "1", "0", and "0" respectively, so that the first end of the second logic gate circuit 102_7 provides a positioning signal of "0" to the positioning signal terminal Y7, and the signals of the second end, third end, and fourth end of the second logic gate circuit 102_8 are "0", "0", and "0" respectively, so that the first end of the second logic gate circuit 102_8 provides a positioning signal of "1" to the positioning signal terminal Y8.

[0102] In some embodiments of the present disclosure, Figure 4 As shown, the first logic circuit (eg Figure 4 101_1, 101_2, 101_3) include: a first transistor T1 and a second transistor T2;

[0103] The gate of the first transistor T1 is connected to the addressing signal terminal (eg Figure 4X1, X2, X3 in FIG, wherein the first electrode of the first transistor T1 is coupled to the first power signal terminal VGH, and the second electrode of the first transistor T1 is coupled to the first electrode of the second transistor T2;

[0104] The gate of the second transistor T2 is connected to the addressing signal terminal (eg Figure 4 The second electrode of the second transistor T2 is coupled to the second power signal terminal VGL.

[0105] In some embodiments of the present disclosure, Figure 4 As shown, the effective level signal of the first transistor T1 is different from the effective level signal of the second transistor T2.

[0106] For example, the first transistor T1 and the second transistor T2 are connected to the addressing signal terminal (eg Figure 4 The signal is turned on under the control of the valid level signal transmitted on the X1, X2, and X3 in the addressing signal terminal (for example Figure 4 The first transistor T1 can be configured as a P-type transistor, in which case the active level signal at the addressing signal terminal is a low level signal, and the inactive level signal at the addressing signal terminal is a high level signal; the second transistor T2 can be configured as an N-type transistor, in which case the active level signal at the addressing signal terminal is a high level signal, and the inactive level signal at the addressing signal terminal is a low level signal.

[0107] In some embodiments of the present disclosure, Figure 4 As shown, the second logic circuit (eg Figure 4 102_1, 102_2, 102_3, 102_4, 102_5, 102_6, 102_7, 102_8) include: a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8;

[0108] The gate of the third transistor T3 is coupled to the gate of the sixth transistor T6, the first electrode of the third transistor T3 is coupled to the second power signal terminal VGL, and the second electrode of the third transistor T3 is coupled to the positioning signal terminal (eg Figure 4 Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8) are coupled;

[0109] The gate of the fourth transistor T4 is coupled to the gate of the seventh transistor T7, the first electrode of the fourth transistor T4 is coupled to the second power signal terminal VGL, and the second electrode of the fourth transistor T4 is coupled to the positioning signal terminal (eg Figure 4 Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8) are coupled;

[0110] The gate of the fifth transistor T5 is coupled to the gate of the eighth transistor T8, the first electrode of the fifth transistor T5 is coupled to the second power signal terminal VGL, and the second electrode of the fifth transistor T5 is coupled to the positioning signal terminal (eg Figure 4 Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8) are coupled;

[0111] A first electrode of the sixth transistor T6 is coupled to the first power signal terminal VGH, a second electrode of the sixth transistor T6 is coupled to a first electrode of the seventh transistor T7 , and a second electrode of the seventh transistor T7 is coupled to a first electrode of the eighth transistor T8 .

[0112] In some embodiments of the present disclosure, Figure 4 As shown, the effective level signals of the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are the same;

[0113] The effective level signals of the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are the same;

[0114] The active level signals of the third transistor T3 and the sixth transistor T6 are different.

[0115] Exemplarily, the third transistor, the fourth transistor and the fifth transistor can be turned on under the control of a valid level signal and can be turned off under the control of an invalid level signal; the sixth transistor, the seventh transistor and the eighth transistor can be turned on under the control of a valid level signal and can be turned off under the control of an invalid level signal; for example, the third transistor, the fourth transistor and the fifth transistor can be set as N-type transistors, then the valid level signal is a high level signal, and the invalid level signal is a low level signal; the sixth transistor, the seventh transistor and the eighth transistor can be set as P-type transistors, then the valid level signal is a high level signal, and the invalid level signal is a low level signal.

[0116] In some embodiments of the present disclosure, Figure 5 As shown, the second control circuit 30_2 includes: a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16;

[0117] A gate of the ninth transistor T9 is coupled to the second electrode of the eleventh transistor T11 , a first electrode of the ninth transistor T9 is coupled to the first power signal terminal VGH, and a second electrode of the ninth transistor T9 is coupled to the first electrode of the tenth transistor T10 ;

[0118] The gate of the tenth transistor T10 is coupled to the second electrode of the eleventh transistor T11 , and the second electrode of the tenth transistor T10 is coupled to the second power signal terminal VGL;

[0119] The gate of the eleventh transistor T11 is coupled to the positioning signal terminal Y2, the first electrode of the eleventh transistor T11 is coupled to the first power signal terminal VGH, the second electrode of the eleventh transistor T11 is coupled to the first electrode of the twelfth transistor T12,

[0120] A gate of the twelfth transistor T12 is coupled to the positioning signal terminal Y2, and a second electrode of the twelfth transistor T12 is coupled to the second power signal terminal VGL;

[0121] A gate of the thirteenth transistor T13 is coupled to the positioning signal terminal Y2 , a first electrode of the thirteenth transistor T13 is coupled to the output signal terminal OUT, and a second electrode of the thirteenth transistor T13 is coupled to the first-row shift register unit SR1 in the gate driving sub-circuit 201_2 ;

[0122] A gate of the fourteenth transistor T14 is coupled to the second electrode of the eleventh transistor T11 , a first electrode of the fourteenth transistor T14 is coupled to the output signal terminal OUT, and a second electrode of the fourteenth transistor T14 is coupled to the first-row shift register unit SR1 in the gate driving sub-circuit 201_2 ;

[0123] A gate of the fifteenth transistor T15 is coupled to the second electrode of the eleventh transistor T11 , a first electrode of the fifteenth transistor T15 is coupled to the frame start signal terminal STV, and a second electrode of the fifteenth transistor T15 is coupled to the first-row shift register unit SR1 in the gate driving sub-circuit 201_2 .

[0124] A gate of the sixteenth transistor T16 is coupled to the positioning signal terminal Y2 , a first electrode of the sixteenth transistor T16 is coupled to the frame start signal terminal STV, and a second electrode of the sixteenth transistor T16 is coupled to the first row shift register unit SR1 in the gate driving sub-circuit 201_2 .

[0125] Illustratively, the first electrode of the transistor serves as its source and the second electrode serves as its drain, or the first electrode of the transistor serves as its drain and the second electrode serves as its source, which is not limited here.

[0126] In some embodiments of the present disclosure, Figure 1 As shown, each gate driver sub-circuit 201 includes the same or different numbers of shift register units. For example, gate driver sub-circuits 201_1 to 201_7 include five shift register units, namely SR1, SR2, SR3, SR4, and SR5; and gate driver sub-circuit 201_8 includes seven shift register units, namely SR1, SR2, SR3, SR4, SR5, SR6, and SR7. Of course, the specific number can be set according to needs and is not specifically limited here.

[0127] The driving method of the display panel provided by the embodiment of the present disclosure includes: a first operating mode and a second operating mode;

[0128] In a first operating mode, the first control circuit provides positioning signals to the N positioning signal terminals in response to signals from the M addressing signal terminals; the first control circuit is configured to provide signals from the output signal terminals to the first row shift register units in the corresponding coupled gate drive sub-circuit in response to the positioning signals from the positioning signal terminals;

[0129] In the second operating mode, the first control circuit provides a positioning signal to the N positioning signal terminals in response to the signals of the M addressing signal terminals; the first control circuit is configured to provide the signal of the frame start signal terminal to the first row shift register unit in the corresponding coupled gate drive sub-circuit in response to the positioning signal of the positioning signal terminal.

[0130] Below Figure 1 、 4 , 5 as an example, combined with Figure 6 The signal timing diagram shown describes the working process of the display panel provided by the embodiment of the present disclosure.

[0131] Among them, such as Figure 6 As shown, x1 represents the signal on the addressing signal terminal X1, x2 represents the signal on the addressing signal terminal X2, x3 represents the signal on the addressing signal terminal X3, y1 represents the positioning signal on the positioning signal terminal Y1, y2 represents the positioning signal on the positioning signal terminal Y2, y3 represents the positioning signal on the positioning signal terminal Y3, y4 represents the positioning signal on the positioning signal terminal Y4, y5 represents the positioning signal on the positioning signal terminal Y5, y6 represents the positioning signal on the positioning signal terminal Y6, y7 represents the positioning signal on the positioning signal terminal Y7, and y8 represents the positioning signal on the positioning signal terminal Y8.

[0132] For example, Figure 7 As shown, when it is necessary to select display areas AA2, AA5 and AA7 as refresh areas and select display areas AA1, AA3, AA4, AA6 and AA8 as hold areas;

[0133] At the first time t1, specifically including: a first working mode and a second working mode;

[0134] The signal x1 on the addressing signal terminal X1 is a low-level signal, the signal x2 on the addressing signal terminal X2 is a high-level signal, and the signal x3 on the addressing signal terminal X3 is a high-level signal; then the first transistor T1 in the first logic circuit 101_1 is turned on under the control of the low-level signal x1, and the second transistor T2 is turned off under the control of the low-level signal x2. The turned-on first transistor T1 outputs the high-level signal of the first power supply signal terminal VGH, that is, the first logic signal provided by the first logic circuit 101_1 is a high-level signal; the first transistor T1 in the first logic circuit 101_2 is turned off under the control of the high-level signal x2. The first transistor T1 in the first logic circuit 101_3 is turned off under the control of the high level of the signal x3, and the second transistor T2 is turned on under the control of the high level of the signal x3. The turned-on second transistor T2 outputs the low level signal of the second power supply signal terminal VGL, that is, the first logic signal provided by the first logic circuit 101_2 is a low level signal. The first transistor T1 in the first logic circuit 101_3 is turned off under the control of the high level of the signal x3, and the second transistor T2 is turned on under the control of the high level of the signal x3. The turned-on second transistor T2 outputs the low level signal of the second power supply signal terminal VGL, that is, the first logic signal provided by the first logic circuit 101_3 is a low level signal.

[0135] The third transistor T3, the seventh transistor T7, and the eighth transistor T8 in the second logic gate circuit 102_1 are turned on, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. Then, the turned-on third transistor T3 provides the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y1, and the turned-on seventh transistor T7 and the eighth transistor T8 connect the second electrode of the sixth transistor T6 to the positioning signal terminal Y1, that is, the positioning signal of the positioning signal terminal Y1 is a low-level signal; then, the signal on the first node N1 in the second control circuit 30_1 is a low-level signal, and the eleventh transistor T11 is turned on under the control of the low-level signal. The turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2, then the signal on the second node N2 is a high-level signal, and the twelfth transistor T12 is turned off under the control of the low-level signal. The ninth transistor T9 is turned off under the control of the high-level signal, and the tenth transistor T10 is turned on under the control of the high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable. The thirteenth transistor T13 is turned on under the control of the low-level signal. The turned-on thirteenth transistor T13 provides the signal at the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_1. The fourteenth transistor T14 is turned on under the control of the high-level signal. The turned-on fourteenth transistor T14 provides the signal at the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_1. The fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal. Then, the display area AA1 becomes the holding area.

[0136] The sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 in the second logic gate circuit 102_2 are turned on, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off. Then, the turned-on sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 provide the high-level signal of the first power supply signal terminal VGH to the positioning signal terminal Y2, that is, the positioning signal of the positioning signal terminal Y2 is a high-level signal; then, the signal on the first node N1 in the second control circuit 30_2 is a high-level signal, the eleventh transistor T11 is turned off under the control of the high-level signal, and the twelfth transistor T12 is turned on under the control of the high-level signal. The turned-on twelfth transistor T12 provides the low-level signal of the second power supply signal terminal VGL to the second node N2, then the signal on the second node N2 is a low-level signal, and the ninth transistor T9 is turned off under the control of the low-level signal. The ninth transistor T9 is turned on under the control of the low-level signal, and the turned-on ninth transistor T9 provides the high-level signal of the first power supply signal terminal VGH to the first node N1, maintaining the voltage of the first node N1 stable. The tenth transistor T10 is turned off under the control of the low-level signal, the thirteenth transistor T13 is turned off under the control of the high-level signal, the fourteenth transistor T14 is turned off under the control of the low-level signal, and the fifteenth transistor T15 is turned on under the control of the low-level signal, and the turned-on fifteenth transistor T15 provides the signal on the frame start signal terminal STV to the shift register unit SR1 in the gate driver sub-circuit 201_2. The sixteenth transistor T16 is turned on under the control of the high-level signal, and the turned-on sixteenth transistor T16 provides the signal on the frame start signal terminal STV to the shift register unit SR1 in the gate driver sub-circuit 201_2, then the display area AA2 is the refresh area;

[0137] The third transistor T3, the fifth transistor T5, and the seventh transistor T7 in the second logic gate circuit 102_3 are turned on, and the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are turned off. Then, the turned-on third transistor T3 provides the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y3, the turned-on fifth transistor T5 provides the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y3, and the turned-on seventh transistor T7 connects the second electrode of the sixth transistor T6 with the first electrode of the eighth transistor T8, that is, the positioning signal of the positioning signal terminal Y3 is a low-level signal; then, the signal on the first node N1 in the second control circuit 30_3 is a low-level signal, the eleventh transistor T11 is turned on under the control of the low-level signal, and the turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2, then the signal on the second node N2 is a high-level signal, and the twelfth transistor T12 is turned off under the control of the low-level signal, the ninth transistor T9 is turned off under the control of the high-level signal, and the tenth transistor T10 is turned on under the control of the high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable; the thirteenth transistor T13 is turned on under the control of the low-level signal, and the turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_3; the fourteenth transistor T14 is turned on under the control of the high-level signal, and the turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_3; the fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal, then the display area AA3 becomes the holding area;

[0138] The fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the second logic gate circuit 102_4 are turned on, and the third transistor T3, the fourth transistor T4, and the eighth transistor T8 are turned off. Then, the turned-on fifth transistor T5 provides the low-level signal of the second power signal terminal VGL to the positioning signal terminal Y4, and the turned-on sixth transistor T6 and the turned-on seventh transistor T7 connect the first power signal terminal VGH to the first electrode of the eighth transistor T8, that is, the positioning signal of the positioning signal terminal Y4 is a low-level signal; then, the signal at the first node N1 in the second control circuit 30_4 is a low-level signal, and the eleventh transistor T11 is turned on under the control of the low-level signal. The turned-on eleventh transistor T11 provides the high-level signal of the first power signal terminal VGH to the second node N2, and the signal at the second node N2 is a high-level signal. The twelfth transistor T12 is turned off under the control of the low-level signal. The ninth transistor T9 is turned off under the control of the high-level signal, and the tenth transistor T10 is turned on under the control of the high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable. The thirteenth transistor T13 is turned on under the control of the low-level signal. The turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_4. The fourteenth transistor T14 is turned on under the control of the high-level signal. The turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_4. The fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal. Then, the display area AA4 becomes the holding area.

[0139] The fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the second logic gate circuit 102_5 are turned off, and the third transistor T3, the fourth transistor T4, and the eighth transistor T8 are turned on. The turned-on third transistor T3 and the fourth transistor T4 provide the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y5. The turned-on eighth transistor T8 connects the first electrode of the seventh transistor T7 to the positioning signal terminal Y5, that is, the positioning signal of the positioning signal terminal Y5 is a low-level signal. The signal on the first node N1 in the second control circuit 30_5 is a low-level signal. The eleventh transistor T11 is turned on under the control of the low-level signal. The turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2. The signal on the second node N2 is a high-level signal. The twelfth transistor T12 is turned off under the control of the low-level signal. The ninth transistor T9 is turned off under the control of the high-level signal, and the tenth transistor T10 is turned on under the control of the high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable. The thirteenth transistor T13 is turned on under the control of the low-level signal. The turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_5. The fourteenth transistor T14 is turned on under the control of the high-level signal. The turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_5. The fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal. Then, the display area AA5 becomes the holding area.

[0140] The third transistor T3, the fifth transistor T5, and the seventh transistor T7 in the second logic gate circuit 102_6 are turned off, and the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are turned on. The turned-on fourth transistor T4 provides the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y6, the turned-on sixth transistor T6 connects the first power supply signal terminal VGH with the first electrode of the seventh transistor T7, and the turned-on eighth transistor T8 connects the second electrode of the seventh transistor T7 with the positioning signal terminal Y6, that is, the positioning signal of the positioning signal terminal Y6 is a low-level signal; then the signal on the first node N1 in the second control circuit 30_6 is a low-level signal, the eleventh transistor T11 is turned on under the control of the low-level signal, and the turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2, then the signal on the second node N2 is a high-level signal, and the twelfth transistor T12 is turned on. The ninth transistor T9 is turned off under the control of the low-level signal, the tenth transistor T10 is turned on under the control of the high-level signal, and the turned-on tenth transistor T10 provides the low-level signal of the second power supply signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable; the thirteenth transistor T13 is turned on under the control of the low-level signal, and the turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_6; the fourteenth transistor T14 is turned on under the control of the high-level signal, and the turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_6; the fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal, then the display area AA6 becomes the holding area;

[0141] The sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 in the second logic gate circuit 102_7 are turned off, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on. Then, the turned-on third transistor T3, the fourth transistor T4, and the fifth transistor T5 provide the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y7, that is, the positioning signal of the positioning signal terminal Y7 is a high-level signal; then, the signal on the first node N1 in the second control circuit 30_7 is a low-level signal, and the eleventh transistor T11 is turned on under the control of the low-level signal. The turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2, then the signal on the second node N2 is a high-level signal, the twelfth transistor T12 is turned off under the control of the low-level signal, and the ninth transistor T9 is turned on under the control of the high-level signal. The display area AA7 is a holding area.

[0142] The third transistor T3, the seventh transistor T7, and the eighth transistor T8 in the second logic gate circuit 102_8 are turned off, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned on. The turned-on fourth transistor T4 and the fifth transistor T5 provide the low-level signal of the second power signal terminal VGL to the positioning signal terminal Y8, and the turned-on sixth transistor T6 connects the first power signal terminal VGH to the first electrode of the seventh transistor T7, that is, the positioning signal of the positioning signal terminal Y8 is a low-level signal; then the signal on the first node N1 in the second control circuit 30_8 is a low-level signal, and the eleventh transistor T11 is turned on under the control of the low-level signal. The turned-on eleventh transistor T11 provides the high-level signal of the first power signal terminal VGH to the second node N2, and the signal on the second node N2 is a high-level signal. The twelfth transistor T12 is turned off under the control of the low-level signal. The ninth transistor T9 is turned off under the control of the high-level signal, and the tenth transistor T10 is turned on under the control of the high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power supply signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable; the thirteenth transistor T13 is turned on under the control of the low-level signal, and the turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_8; the fourteenth transistor T14 is turned on under the control of the high-level signal, and the turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_8; the fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal, and the display area AA8 is a holding area.

[0143] At the second time t1, specifically including: the first working mode and the second working mode;

[0144] The signal x1 on the addressing signal terminal X1 is a high-level signal, the signal x2 on the addressing signal terminal X2 is a low-level signal, and the signal x3 on the addressing signal terminal X3 is a high-level signal; then the first transistor T1 in the first logic circuit 101_1 is turned off under the control of the high-level signal x1, and the second transistor T2 is turned on under the control of the high-level signal x2. The turned-on second transistor T2 outputs the low-level signal of the second power supply signal terminal VGL, that is, the first logic signal provided by the first logic circuit 101_1 is a low-level signal; the first transistor T1 in the first logic circuit 101_2 is turned off under the control of the low-level signal x2. The first transistor T1 in the first logic circuit 101_3 is turned on by the high level of the signal x3, and the second transistor T2 is turned off by the low level of the signal x2. The turned-on first transistor T1 outputs a high-level signal of the first power supply signal terminal VGH, that is, the first logic signal provided by the first logic circuit 101_2 is a high-level signal. The first transistor T1 in the first logic circuit 101_3 is turned off by the high level of the signal x3, and the second transistor T2 is turned on by the high level of the signal x3. The turned-on second transistor T2 outputs a low-level signal of the second power supply signal terminal VGL, that is, the first logic signal provided by the first logic circuit 101_3 is a low-level signal.

[0145] The third transistor T3, the fifth transistor T5, and the seventh transistor T7 in the second logic gate circuit 102_1 are turned off, and the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are turned on. The turned-on fourth transistor T4 provides the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y1, the turned-on sixth transistor T6 connects the first power supply signal terminal VGH to the first electrode of the seventh transistor T7, and the turned-on eighth transistor T8 connects the second electrode of the seventh transistor T7 to the positioning signal terminal Y1, that is, the positioning signal of the positioning signal terminal Y1 is a low-level signal; then the signal on the first node N1 in the second control circuit 30_1 is a low-level signal, the eleventh transistor T11 is turned on under the control of the low-level signal, and the turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2, then the signal on the second node N2 is a high-level signal, and the twelfth transistor T12 is turned on. The ninth transistor T9 is turned off under the control of the low-level signal, the tenth transistor T10 is turned on under the control of the high-level signal, and the turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable; the thirteenth transistor T13 is turned on under the control of the low-level signal, and the turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_1; the fourteenth transistor T14 is turned on under the control of the high-level signal, and the turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_1; the fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal, then the display area AA1 becomes the holding area;

[0146] The fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the second logic gate circuit 102_2 are turned off, and the third transistor T3, the fourth transistor T4, and the eighth transistor T8 are turned on. The turned-on third transistor T3 and the fourth transistor T4 provide the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y2. The turned-on eighth transistor T8 connects the first electrode of the seventh transistor T7 to the positioning signal terminal Y2, that is, the positioning signal of the positioning signal terminal Y2 is a low-level signal. The signal on the first node N1 in the second control circuit 30_2 is a low-level signal. The eleventh transistor T11 is turned on under the control of the low-level signal. The turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2. The signal on the second node N2 is a high-level signal. The twelfth transistor T12 is turned off under the control of the low-level signal. The ninth transistor T9 is turned off under the control of the high-level signal, and the tenth transistor T10 is turned on under the control of the high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable. The thirteenth transistor T13 is turned on under the control of the low-level signal. The turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_2. The fourteenth transistor T14 is turned on under the control of the high-level signal. The turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_2. The fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal. Then, the display area AA2 becomes the holding area.

[0147] The third transistor T3, the seventh transistor T7, and the eighth transistor T8 in the second logic gate circuit 102_3 are turned off, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned on. The turned-on fourth transistor T4 and the fifth transistor T5 provide the low-level signal of the second power signal terminal VGL to the positioning signal terminal Y3, and the turned-on sixth transistor T6 connects the first power signal terminal VGH to the first electrode of the seventh transistor T7, that is, the positioning signal of the positioning signal terminal Y3 is a low-level signal; then the signal on the first node N1 in the second control circuit 30_3 is a low-level signal, and the eleventh transistor T11 is turned on under the control of the low-level signal. The turned-on eleventh transistor T11 provides the high-level signal of the first power signal terminal VGH to the second node N2, and the signal on the second node N2 is a high-level signal. The twelfth transistor T12 is turned off under the control of the low-level signal. The ninth transistor T9 is turned off under the control of the high-level signal, and the tenth transistor T10 is turned on under the control of the high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable. The thirteenth transistor T13 is turned on under the control of the low-level signal. The turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_3. The fourteenth transistor T14 is turned on under the control of the high-level signal. The turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_3. The fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal. Then, the display area AA3 becomes the holding area.

[0148] The sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 in the second logic gate circuit 102_4 are turned off, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on. The turned-on third transistor T3, the fourth transistor T4, and the fifth transistor T5 provide the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y4, that is, the positioning signal of the positioning signal terminal Y4 is a high-level signal; the signal on the first node N1 in the second control circuit 30_4 is a low-level signal, the eleventh transistor T11 is turned on under the control of the low-level signal, and the turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2, then the signal on the second node N2 is a high-level signal, the twelfth transistor T12 is turned off under the control of the low-level signal, and the ninth transistor T9 is turned on under the control of the high-level signal. The display area AA4 is a holding area.

[0149] The sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 in the second logic gate circuit 102_5 are turned on, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off. Then, the turned-on sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 provide the high-level signal of the first power supply signal terminal VGH to the positioning signal terminal Y5, that is, the positioning signal of the positioning signal terminal Y5 is a high-level signal; then, the signal on the first node N1 in the second control circuit 30_5 is a high-level signal, the eleventh transistor T11 is turned off under the control of the high-level signal, and the twelfth transistor T12 is turned on under the control of the high-level signal. The turned-on twelfth transistor T12 provides the low-level signal of the second power supply signal terminal VGL to the second node N2, then the signal on the second node N2 is a low-level signal, and the ninth transistor T9 is turned off under the control of the low-level signal. The ninth transistor T9 is turned on under the control of the low-level signal, and the turned-on ninth transistor T9 provides the high-level signal of the first power supply signal terminal VGH to the first node N1, maintaining the voltage of the first node N1 stable. The tenth transistor T10 is turned off under the control of the low-level signal, the thirteenth transistor T13 is turned off under the control of the high-level signal, the fourteenth transistor T14 is turned off under the control of the low-level signal, and the fifteenth transistor T15 is turned on under the control of the low-level signal, and the turned-on fifteenth transistor T15 provides the signal on the frame start signal terminal STV to the shift register unit SR1 in the gate driver sub-circuit 201_5. The sixteenth transistor T16 is turned on under the control of the high-level signal, and the turned-on sixteenth transistor T16 provides the signal on the frame start signal terminal STV to the shift register unit SR1 in the gate driver sub-circuit 201_5, then the display area AA5 is the refresh area;

[0150] The third transistor T3, the seventh transistor T7, and the eighth transistor T8 in the second logic gate circuit 102_6 are turned on, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. Then, the turned-on third transistor T3 provides the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y6, and the turned-on seventh transistor T7 and the eighth transistor T8 connect the second electrode of the sixth transistor T6 to the positioning signal terminal Y6, that is, the positioning signal of the positioning signal terminal Y6 is a low-level signal; then, the signal on the first node N1 in the second control circuit 30_6 is a low-level signal, and the eleventh transistor T11 is turned on under the control of the low-level signal. The turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2, then the signal on the second node N2 is a high-level signal, and the twelfth transistor T12 is turned off under the control of the low-level signal. The ninth transistor T9 is turned off under the control of the high-level signal, and the tenth transistor T10 is turned on under the control of the high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable. The thirteenth transistor T13 is turned on under the control of the low-level signal. The turned-on thirteenth transistor T13 provides the signal at the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_6. The fourteenth transistor T14 is turned on under the control of the high-level signal. The turned-on fourteenth transistor T14 provides the signal at the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_6. The fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal. Then, the display area AA6 becomes the holding area.

[0151] The fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the second logic gate circuit 102_7 are turned on, and the third transistor T3, the fourth transistor T4, and the eighth transistor T8 are turned off. Then, the turned-on fifth transistor T5 provides the low-level signal of the second power signal terminal VGL to the positioning signal terminal Y7, and the turned-on sixth transistor T6 and the turned-on seventh transistor T7 connect the first power signal terminal VGH to the first electrode of the eighth transistor T8, that is, the positioning signal of the positioning signal terminal Y7 is a low-level signal; then, the signal at the first node N1 in the second control circuit 30_7 is a low-level signal, and the eleventh transistor T11 is turned on under the control of the low-level signal. The turned-on eleventh transistor T11 provides the high-level signal of the first power signal terminal VGH to the second node N2, and the signal at the second node N2 is a high-level signal. The twelfth transistor T12 is turned off under the control of the low-level signal. The ninth transistor T9 is turned off under the control of the high-level signal, and the tenth transistor T10 is turned on under the control of the high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable. The thirteenth transistor T13 is turned on under the control of the low-level signal. The turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_7. The fourteenth transistor T14 is turned on under the control of the high-level signal. The turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_7. The fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal. Then, the display area AA7 becomes the holding area.

[0152] The third transistor T3, the fifth transistor T5, and the seventh transistor T7 in the second logic gate circuit 102_8 are turned on, and the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are turned off. Then, the turned-on third transistor T3 provides the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y8, the turned-on fifth transistor T5 provides the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y8, and the turned-on seventh transistor T7 connects the second electrode of the sixth transistor T6 with the first electrode of the eighth transistor T8, that is, the positioning signal of the positioning signal terminal Y8 is a low-level signal; then, the signal on the first node N1 in the second control circuit 30_8 is a low-level signal, the eleventh transistor T11 is turned on under the control of the low-level signal, and the turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2, then the signal on the second node N2 is a high-level signal, and the twelfth transistor T12 is turned off under the control of a low-level signal, the ninth transistor T9 is turned off under the control of a high-level signal, and the tenth transistor T10 is turned on under the control of a high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power supply signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable; the thirteenth transistor T13 is turned on under the control of a low-level signal, and the turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_8; the fourteenth transistor T14 is turned on under the control of a high-level signal, and the turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_8; the fifteenth transistor T15 is turned off under the control of a high-level signal, and the sixteenth transistor T16 is turned off under the control of a low-level signal, then the display area AA8 becomes the holding area.

[0153] At the third time t3, specifically including: the first working mode and the second working mode;

[0154] The signal x1 on the addressing signal terminal X1 is a high-level signal, the signal x2 on the addressing signal terminal X2 is a low-level signal, and the signal x3 on the addressing signal terminal X3 is a low-level signal; then the first transistor T1 in the first logic circuit 101_1 is turned off under the control of the high-level signal x1, and the second transistor T2 is turned on under the control of the high-level signal x2. The turned-on second transistor T2 outputs the low-level signal of the second power supply signal terminal VGL, that is, the first logic signal provided by the first logic circuit 101_1 is a low-level signal; the first transistor T1 in the first logic circuit 101_2 is turned off under the control of the low-level signal x2. The first transistor T1 in the first logic circuit 101_3 is turned on by the low level of the signal x3 and the second transistor T2 is turned off by the low level of the signal x3. The turned-on first transistor T1 outputs the high level signal of the first power supply signal terminal VGH, that is, the first logic signal provided by the first logic circuit 101_2 is a high level signal. The first transistor T1 in the first logic circuit 101_3 is turned on by the low level of the signal x3 and the second transistor T2 is turned off by the low level of the signal x3. The turned-on first transistor T1 outputs the high level signal of the first power supply signal terminal VGH, that is, the first logic signal provided by the first logic circuit 101_3 is a high level signal.

[0155] The third transistor T3, the seventh transistor T7, and the eighth transistor T8 in the second logic gate circuit 102_1 are turned off, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned on. Then, the turned-on fourth transistor T4 and the fifth transistor T5 provide the low-level signal of the second power signal terminal VGL to the positioning signal terminal Y1, and the turned-on sixth transistor T6 conducts the first power signal terminal VGH with the first electrode of the seventh transistor T7, that is, the positioning signal of the positioning signal terminal Y1 is a low-level signal. Then, the signal at the first node N1 in the second control circuit 30_1 is a low-level signal. The eleventh transistor T11 is turned on under the control of the low-level signal. The turned-on eleventh transistor T11 provides the high-level signal of the first power signal terminal VGH to the second node N2. Then, the signal at the second node N2 is a high-level signal. The twelfth transistor T12 is turned off under the control of the low-level signal. The ninth transistor T9 is turned off under the control of the high-level signal, and the tenth transistor T10 is turned on under the control of the high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable. The thirteenth transistor T13 is turned on under the control of the low-level signal. The turned-on thirteenth transistor T13 provides the signal at the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_1. The fourteenth transistor T14 is turned on under the control of the high-level signal. The turned-on fourteenth transistor T14 provides the signal at the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_1. The fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal. Then, the display area AA1 becomes the holding area.

[0156] The sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 in the second logic gate circuit 102_2 are turned off, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on. Then, the turned-on third transistor T3, the fourth transistor T4, and the fifth transistor T5 provide the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y2, that is, the positioning signal of the positioning signal terminal Y2 is a high-level signal; then, the signal on the first node N1 in the second control circuit 30_2 is a low-level signal, and the eleventh transistor T11 is turned on under the control of the low-level signal. The turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2, then the signal on the second node N2 is a high-level signal, the twelfth transistor T12 is turned off under the control of the low-level signal, and the ninth transistor T9 is turned on under the control of the high-level signal. The display area AA2 is turned on under the control of the high-level signal, the tenth transistor T10 is turned on under the control of the high-level signal, and the turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable; the thirteenth transistor T13 is turned on under the control of the low-level signal, and the turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_2; the fourteenth transistor T14 is turned on under the control of the high-level signal, and the turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_2; the fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal, then the display area AA2 is the holding area;

[0157] The third transistor T3, the fifth transistor T5, and the seventh transistor T7 in the second logic gate circuit 102_3 are turned off, and the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are turned on. The turned-on fourth transistor T4 provides the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y3, the turned-on sixth transistor T6 connects the first power supply signal terminal VGH with the first electrode of the seventh transistor T7, and the turned-on eighth transistor T8 connects the second electrode of the seventh transistor T7 with the positioning signal terminal Y3, that is, the positioning signal of the positioning signal terminal Y3 is a low-level signal; then the signal on the first node N1 in the second control circuit 30_3 is a low-level signal, the eleventh transistor T11 is turned on under the control of the low-level signal, and the turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2, then the signal on the second node N2 is a high-level signal, and the twelfth transistor T12 is turned on. The ninth transistor T9 is turned off under the control of the low-level signal, the tenth transistor T10 is turned on under the control of the high-level signal, and the turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable; the thirteenth transistor T13 is turned on under the control of the low-level signal, and the turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_3; the fourteenth transistor T14 is turned on under the control of the high-level signal, and the turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_3; the fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal, then the display area AA3 becomes the holding area;

[0158] The fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the second logic gate circuit 102_4 are turned off, and the third transistor T3, the fourth transistor T4, and the eighth transistor T8 are turned on. The turned-on third transistor T3 and the fourth transistor T4 provide the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y4. The turned-on eighth transistor T8 connects the first electrode of the seventh transistor T7 to the positioning signal terminal Y4, that is, the positioning signal of the positioning signal terminal Y4 is a low-level signal. The signal on the first node N1 in the second control circuit 30_4 is a low-level signal. The eleventh transistor T11 is turned on under the control of the low-level signal. The turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2. The signal on the second node N2 is a high-level signal. The twelfth transistor T12 is turned off under the control of the low-level signal. The ninth transistor T9 is turned off under the control of the high-level signal, and the tenth transistor T10 is turned on under the control of the high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable. The thirteenth transistor T13 is turned on under the control of the low-level signal. The turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_4. The fourteenth transistor T14 is turned on under the control of the high-level signal. The turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_4. The fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal. Then, the display area AA4 becomes the holding area.

[0159] The fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the second logic gate circuit 102_5 are turned on, and the third transistor T3, the fourth transistor T4, and the eighth transistor T8 are turned off. Then, the turned-on fifth transistor T5 provides the low-level signal of the second power signal terminal VGL to the positioning signal terminal Y5, and the turned-on sixth transistor T6 and the turned-on seventh transistor T7 connect the first power signal terminal VGH to the first electrode of the eighth transistor T8, that is, the positioning signal of the positioning signal terminal Y5 is a low-level signal; then, the signal at the first node N1 in the second control circuit 30_5 is a low-level signal, and the eleventh transistor T11 is turned on under the control of the low-level signal. The turned-on eleventh transistor T11 provides the high-level signal of the first power signal terminal VGH to the second node N2, and the signal at the second node N2 is a high-level signal. The twelfth transistor T12 is turned off under the control of the low-level signal. The ninth transistor T9 is turned off under the control of the high-level signal, and the tenth transistor T10 is turned on under the control of the high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable. The thirteenth transistor T13 is turned on under the control of the low-level signal. The turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_5. The fourteenth transistor T14 is turned on under the control of the high-level signal. The turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_5. The fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal. Then, the display area AA5 becomes the holding area.

[0160] The third transistor T3, the fifth transistor T5, and the seventh transistor T7 in the second logic gate circuit 102_6 are turned on, and the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are turned off. Then, the turned-on third transistor T3 provides the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y6, the turned-on fifth transistor T5 provides the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y6, and the turned-on seventh transistor T7 connects the second electrode of the sixth transistor T6 with the first electrode of the eighth transistor T8, that is, the positioning signal of the positioning signal terminal Y6 is a low-level signal; then, the signal on the first node N1 in the second control circuit 30_6 is a low-level signal, the eleventh transistor T11 is turned on under the control of the low-level signal, and the turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2, then the signal on the second node N2 is a high-level signal, and the twelfth transistor T12 is turned off under the control of the low-level signal, the ninth transistor T9 is turned off under the control of the high-level signal, and the tenth transistor T10 is turned on under the control of the high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable; the thirteenth transistor T13 is turned on under the control of the low-level signal, and the turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_6; the fourteenth transistor T14 is turned on under the control of the high-level signal, and the turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_6; the fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal, then the display area AA6 becomes the holding area;

[0161] The sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 in the second logic gate circuit 102_7 are turned on, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off. Then, the turned-on sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 provide the high-level signal of the first power supply signal terminal VGH to the positioning signal terminal Y7, that is, the positioning signal of the positioning signal terminal Y7 is a high-level signal; then, the signal on the first node N1 in the second control circuit 30_7 is a high-level signal, the eleventh transistor T11 is turned off under the control of the high-level signal, and the twelfth transistor T12 is turned on under the control of the high-level signal. The turned-on twelfth transistor T12 provides the low-level signal of the second power supply signal terminal VGL to the second node N2, then the signal on the second node N2 is a low-level signal, and the ninth transistor T9 is turned off under the control of the low-level signal. The ninth transistor T9 is turned on under the control of the low-level signal, and the turned-on ninth transistor T9 provides the high-level signal of the first power supply signal terminal VGH to the first node N1, maintaining the voltage of the first node N1 stable. The tenth transistor T10 is turned off under the control of the low-level signal, the thirteenth transistor T13 is turned off under the control of the high-level signal, the fourteenth transistor T14 is turned off under the control of the low-level signal, and the fifteenth transistor T15 is turned on under the control of the low-level signal, and the turned-on fifteenth transistor T15 provides the signal on the frame start signal terminal STV to the shift register unit SR1 in the gate driver sub-circuit 201_7. The sixteenth transistor T16 is turned on under the control of the high-level signal, and the turned-on sixteenth transistor T16 provides the signal on the frame start signal terminal STV to the shift register unit SR1 in the gate driver sub-circuit 201_7, then the display area AA7 is the refresh area;

[0162] The third transistor T3, the seventh transistor T7, and the eighth transistor T8 in the second logic gate circuit 102_8 are turned on, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. Then, the turned-on third transistor T3 provides the low-level signal of the second power supply signal terminal VGL to the positioning signal terminal Y8, and the turned-on seventh transistor T7 and the eighth transistor T8 connect the second electrode of the sixth transistor T6 to the positioning signal terminal Y8, that is, the positioning signal of the positioning signal terminal Y8 is a low-level signal; then, the signal on the first node N1 in the second control circuit 30_8 is a low-level signal, and the eleventh transistor T11 is turned on under the control of the low-level signal. The turned-on eleventh transistor T11 provides the high-level signal of the first power supply signal terminal VGH to the second node N2, then the signal on the second node N2 is a high-level signal, and the twelfth transistor T12 is turned off under the control of the low-level signal. The ninth transistor T9 is turned off under the control of the high-level signal, and the tenth transistor T10 is turned on under the control of the high-level signal. The turned-on tenth transistor T10 provides the low-level signal of the second power supply signal terminal VGL to the first node N1, maintaining the voltage of the first node N1 stable; the thirteenth transistor T13 is turned on under the control of the low-level signal, and the turned-on thirteenth transistor T13 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_8; the fourteenth transistor T14 is turned on under the control of the high-level signal, and the turned-on fourteenth transistor T14 provides the signal on the output signal terminal OUT to the shift register unit SR1 in the gate driver sub-circuit 201_8; the fifteenth transistor T15 is turned off under the control of the high-level signal, and the sixteenth transistor T16 is turned off under the control of the low-level signal, and the display area AA8 is the holding area.

[0163] For example, Figure 8As shown, each sub-pixel in the embodiment of the present disclosure has a pixel circuit 40, wherein the pixel circuit 40 may specifically include: a first reset transistor M1, a conduction transistor M2, a driving transistor M3, a data writing transistor M4, a first light emitting transistor M5, a second light emitting transistor M6, a second reset transistor M7, a third reset transistor M8, a capacitor Cst and a light emitting device L; wherein the gate of the first reset transistor M1 is coupled to the first reset signal terminal Reset_P(n), the first electrode of the first reset transistor M1 is coupled to the second electrode of the driving transistor M3, and the first reset transistor The second electrode of the transistor M1 is coupled to the first initialization signal terminal Vinit1; the gate of the conduction transistor M2 is coupled to the first scan signal terminal Gate_N(n), the first electrode of the conduction transistor M2 is coupled to the gate of the drive transistor M3, and the second electrode of the conduction transistor M2 is coupled to the second electrode of the drive transistor M3; the gate of the data write transistor M4 is coupled to the second scan signal terminal Gate_P(n), the first electrode of the data write transistor M4 is coupled to the first electrode of the drive transistor M3, and the second electrode of the data write transistor M4 is coupled to the data signal terminal Data; the first light-emitting transistor M5 The gate of the first light emitting transistor M5 is coupled to the light emitting control signal terminal EM, the first electrode of the first light emitting transistor M5 is coupled to the first voltage signal terminal VDD, and the second electrode of the first light emitting transistor M5 is coupled to the first electrode of the driving transistor M3; the gate of the second light emitting transistor M6 is coupled to the light emitting control signal terminal EM, the first electrode of the second light emitting transistor M6 is coupled to the second electrode of the driving transistor M3, and the second electrode of the second light emitting transistor M6 is coupled to the first electrode of the light emitting device L; the second electrode of the light emitting device L is coupled to the second voltage signal terminal VSS; the gate of the second reset transistor M7 is coupled to the second reset signal terminal Reset_H ( n), a first electrode of the second reset transistor M7 is coupled to the first electrode of the light-emitting device L, and a second electrode of the second reset transistor M7 is coupled to the second initialization signal terminal Vinit2; a gate of the third reset transistor M8 is coupled to the second reset signal terminal Reset_H(n), a first electrode of the third reset transistor M8 is coupled to the first electrode of the driving transistor M3, and a second electrode of the third reset transistor M8 is coupled to the third initialization signal terminal Vinit3; a first electrode of the capacitor Cst is coupled to the first voltage signal terminal VDD, and a second electrode of the capacitor Cst is coupled to the gate of the driving transistor M3.

[0164] Exemplarily, the light-emitting device L may be an electroluminescent diode. For example, the light-emitting device L may include at least one of: an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro light-emitting diode (MicroLED), and a mini light-emitting diode (Mini LED). Exemplarily, the light-emitting device L may include a stacked anode, a light-emitting layer, and a cathode. Furthermore, the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Of course, in actual applications, the specific structure of the light-emitting device L can be determined according to the needs of the actual application, and is not limited here.

[0165] Generally, transistors using metal oxide semiconductor materials as their active layers have low leakage current. Therefore, to reduce leakage current, in some embodiments of the present disclosure, the active layer of the transistor may include a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other metal oxide semiconductor materials are also possible and are not limited here. This allows the transistor to be configured as an oxide thin film transistor, thereby reducing leakage current in the pixel circuit.

[0166] Transistors using low-temperature polysilicon (LTPS) as active layers generally have high mobility and can be made thinner and smaller, with lower power consumption. In specific implementations, the active layer of the transistor can also be made of low-temperature polysilicon. This allows the transistor to be an LTPS transistor, enabling the pixel circuit to achieve high mobility, be thinner and smaller, and have lower power consumption.

[0167] For example, all transistors in the pixel circuit in the embodiment of the present disclosure can be set as oxide-type transistors, or all transistors in the pixel circuit in the embodiment of the present disclosure can be set as LTPS-type transistors, or some transistors in the pixel circuit in the embodiment of the present disclosure can be set as oxide-type transistors and another part of the transistors can be set as LTPS-type transistors.

[0168] The above is only an example of the specific structure of the pixel circuit provided in the embodiment of the present disclosure. In specific implementation, the specific structure of the above pixel circuit is not limited to the above structure provided in the embodiment of the present disclosure, and can also be other structures known to those skilled in the art. These are all within the scope of protection of the present disclosure and are not specifically limited here.

[0169] For example, Figure 9 As shown, each shift register unit (eg Figure 114, 15, 16, 17, 18, 19, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140, 150, 160, 170, 180, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 2000, 3000, 4000, 5000, 6000, 7000, 8000, 8000, 9000, 1100, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800 A fifth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18; wherein the gate of the first transistor T1 is coupled to the first clock signal terminal CB1, the first electrode of the first transistor T1 is coupled to the first level signal terminal VGH1, and the second electrode of the first transistor T1 is coupled to the first electrode of the second transistor T2; the gate of the second transistor T2 is coupled to the input signal terminal Input, and the second electrode of the second transistor T2 is coupled to the first node P; the gate of the third transistor T3 is coupled to the input signal terminal Input, the first electrode of the third transistor T3 is coupled to the first node P, and the second electrode of the third transistor T3 is coupled to the first electrode of the fourth transistor T4; the gate of the fourth transistor T4 The gate of the fifth transistor T5 is coupled to the second clock signal terminal CK1, the first electrode of the fifth transistor T5 is coupled to the first level signal terminal VGH1, and the second electrode of the fifth transistor T5 is coupled to the first electrode of the sixth transistor T6; the gate of the sixth transistor T6 is coupled to the second node Q, and the second electrode of the sixth transistor T6 is coupled to the first node P; the gate of the seventh transistor T7 is coupled to the second node Q, the first electrode of the seventh transistor T7 is coupled to the first node P, and the second electrode of the seventh transistor T7 is coupled to the first electrode of the eighth transistor T8; the gate of the eighth transistor T8 is coupled to the first clock signal terminal CB1 The first electrode of the ninth transistor T9 is coupled to the first node P, the first electrode of the ninth transistor T9 is coupled to the first signal terminal VGH1, and the second electrode of the ninth transistor T9 is coupled to the second node Q. The gate of the tenth transistor T10 is coupled to the first node P, the first electrode of the tenth transistor T10 is coupled to the second node Q, and the second electrode of the tenth transistor T10 is coupled to the second signal terminal VGL1. The gate of the eleventh transistor T11 is coupled to the second node Q, the first electrode of the eleventh transistor T11 is coupled to the first signal terminal VGH1, and the second electrode of the eleventh transistor T11 is coupled to the first electrode of the twelfth transistor T12.The gate of the twelfth transistor T12 is coupled to the second node Q, the second electrode of the twelfth transistor T12 is coupled to the first electrode of the thirteenth transistor T13; the gate of the thirteenth transistor T13 is coupled to the third clock signal terminal CK2, the second electrode of the thirteenth transistor T13 is coupled to the second level signal terminal VGL1; the gate of the fourteenth transistor T14 is coupled to the third clock signal terminal CK2, the first electrode of the fourteenth transistor T14 is coupled to the first level signal terminal VGH1, the second electrode of the fourteenth transistor T14 is coupled to the gates of the fifteenth transistor T15 and the sixteenth transistor T16; the first electrode of the fifteenth transistor T15 is coupled to the first level signal terminal VGL1. The signal terminal VGH1 is coupled, the second electrode of the fifteenth transistor T15 is coupled to the first electrode of the sixteenth transistor T16; the second electrode of the sixteenth transistor T16 is coupled to the second-level signal terminal VGL1; the gates of the seventeenth transistor T17 and the eighteenth transistor T18 are coupled to the second electrode of the fifteenth transistor T15; the first electrode of the seventeenth transistor T17 is coupled to the third-level signal terminal VGH2, and the second electrode of the seventeenth transistor T17 is coupled to the signal output terminal Output; the first electrode of the eighteenth transistor T18 is coupled to the signal output terminal Output, and the second electrode of the eighteenth transistor T18 is coupled to the fourth-level signal terminal VGL2.

[0170] It should be noted that, Figure 9 As shown, the second scanning control circuit Gate_P in the embodiment of the present disclosure does not need to set a reset transistor separately, and can be reset by combining the timing; and the first row shift register unit (for example Figure 1 The input signal terminal Input in SR1) is coupled to the corresponding second control circuit 30; the next row of shift register units (eg Figure 1 The input signal terminal Input of the SR2 in the previous row is connected to the shift register unit (for example Figure 1 The signal output terminal Output of SR1 in the gate drive sub-circuit is coupled; the last row shift register unit (eg Figure 1 The signal output terminal Output in SR5) in the corresponding second control circuit 30 is coupled to the output signal terminal OUT.

[0171] For example, Figure 10 As shown, each shift register unit (eg Figure 1SR1, SR2, SR3, SR4, SR5, SR6, SR7) in the embodiment may include: a first scan control circuit Gate_N, coupled to the first scan signal terminal Gate_N(n), and configured to provide a signal to the first scan signal terminal Gate_N(n); a light emitting control circuit EMn, coupled to the light emitting control signal terminal EM, and configured to provide a signal to the light emitting control signal terminal EM; wherein the first scan control circuit Gate_N and the light emitting control circuit EMn include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16; wherein the gate of the first transistor T1 is coupled to the first clock signal terminal CB1, the first electrode of the first transistor T1 is coupled to the first level signal terminal VGH1, and the second electrode of the first transistor T1 is coupled to the first electrode of the second transistor T2; the gate of the second transistor T2 is coupled to the input signal terminal Input, and the second electrode of the second transistor T2 is coupled to the first node P; the gate of the third transistor T3 is coupled to the input signal terminal Input, the first electrode of the third transistor T3 is coupled to the first node P, and the second electrode of the third transistor T3 is coupled to the fourth transistor T4 The first electrode of the fourth transistor T4 is coupled to the second clock signal terminal CK1, and the second electrode of the fourth transistor T4 is coupled to the second level signal terminal VGL1; the gate of the fifth transistor T5 is coupled to the second clock signal terminal CK1, the first electrode of the fifth transistor T5 is coupled to the first level signal terminal VGH1, and the second electrode of the fifth transistor T5 is coupled to the first electrode of the sixth transistor T6; the gate of the sixth transistor T6 is coupled to the second node Q, and the second electrode of the sixth transistor T6 is coupled to the first node P; the gate of the seventh transistor T7 is coupled to the second node Q, the first electrode of the seventh transistor T7 is coupled to the first node P, and the second electrode of the seventh transistor T7 is coupled to the first electrode of the eighth transistor T8; the gate of the eighth transistor T8 ... A clock signal terminal CB1 is coupled to the first transistor T8, a second electrode of the eighth transistor T8 is coupled to the second level signal terminal VGL1; a gate of the ninth transistor T9 is coupled to the first node P, a first electrode of the ninth transistor T9 is coupled to the first level signal terminal VGH1, and a second electrode of the ninth transistor T9 is coupled to the second node Q; a gate of the tenth transistor T10 is coupled to the first node P, a first electrode of the tenth transistor T10 is coupled to the second node Q, and a second electrode of the tenth transistor T10 is coupled to the second level signal terminal VGL1; a gate of the eleventh transistor T11 is coupled to the second node Q, a first electrode of the eleventh transistor T11 is coupled to the first level signal terminal VGH1, and a second electrode of the eleventh transistor T11 is coupled to the first electrode of the twelfth transistor T12;The gate of the twelfth transistor T12 is coupled to the second node Q, and the second electrode of the twelfth transistor T12 is coupled to the second-level signal terminal VGL1. The gates of the thirteenth transistor T13 and the fourteenth transistor T14 are coupled to the second electrode of the eleventh transistor T11. The first electrode of the thirteenth transistor T13 is coupled to the first-level signal terminal VGH1, and the second electrode of the thirteenth transistor T13 is coupled to the first electrode of the fourteenth transistor T14. The second electrode of the fourteenth transistor T14 is coupled to the second-level signal terminal VGL1. The gates of the fifteenth transistor T15 and the sixteenth transistor T16 are coupled to the second electrode of the thirteenth transistor T13. The first electrode of the fifteenth transistor T15 is coupled to the third-level signal terminal VGH2, and the second electrode of the fifteenth transistor T15 is coupled to the signal output terminal Output. The first electrode of the sixteenth transistor T16 is coupled to the signal output terminal Output, and the second electrode of the sixteenth transistor T16 is coupled to the fourth-level signal terminal VGL2.

[0172] It should be noted that, Figure 10 As shown, the first scanning control circuit Gate_N and the light emitting control circuit EMn in the embodiment of the present disclosure do not need to set up reset transistors separately, and can be reset by combining timing; and the first row shift register unit (for example Figure 1 The input signal terminal Input in SR1) is coupled to the corresponding second control circuit 30; the next row of shift register units (eg Figure 1 The input signal terminal Input of the SR2 in the previous row is connected to the shift register unit (for example Figure 1 The signal output terminal Output of SR1 in the gate drive sub-circuit is coupled; the last row shift register unit (eg Figure 1 The signal output terminal Output in SR5) in the corresponding second control circuit 30 is coupled to the output signal terminal OUT.

[0173] For example, Figure 11 As shown, each shift register unit (eg Figure 1SR1, SR2, SR3, SR4, SR5, SR6, SR7) in the embodiment may include: a first reset control circuit Reset_P, coupled to the first reset signal terminal Reset_P(n), configured to provide a signal to the first reset signal terminal Reset_P(n); a second reset control circuit Reset_H, coupled to the second reset signal terminal Reset_H(n), configured to provide a signal to the second reset signal terminal Reset_H(n); wherein the first reset control circuit Reset_P and the second reset control circuit Reset_H include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a fifth transistor T6, a fifth transistor T7, a fifth transistor T8, a fifth transistor T9, a fifth transistor T10, a fifth transistor T11, a fifth transistor T12, a fifth transistor T13, a fifth transistor T14, a fifth transistor T15, a fifth transistor T16, a fifth transistor T17, a fifth transistor T18, a fifth transistor T19, a fifth transistor T20, a fifth transistor T21, a fifth transistor T22, a fifth transistor T33, a fifth transistor T4 5. a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18; wherein a gate of the first transistor T1 is coupled to the first clock signal terminal CB1, a first electrode of the first transistor T1 is coupled to the first level signal terminal VGH1, a second electrode of the first transistor T1 is coupled to the first electrode of the second transistor T2; a gate of the second transistor T2 is coupled to the input signal terminal Input, a second electrode of the second transistor T2 is coupled to the first node P The gate of the third transistor T3 is coupled to the input signal terminal Input, the first electrode of the third transistor T3 is coupled to the first node P, and the second electrode of the third transistor T3 is coupled to the first electrode of the fourth transistor T4; the gate of the fourth transistor T4 is coupled to the second clock signal terminal CK1, and the second electrode of the fourth transistor T4 is coupled to the second level signal terminal VGL1; the gate of the fifth transistor T5 is coupled to the second clock signal terminal CK1, the first electrode of the fifth transistor T5 is coupled to the first level signal terminal VGH1, and the second electrode of the fifth transistor T5 is coupled to the first electrode of the sixth transistor T6; the gate of the sixth transistor T6 is coupled to the second node Q, and the second electrode of the sixth transistor T6 is coupled to the first node P; the seventh transistor A gate of the seventh transistor T7 is coupled to the second node Q, a first electrode of the seventh transistor T7 is coupled to the first node P, and a second electrode of the seventh transistor T7 is coupled to a first electrode of the eighth transistor T8; a gate of the eighth transistor T8 is coupled to the first clock signal terminal CB1, and a second electrode of the eighth transistor T8 is coupled to the second level signal terminal VGL1; a gate of the ninth transistor T9 is coupled to the first node P, a first electrode of the ninth transistor T9 is coupled to the first level signal terminal VGH1, and a second electrode of the ninth transistor T9 is coupled to the second node Q; a gate of the tenth transistor T10 is coupled to the first node P, a first electrode of the tenth transistor T10 is coupled to the second node Q, and a second electrode of the tenth transistor T10 is coupled to the second level signal terminal VGL1;The gate of the eleventh transistor T11 is coupled to the second node Q, the first electrode of the eleventh transistor T11 is coupled to the first level signal terminal VGH1, and the second electrode of the eleventh transistor T11 is coupled to the first electrode of the twelfth transistor T12; the gate of the twelfth transistor T12 is coupled to the second node Q, and the second electrode of the twelfth transistor T12 is coupled to the second level signal terminal VGL1; the gates of the thirteenth transistor T13 and the fourteenth transistor T14 are coupled to the second electrode of the eleventh transistor T11; the first electrode of the thirteenth transistor T13 is coupled to the first level signal terminal VGH1, the second electrode of the thirteenth transistor T13 is coupled to the first electrode of the fourteenth transistor T14; the second electrode of the fourteenth transistor T14 is coupled to the second level signal terminal VGL1; the fifteenth transistor T15 and the fifteenth transistor T16 are coupled to the first node Q, and the second electrode of the twelfth transistor T16 is coupled to the second level signal terminal VGL1. The gate of the sixth transistor T16 is coupled to the second electrode of the thirteenth transistor T13; the first electrode of the fifteenth transistor T15 is coupled to the first-level signal terminal VGH1, and the second electrode of the fifteenth transistor T15 is coupled to the first electrode of the sixteenth transistor T16; the second electrode of the sixteenth transistor T16 is coupled to the second-level signal terminal VGL1; the gates of the seventeenth transistor T17 and the eighteenth transistor T18 are coupled to the second electrode of the fifteenth transistor T15; the first electrode of the seventeenth transistor T17 is coupled to the third-level signal terminal VGH2, and the second electrode of the seventeenth transistor T17 is coupled to the signal output terminal Output; the first electrode of the eighteenth transistor T18 is coupled to the signal output terminal Output, and the second electrode of the eighteenth transistor T18 is coupled to the fourth-level signal terminal VGL2.

[0174] It should be noted that, Figure 11 As shown, the first reset control circuit Reset_P and the second reset control circuit Reset_H in the embodiment of the present disclosure do not need to set reset transistors separately, and can achieve reset by combining timing; and the first row shift register unit (for example Figure 1 The input signal terminal Input in SR1) is coupled to the corresponding second control circuit 30; the next row of shift register units (eg Figure 1 The input signal terminal Input of the SR2 in the previous row is connected to the shift register unit (for example Figure 1 The signal output terminal Output of SR1 in the gate drive sub-circuit is coupled; the last row shift register unit (eg Figure 1 The signal output terminal Output in SR5) in the corresponding second control circuit 30 is coupled to the output signal terminal OUT.

[0175] The following will Figure 10 As an example, the structure shown in Figure 12 and Figure 13 The signal timing diagram shown is used for explanation;

[0176] like Figure 12 and Figure 13 As shown, input represents the signal of the input signal terminal Input, ck1 represents the signal of the second clock signal terminal CK1, cb1 represents the signal of the first clock signal terminal CB1, ck2 represents the signal of the third clock signal terminal CK2, cb2 represents the signal of the fourth clock signal terminal CB2, out1 represents the signal of the signal output terminal Output in the shift register unit SR1, out2 represents the signal of the signal output terminal Output in the shift register unit SR2, out3 represents the signal of the signal output terminal Output in the shift register unit SR3, and out4 represents the signal of the signal output terminal Output in the shift register unit SR4; wherein, Figure 12 Represents the timing signal diagram of frame 1. Figure 13 Represents the timing signal diagram of frame 2.

[0177] For example, when the signal input of the input signal terminal Input is at a low level, the signal ck1 of the second clock signal terminal CK1 is at a high level, and the signal cb1 of the first clock signal terminal CB1 is at a low level, the first transistor T1 is turned on under the control of the low level of the signal cb1, and the turned-on first transistor T1 provides the low level signal of the first level signal terminal VGH1 to the second transistor T2; the second transistor T2 is turned on under the control of the low level of the signal input, and the turned-on second transistor T2 provides the low level signal to the first node P; the third transistor T3 is turned on under the control of the low level of the signal input The fourth transistor T4 is turned on under the control of the high level of the signal ck1, and the turned-on fourth transistor T4 provides the low level signal of the second level signal terminal VGL1 to the third transistor T3; the ninth transistor T9 is turned on under the control of the low level signal on the first node P, and the turned-on ninth transistor T9 provides the high level signal of the first level signal terminal VGH1 to the second node Q; the tenth transistor T10 is turned off under the control of the low level signal on the first node P; the fifth transistor T5 is turned off under the control of the high level of the signal ck1; the sixth transistor T6 is turned off under the control of the high level signal on the second node Q The seventh transistor T7 is turned on under the control of the high-level signal at the second node Q, and the turned-on seventh transistor T7 conducts the first node P and the eighth transistor T8; the eighth transistor T8 is turned off under the control of the low-level signal cb1; the eleventh transistor T11 is turned off under the control of the high-level signal at the second node Q; the twelfth transistor T12 is turned on under the control of the high-level signal at the second node Q, and the turned-on twelfth transistor T12 provides the low-level signal of the second-level signal terminal VGL1 to the gates of the thirteenth transistor T13 and the fourteenth transistor T14; the thirteenth transistor T13 is turned on under the control of the low-level signal, and the turned-on thirteenth transistor T13 provides the high-level signal of the first-level signal terminal VGH1 to the gates of the fifteenth transistor T15 and the sixteenth transistor T16; the fourteenth transistor T14 is turned off under the control of the low-level signal; the fifteenth transistor T15 is turned off under the control of the high-level signal; the sixteenth transistor T16 is turned on under the control of the high-level signal, and the turned-on sixteenth transistor T16 provides the low-level signal of the fourth-level signal terminal VGL2 to the signal output terminal Output, and the signal at the signal output terminal Output is a low-level signal.

[0178] For example, Figure 7 As shown, when it is necessary to select display areas AA2, AA5 and AA7 as refresh areas and select display areas AA1, AA3, AA4, AA6 and AA8 as hold areas; Figure 14As shown, when the display panel is in a normal scene output (for example, 120Hz), the second scan control circuit Gate_P in the shift register unit in the gate drive sub-circuit corresponding to the display areas AA2, AA5 and AA7 in the refresh area is turned on once, and the data write transistor M4 in the pixel circuit 40 writes the data signal terminal Data once; when the display panel is in a variable frequency scene output (for example, 360Hz), the second scan control circuit Gate_P in the shift register unit in the gate drive sub-circuit corresponding to the display areas AA2, AA5 and AA7 in the refresh area is turned on three times, and the data write transistor M4 in the pixel circuit 40 writes the data signal terminal Data three times, and at the same time, the input of the data signal terminal Data is matched through the IC to achieve overclocking refresh.

[0179] The present disclosure also provides a display device including the display panel provided in the present disclosure. The display device solves the problem in a similar manner to the display panel, so the implementation of the display device can refer to the implementation of the display panel, and the repeated parts are not repeated here.

[0180] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0181] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0182] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display panel, wherein: include: A first control circuit is configured to provide positioning signals to N positioning signal terminals in response to signals from M addressing signal terminals; wherein M and N are both positive integers greater than 0; A gate driving circuit, comprising a plurality of gate driving sub-circuits, each of the gate driving sub-circuits comprising a plurality of shift register units cascaded in sequence; Multiple second control circuits, the nth second control circuit is coupled to the nth positioning signal terminal and the first row shift register unit in the nth gate drive sub-circuit, and the second control circuit is configured to provide the signal of the frame start signal terminal or the signal of the output signal terminal to the first row shift register unit in the corresponding coupled gate drive sub-circuit in response to the positioning signal of the positioning signal terminal; wherein the output signal terminal in the nth second control circuit is coupled to the last row shift register unit in the n-1th gate drive sub-circuit.

2. The display panel according to claim 1, wherein: The first control circuit includes: M first logic gate circuits and N second logic gate circuits; wherein, one first logic gate circuit is coupled to one addressing signal terminal, and one second logic gate circuit is coupled to one positioning signal terminal; The first logic gate circuit is configured to generate a first logic signal in response to a signal at the addressing signal terminal; The second logic gate circuit is coupled to the first logic gate circuit and / or the addressing signal terminal, and is configured to provide a positioning signal to the positioning signal terminal in response to the first logic signal and / or the signal of the addressing signal terminal.

3. The display panel according to claim 1, wherein: N＝2 M 。 4. The display panel according to claim 3, wherein: M=3, N=8; a first end of the first second logic gate circuit coupled to the first positioning signal end, a second end of the first second logic gate circuit coupled to the first end of the first first logic gate circuit, a third end of the first second logic gate circuit coupled to the first end of the second first logic gate circuit, and a fourth end of the first second logic gate circuit coupled to the first end of the third first logic gate circuit; a first terminal of a second second logic gate circuit coupled to the second positioning signal terminal, a second terminal of a second second logic gate circuit coupled to the first addressing signal terminal, a third terminal of a second second logic gate circuit coupled to the first terminal of a second first logic gate circuit, and a fourth terminal of a second second logic gate circuit coupled to the first terminal of a third first logic gate circuit; a first terminal of the third second logic gate circuit coupled to the third positioning signal terminal, a second terminal of the third second logic gate circuit coupled to the first terminal of the first first logic gate circuit, a third terminal of the third second logic gate circuit coupled to the first terminal of the second first logic gate circuit, and a fourth terminal of the third second logic gate circuit coupled to the third addressing signal terminal; a first terminal of a fourth second logic gate circuit coupled to the fourth positioning signal terminal, a second terminal of the fourth second logic gate circuit coupled to the first addressing signal terminal, a third terminal of the fourth second logic gate circuit coupled to the first terminal of the second first logic gate circuit, and a fourth terminal of the fourth second logic gate circuit coupled to the third addressing signal terminal; a first terminal of the fifth second logic gate circuit coupled to the fifth positioning signal terminal, a second terminal of the fifth second logic gate circuit coupled to the first terminal of the first first logic gate circuit, a third terminal of the fifth second logic gate circuit coupled to the second addressing signal terminal, and a fourth terminal of the fifth second logic gate circuit coupled to the first terminal of the third first logic gate circuit; a first terminal of the sixth second logic gate circuit is coupled to the sixth positioning signal terminal, a second terminal of the sixth second logic gate circuit is coupled to the first addressing signal terminal, a third terminal of the sixth second logic gate circuit is coupled to the second addressing signal terminal, and a fourth terminal of the sixth second logic gate circuit is coupled to the first terminal of the third first logic gate circuit; a first terminal of the seventh second logic gate circuit is coupled to the seventh positioning signal terminal, a second terminal of the seventh second logic gate circuit is coupled to the first terminal of the first first logic gate circuit, a third terminal of the seventh second logic gate circuit is coupled to the second addressing signal terminal, and a fourth terminal of the seventh second logic gate circuit is coupled to the third addressing signal terminal; a first terminal of the eighth second logic gate circuit is coupled to the eighth positioning signal terminal, a second terminal of the eighth second logic gate circuit is coupled to the first addressing signal terminal, a third terminal of the eighth second logic gate circuit is coupled to the second addressing signal terminal, and a fourth terminal of the eighth second logic gate circuit is coupled to the third addressing signal terminal; The second terminal of the first first logic gate circuit is coupled to the first addressing signal terminal; The second end of the second first logic gate circuit is coupled to the second addressing signal end; The second terminal of the third first logic gate circuit is coupled to the third addressing signal terminal.

5. The display panel according to claim 4, wherein: The first logic circuit includes: a first transistor and a second transistor; The gate of the first transistor is coupled to the addressing signal terminal, the first electrode of the first transistor is coupled to the first power signal terminal, and the second electrode of the first transistor is coupled to the first electrode of the second transistor; A gate of the second transistor is coupled to the addressing signal terminal, and a second electrode of the second transistor is coupled to a second power signal terminal.

6. The display panel according to claim 5, wherein: The effective level signal of the first transistor is different from the effective level signal of the second transistor.

7. The display panel according to claim 4, wherein: The second logic circuit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The gate of the third transistor is coupled to the gate of the sixth transistor, the first electrode of the third transistor is coupled to the second power signal terminal, and the second electrode of the third transistor is coupled to the positioning signal terminal; The gate of the fourth transistor is coupled to the gate of the seventh transistor, the first electrode of the fourth transistor is coupled to the second power signal terminal, and the second electrode of the fourth transistor is coupled to the positioning signal terminal; The gate of the fifth transistor is coupled to the gate of the eighth transistor, the first electrode of the fifth transistor is coupled to the second power signal terminal, and the second electrode of the fifth transistor is coupled to the positioning signal terminal; A first electrode of the sixth transistor is coupled to the first power signal terminal, a second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor, and a second electrode of the seventh transistor is coupled to the first electrode of the eighth transistor.

8. The display panel according to claim 7, wherein: The effective level signals of the third transistor, the fourth transistor and the fifth transistor are the same; The effective level signals of the sixth transistor, the seventh transistor and the eighth transistor are the same; The third transistor and the sixth transistor have different effective level signals.

9. The display panel according to any one of claims 1 to 8, wherein: The second control circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor; The gate of the ninth transistor is coupled to the second electrode of the eleventh transistor, the first electrode of the ninth transistor is coupled to the first power signal terminal, and the second electrode of the ninth transistor is coupled to the first electrode of the tenth transistor; The gate of the tenth transistor is coupled to the second electrode of the eleventh transistor, and the second electrode of the tenth transistor is coupled to the second power signal terminal; The gate of the eleventh transistor is coupled to the positioning signal terminal, the first electrode of the eleventh transistor is coupled to the first power signal terminal, and the second electrode of the eleventh transistor is coupled to the first electrode of the twelfth transistor. The gate of the twelfth transistor is coupled to the positioning signal terminal, and the second electrode of the twelfth transistor is coupled to the second power signal terminal; The gate of the thirteenth transistor is coupled to the positioning signal terminal, the first electrode of the thirteenth transistor is coupled to the output signal terminal, and the second electrode of the thirteenth transistor is coupled to the first row shift register unit in the gate driving sub-circuit; The gate of the fourteenth transistor is coupled to the second electrode of the eleventh transistor, the first electrode of the fourteenth transistor is coupled to the output signal terminal, and the second electrode of the fourteenth transistor is coupled to the first row shift register unit in the gate driving sub-circuit; The gate of the fifteenth transistor is coupled to the second electrode of the eleventh transistor, the first electrode of the fifteenth transistor is coupled to the frame start signal terminal, and the second electrode of the fifteenth transistor is coupled to the first row shift register unit in the gate driving sub-circuit; The gate of the sixteenth transistor is coupled to the positioning signal terminal, the first electrode of the sixteenth transistor is coupled to the frame start signal terminal, and the second electrode of the sixteenth transistor is coupled to the first row shift register unit in the gate driving subcircuit.

10. The display panel according to any one of claims 1 to 8, wherein: The number of shift register units included in each gate driving sub-circuit is the same or different.

11. A display device, wherein: The device comprises a display panel according to any one of claims 1 to 10.

12. A method for driving a display panel according to any one of claims 1 to 10, wherein: include: a first working mode and a second working mode; In the first operating mode, the first control circuit provides positioning signals to the N positioning signal terminals in response to signals from the M addressing signal terminals; the first control circuit is configured to provide signals from the output signal terminal to the first row shift register unit in the corresponding coupled gate drive sub-circuit in response to the positioning signals from the positioning signal terminals; In the second operating mode, the first control circuit provides a positioning signal to N positioning signal terminals in response to the signals of the M addressing signal terminals; the first control circuit is configured to provide the signal of the frame start signal terminal to the first row shift register unit in the corresponding coupled gate drive sub-circuit in response to the positioning signal of the positioning signal terminal.

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