Source driver circuit and display panel

Abstract

The application provides a source driving circuit and a display panel. The source driving circuit is applied to the display panel and comprises a data receiving unit configured to receive original display data row by row; a first latch unit group comprising a plurality of first latch units, and the plurality of first latch units are connected to the data receiving unit respectively, and each first latch unit is configured to buffer one column of original display data; a data processing unit group comprising a plurality of data processing units, and the plurality of data processing units are connected to the first latch unit group respectively, and the data processing unit group is configured to expand and recombine the original display data to obtain recombined display data, wherein the recombined display data comprises the original display data and expanded display data; and a second latch unit group comprising a plurality of second latch units, and the plurality of second latch units are connected to the data processing unit group respectively, and each second latch unit is configured to buffer one column of recombined display data.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a source driving circuit and a display panel. Background Technology

[0002] With the convergence of high refresh rate and high resolution display demands, dual-mode variable resolution / refresh rate display panels are becoming a new trend. For example, a monitor with a physical resolution of 4K×2K can operate in two modes: 4K×2K@60Hz and 2K×1K@120Hz. In 4K×2K@60Hz mode, the refresh rate is lower, but the image quality is more detailed, suitable for watching movies or playing AAA games and other scenarios with high image quality requirements. In 2K×1K@120Hz mode, the refresh rate is higher, suitable for playing competitive games, sacrificing some image quality for smoother operation. Switching between these two modes utilizes the panel scanning two lines simultaneously to achieve the effect of doubling the refresh rate.

[0003] In 2K×1K@120Hz display mode, the horizontal scaling of display data is achieved by the monitor's SOC, and then transmitted to the pixels via the timing controller and source driver. However, due to the need to pass through multiple chips, the data transmission bandwidth is limited, and the refresh rate can only be increased from 60Hz to 120Hz, which is a doubling of the frequency. This limits the improvement of the display panel's refresh rate.

[0004] Some current solutions propose using source drivers for horizontal scaling of display data. The display data output from the source driver directly affects the pixels, and the data transmission bandwidth is unlimited. However, existing solutions using source drivers for horizontal scaling of display data do not produce satisfactory display results. Summary of the Invention

[0005] This invention mainly provides a source drive circuit and a display panel, which can improve the display effect.

[0006] To solve the above-mentioned technical problems, the first technical solution adopted by the present invention is: to provide a source driving circuit applied to a display panel, comprising:

[0007] The data receiving unit is configured to receive raw display data line by line;

[0008] The first latch unit group includes multiple first latch units, and the multiple first latch units are respectively connected to the data receiving unit. Each first latch unit is configured to cache a column of original display data.

[0009] The data processing unit group includes multiple data processing units, which are respectively connected to the first latching unit group. The data processing unit group is configured to expand and reorganize the original display data to obtain reorganized display data, wherein the reorganized display data includes the original display data and the expanded display data.

[0010] The second latch unit group includes multiple second latch units, which are respectively connected to the data processing unit group. Each second latch unit is configured to cache a column of reconstructed display data, wherein the cached column of reconstructed display data is either a column of original display data or a column of extended display data.

[0011] In one embodiment, each column of extended display data is determined by the adjacent column of original display data; or

[0012] Each column of extended display data is determined by at least two adjacent columns of original display data.

[0013] In one embodiment, each column of extended display data is determined by combining a first portion of the original display data of an adjacent column and a second portion of the original display data of another adjacent column; or

[0014] When the data receiving unit receives the original display data of the nth row, the extended display data of each column is determined by the original display data of the adjacent column; when the data receiving unit receives the original display data of the (n+1)th row, the extended display data of each column is determined by the original display data of the adjacent column; or

[0015] When the data receiving unit receives the original display data of the m-th frame image, each column of extended display data is determined by the adjacent column of original display data; when receiving the original display data of the (m+1)-th frame image, each column of extended display data is determined by the adjacent column of original display data.

[0016] In one embodiment, each first latch unit includes a plurality of first latches, each first latch being configured to cache a column of original display data, and the pixel colors corresponding to the original display data cached by different first latches in each first latch unit are different.

[0017] Each second latch unit includes multiple second latches, and each second latch is configured to cache a column of recombined display data. The pixel colors corresponding to the recombined display data cached by different second latches in each second latch unit are different.

[0018] Each data processing unit includes multiple data processing sub-units, and each data processing sub-unit is configured to expand and reorganize the original display data to obtain reorganized display data.

[0019] In one embodiment, the data processing subunit includes a first data processing path and a second data processing path. The first data processing path connects a first latch and a second latch, and is configured to transmit a column of original display data cached in the first latch to the corresponding connected second latch as original display data in the reconstructed display data. The second data processing path connects the first data processing path and a second latch, and is configured to transmit the original display data to the corresponding connected second latch as extended display data in the reconstructed display data. The second latch connected to the second data processing path and the second latch connected to the first data processing path are respectively located in two adjacent second latch units.

[0020] In one embodiment, each first latch includes a plurality of first registers, each first register being configured to cache one bit of data in a column of original display data; each second latch includes a plurality of second registers, each second register being configured to cache one bit of data in a column of reconstructed display data;

[0021] The data processing subunit includes a first data processing path and a second data processing path. Each first data processing path includes multiple first data transmission channels, and each second data processing path includes multiple second data transmission channels. Each first data transmission channel is configured to transmit one bit of data from a column of original display data. A portion of the second data transmission channels in the second data processing path are connected to a portion of the first data transmission channels in an adjacent first data processing path, and another portion of the second data transmission channels in the second data processing path are connected to another portion of the first data transmission channels in an adjacent first data processing path.

[0022] In one embodiment, when receiving the nth row of original display data or the mth frame of image, the first data processing path is configured to transmit a column of original display data cached in the first latch to the corresponding connected second latch as the original display data in the reconstructed display data, and the second data processing path is configured to transmit the original display data to the corresponding connected second latch as the extended display data in the reconstructed display data.

[0023] In one embodiment, the data processing subunit further includes a third data processing path, which is connected to a first data processing path and a second latch. When receiving the (n+1)th row of original display data or the (m+1)th frame of image original display data, the first data processing path is configured to transmit a column of original display data cached in the first latch to the corresponding connected second latch as original display data in the reconstructed display data. The third data processing path is configured to transmit the original display data to the corresponding connected second latch as extended display data in the reconstructed display data. The second latch unit corresponding to the second latch connected to the third data processing path and the second latch unit corresponding to the second latch connected to the second data processing path are two adjacent second latch units of the second latch unit corresponding to the second latch unit connected to the first data processing path.

[0024] In one embodiment, the number of first latch units and second latch units is the same.

[0025] To solve the above-mentioned technical problems, the second technical solution adopted by the present invention is: to provide a display panel, including a timing control circuit and a source driving circuit connected to the timing control circuit, wherein the source driving circuit receives raw display data from the timing control circuit, and the source driving circuit includes any of the above-mentioned source driving circuits.

[0026] The beneficial effects of this invention are as follows: Unlike existing technologies, the source drive circuit of this invention comprises a first latch unit group, a data processing unit group, and a second latch unit group. The data processing unit group expands and reassembles the original display data cached in the first latch unit group to obtain reassembled display data, which is then cached in the second latch unit group. This enables horizontal expansion of display data within the source drive circuit, and since the reassembled display data is obtained by expanding and reassembling the original display data, the display effect is improved. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the structure of the first embodiment of the source drive circuit of this application;

[0029] Figure 2 This is a schematic diagram of the first embodiment of the data reconstruction and display method of this application;

[0030] Figure 3 To obtain Figure 2A schematic diagram of one embodiment of the source drive circuit corresponding to the recombined display data shown;

[0031] Figure 4 for Figure 3 A schematic diagram of the structure of the first embodiment of the first latch unit and the second latch unit;

[0032] Figure 5 for Figure 3 A schematic diagram of the source drive circuit at a low refresh rate;

[0033] Figure 6 for Figure 3 A schematic diagram of the structure of the second embodiment of the first latch unit and the second latch unit;

[0034] Figure 7 This is a schematic diagram of the second embodiment of the data reconstruction display in this application;

[0035] Figure 8 To obtain Figure 7 A schematic diagram of one embodiment of the source drive circuit corresponding to the recombined display data shown;

[0036] Figure 9 This is a schematic diagram of the third embodiment of the reconstructed display data in this application;

[0037] Figure 10 for Figure 9 A schematic diagram of an embodiment of the source drive circuit corresponding to the recombined display data shown;

[0038] Figure 11 for Figure 10 Timing diagram of the switching of the first, second, and third data processing paths;

[0039] Figure 12 This is a schematic diagram of the fourth embodiment of the reconstructed display data in this application;

[0040] Figure 13 This is a schematic diagram of the structure of the second embodiment of the source drive circuit of this application;

[0041] Figure 14 This is a schematic diagram of the structure of one embodiment of the display panel of this application.

[0042] Explanation of reference numerals in the attached figures: Source drive circuit 10, data receiving unit 11, first latch unit group 12, first latch unit 121, data processing unit group 13, data processing unit 131, second latch unit group 14, second latch unit 141, first latch 120, first data processing path Ia, second data processing path Ib, second latch 140, first register 1200, second register 1400, first data transmission channel A, second data transmission channel B, third data processing path Ic, level conversion unit 15, digital-to-analog conversion unit 16, output buffer unit 17, display panel 40, timing control circuit 41. Detailed Implementation

[0043] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0044] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0045] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, "more" in this article means two or more objects.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0047] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0048] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] See Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the source drive circuit of this application. The source drive circuit 10 specifically includes: a data receiving unit 11, a first latch unit group 12, a data processing unit group 13, and a second latch unit group 14.

[0050] The data receiving unit 11 is configured to receive raw display data line by line. The first latch unit group 12 includes multiple first latch units 121, each connected to the data receiving unit 11. Each first latch unit 121 is configured to cache a column of raw display data. The data processing unit group 13 includes multiple data processing units 131, each connected to the first latch unit group 12. The data processing unit group 13 is configured to expand and reassemble the raw display data to obtain reassembled display data, wherein the reassembled display data includes both raw display data and expanded display data. The second latch unit group 14 includes multiple second latch units 141, each connected to the data processing unit group 13. Each second latch unit 141 is configured to cache a column of reassembled display data, wherein the cached column of reassembled display data is either a column of raw display data or a column of expanded display data.

[0051] In this embodiment, the source drive circuit provides a data processing unit group 13 between the first latch unit group 12 and the second latch unit group 14. The data processing unit group 13 enables the expansion and reconstruction of the original display data to obtain reconstructed display data, thereby increasing the resolution of the original display data and thus increasing the resolution of the display panel.

[0052] In one embodiment, each column of extended display data is determined by the adjacent column of original display data. For example, in reorganized display data, if the odd-numbered columns are the original display data and the even-numbered columns are the extended display data, then the even-numbered column display data (extended display data) is determined by the adjacent odd-numbered column of original display data. Figure 2 As shown, columns 2, 4, 6, ..., 2n are extended display data, and columns 1, 3, 5, ..., 2n-1 are original display data. The extended display data in columns 2, 4, 6, ..., 2n is obtained by copying the original display data in columns 1, 3, 5, ..., 2n-1. Specifically, the extended display data in column 2 is obtained by copying the original display data in column 1, the extended display data in column 4 is obtained by copying the original display data in column 3, and the extended display data in column 2n is obtained by copying the original display data in column 2n-1.

[0053] Further integration Figure 3 and Figure 4Each first latch unit 121 includes multiple first latches 120, each configured to cache a column of original display data. The pixel colors corresponding to the original display data cached by different first latches 120 in each first latch unit 121 are different. Specifically, each first latch unit 121 includes three first latches 120, each caches a column of original display data corresponding to red pixels, green pixels, and blue pixels, respectively. Similarly, each second latch unit 141 includes multiple second latches 140, each configured to cache a column of reconstructed display data. The pixel colors corresponding to the reconstructed display data cached by different second latches 140 in each second latch unit 141 are different. Specifically, the second latch unit 141 includes three second latches 140, which respectively cache the recombined display data corresponding to a column of red pixels, the recombined display data corresponding to green pixels, and the recombined display data corresponding to blue pixels. Further, the data processing unit 131 includes multiple data processing subunits, each configured to expand and recombinate the original display data to obtain recombined display data. Specifically, each data processing unit 131 includes three data processing subunits (one such as...). Figure 4 As shown by the thin solid line, one is as Figure 4 As shown by the dashed line, a... Figure 4 (As shown by the thick solid line). The data processing subunit shown by the thin solid line is configured to expand the original display data corresponding to the red pixels to obtain the reconstructed display data corresponding to the red pixels; the data processing subunit shown by the dashed line is configured to expand the original display data corresponding to the green pixels to obtain the reconstructed display data corresponding to the green pixels; the data processing subunit shown by the thick solid line is configured to expand the original display data corresponding to the blue pixels to obtain the reconstructed display data corresponding to the blue pixels.

[0054] Furthermore, each data processing subunit includes a first data processing path Ia and a second data processing path Ib. In this embodiment, the data processing subunit corresponding to the red pixel (i.e....) Figure 4The following explanation uses the data processing subunit (shown by the thin solid line) as an example. The first data processing path Ia connects a first latch 120 and a second latch 140, and is configured to transmit a column of raw display data cached in the first latch 120 to the corresponding connected second latch 140 as raw display data in the reconstructed display data. The second data processing path Ib connects the first data processing path Ia and a second latch 140, and is configured to transmit the raw display data to the corresponding connected second latch 140 as extended display data in the reconstructed display data. It should be noted that the second latch 140 connected to the second data processing path Ib and the second latch 140 connected to the first data processing path Ia are located in two adjacent second latch units 141.

[0055] by Figure 4 The illustrated embodiment is used as an example for explanation. Assume the original display data has n columns, corresponding to n first latch units 121. Then, the three first latches 120 in the nth first latch unit 121 respectively cache the original display data Rn corresponding to the red pixels in the nth column, the original display data Gn corresponding to the green pixels in the nth column, and the original display data Bn corresponding to the blue pixels in the nth column. Assume the number of columns in the reconstructed display data is twice that of the original display data, then the reconstructed display data has 2n columns, corresponding to 2n second latch units 141.

[0056] The three first latches 120 in the nth first latch unit 121 respectively cache the original display data of the three colors. For the original display data Rn corresponding to the red pixels, the first data processing path Ia in the data processing subunit shown by the thin solid line connects the first first latch 120 in the nth first latch unit 121 and the first second latch 140 in the (2n-1)th second latch unit 141. The second data processing path Ib connects the first data processing path Ia and the first second latch 140 in the (2n-1)th second latch unit 141. The first data processing path Ia transmits the original display data Rn corresponding to the nth column of red pixels in the corresponding first latch 120 to the corresponding second latch 140, obtaining the recombined display data R2n-1 corresponding to the (2n-1)th column of red pixels. The second data processing path Ib transmits the original display data Rn corresponding to the nth column of red pixels to the corresponding second latch 140, obtaining the recombined display data R2n corresponding to the 2nth column of red pixels. The process of converting the original display data corresponding to green and blue pixels into reconstructed display data is the same, and will not be repeated here.

[0057] In one embodiment, a switch is provided on the second data processing path Ib. In this embodiment, the source drive circuit sets up a data processing unit group 13 between the first latch unit group 12 and the second latch unit group 14 to realize data expansion and recombination, completing the horizontal expansion of the display data. It should be noted that the data processing unit group 13 is controlled by a timing control circuit. When the system is in low refresh rate mode, the timing control circuit outputs a low-level enable signal to the switch on the second data processing path Ib, controlling the second data processing path Ib to close. At this time, no display data expansion is performed; that is, the recombined display data is the same as the original display data. The circuit structure is equivalent to... Figure 5 When the system is in high refresh rate multiplication mode, the timing control circuit outputs a high-level enable signal to control the second data processing path Ib to conduct. At this time, display data expansion is performed, that is, the display data is reconstructed, including the original display data and the expanded display data. The structure at this time is as follows: Figure 3 As shown. It is understood that the resolution of the display panel in the row direction can be expanded by 2 times through the method of this application, such as from 2K to 4K.

[0058] In another embodiment of this application, a switch is also provided on the first data processing path Ia, such as... Figure 6 As shown, the switch on the first data processing path Ia is also controlled by the timing control circuit. Specifically, when the system is in low refresh rate mode, the timing control circuit outputs a high-level enable signal to the switch on the first data processing path Ia, controlling the first data processing path Ia to be turned on, and outputs a low-level enable signal to the switch on the second data processing path Ib, controlling the second data processing path Ib to be turned off. At this time, no display data expansion is performed, that is, the reconstructed display data is the same as the original display data. When the system is in high refresh rate multiplication mode, the timing control circuit outputs a high-level enable signal to the switch on the first data processing path Ia and the switch on the second data processing path Ib, controlling the first data processing path Ia and the second data processing path Ib to be turned on. At this time, display data expansion is performed, that is, the reconstructed display data includes the original display data and the expanded display data. In one embodiment, the enable signal of the switch on the first data processing path Ia is later than the enable signal of the switch on the second data processing path Ib, which can ensure that the original display data and the expanded display data are transmitted to the second latch unit 141 simultaneously.

[0059] In the above embodiments, the display data is obtained by simply copying the original display data to obtain extended display data. The original display data and the extended display data are interleaved to form recombined display data. When displaying based on the recombined display data, jagged edges may occur, for example, jagged edges may appear when displaying text content.

[0060] In another embodiment, each column of extended display data is determined by at least two adjacent columns of original display data. For example, in reorganized display data, if odd-numbered columns are the original display data and even-numbered columns are the extended display data, then the even-numbered column display data (extended display data) is determined by at least two adjacent odd-numbered column original display data. Figure 7 As shown, columns 2, 4, 6, ..., 2n are extended display data, and columns 1, 3, 5, ..., 2n-1 are original display data. The extended display data in column 2 is obtained by combining the original display data in column 1 and column 3. The extended display data in column 4 is obtained by combining the original display data in column 3 and column 5. The extended display data in column 2n is obtained by combining the original display data in column 2n-1 and column 2n+1.

[0061] It should be noted that the extended display data of each column is determined by combining the first part of the original display data of the adjacent column and the second part of the original display data of the adjacent column. Specifically, the extended display data of column 2 is obtained by combining the first part of the original display data of column 1 and the second part of the original display data of column 3; the extended display data of column 4 is obtained by combining the first part of the original display data of column 3 and the second part of the original display data of column 5; and the extended display data of column 2n is obtained by combining the first part of the original display data of column 2n-1 and the second part of the original display data of column 2n+1.

[0062] It should be noted that the original display data for each color is generally 8 bits. Taking the red pixel as an example, the original display data for the red pixel is generally denoted as R[7:0]. The green and blue pixels are the same, and the details will not be elaborated further.

[0063] Combination Figure 8 Taking the original display data of the red pixel as an example, each first latch 120 includes multiple first registers 1200, each configured to cache one bit of data from a column of original display data. It can be understood that the original display data of the red pixel includes 8 bits of data, so each first latch 120 includes eight first registers 1200, each caching one bit of the 8 bits of original display data. Each second latch 140 includes multiple second registers 1400, each configured to cache one bit of data from a column of reconstructed display data. It can be understood that the reconstructed display data of the red pixel also includes 8 bits of data, so each second latch 140 includes eight second registers 1400, each caching one bit of the 8 bits of reconstructed display data.

[0064] The data processing subunit includes a first data processing path and a second data processing path. Each first data processing path includes multiple first data transmission channels A, and each second data processing path includes multiple second data transmission channels B. Each first data transmission channel A is configured to transmit one bit of data from a column of original display data. A portion of the second data transmission channels B in the second data processing path is connected to a portion of the first data transmission channels A in an adjacent first data processing path, and another portion of the second data transmission channels B in the second data processing path is connected to another portion of the first data transmission channels A in an adjacent first data processing path.

[0065] Specifically, the second register 1400 in the (2n-2)th second latch 140 is connected to the first register 1200 in the (n-1)th first latch 120 via the first data transmission channel A. The first data transmission channel A is configured to transmit the original display data buffered in the first register 1200 of the (n-1)th first latch 120 to the second register 1400 of the (2n-2)th second latch 140 to obtain the recombined display data for the (2n-2)th column. Similarly, the second register 1400 in the (2n)th second latch 140 is connected to the first register 1200 of the nth first latch 120 via the first data transmission channel A. The first data transmission channel A is configured to transmit the original display data buffered in the first register 1200 of the nth first latch 120 to the second register 1400 of the (2n)th second latch 140 to obtain the recombined display data for the nth column. Part of the second register 1400 in the (2n-1)th second latch 140 is connected to part of the first register 1200 in the (n-1)th first latch 120 through part of the second data transmission channel B. Another part of the second register 1400 is connected to another part of the first register 1200 in the nth first latch 120 through another part of the second data transmission channel B. The data cached in part of the first register 1200 in the (n-1)th first latch 120 and the data cached in another part of the first register 1200 in the nth first latch 120 are combined to obtain the (2n-1)th column of recombined display data. In this embodiment, the reconstructed display data of column 2n is the same as the original display data of column n, and the reconstructed display data of column 2n-2 is the same as the original display data of column n-1. The reconstructed display data of column 2n-1 is obtained by combining the first part of the original display data of column n (i.e., the reconstructed display data of column 2n-2) and the second part of the original display data of column n-1 (i.e., the reconstructed display data of column 2n). The method of this embodiment can solve the problem of jagged edges.

[0066] In one embodiment, R2n-1[7:0] = Rn-1[7:4] + Rn[3:0], that is, the recombined display data of column 2n-1 is obtained by combining the high four bits of the original display data of column n-1 (that is, the recombined display data of column 2n-2) and the low four bits of the original display data of column n (that is, the recombined display data of column 2n). Specifically, the high four bits and the low four bits are concatenated. Of course, the high three bits and the low five bits can also be concatenated, and there is no specific limitation. In another embodiment, the average value of R2n-2[0]~R2n-2[7] and R2n[0]~R2n[7] can also be calculated to obtain R2n-1[0]~R2n-1[7].

[0067] Let's analyze the specific effect of the splicing using the formula R2[7:0] = R1[7:4] + R3[3:0]. For example, if R1 is 150 gray levels (10010110 in binary) and R3 is 170 gray levels (10101010 in binary), after splicing (the high four bits of R1 and the low four bits of R3), R2 becomes 10011010, which is 154 gray levels. That is, the gray level after splicing is between R1 and R3. Another example: if R1 is 120 gray levels (01111000 in binary) and R3 is 200 gray levels (11001000 in binary), after splicing (the high four bits of R1 and the low four bits of R3), it becomes 01111000, still 120 gray levels. For example, if R1 has 30 gray levels (00011110 in binary) and R3 has 247 gray levels (11110111 in binary), concatenating them (the high four bits of R1 and the low four bits of R3) results in 00010111, which is 23 gray levels. This demonstrates that when the difference between the gray levels of R1 and R3 is small (e.g., less than 15 gray levels), it is more likely that the concatenated R2 will fall between R1 and R3. Therefore, the concatenation scheme can optimize the display effect to a certain extent.

[0068] In this embodiment, switches are provided on both the first data transmission channel A and the second data transmission channel B. The switches are controlled by a timing control circuit, and the control of the switches is the same as described above. Figure 6 The control methods for the switches of the first data processing path Ia and the second data processing path Ib are the same, and will not be described again here.

[0069] Furthermore, to address the jagged edges in the display and improve the display effect, when the data receiving unit 11 in the source drive circuit of this application receives the nth row of original display data, the extended display data for each column is determined by the adjacent column of original display data; when the data receiving unit 11 receives the (n+1)th row of original display data, the extended display data for each column is determined by the adjacent column of original display data. See details... Figure 9That is, when the data receiving unit 11 receives the original display data for odd-numbered rows, the display data (extended display data) for even-numbered columns is determined by the original display data of the adjacent odd-numbered columns. For example, if columns 2, 4, 6, ..., 2n are extended display data and columns 1, 3, 5, ..., 2n-1 are the original display data, then the extended display data for columns 2, 4, 6, ..., 2n is copied from the original display data of columns 1, 3, 5, ..., 2n-1. When the data receiving unit 11 receives the original display data for even-numbered rows, the display data (extended display data) for even-numbered columns is determined by the original display data of another adjacent odd-numbered column. For example, if columns 2, 4, 6, ..., 2n are extended display data and columns 1, 3, 5, ..., 2n-1 are the original display data, then the extended display data for columns 2, 4, 6, ..., 2n-2 is copied from the original display data of columns 3, 5, 7, ..., 2n-1. In the recombined display data generated in this embodiment, no two adjacent columns of recombined display data will be completely identical, which can reduce the jagged edges.

[0070] Combination Figure 10 In this embodiment, each data processing subunit includes a first data processing path Ia and a second data processing path Ib. This embodiment uses the data processing subunit corresponding to the red pixel (i.e.,...) Figure 10 The following explanation uses the data processing subunit (shown by the thin solid line) as an example. The first data processing path Ia connects a first latch 120 and a second latch 140. The second data processing path Ib connects the first data processing path Ia and the second latch 140. When the data receiving unit 11 receives the nth row of original display data, the first data processing path Ia is configured to transfer a column of original display data cached in the first latch 120 to the corresponding connected second latch 140 as original display data in the reconstructed display data. The second data processing path Ib is configured to transfer the original display data to the corresponding connected second latch 140 as extended display data in the reconstructed display data. It should be noted that the second latch 140 connected to the second data processing path Ib and the second latch 140 connected to the first data processing path Ia are located in two adjacent second latch units 141.

[0071] Furthermore, each data processing subunit also includes a third data processing path Ic, which connects to the first data processing path Ia and a second latch 140. When the data receiving unit 11 receives the (n+1)th row of original display data, the first data processing path Ia is configured to transmit a column of original display data cached in the first latch 120 to the corresponding connected second latch 140 as the original display data in the reconstructed display data. The third data processing path Ic is configured to transmit the original display data to the corresponding connected second latch 140 as the extended display data in the reconstructed display data. It should be noted that the second latch unit 141 corresponding to the second latch 140 connected to the third data processing path Ic and the second latch unit 141 corresponding to the second latch 140 connected to the second data processing path Ib are the two adjacent second latch units 141 of the second latch unit 141 connected to the second latch 140 of the first data processing path.

[0072] Specifically, when the data receiving unit 11 receives the original display data of the nth row, the first data processing path Ia transmits the original display data Rn corresponding to the red pixel of the nth column in the first latch 120 connected to the corresponding second latch 140 to obtain the recombined display data R2n-1 corresponding to the red pixel of the (2n-1)th column, and the second data processing path Ib transmits the original display data Rn corresponding to the red pixel of the nth column to the corresponding second latch 140 to obtain the recombined display data R2n corresponding to the red pixel of the 2nth column. When the data receiving unit 11 receives the (n+1)th row of original display data, the first data processing path Ia transmits the original display data Rn corresponding to the nth column of red pixels in the corresponding first latch 120 to the corresponding second latch 140 to obtain the recombined display data R2n-1 corresponding to the 2n-1th column of red pixels. The third data processing path Ic transmits the original display data Rn corresponding to the nth column of red pixels to the corresponding second latch 140 to obtain the recombined display data R2n-2 corresponding to the 2n-2th column of red pixels.

[0073] Understandably, the third data processing path IC in this embodiment is also equipped with a switch. Combined with... Figure 11In high refresh rate multiplication mode, when data receiving unit 11 receives the nth line of original display data, the timing control circuit outputs a high-level TP signal and a high-level EN1 signal to control the switching of the first data processing path Ia and the second data processing path Ib to turn on, and the timing control circuit outputs a low-level EN2 signal to control the switching of the third data processing path Ic to turn off. When data receiving unit 11 receives the (n+1)th line of original display data, the timing control circuit outputs a high-level TP signal and a high-level EN2 signal to control the switching of the first data processing path Ia and the third data processing path Ic to turn on, and the timing control circuit outputs a low-level EN1 signal to control the switching of the second data processing path Ib to turn off. It should be noted that the high-level EN1 signal precedes the high-level TP signal; or the high-level EN2 signal precedes the high-level TP signal. Specifically, the purpose of setting the high-level EN1 signal before the high-level TP signal is to ensure that the switches of the second data processing path Ib are all turned on before the switches of the first data processing path Ia are turned on, thereby allowing the recombined display data of each column to arrive at the second latch 140 simultaneously. The principle of setting the high-level EN2 signal before the high-level TP signal is the same.

[0074] In this embodiment, although the jagged edges of the displayed image can be improved and the display effect enhanced, the switch needs to be toggled once when scanning each line, which increases the power consumption of the source drive circuit. Therefore, this application also proposes an embodiment, such as... Figure 12 As shown. Combined with Figure 10 When the data receiving unit 11 receives the m-th frame of original display data, the first data processing path Ia is configured to transmit a column of original display data cached in the first latch 120 to the corresponding connected second latch 140 as original display data in the reconstructed display data. The second data processing path Ib is configured to transmit the original display data to the corresponding connected second latch 140 as extended display data in the reconstructed display data. When the data receiving unit 11 receives the (m+1)-th frame of original display data, the first data processing path Ia is configured to transmit a column of original display data cached in the first latch 120 to the corresponding connected second latch 140 as original display data in the reconstructed display data. The third data processing path Ic is configured to transmit the original display data to the corresponding connected second latch 140 as extended display data in the reconstructed display data.

[0075] Specifically, when the data receiving unit 11 receives the original display data of the m-th frame Frame_m, the first data processing path Ia transmits the original display data Rn corresponding to the n-th column of red pixels in the corresponding first latch 120 to the corresponding second latch 140 to obtain the recombined display data R2n-1 corresponding to the 2n-1-th column of red pixels. The second data processing path Ib transmits the original display data Rn corresponding to the n-th column of red pixels to the corresponding second latch 140 to obtain the recombined display data R2n corresponding to the 2n-th column of red pixels. When the data receiving unit 11 receives the original display data of the (m+1)th frame Frame_m+1, the first data processing path Ia transmits the original display data Rn corresponding to the nth column of red pixels in the corresponding first latch 120 to the corresponding second latch 140 to obtain the recombined display data R2n-1 corresponding to the 2n-1th column of red pixels. The third data processing path Ic transmits the original display data Rn corresponding to the nth column of red pixels to the corresponding second latch 140 to obtain the recombined display data R2n-2 corresponding to the 2n-2th column of red pixels.

[0076] In this embodiment, due to the accumulation of time, the pixels in the even-numbered columns achieve a display effect that is 1 / 3 of the average value of the original display effect (3 refers to the three colors of red, green and blue), making the display effect in the horizontal direction more uniform.

[0077] In this embodiment, the on / off switching is performed once per frame, eliminating the need for on / off switching for each line. Compared to the above... Figure 9 The embodiment shown reduces the power consumption of the source drive circuit.

[0078] This application Figure 2 , Figure 7 , Figure 9 and Figure 12 Each provides a schematic diagram of recombining and displaying data; Figure 2 The recombined display data shown is obtained by directly copying the adjacent original display data. This solution requires fewer switches, has a simple circuit structure, and consumes less power, but the display will have a jagged edge and the display effect will be poor. Figure 7 The reorganized display data shown here, in which the expanded display data is composed of two adjacent columns of original display data, has a display effect compared to... Figure 2 The illustrated embodiment is better. Figure 9 The recombined display data shown achieves spatial color mixing, resulting in a better display effect. However, it requires setting up a large number of switches, and each row needs to be switched once, which increases power consumption. Figure 12The recombined display data shown achieves color mixing over time, resulting in good display effects. Although it requires setting a relatively large number of switches, it switches once per frame, which is more efficient than... Figure 9 In the embodiment shown, power consumption is low.

[0079] In the above embodiments, it is assumed that the original display data has n columns, corresponding to n first latch units 121, and the reconstructed display data has 2n columns, corresponding to 2n second latch units 141. That is, the number of second latch units 141 is twice that of the first latch units 121. However, in actual production, all second latch units 141 and all first latch units 121 need to be fabricated on the same device, which requires the production of two devices with different structures, which is not conducive to mass production. Therefore, this application sets the number of first latch units and second latch units to be the same, so that they can be mass-produced as a single device. In practical applications, unused first latch units can transmit empty or zero signals, as long as it does not affect the overall operation of the source drive circuit.

[0080] Further, see Figure 13 , with the above Figure 1 Compared to the illustrated embodiment, the source driving circuit 10 of this application further includes a level conversion unit 15, a digital-to-analog converter 16, and an output buffer unit 17. The level conversion unit 15 is the signal adapter of the source driving circuit 10, primarily responsible for amplitude conversion of the voltage signal to ensure signal compatibility between different circuit modules. In the liquid crystal display panel, the reconstructed display data is generally at a low voltage, which needs to be converted to a high voltage by the level conversion unit 15 to drive the liquid crystal molecules to deflect. The digital-to-analog converter 16 is the signal converter of the source driving circuit 10, used to convert digital image signals into analog voltage signals. The output buffer unit 17 is the power amplifier of the source driving circuit 10, used to amplify the analog voltage signal and drive the pixel electrodes of the display panel. Typically, the analog voltage signal current output by the digital-to-analog converter 16 is relatively small and cannot directly drive the pixel electrodes; therefore, it needs to be amplified by the output buffer unit 17 to improve the driving capability.

[0081] See Figure 14 , Figure 14 This is a schematic diagram of the structure of the display panel of this application. The display panel 40 includes a timing control circuit 41 and a source drive circuit 10 connected to the timing control circuit 41. The source drive circuit 10 receives raw display data from the timing control circuit 41. The source drive circuit 10 includes any of the above-mentioned source drive circuits.

[0082] The above are merely embodiments of the present invention and do not limit the scope of patent protection of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A source driving circuit applied to a display panel, characterized in that, The display device comprises: a data receiving unit configured to receive original display data row by row; a first latch unit group comprising a plurality of first latch units, and the plurality of first latch units are connected to the data receiving unit respectively, each first latch unit is configured to buffer a column of the original display data; a data processing unit group comprising a plurality of data processing units, and the plurality of data processing units are connected to the first latch unit group respectively, the data processing unit group is configured to expand and reorganize the original display data to obtain reorganized display data, wherein the reorganized display data comprises the original display data and expanded display data; a second latch unit group comprising a plurality of second latch units, and the plurality of second latch units are connected to the data processing unit group respectively, each second latch unit is configured to buffer a column of the reorganized display data, wherein the column of the reorganized display data buffered by each second latch unit is a column of the original display data or a column of the expanded display data; each column of the expanded display data is determined by at least two adjacent columns of the original display data; wherein each column of the expanded display data is determined by a first part of one adjacent column of the original display data and a second part of another adjacent column of the original display data; or when the data receiving unit receives the nth row of the original display data, each column of the expanded display data is determined by one adjacent column of the original display data; when the data receiving unit receives the (n+1)th row of the original display data, each column of the expanded display data is determined by another adjacent column of the original display data; or when the data receiving unit receives the original display data of the mth frame of image, each column of the expanded display data is determined by one adjacent column of the original display data; when the data receiving unit receives the original display data of the (m+1)th frame of image, each column of the expanded display data is determined by another adjacent column of the original display data.

2. The source driving circuit according to claim 1, wherein each first latch unit comprises a plurality of first latches, each first latch is configured to buffer a column of the original display data, and the original display data buffered by different first latches in each first latch unit correspond to different pixel colors; each second latch unit comprises a plurality of second latches, each second latch is configured to buffer a column of the reorganized display data, and the reorganized display data buffered by different second latches in each second latch unit correspond to different pixel colors; each data processing unit comprises a plurality of data processing subunits, and each data processing subunit is configured to expand and reorganize the original display data to obtain the reorganized display data.

3. The source driving circuit according to claim 2, wherein The data processing subunit comprises a first data processing path and a second data processing path. The first data processing path is connected with one first latch and one second latch, and is configured to transmit a column of the original display data stored in the first latch to the corresponding connected second latch as the original display data in the reorganized display data. The second data processing path is connected with the first data processing path and one second latch, and is configured to transmit the original display data to the corresponding connected second latch as the extended display data in the reorganized display data. The second latch connected with the second data processing path and the second latch connected with the first data processing path are respectively located in two adjacent second latch units.

4. The source driving circuit according to claim 2, wherein Each first latch comprises a plurality of first registers, and each first register is configured to store one bit of data in one column of the original display data. Each second latch comprises a plurality of second registers, and each second register is configured to store one bit of data in one column of the reorganized display data. The data processing subunit comprises a first data processing path and a second data processing path. Each first data processing path comprises a plurality of first data transmission channels. Each second data processing path comprises a plurality of second data transmission channels. Each first data transmission channel is configured to transmit one bit of data in one column of the original display data. A part of the second data transmission channels in the second data processing path are connected with a part of the first data transmission channels in one adjacent first data processing path. Another part of the second data transmission channels in the second data processing path are connected with another part of the first data transmission channels in another adjacent first data processing path.

5. The source driving circuit according to claim 3, wherein When receiving the nth row of the original display data or receiving the mth frame of the original display data, the first data processing path is configured to transmit a column of the original display data stored in the first latch to the corresponding connected second latch as the original display data in the reorganized display data. The second data processing path is configured to transmit the original display data to the corresponding connected second latch as the extended display data in the reorganized display data.

6. The source driving circuit according to claim 5, wherein The data processing subunit further comprises a third data processing path, the third data processing path connects the first data processing path and one of the second latch, when receiving the nth+1 row of original display data or receiving the m+1 frame of original display data, the first data processing path is configured to transmit one column of the original display data cached in the first latch to the corresponding connected second latch as the original display data in the reorganized display data, the third data processing path is configured to transmit the original display data to the corresponding connected second latch as the expanded display data in the reorganized display data; wherein the corresponding second latch unit of the second latch connected by the third data processing path and the corresponding second latch unit of the second latch connected by the second data processing path are two adjacent second latch units of the corresponding second latch unit of the second latch connected by the first data processing path.

7. The source driving circuit according to claim 2, wherein The number of the first latch units is the same as the number of the second latch units.

8. A display panel, characterized by, The source driving circuit comprises a timing control circuit and a source driving circuit connected to the timing control circuit, the source driving circuit receives original display data from the timing control circuit, and the source driving circuit comprises the source driving circuit according to any one of claims 1-7.

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