Shifting register unit and driving method thereof, gate driving circuit and display panel

Abstract

The invention relates to the technical field of display, and provides a shift register unit and a driving method thereof, a gate driving circuit and a display panel, and the shift register unit comprises a first input circuit, a first coupling circuit, a first control circuit, an isolation circuit, a first output circuit and a second coupling circuit. The first input circuit is used for responding to a signal of a signal input end to provide an input signal for a first control node; the first coupling circuit is used for coupling the voltage change of the second control node to the first control node; the first control circuit is used for transmitting a signal of a first clock signal end to a second control node; the isolation circuit is used for communicating the first control node and the third control node; the first output circuit is used for transmitting a signal of a second clock signal end to a signal output end; the second coupling circuit is used for coupling the voltage change of the signal output end or the second clock signal end to a third control node. The shift register unit has relatively high driving capability.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit and a driving method thereof, a gate driving circuit, and a display panel. Background Art

[0002] On large, high-resolution displays, the row strobe time is very short. For example, the row strobe time for a 4K TV at a 60Hz refresh rate is approximately 8µs, and for an 8K TV it is approximately 4µs. Consequently, the gate drive circuit outputs an extremely short pulse width. However, due to the presence of rising and falling edges in the pulse signal, the actual pulse width of the effective pulse signal is relatively short. Furthermore, voltage loss at the control node in the gate drive circuit can result in insufficient gate drive signal voltage.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] The present disclosure first provides a shift register unit, wherein the shift register unit includes:

[0005] a first input circuit connected to the first control node and the signal input terminal, wherein the first input circuit is configured to respond to a signal from the signal input terminal to provide an input signal to the first control node;

[0006] a first coupling circuit connected between the first control node and a second control node, the first coupling circuit being configured to couple a voltage change of the second control node to the first control node;

[0007] a first control circuit connected to a first clock signal terminal, a first control node, and a second control node, wherein the first control circuit is configured to respond to a signal from the first control node to transmit a signal from the first clock signal terminal to the second control node;

[0008] an isolation circuit connected to the first control node and the third control node, wherein the isolation circuit is configured to connect the first control node and the third control node in response to a control signal;

[0009] a first output circuit connected to the second clock signal terminal, the signal output terminal, and a third control node, wherein the first output circuit is configured to respond to a signal of the third control node to transmit the signal of the second clock signal terminal to the signal output terminal;

[0010] a second coupling circuit, wherein a first end of the second coupling circuit is connected to the third control node, and a second end is connected to the signal output end or the second clock signal end, and the second coupling circuit is used to couple the voltage change of the signal output end or the second clock signal end to the third control node.

[0011] In an exemplary embodiment of the present disclosure, the second coupling circuit includes a second capacitor, the first coupling circuit includes a first capacitor, and the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

[0012] In an exemplary embodiment of the present disclosure, the isolation circuit is connected to the first clock signal terminal, and the isolation circuit is configured to respond to a signal at the first clock signal terminal to connect the first control node and the third control node.

[0013] In an exemplary embodiment of the present disclosure, the first input circuit is configured to respond to the signal input terminal to transmit the signal of the signal input terminal to the first control node, and the first input circuit includes:

[0014] a first transistor, having a first electrode connected to the signal input terminal, a second electrode connected to the first control node, and a control electrode connected to the signal input terminal;

[0015] The first coupling circuit includes:

[0016] a first capacitor connected between the first control node and the second control node;

[0017] The first control circuit includes:

[0018] a second transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the second control node, and a control electrode connected to the first control node;

[0019] The isolation circuit comprises:

[0020] a third transistor, having a first electrode connected to the first control node, a second electrode connected to the third control node, and a control electrode connected to the first clock signal terminal;

[0021] The first output circuit includes:

[0022] a fourth transistor, having a first electrode connected to the second clock signal terminal, a second electrode connected to the signal output terminal, and a control electrode connected to the third control node;

[0023] The second coupling circuit includes:

[0024] The second capacitor has a first electrode connected to the third control node and a second electrode connected to the second clock signal terminal or the signal output terminal.

[0025] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0026] a second input circuit connected to the first power supply terminal, the third clock signal terminal, and the fourth control node, wherein the second input circuit is configured to transmit the signal of the first power supply terminal to the fourth control node in response to the signal of the third clock signal terminal;

[0027] a first reset circuit connected to the second power supply terminal, the first control node, and the reset signal terminal, wherein the first reset circuit is configured to respond to a signal from the reset signal terminal to transmit a signal from the second power supply terminal to the first control node;

[0028] a second reset circuit connected to the first power supply terminal, the fourth control node, and the reset signal terminal, the second reset circuit being configured to respond to a signal from the reset signal terminal to transmit a signal from the first power supply terminal to the fourth control node;

[0029] a first pull-down circuit connected to the second power supply terminal, the third clock signal terminal, the fourth control node, the second control node, and the third control node, the first pull-down circuit being configured to respond to signals from the third clock signal terminal and the fourth control node to transmit the signal from the second power supply terminal to the second control node, and to respond to signals from the third clock signal terminal to transmit the signal from the second power supply terminal to the third control node;

[0030] a second pull-down circuit connected to the third clock signal terminal, the first control node, and the fourth control node, the second pull-down circuit being configured to respond to a signal of the first control node to transmit the signal of the third clock signal terminal to the fourth control node;

[0031] The second output circuit is connected to the second power supply end, the fourth control node, and the signal output end. The second output circuit is used to respond to the signal of the fourth control node to transmit the signal of the second power supply end to the signal output end.

[0032] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0033] A third capacitor is connected between the fourth control node and the second power supply terminal.

[0034] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0035] The third pull-down circuit is connected to the second power supply terminal, the third clock signal terminal, and the second control node. The third pull-down circuit is used to respond to the signal of the third clock signal terminal to transmit the signal of the second power supply terminal to the second control node.

[0036] In an exemplary embodiment of the present disclosure, the second input circuit includes:

[0037] a fifth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the fourth control node, and a control electrode connected to the third clock signal terminal;

[0038] The first reset circuit includes:

[0039] a seventh transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the first control node, and a control electrode connected to the reset signal terminal;

[0040] The second reset circuit includes:

[0041] an eighth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the fourth control node, and a control electrode connected to the reset signal terminal;

[0042] The first pull-down circuit comprises:

[0043] a sixth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the third control node, and a control electrode connected to the third clock signal terminal;

[0044] a ninth transistor, having a first electrode connected to the second power supply terminal and a control electrode connected to the third clock signal terminal;

[0045] a tenth transistor, having a first electrode connected to the second electrode of the ninth transistor, a second electrode connected to the second control node, and a control electrode connected to the fourth control node;

[0046] The second pull-down circuit includes:

[0047] an eleventh transistor, having a first electrode connected to the third clock signal terminal, a second electrode connected to the fourth control node, and a control electrode connected to the first control node;

[0048] The second output circuit includes:

[0049] a twelfth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the signal output terminal, and a control electrode connected to the fourth control node;

[0050] The third pull-down circuit comprises:

[0051] A thirteenth transistor has a first electrode connected to the second power supply terminal, a second electrode connected to the second control node, and a control electrode connected to the third clock signal terminal.

[0052] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0053] a second input circuit connected to the first power supply terminal and a fourth control node, wherein the second input circuit is configured to transmit a signal from the first power supply terminal to the fourth control node;

[0054] a first reset circuit connected to the first control node, the second power supply terminal, and a reset signal terminal, the reset circuit being configured to respond to a signal from the reset signal terminal to transmit a signal from the second power supply terminal to the first control node;

[0055] a first pull-down circuit connected to the second power supply end, the first control node, the fourth control node, and the second control node, the first pull-down circuit being configured to respond to a signal from the fourth control node to transmit a signal from the second power supply end to the first control node and the second control node;

[0056] a second pull-down circuit connected to the second power supply terminal, the first control node, and a fourth control node, the second pull-down circuit being configured to respond to a signal from the first control node to transmit a signal from the second power supply terminal to the fourth control node;

[0057] The second output circuit is connected to the second power supply end, the fourth control node, and the signal output end. The second output circuit is used to respond to the signal of the fourth control node to transmit the signal of the second power supply end to the signal output end.

[0058] In an exemplary embodiment of the present disclosure, the isolation circuit is connected to a third clock signal terminal, and the isolation circuit is configured to respond to a signal at the third clock signal terminal to connect the first control node and the third control node.

[0059] In an exemplary embodiment of the present disclosure, the second input circuit includes:

[0060] a fifth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the fourth control node, and a control electrode connected to the first power supply terminal;

[0061] The first reset circuit includes:

[0062] a sixth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the first control node, and a control electrode connected to the reset signal terminal;

[0063] The first pull-down circuit comprises:

[0064] a seventh transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the first control node, and a control electrode connected to the fourth control node;

[0065] an eighth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the second control node, and a control electrode connected to the fourth control node;

[0066] The second pull-down circuit includes:

[0067] a ninth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the fourth control node, and a control electrode connected to the first control node;

[0068] The second output circuit includes:

[0069] a tenth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the signal output terminal, and a control electrode connected to the fourth control node;

[0070] The isolation circuit comprises:

[0071] The third transistor has a first electrode connected to the first node, a second electrode connected to the third node, and a control electrode connected to the third clock signal terminal.

[0072] The present disclosure further provides a shift register unit driving method, wherein the driving method is used to drive the above-mentioned shift register unit, and the driving method includes:

[0073] In the first stage, the first control node and the third control node are disconnected by the isolation circuit, and the signal from the signal input terminal is transmitted to the first control node by the first input circuit;

[0074] In the second stage, the signal at the first clock signal terminal is transmitted to the second control node by using the first control circuit, the voltage change of the second control node is coupled to the first control node by using the first coupling circuit, and the first control node and the third control node are connected by using the isolation circuit;

[0075] In the third stage, the isolation circuit is used to shut down the first control node and the third control node, the second coupling circuit is used to couple the signal change of the second clock signal end or the signal output end to the third node, and the first output circuit is used to transmit the signal of the second clock signal end to the signal output end.

[0076] The present disclosure further provides a gate driving circuit, wherein the gate driving circuit includes the above-mentioned shift register unit, and a plurality of the shift register units are cascaded.

[0077] The present disclosure also provides a display panel, wherein the display panel includes the above-mentioned gate driving circuit.

[0078] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0080] Figure 1 Schematic diagram of the structure of an exemplary embodiment of the shift register unit disclosed in the present invention;

[0081] Figure 2 Schematic diagram of the structure of another exemplary embodiment of the shift register unit disclosed in the present invention;

[0082] Figure 3 Schematic diagram of the structure of another exemplary embodiment of the shift register unit disclosed in the present invention;

[0083] Figure 4 This is a schematic structural diagram of an exemplary embodiment of the gate drive circuit disclosed herein;

[0084] Figure 5 for Figure 4 The timing diagram of each node in a driving method of the gate driving circuit shown;

[0085] Figure 6 is a driving state diagram of the shift register unit in the first stage;

[0086] Figure 7 is a driving state diagram of the shift register unit in the second stage;

[0087] Figure 8 is a driving state diagram of the shift register unit in the third stage;

[0088] Figure 9 is a driving state diagram of the shift register unit in the fourth stage;

[0089] Figure 10 is a driving state diagram of the shift register unit in the fifth stage;

[0090] Figure 11 is a driving state diagram of the shift register unit in the sixth stage;

[0091] Figure 12 is a structural schematic diagram of another exemplary embodiment of the gate driving circuit disclosed herein;

[0092] Figure 13 for Figure 12 The timing diagram of each node in a driving method of the gate driving circuit shown;

[0093] Figure 14Schematic diagram of the structure of another exemplary embodiment of the shift register unit disclosed in the present invention;

[0094] Figure 15 for Figure 14 A timing diagram of each node in a driving method of the shift register unit shown;

[0095] Figure 16 FIG. 4 is a schematic structural diagram of a first input circuit in another exemplary embodiment of the shift register unit disclosed herein. DETAILED DESCRIPTION

[0096] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0097] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0098] In the description of this disclosure, unless otherwise expressly provided or limited, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance; the term "plurality" refers to two or more; and the term "and / or" includes any and all combinations of one or more of the associated listed items. In particular, reference to "the" or "an" object is also intended to mean one of a possible plurality of such objects.

[0099] Unless otherwise specified or explained, the terms "connect," "fixed," etc. should be understood broadly. For example, "connected" may refer to a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; and "connected" may refer to a direct connection or an indirect connection through an intermediary. Those skilled in the art will understand the specific meanings of the above terms in this disclosure based on specific circumstances.

[0100] Furthermore, in the description of the present disclosure, it should be understood that the directional words such as "upper", "lower", "inner", and "outer" described in the exemplary embodiments of the present disclosure are described from the perspectives shown in the accompanying drawings and should not be understood as limiting the exemplary embodiments of the present disclosure. It should also be understood that, in the context, when it is mentioned that an element or feature is connected to one or more "upper", "lower", or "inner" or "outer" of another element, it can not only be directly connected to the "upper", "lower", or "inner" or "outer" of the other one or more elements, but can also be indirectly connected to the "upper", "lower", or "inner" or "outer" of the other one or more elements through an intermediate element.

[0101] This exemplary embodiment first provides a shift register unit, such as Figure 1 As shown, it is a structural diagram of an exemplary embodiment of the shift register unit disclosed in the present invention. The shift register unit may include: a first input circuit 11, a first coupling circuit 21, a first control circuit 31, an isolation circuit 4, a first output circuit 51, and a second coupling circuit 22. The first input circuit 11 is connected to the first control node N1 and the signal input terminal IN. The first input circuit 11 is used to respond to a control signal to transmit the signal of the signal input terminal IN to the first control node N1; the first coupling circuit 21 is connected between the first control node N1 and the second control node N2. The first coupling circuit 21 is used to couple the voltage change of the second control node N2 to the first control node N1; the first control circuit 31 is connected to the first clock signal terminal CK1, the first control node N1, and the second control node N2. The first control circuit 31 is used to respond to the signal of the first control node N1 and transmit the signal of the first clock signal terminal CK1 to the second control node N2. 2; the isolation circuit 4 is connected to the first control node N1 and the third control node N3, and the isolation circuit 4 is used to respond to a control signal to connect the first control node N1 and the third control node N3; the first output circuit 51 is connected to the second clock signal terminal CK2, the signal output terminal OUT, and the third control node N3, and the first output circuit 51 is used to respond to the signal of the third control node N3 to transmit the signal of the second clock signal terminal CK2 to the signal output terminal OUT; the second coupling circuit 22 is connected between the third control node N3 and the second clock signal terminal CK2, and the second coupling circuit 22 is used to couple the voltage change of the second clock signal terminal CK2 to the third control node N3.

[0102] In this exemplary embodiment, in the first stage, the isolation circuit 4 can be used to turn off the first control node N1 and the third control node N3, and the first input circuit 11 can be used to transmit the signal of the signal input terminal IN to the first control node N1; in the second stage, the isolation circuit 4 can be used to turn on the first control node N1 and the third control node N3, and at the same time, the first control circuit 31 can be used to transmit the signal of the first clock signal terminal CK1 to the second control node N2, and the first coupling circuit 21 can couple the voltage change of the second control node N2 to the first control node N1, so that the voltage of the third control node N3 can be pulled up; in the third stage, the isolation circuit 4 can be used to turn off the first control node N1 and the third control node N3, and the first output circuit 51 can be used to transmit the signal of the second clock signal terminal CK2 to the signal output terminal OUT. At the same time, in the third stage, the second coupling circuit 22 can further pull up the voltage of the third control node N3. The shift register unit can pull up the voltage of the third control node N3 through the first coupling circuit 21 and the second coupling circuit 22, so that this setting can improve the driving capability of the signal on the signal output terminal OUT, that is, it can increase the voltage of the effective pulse signal of the gate drive signal output by the signal output terminal OUT, and reduce the duration of the rising edge and falling edge of the gate drive signal output by the signal output terminal.

[0103] In this exemplary embodiment, Figure 1 As shown, the isolation circuit 4 is connected to the first clock signal terminal CK1 , and the isolation circuit 4 is configured to connect the first control node N1 and the third control node N3 in response to the signal of the first clock signal terminal CK1 .

[0104] In this exemplary embodiment, Figure 1 As shown, the first input circuit 11 includes a first transistor T1, with a first electrode connected to the signal input terminal IN, a second electrode connected to the first control node N1, and a control electrode connected to the signal input terminal IN. The first coupling circuit 21 includes a first capacitor C1, connected between the first control node N1 and the second control node N2. The first control circuit 31 includes a second transistor T2, with a first electrode connected to the first clock signal terminal CK1, a second electrode connected to the second control node N2, and a control electrode connected to the first control node N1. The isolation circuit 4 includes a third transistor T3, with a first electrode connected to the first control node N1, a second electrode connected to the third control node N3, and a control electrode connected to the first clock signal terminal CK1. The first output circuit 51 includes a fourth transistor T4, with a first electrode connected to the second clock signal terminal CK2, a second electrode connected to the signal output terminal OUT, and a control electrode connected to the third control node N3. The second coupling circuit 22 includes a second capacitor C2, connected between the third control node N3 and the second clock signal terminal CK2.

[0105] In this exemplary embodiment, Figure 1 As shown, the shift register unit further includes: a second input circuit 12, a first reset circuit 61, a second reset circuit 62, a first pull-down circuit 71, a second pull-down circuit 72, and a second output circuit 52. The second input circuit 12 is connected to the first power supply terminal VGH, the third clock signal terminal CK3, and the fourth control node N4. The second input circuit 12 is used to respond to the signal of the third clock signal terminal CK3 to transmit the signal of the first power supply terminal VGH to the fourth control node N4; the first reset circuit 61 is connected to the second power supply terminal VGL, the first control node N1, and the reset signal terminal Re. The first reset circuit 61 is used to respond to the signal of the reset signal terminal Re to transmit the signal of the second power supply terminal VGL to the first control node N1; the second reset circuit 62 is connected to the first power supply terminal VGH, the fourth control node N4, and the reset signal terminal Re. The second reset circuit 62 is used to respond to the signal of the reset signal terminal Re to transmit the signal of the first power supply terminal VGH to the fourth control node N4; the first pull-down circuit 71 is connected to the second power supply terminal VGL, the third clock signal terminal CK3, the fourth control node N4, The second control node N2 and the third control node N3, the first pull-down circuit 71 is used to respond to the signal of the third clock signal terminal CK3 and the fourth control node N4 to transmit the signal of the second power supply terminal VGL to the second control node N2, and is used to respond to the signal of the third clock signal terminal CK3 to transmit the signal of the second power supply terminal VGL to the third control node N3; the second pull-down circuit 72 is connected to the third clock signal terminal CK3, the first control node N1, and the fourth control node N4, the second pull-down circuit 72 is used to respond to the signal of the first control node N1 to transmit the signal of the third clock signal terminal CK3 to the fourth control node N4; the second output circuit 52 is connected to the second power supply terminal VGL, the fourth control node N4, and the signal output terminal OUT, the second output circuit 52 is used to respond to the signal of the fourth control node N4 to transmit the signal of the second power supply terminal VGL to the signal output terminal OUT.

[0106] In this exemplary embodiment, Figure 1As shown, the second input circuit 12 includes a fifth transistor T5, with a first electrode connected to the first power supply terminal VGH, a second electrode connected to the fourth control node N4, and a control electrode connected to the third clock signal terminal CK3. The first reset circuit 61 includes a seventh transistor T7, with a first electrode connected to the second power supply terminal VGL, a second electrode connected to the first control node N1, and a control electrode connected to the reset signal terminal Re. The second reset circuit 62 includes an eighth transistor T8, with a first electrode connected to the first power supply terminal VGH, a second electrode connected to the fourth control node N4, and a control electrode connected to the reset signal terminal Re. The first pull-down circuit 71 includes a sixth transistor T6, a ninth transistor T9, and a tenth transistor T10. The sixth transistor T6 has a first electrode connected to the second power supply terminal VGL, a second electrode connected to the third control node N3, and a control electrode connected to the third clock signal terminal CK3. The ninth transistor T9 has a first electrode connected to the second power supply terminal VGL and a control electrode connected to the third clock signal terminal CK3. The tenth transistor T10 has a first electrode connected to the second electrode of the ninth transistor T9, a second electrode connected to the second control node N2, and a control electrode connected to the fourth control node N4. The second pull-down circuit 72 includes an eleventh transistor T11, wherein a first electrode of the eleventh transistor T11 is connected to the third clock signal terminal CK3, a second electrode is connected to the fourth control node N4, and a control electrode is connected to the first control node N1. The second output circuit 52 includes a twelfth transistor T12, wherein a first electrode of the twelfth transistor T12 is connected to the second power supply terminal VGL, a second electrode is connected to the signal output terminal OUT, and a control electrode is connected to the fourth control node N4.

[0107] In this exemplary embodiment, Figure 1 As shown, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 can be N-type transistors, the first power supply terminal VGH is a high-level power supply terminal, and the second power supply terminal VGL is a low-level power supply terminal.

[0108] like Figure 2 FIG. 1 is a structural diagram of another exemplary embodiment of a shift register unit disclosed in the present invention, and FIG. Figure 1 Compared to the shift register unit shown, Figure 2The shift register unit shown is further provided with a third capacitor C3, which can be connected between the fourth control node N4 and the second power supply terminal VGL. The third capacitor C3 can store the charge of the fourth control node N4, so that when the fourth control node N4 is floating (not connected to the signal terminal), the signal stored in the fourth control node N4 can continuously turn on or off the twelfth transistor T12. It should be understood that in other exemplary embodiments, the third capacitor C3 can also be connected between the fourth control node N4 and another stable power supply terminal.

[0109] like Figure 3 FIG. 1 is a structural diagram of another exemplary embodiment of a shift register unit disclosed in the present invention, and FIG. Figure 1 Compared to the shift register unit shown, Figure 3 The shift register unit shown is additionally provided with a third pull-down circuit 73, which is connected to the second power supply terminal VGL, the third clock signal terminal CK3, and the second control node N2. The third pull-down circuit 73 is used to respond to the signal of the third clock signal terminal CK3 to transmit the signal of the second power supply terminal VGL to the second control node N2. The third pull-down circuit 73 may include: a thirteenth transistor T13, the first electrode of the thirteenth transistor T13 is connected to the second power supply terminal VGL, the second electrode is connected to the second control node N2, and the control electrode is connected to the third clock signal terminal CK3. The thirteenth transistor T13 may be an N-type transistor. The shift register unit can pull down the second control node N2 through the second power supply terminal VGL when the third clock signal terminal CK3 outputs a high level, so as to reset and reduce noise on the second control node N2. In addition, Figure 3 The shift register unit shown may also be provided with a third capacitor, and the third capacitor is connected to the fourth control node.

[0110] It should be understood that in other exemplary embodiments, Figure 1-Figure 3 The second capacitor in the shift register unit may also be connected between the third control node N3 and the signal output terminal OUT.

[0111] like Figure 4 FIG. 1 is a schematic diagram showing a structure of an exemplary embodiment of a gate drive circuit disclosed herein. The gate drive circuit includes a plurality of shift register units GOA, and the structure of the shift register unit can be Figure 1 、 Figure 2 、 Figure 3Any one shown. Multiple shift register units can be cascaded. For example, the signal output terminal OUT of the shift register unit at this stage is connected to the signal input terminal IN of the adjacent next stage shift register unit, and the signal output terminal OUT of the shift register unit at this stage is connected to the reset signal terminal Re of the adjacent previous stage shift register unit. The display panel may also include an initial signal line STV, a first clock signal line LCK1, a second clock signal line LCK2, and a third clock signal line LCK3. Among them, the initial signal line STV is connected to the signal input terminal IN of the first stage shift register unit GOA; the first clock signal line LCK1 is connected to the first clock signal terminal of each stage shift register unit GOA; the second clock signal line LCK2 is connected to the second clock signal terminal of the odd-numbered stage shift register unit and the third clock signal terminal of the even-numbered stage shift register unit; the third clock signal line LCK3 is connected to the third clock signal terminal of the odd-numbered stage shift register unit and the second clock signal terminal of the even-numbered stage shift register unit.

[0112] like Figure 5 As shown, Figure 4 The following is a timing diagram of each node in a driving method for a gate drive circuit. STV represents the timing of the signal on the initial signal line, LCK1 represents the timing of the signal on the first clock signal line, LCK2 represents the timing of the signal on the second clock signal line, and LCK3 represents the timing of the signal on the third clock signal line. This exemplary embodiment is described using the first-stage shift register unit as an example. OUT represents the timing of the signal at the signal output terminal of the first-stage shift register unit, Re represents the timing of the signal at the reset signal terminal of the first-stage shift register unit, N1 represents the timing of the signal at the first control node of the first-stage shift register unit, N2 represents the timing of the signal at the second control node of the first-stage shift register unit, and N3 represents the timing of the signal at the third control node of the first-stage shift register unit.

[0113] The driving method of the shift register unit includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, and a sixth stage t6.

[0114] In the first stage t1: Figure 6The figure shows the driving state of the shift register unit in the first phase, where the crossed-out transistors are in the off state and the uncrossed transistors are in the on state. In the first phase t1, the initial signal line STV and the third clock signal line LCK3 input high-level signals, while the first clock signal line LCK1 and the second clock signal line LCK2 output low-level signals. The first transistor T1 is turned on, the initial signal line STV inputs a high-level signal to the first control node N1, the eleventh transistor T11 is turned on, the third clock signal line LCK3 inputs a high-level signal to the fourth control node N4, the twelfth transistor T12 is turned on, and the second power supply terminal VGL inputs a low-level signal to the signal output terminal OUT. Simultaneously, the sixth transistor T6 is turned on, the second power supply terminal VGL inputs a low-level signal to the third control node N3, and the fourth transistor T4 is turned off. The second transistor T2 is turned on, and the first clock signal line LCK1 inputs a low-level signal to the second control node N2. Simultaneously, the ninth transistor T9 and the tenth transistor T10 are turned on, and the second power supply terminal VGL inputs a low-level signal to the second control node N2.

[0115] In the second stage t2: Figure 7 The figure shows the driving state diagram of the shift register unit in the second stage, in which the crossed transistors are in the off state and the uncrossed transistors are in the on state. The first clock signal line LCK1 outputs a high-level signal, the second clock signal line LCK2 and the third clock signal line LCK3 output a low-level signal, and the third transistor T3 is turned on. The first transistor T1 is turned off, the first control node N1 maintains a high-level signal, the second transistor T2 is turned on, the first clock signal line LCK1 inputs a high-level signal to the second control node N2, and the second control node N2 jumps from a low level to a high level. Under the coupling effect of the first capacitor C1, the first control node N1 is pulled high. For example, the voltage input to the first control node N1 in the first stage is Vh, the voltage input to the third control node N3 in the first stage is -Vh, the voltage input to the second control node N2 in the first stage is -Vh, and the voltage input to the second control node N2 in the second stage is Vh. According to the total charge conservation principle on the third control node N3 and the first control node N1, the voltage formula of the third control node N3 is:

[0116]

[0117] Wherein, V3 is the voltage of the third control node, Cst1 is the capacitance value of the first capacitor, and Cst1 is the capacitance value of the second capacitor. In order to make the voltage of the third control node N3 greater than Vh, the capacitance value of the first capacitor C1 can be greater than the capacitance value of the second capacitor C2. For example, the capacitance value of the first capacitor C1 can be 1.5 times, 2 times, 2.5 times, 3 times, etc. of the capacitance value of the second capacitor C2. At the same time, the fourth transistor T4 can be turned on, and the second clock signal line LCK2 inputs a low-level signal to the signal output terminal OUT. The eleventh transistor T11 is turned on, and the third clock signal line LCK3 inputs a low-level signal to the fourth control node N4 to turn off the twelfth transistor T12. In the second stage, this exemplary embodiment performs a first pull-up on the third control node N3. The first pull-up can enable the third control node N3 to obtain a voltage higher than Vh, thereby fully turning on the fourth transistor T4, and the signal output terminal OUT can fully output the high-level signal of the second clock signal terminal CK2.

[0118] In the third stage t3: Figure 8 Figure 2 shows the driving state of the shift register unit in the third stage, where the crossed transistors are in the off state and the uncrossed transistors are in the on state. The second clock signal line LCK2 outputs a high-level signal, while the first clock signal line LCK1 and the third clock signal line LCK3 output low-level signals. The third transistor T3 is turned off, and the second clock signal line LCK2 inputs a high-level signal to the signal output terminal OUT. Simultaneously, the second clock signal line LCK2 changes from a low level to a high level. Under the coupling effect of the second capacitor C2, the voltage of the third control node N3 is pulled up a second time. Simultaneously, because the third transistor T3 is turned off, the third transistor T3 disconnects the first control node N1 and the third control node N3, so that the potential change of the first control node N1 does not affect the potential of the third control node N3. It also disconnects the first capacitor C1 and the second capacitor C2, preventing the first capacitor C1 from dividing a portion of the voltage of the second capacitor C2 that rises when the second clock signal terminal transitions from a low level to a high level. Therefore, based on the initial pull-up, the voltage of the third control node N3 is pulled up again. This configuration can improve the driving capability of the signal at the signal output terminal OUT and reduce the duration of the rising and falling edges of the signal at the signal output terminal OUT. Simultaneously, the eleventh transistor T11 is turned on, and the third clock signal line LCK3 inputs a low-level signal to the fourth control node N4, turning off the twelfth transistor T12.

[0119] In the fourth stage t4: Figure 9, which is a driving state diagram of the shift register unit in the fourth stage, wherein the crossed-out transistors are in the off state and the uncrossed transistors are in the on state. The first clock signal line LCK1 outputs a high-level signal, while the second clock signal line LCK2 and the third clock signal line LCK3 output low-level signals. The second transistor T2 is turned on, and the first clock signal line LCK1 inputs a high-level signal to the second control node N2 of the first-stage shift register unit. Under the coupling of the first capacitor C1 and the second capacitor C2, the first control node N1 and the third control node N3 are pulled high, the fourth transistor T4 is turned on, and the second clock signal line LCK2 inputs a low-level signal to the signal output terminal OUT. At the same time, the eleventh transistor T11 is turned on, the third clock signal line LCK3 inputs a low-level signal to the fourth control node N4 in the first-stage shift register unit, and the twelfth transistor T12 is turned off.

[0120] In the fifth stage t5: Figure 10 , which is a driving state diagram of the shift register unit in the fifth stage, wherein the crossed-out transistors are in the off state, and the uncrossed transistors are in the on state. The reset signal terminal Re and the third clock signal line LCK3 output high-level signals, while the first clock signal line LCK1 and the second clock signal line LCK2 output low-level signals. The sixth transistor T6 is turned on, the second power supply terminal VGL inputs a low-level signal to the third control node N3, the fourth transistor T4 is turned off, the eighth transistor T8 is turned on, the first power supply terminal VGH inputs a high-level signal to the fourth control node N4, the twelfth transistor T12 is turned on, and the second power supply terminal VGL inputs a low-level signal to the signal output terminal OUT. Simultaneously, the ninth transistor T9 and the tenth transistor T10 are turned on, the second power supply terminal VGL inputs a low-level signal to the second control node N2, the seventh transistor T7 is turned on, and the second power supply terminal VGL inputs a low-level signal to the first control node N1, turning off the eleventh transistor.

[0121] In the sixth stage t6: Figure 11 Figure 2 shows the driving state of the shift register unit in the sixth stage, where the crossed transistors are in the off state and the uncrossed transistors are in the on state. The first clock signal line LCK1 outputs a high-level signal, while the second clock signal line LCK2 and the third clock signal line LCK3 output low-level signals. The first control node N1 and the third control node N3 maintain low-level signals, the second transistor T2, the fourth transistor T4, and the eleventh transistor T11 are off, the fourth control node N4 maintains a high-level signal, the twelfth transistor T12 is on, and the second power supply terminal VGL inputs a low-level signal to the signal output terminal OUT.

[0122] when Figure 4 The shift register unit in the gate drive circuit shown is Figure 3 When shown, Figure 3The shift register unit shown can pull down the second control node N2 through the second power supply terminal VGL in the fifth phase to reset the second control node N2 and reduce noise.

[0123] like Figure 12 FIG. 1 is a schematic diagram of another exemplary embodiment of a gate drive circuit disclosed herein. The gate drive circuit includes a plurality of shift register units GOA, and the structure of the shift register unit can be as follows: Figure 1 、 2 , 3. Multiple shift register units can be cascaded. For example, the signal output terminal OUT of the shift register unit at this stage is connected to the signal input terminal IN of the adjacent shift register unit at the next stage, and the signal output terminal OUT of the shift register unit at this stage is connected to the reset signal terminal Re of the adjacent shift register unit at the previous stage. The display panel may also include an initial signal line STV, a first clock signal line LCK1, a second clock signal line LCK2, a third clock signal line LCK3, a fourth clock signal line LCK4, and a fifth clock signal line LCK5. Among them, the initial signal line STV is connected to the signal input terminal IN of the first-stage shift register unit GOA; the first clock signal line LCK1 is connected to the first clock signal terminal of the shift register units GOA at each level; the third clock signal line LCK3 is connected to the third clock signal terminal of the (1+4n)-stage shift register unit and the second clock signal terminal of the (4+4n)-stage shift register unit; the second clock signal line LCK2 is connected to the second clock signal terminal of the (1+4n)-stage shift register unit and the third clock signal terminal of the (2+4n)-stage shift register unit; the fourth clock signal line LCK4 is connected to the second clock signal terminal of the (2+4n)-stage shift register unit and the third clock signal terminal of the (3+4n)-stage shift register unit; the fifth clock signal line LCK5 is connected to the third clock signal terminal of the (4+4n)-stage shift register unit and the second clock signal terminal of the (3+4n)-stage shift register unit, wherein n is an integer greater than or equal to 0.

[0124] like Figure 13 As shown, Figure 12 The timing diagram of each node in a driving method of the gate drive circuit shown in the figure. Among them, STV represents the timing of the initial signal line, LCK1 represents the timing of the signal on the first clock signal line, LCK2 represents the timing of the signal on the second clock signal line, LCK3 represents the timing of the signal on the third clock signal line, LCK4 represents the timing of the signal on the fourth clock signal line, LCK5 represents the timing of the signal on the fifth clock signal line, OUT represents the timing of the signal on the signal output end of the first stage shift register unit, and Re represents the timing of the signal on the reset signal end of the first stage shift register unit. The driving method of the shift register unit in the gate drive circuit and Figure 4The driving method of the shift register unit in the gate driving circuit is the same, and the driving method of the shift register unit may also include a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, and a sixth stage t6. Figure 12 The gate drive circuit shown can reduce the number of shift register units connected to some clock signal lines (e.g., the second clock signal line, the third clock signal line, the fourth clock signal line, and the fifth clock signal line), thereby reducing the load on these clock signal lines. This configuration can further improve the driving capability of the gate drive signal output by the gate drive circuit. It should be understood that in other exemplary embodiments, the display panel can further be provided with a greater number of clock signal lines to further reduce the load on the clock signal lines.

[0125] like Figure 14 FIG2 is a schematic diagram of the structure of another exemplary embodiment of a shift register unit according to the present disclosure. In addition to the first input circuit 11, the first coupling circuit 21, the first control circuit 31, the isolation circuit 4, and the first output circuit 51, the shift register unit may also include a second coupling circuit 22, a second input circuit 12, a first reset circuit 61, a first pull-down circuit 71, a second pull-down circuit 72, and a second output circuit 52. The second coupling circuit 22 is connected between the third control node N3 and the signal output terminal OUT. The second coupling circuit 22 is used to couple the voltage change of the signal output terminal OUT to the third control node N3. The second input circuit 12 is connected to the first power supply terminal VGH and the fourth control node N4, and is used to transmit the signal of the first power supply terminal VGH to the fourth control node N4; the first reset circuit 61 is connected to the first control node N1, the second power supply terminal VGL, and the reset signal terminal Re, and is used to respond to the signal of the reset signal terminal Re to transmit the signal of the second power supply terminal VGL to the first control node N1; the first pull-down circuit 71 is connected to the second power supply terminal VGL, the first control node N1, the fourth control node N4, and the second control node N2, and is used to respond to the signal of the fourth control node N4 The second pull-down circuit 72 is connected to the second power supply terminal VGL, the first control node N1, and the fourth control node N4. The second pull-down circuit 72 is used to respond to the signal of the first control node N1 to transmit the signal of the second power supply terminal VGL to the fourth control node N4; the second output circuit 52 is connected to the second power supply terminal VGL, the fourth control node N4, and the signal output terminal OUT. The second output circuit 52 is used to respond to the signal of the fourth control node N4 to transmit the signal of the second power supply terminal VGL to the signal output terminal OUT.

[0126] In this exemplary embodiment, Figure 14As shown, the second coupling circuit 22 includes a second capacitor C2 connected between the signal output terminal OUT and the third control node N3. The second input circuit 12 includes a fifth transistor T5, with a first electrode connected to the first power supply terminal VGH, a second electrode connected to the fourth control node N4, and a control electrode connected to the first power supply terminal VGH. The first reset circuit 61 includes a sixth transistor T6, with a first electrode connected to the second power supply terminal VGL, a second electrode connected to the first control node N1, and a control electrode connected to the reset signal terminal Re. The first pull-down circuit 71 includes a seventh transistor T7 and an eighth transistor T8, with a first electrode connected to the second power supply terminal VGL, a second electrode connected to the first control node, and a control electrode connected to the fourth control node N4. The eighth transistor T8 has a first electrode connected to the second power supply terminal VGL, a second electrode connected to the second control node N2, and a control electrode connected to the fourth control node N4. The second pull-down circuit 72 includes: a ninth transistor T9, a first electrode of the ninth transistor T9 is connected to the second power supply terminal VGL, a second electrode is connected to the fourth control node N4, and a control electrode is connected to the first control node; the second output circuit 52 includes: a tenth transistor T10, a first electrode of the tenth transistor T10 is connected to the first power supply terminal VGH, a second electrode is connected to the signal output terminal OUT, and a control electrode is connected to the fourth control node N4.

[0127] It should be understood that in other exemplary embodiments, the second capacitor C2 may also be connected between the third control node N3 and the second clock signal terminal CK2. The control electrode of the third transistor T3 may also be connected to the first clock signal terminal.

[0128] like Figure 14 As shown, the first transistor T1 to the tenth transistor T10 may be N-type transistors, the first power supply terminal VGH is a high-level power supply terminal, and the second power supply terminal VGL is a low-level power supply terminal.

[0129] like Figure 15 As shown, Figure 14 The timing diagram of each node in a driving method of a shift register unit is shown. In it, IN represents the timing of the signal at the signal input terminal, CK1 represents the timing of the signal at the first clock signal terminal, CK2 represents the timing of the signal at the second clock signal terminal, CK3 represents the timing of the signal at the third clock signal terminal, OUT represents the timing of the signal at the signal output terminal, Re represents the timing of the signal at the reset signal terminal, N1 represents the timing of the signal at the first control node, N2 represents the timing of the signal at the second control node, and N3 represents the timing of the signal at the third control node.

[0130] The driving method of the shift register unit includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, and a sixth stage t6.

[0131] In the first phase t1, a high-level signal is input to the signal input terminal IN, while the first, second, and third clock signal terminals CK1, CK2, and CK3 output low-level signals. The first transistor T1 is turned on, and the signal input terminal IN inputs a high-level signal to the first control node N1. The second transistor T2 is turned on, and the first clock signal terminal CK1 inputs a low-level signal to the second control node N2. The signal output terminal OUT maintains the low level of the previous phase. Simultaneously, the ninth transistor T9 is turned on, the second power supply terminal VGL inputs a low-level signal to the fourth control node N4, and the seventh and tenth transistors T7 and T10 are turned off.

[0132] In the second phase t2: the first clock signal terminal CK1 and the third clock signal terminal CK3 output high-level signals, and the second clock signal terminal CK2 and the signal input terminal IN output low-level signals. The first transistor T1 is turned off, and the first control node N1 maintains the high level of the previous phase. The second transistor T2 and the third transistor T3 are turned on. The first clock signal terminal CK1 inputs a high-level signal to the second control node N2, and the second control node N2 jumps from the low level to the high level. Under the coupling effect of the first capacitor C1, the first control node N1 is pulled high. For example, the voltage input to the first control node N1 in the first phase is Vh, the voltage maintained at the third control node N3 in the first phase is -Vh, the voltage input to the second control node N2 in the first phase is -Vh, and the voltage input to the second control node N2 in the second phase is Vh. According to the total charge conservation principle on the third control node N3 and the first control node N1, the voltage formula of the third control node N3 is:

[0133]

[0134] Wherein, V3 is the voltage of the third control node, Cst1 is the capacitance value of the first capacitor, and Cst2 is the capacitance value of the second capacitor. In order to make the voltage of the third control node N3 greater than Vh, the capacitance value of the first capacitor C1 can be greater than the capacitance value of the second capacitor C2. At the same time, the fourth transistor T4 can be turned on, and the second clock signal line LCK2 inputs a low-level signal to the signal output terminal OUT. In the second phase, this exemplary embodiment performs a first pull-up on the third control node N3. This first pull-up can enable the third control node N3 to obtain a voltage higher than Vh, thereby fully turning on the fourth transistor T4, and the signal output terminal OUT can fully output the high-level signal of the second clock signal terminal CK2.

[0135] In the third phase t3, the first clock signal terminal CK1 outputs a high-level signal, while the second and third clock signal terminals CK2 and CK3 output low-level signals. The third transistor T3 is turned off, the third control node N3 remains high, the fourth transistor T4 is turned on, and the second clock signal terminal CK2 inputs a low-level signal to the signal output terminal OUT via the fourth transistor T4. Simultaneously, the first and second control nodes N1 and N2 maintain their high potentials from the previous phase, the ninth transistor T9 is turned on, the second power supply terminal VGL inputs a low-level signal to the fourth control node N4, and the tenth transistor T10 is turned off.

[0136] In the fourth phase t4, the first clock signal terminal CK1 and the third clock signal terminal CK3 output low-level signals, and the second clock signal terminal CK2 outputs a high-level signal. The second clock signal terminal CK2 inputs a high-level signal to the signal output terminal OUT. Simultaneously, the signal output terminal OUT changes from a low level to a high level. Under the coupling effect of the signal output terminal OUT, the voltage of the third control node N3 is pulled up a second time. At the same time, because the third transistor T3 is turned off, the third transistor T3 disconnects the first control node N1 and the third control node N3, so that the potential change of the first control node N1 does not affect the potential of the third control node N3. At the same time, the connection between the first capacitor C1 and the second capacitor C2 is disconnected, preventing the first capacitor C1 from dividing a portion of the voltage of the second capacitor C2 that rises due to the jump from the second clock signal terminal from a low level to a high level. Therefore, based on the first pull-up, the voltage of the third control node N3 is pulled up again. This configuration can improve the driving capability of the signal at the signal output terminal OUT and shorten the duration of the rising and falling edges of the signal at the signal output terminal OUT.

[0137] In the fifth phase t5, the first clock signal terminal CK1, the third clock signal terminal CK3, and the second clock signal terminal CK2 output low levels. The third transistor T3 is turned off, the third control node N3 remains high, the fourth transistor T4 is turned on, and the second clock signal terminal CK2 inputs a low-level signal to the signal output terminal OUT. The first control node N1 remains high, the ninth transistor T9 is turned on, the second power supply terminal VGL inputs a low-level signal to the fourth control node N4, and the tenth transistor T10 is turned off. The second transistor T2 is turned on, and the first clock signal terminal CK1 pulls down the voltage of the second control node N2. Due to the action of the first capacitor C1, the voltage of the first control node N1 drops slightly.

[0138] In the sixth phase t6, the first clock signal terminal CK1, the third clock signal terminal CK3, and the reset signal terminal Re output high-level signals, and the second clock signal terminal CK2 outputs a low-level signal. The third transistor T3 and the sixth transistor T6 are turned on, and the second power supply terminal VGL inputs a low-level signal to the first control node N1 and the third control node N3. The ninth transistor T9, the fourth transistor T4, and the second transistor T2 are turned off, and the fifth transistor T5 is turned on. The first power supply terminal VGH inputs a high-level signal to the fourth control node N4. The seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 are turned on, and the second power supply terminal VGL inputs a low-level signal to the second control node N2 and the signal output terminal OUT.

[0139] This exemplary embodiment also provides another gate driving circuit, which may include multiple Figure 14 As shown in the shift register unit, multiple shift register units can be cascaded. For example, the signal output end OUT of the shift register unit at this level is connected to the signal input end IN of the adjacent next-level shift register unit, and the signal output end OUT of the shift register unit at this level is connected to the reset signal end Re of the adjacent previous-level shift register unit.

[0140] Figure 1 、 2 In the shift register units shown in , 3, and 14, the first input circuit 11 responds to the signal of the signal input terminal IN to transmit the signal of the signal input terminal IN to the first control node, that is, Figure 1 、 2 The shift register units shown in FIG3 and FIG14 all provide input signals to the first control node N1 via the signal input terminal IN. It should be understood that in other exemplary embodiments, the first input circuit 11 may also respond to the signal of the signal input terminal IN and provide input signals to the first control node N1 via other signal terminals. For example, Figure 16 FIG. 1 is a schematic diagram of the structure of the first input circuit in another exemplary embodiment of the shift register unit disclosed herein. The first input circuit 11 can be connected to the first power supply terminal VGH. The first input circuit 11 can be used to respond to the signal of the signal input terminal IN to transmit the signal of the first power supply terminal VGH to the first control node N1. Figure 16 The first input circuit 11 shown can be applied to Figure 1 、 2 , 3, and 14 show the shift register units.

[0141] It should be noted that, in this exemplary embodiment, the first electrode and the second electrode of the transistor may be a source electrode or a drain electrode, and the control electrode may be a gate electrode.

[0142] This exemplary embodiment also provides a display panel, which may include the above-mentioned gate driving circuit and may be applied to display devices such as mobile phones, tablet computers, televisions, and car displays.

[0143] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0144] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A shift register unit, wherein: The shift register unit includes: a first input circuit connected to the first control node and the signal input terminal, wherein the first input circuit is configured to respond to a signal from the signal input terminal to provide an input signal to the first control node; a first coupling circuit connected between the first control node and a second control node, the first coupling circuit being configured to couple a voltage change of the second control node to the first control node; a first control circuit connected to a first clock signal terminal, a first control node, and a second control node, wherein the first control circuit is configured to respond to a signal from the first control node to transmit a signal from the first clock signal terminal to the second control node; an isolation circuit connected to the first control node and the third control node, wherein the isolation circuit is configured to connect the first control node and the third control node in response to a control signal; a first output circuit connected to the second clock signal terminal, the signal output terminal, and a third control node, wherein the first output circuit is configured to respond to a signal of the third control node to transmit the signal of the second clock signal terminal to the signal output terminal; a second coupling circuit, wherein a first end of the second coupling circuit is connected to the third control node, and a second end is connected to the signal output end or the second clock signal end, and the second coupling circuit is used to couple the voltage change of the signal output end or the second clock signal end to the third control node.

2. The shift register unit according to claim 1, wherein: The second coupling circuit includes a second capacitor, and the first coupling circuit includes a first capacitor. The capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

3. The shift register unit according to claim 1, wherein: The isolation circuit is connected to the first clock signal terminal, and is configured to respond to a signal at the first clock signal terminal to connect the first control node and the third control node.

4. The shift register unit according to claim 1, wherein: The first input circuit is configured to respond to the signal input terminal to transmit the signal of the signal input terminal to the first control node, and the first input circuit includes: a first transistor, having a first electrode connected to the signal input terminal, a second electrode connected to the first control node, and a control electrode connected to the signal input terminal; The first coupling circuit includes: a first capacitor connected between the first control node and the second control node; The first control circuit includes: a second transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the second control node, and a control electrode connected to the first control node; The isolation circuit comprises: a third transistor, having a first electrode connected to the first control node, a second electrode connected to the third control node, and a control electrode connected to the first clock signal terminal; The first output circuit includes: a fourth transistor, having a first electrode connected to the second clock signal terminal, a second electrode connected to the signal output terminal, and a control electrode connected to the third control node; The second coupling circuit includes: The second capacitor has a first electrode connected to the third control node and a second electrode connected to the second clock signal terminal or the signal output terminal.

5. The shift register unit according to claim 1, wherein: The shift register unit further includes: a second input circuit connected to the first power supply terminal, the third clock signal terminal, and the fourth control node, wherein the second input circuit is configured to transmit the signal of the first power supply terminal to the fourth control node in response to the signal of the third clock signal terminal; a first reset circuit connected to the second power supply terminal, the first control node, and the reset signal terminal, wherein the first reset circuit is configured to respond to a signal from the reset signal terminal to transmit a signal from the second power supply terminal to the first control node; a second reset circuit connected to the first power supply terminal, the fourth control node, and the reset signal terminal, the second reset circuit being configured to respond to a signal from the reset signal terminal to transmit a signal from the first power supply terminal to the fourth control node; a first pull-down circuit connected to the second power supply terminal, the third clock signal terminal, the fourth control node, the second control node, and the third control node, the first pull-down circuit being configured to respond to signals from the third clock signal terminal and the fourth control node to transmit the signal from the second power supply terminal to the second control node, and to respond to signals from the third clock signal terminal to transmit the signal from the second power supply terminal to the third control node; a second pull-down circuit connected to the third clock signal terminal, the first control node, and the fourth control node, the second pull-down circuit being configured to respond to a signal of the first control node to transmit the signal of the third clock signal terminal to the fourth control node; The second output circuit is connected to the second power supply end, the fourth control node, and the signal output end. The second output circuit is used to respond to the signal of the fourth control node to transmit the signal of the second power supply end to the signal output end. The shift register unit according to claim 5 , wherein: The shift register unit further includes: A third capacitor is connected between the fourth control node and the second power supply terminal.

7. The shift register unit according to claim 5, wherein: The shift register unit further includes: The third pull-down circuit is connected to the second power supply terminal, the third clock signal terminal, and the second control node. The third pull-down circuit is used to respond to the signal of the third clock signal terminal to transmit the signal of the second power supply terminal to the second control node.

8. The shift register unit according to claim 7, wherein: The second input circuit includes: a fifth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the fourth control node, and a control electrode connected to the third clock signal terminal; The first reset circuit includes: a seventh transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the first control node, and a control electrode connected to the reset signal terminal; The second reset circuit includes: an eighth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the fourth control node, and a control electrode connected to the reset signal terminal; The first pull-down circuit comprises: a sixth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the third control node, and a control electrode connected to the third clock signal terminal; a ninth transistor, having a first electrode connected to the second power supply terminal and a control electrode connected to the third clock signal terminal; a tenth transistor, having a first electrode connected to the second electrode of the ninth transistor, a second electrode connected to the second control node, and a control electrode connected to the fourth control node; The second pull-down circuit includes: an eleventh transistor, having a first electrode connected to the third clock signal terminal, a second electrode connected to the fourth control node, and a control electrode connected to the first control node; The second output circuit includes: a twelfth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the signal output terminal, and a control electrode connected to the fourth control node; The third pull-down circuit comprises: A thirteenth transistor has a first electrode connected to the second power supply terminal, a second electrode connected to the second control node, and a control electrode connected to the third clock signal terminal.

9. The shift register unit according to claim 1, wherein: The shift register unit further includes: a second input circuit connected to the first power supply terminal and a fourth control node, wherein the second input circuit is configured to transmit a signal from the first power supply terminal to the fourth control node; a first reset circuit connected to the first control node, the second power supply terminal, and a reset signal terminal, the reset circuit being configured to respond to a signal from the reset signal terminal to transmit a signal from the second power supply terminal to the first control node; a first pull-down circuit connected to the second power supply end, the first control node, the fourth control node, and the second control node, the first pull-down circuit being configured to respond to a signal from the fourth control node to transmit a signal from the second power supply end to the first control node and the second control node; a second pull-down circuit connected to the second power supply terminal, the first control node, and a fourth control node, the second pull-down circuit being configured to respond to a signal from the first control node to transmit a signal from the second power supply terminal to the fourth control node; The second output circuit is connected to the second power supply end, the fourth control node, and the signal output end. The second output circuit is used to respond to the signal of the fourth control node to transmit the signal of the second power supply end to the signal output end.

10. The shift register unit according to claim 9, wherein: The isolation circuit is connected to the third clock signal terminal, and is configured to respond to a signal at the third clock signal terminal to connect the first control node and the third control node.

11. The shift register unit according to claim 10, wherein: The second input circuit includes: a fifth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the fourth control node, and a control electrode connected to the first power supply terminal; The first reset circuit includes: a sixth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the first control node, and a control electrode connected to the reset signal terminal; The first pull-down circuit comprises: a seventh transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the first control node, and a control electrode connected to the fourth control node; an eighth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the second control node, and a control electrode connected to the fourth control node; The second pull-down circuit includes: a ninth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the fourth control node, and a control electrode connected to the first control node; The second output circuit includes: a tenth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the signal output terminal, and a control electrode connected to the fourth control node; The isolation circuit comprises: The third transistor has a first electrode connected to the first node, a second electrode connected to the third node, and a control electrode connected to the third clock signal terminal.

12. A shift register unit driving method, wherein: The driving method is used to drive the shift register unit according to any one of claims 1 to 11, and the driving method includes: In the first stage, the first control node and the third control node are disconnected by the isolation circuit, and the signal from the signal input terminal is transmitted to the first control node by the first input circuit; In the second stage, the signal at the first clock signal terminal is transmitted to the second control node by using the first control circuit, the voltage change of the second control node is coupled to the first control node by using the first coupling circuit, and the first control node and the third control node are connected by using the isolation circuit; In the third stage, the isolation circuit is used to shut down the first control node and the third control node, the second coupling circuit is used to couple the signal change of the second clock signal end or the signal output end to the third node, and the first output circuit is used to transmit the signal of the second clock signal end to the signal output end.

13. A gate drive circuit, wherein: The gate driving circuit includes a plurality of shift register units according to any one of claims 1 to 11, and the plurality of shift register units are cascaded.

14. A display panel, wherein: The display panel includes the gate driving circuit according to claim 13.

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