A data transmission method and device based on a network on chip, and an electronic device

Abstract

Embodiments of the present application provide a data transmission method and device based on a network on chip, electronic equipment and a readable storage medium, comprising: receiving a data packet and determining a target routing node corresponding to the data packet; determining a next hop routing node corresponding to the routing node from a tree topology structure according to a receiving direction of the data packet and a position of the routing node in the tree topology structure; the tree topology structure is a structure of a configuration path connecting each routing node; sending the data packet to the next hop routing node, so that the next hop routing node determines a corresponding next hop routing node until the next hop routing node is the target routing node, and sends the data packet to the target routing node, so that the target routing node configures according to the data packet, improves bandwidth utilization during data transmission, and improves real-time data transmission.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data transmission method, apparatus, electronic device, and readable storage medium based on on-chip network. Background Technology

[0002] As chip integration increases, traditional bus architectures, due to their poor scalability, low bandwidth, and high latency, are gradually being replaced by on-chip networks (BTCs). BTCs achieve efficient communication through message switching mechanisms and have become the standard interconnect solution for multi-core processors. In complex BTC systems, the transmission of configuration information becomes a critical challenge. For example, in scenarios such as artificial intelligence chips and heterogeneous computing, configurations need to be adjusted in real time to adapt to load changes; configuration errors can lead to system malfunctions or performance degradation.

[0003] In existing on-chip networks, the same topology bus structure as the main path is usually used, but due to the extremely low bandwidth utilization of configuration information traffic, bandwidth is wasted; or a serial bus structure is used to transmit configuration information, which has poor real-time performance and low configuration efficiency. Summary of the Invention

[0004] This application provides a data transmission method, apparatus, electronic device, and readable storage medium based on on-chip network, which can improve bandwidth utilization and real-time performance during data transmission.

[0005] In a first aspect, embodiments of this application disclose a data transmission method for an on-chip network, applied to a routing node of an on-chip network, the method comprising:

[0006] Receive data packets and determine the target routing node corresponding to the data packets;

[0007] Based on the receiving direction of the data packet and the position of the routing node in the tree topology, the next-hop routing node corresponding to the routing node is determined from the tree topology; the tree topology is a structure that connects the configured paths of each routing node.

[0008] The data packet is sent to the next-hop routing node so that the next-hop routing node can determine the corresponding next-hop routing node, until the next-hop routing node is the target routing node. The data packet is then sent to the target routing node so that the target routing node can be configured according to the data packet.

[0009] Secondly, embodiments of this application disclose a data transmission device based on a network-on-a-chip (NAT), applied to a routing node in a NAT, the device comprising:

[0010] The receiving module is used to receive data packets and determine the target routing node corresponding to the data packets;

[0011] A node determination module is used to determine the next-hop routing node corresponding to the routing node from the tree topology structure based on the receiving direction of the data packet and the position of the routing node in the tree topology structure; the tree topology structure is a structure of configured paths connecting various routing nodes;

[0012] The sending module is used to send the data packet to the next-hop routing node so that the next-hop routing node can determine the corresponding next-hop routing node until the next-hop routing node is the target routing node, and then send the data packet to the target routing node so that the target routing node can be configured according to the data packet.

[0013] Thirdly, embodiments of this application also provide an electronic device, including a processor; a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the method of the first aspect.

[0014] Fourthly, embodiments of this application also provide a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method of the first aspect.

[0015] The embodiments of this application have the following advantages:

[0016] The configuration paths of each routing node in the on-chip network are designed as a tree topology, where each routing node is a leaf node. Messages transmitted on the configuration path travel from the root node to a leaf node and from a leaf node to the root node. The tree topology only involves necessary routing channels between the root node and some leaf nodes, as well as routing channels between some leaf nodes. Therefore, not all leaf nodes in the tree topology are interconnected, reducing unnecessary routing channels between leaf nodes and lowering chip area overhead. When a routing node receives a data packet, it determines the target routing node and the next-hop routing node based on the packet's reception direction and the routing node's position in the tree topology. For data packets carrying the same configuration information, the packet is broadcast to all routing nodes, reducing the latency of unicasting data packets to multiple routing nodes and improving the real-time performance of data packet transmission. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating the steps of an embodiment of a data transmission method based on an on-chip network according to the present invention.

[0019] Figure 2 This is a schematic diagram of a routing node topology according to the present invention;

[0020] Figure 3 This is a schematic diagram of data transmission based on an on-chip network according to the present invention;

[0021] Figure 4 This is a flowchart illustrating the steps of another embodiment of the data transmission method based on an on-chip network according to the present invention;

[0022] Figure 5 This is a schematic diagram of a process for generating hardware components according to the present invention;

[0023] Figure 6 This is a schematic diagram of the structure of a data packet according to the present invention;

[0024] Figure 7 This is a structural block diagram of a data transmission device based on an on-chip network according to the present invention;

[0025] Figure 8 This is a structural block diagram of an electronic device provided by an example of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, the first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In embodiments of this invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0028] Method Implementation Examples

[0029] Reference Figure 1 The diagram illustrates a flowchart of an embodiment of a data transmission method based on an on-chip network according to the present invention. The method may specifically include the following steps:

[0030] Step 101: Receive the data packet and determine the target routing node corresponding to the data packet;

[0031] Step 102: Based on the receiving direction of the data packet and the position of the routing node in the tree topology, determine the next-hop routing node corresponding to the routing node from the tree topology; the tree topology is a structure of configured paths connecting various routing nodes;

[0032] Step 103: Send the data packet to the next-hop routing node so that the next-hop routing node can determine the corresponding next-hop routing node until the next-hop routing node is the target routing node. Then send the data packet to the target routing node so that the target routing node can be configured according to the data packet.

[0033] Regarding steps 101-103, the data transmission method based on on-chip network provided in this application embodiment can be applied to each routing node in the on-chip network. Large system-on-a-chip (SoC) contains numerous intellectual property (IP) cores. During chip startup or operation, configuration information needs to be distributed to each target IP core via a configuration bus. IP cores can be central processing units (CPUs), graphics processing units (GPUs), memory controllers, peripheral controllers, consistency processing modules, integrated circuit dies (DIE) modules, etc. In this application, the configuration bus connecting the various routing nodes has a tree topology, and the configuration bus is also the configuration path. Only routing nodes are distributed in the tree topology, and configuration information is forwarded and transmitted through the routing nodes in the tree topology. When a routing node receives configuration information, it saves the configuration information for configuration, forwards the configuration information to another routing node, or sends the configuration information to the locally mounted IP core.

[0034] It's important to note that a control module exists on the system-on-a-chip (SoC). This control module acts as the "brain" or "source" of the entire configuration system, serving as the root node of the tree-like topology. The control module generates the configuration information and data packets to be distributed; initiates the configuration transmission process, i.e., sending data packets to directly connected routing nodes or leaf nodes; and receives and processes responses or interrupts from leaf nodes or routing nodes. The control module can be a dedicated hardware state machine, a firmware / software module running on the management processor, or a pre-designed configuration engine.

[0035] The data packets carry configuration information, primarily control commands and configuration data. For example, they may be used to read or write registers of the IP core. Data packets typically contain the following fields: destination address, source address, opcode, storage address, data, transaction identifier, and error check code. The destination address uniquely identifies the target routing node to which the configuration information will be applied; the source address refers to the address of the node initiating the configuration request, i.e., the control module, used to send back a response or interrupt; the opcode specifies the type of configuration operation to be performed, such as read register, write register, reset, start, or set mode; the storage address specifies the address of the specific register or storage location that the target routing node needs to access; the data, for write operations, contains the data to be written; for read operations, it may be empty or contain placeholders; the transaction identifier is used to match requests and responses, especially when read operations or complex transactions are supported; the error check code ensures the integrity of data transmission, such as Cyclic Redundancy Check (CRC) or parity bits.

[0036] A destination routing node is the routing node to which a data packet ultimately needs to be delivered. The destination routing node executes the configuration operations carried in the data packet, or sends it to a locally mounted IP core, where the IP core executes the configuration operations. In a tree topology, the destination routing node is also a leaf node, representing a specific hardware functional unit that needs to be configured. From the perspective of configuring a data packet, when a data packet arrives at this node and is consumed by the node itself instead of being forwarded, this node is the "destination routing node" for that data packet. The data packet is sent to and processed by the destination routing node, not merely flows through it.

[0037] It should be noted that after receiving the data packet, the target routing node uses it for configuration or sends it to its local IP core for configuration. The configuration process involves extracting control commands and configuration data from the data packet and executing the control commands on the registers of the target routing node or the IP core.

[0038] like Figure 2A schematic diagram of a routing node topology is shown, illustrating two paths connecting routing nodes: a main path in a mesh topology and a configuration path in a tree-like topology provided in this application. The tree-like topology has a unique root node, which represents the location of the control module and the source of configuration data; the control module can also be called the control center. All other routing nodes are leaf nodes, connected to the root node. As shown in the diagram, the control center is located at a corner of the mesh topology, such as the lower left, upper left, upper right, or lower right corner. In the example, the control center is located at the lower left corner. Routing nodes on the horizontal axis connect not only to nodes along the horizontal axis but also to routing nodes or other routing nodes on the vertical axis. These vertical routing nodes or other routing nodes only connect to nodes in the vertical direction or those located in the south and north directions. It should be noted that the configuration path in the tree-like topology provided in this application can transmit not only configuration information from the root node to the leaf nodes but also interrupt signals from the leaf nodes to the root node. Since the transmission of configuration information is only sent from the control module located at the root node, and the interrupt signal is only sent according to the characteristics of the control module, the tree topology structure given in this application reduces the routing channels between the routing nodes located at the leaf nodes, thereby reducing chip area overhead or cost.

[0039] Interrupt signals are initiated by routing nodes located at leaf nodes and propagated upstream; data packets carrying configuration information are initiated by root nodes and propagated downstream. Interrupt signals are hardware-triggered asynchronous event notification signals, and the occurrence of interrupts typically includes the following types: error interrupts caused by register write verification failures, threshold interrupts caused by temperature sensor exceeding warning values, and event interrupts caused by external pin level transitions.

[0040] It should be noted that a tree-like topology refers to a dedicated path for transmitting configuration information; it is a background channel within the system used for managing, controlling, and initializing hardware modules. A main path structure refers to the channel through which the system processes user or business data during runtime, such as the CPU-to-memory interconnect or the data forwarding bus of a network chip. Main path structures prioritize high bandwidth, low latency, and communication between any endpoints, often employing more complex topologies and even including dedicated routing protocols.

[0041] like Figure 3This diagram illustrates data transmission based on an on-chip network. When the control center at the root node sends a data packet, it forwards the packet to the directly connected routing nodes. On the horizontal axis, the last routing node needs to determine whether the packet should be sent to its local, eastward, or northward routing node; on the vertical axis, each routing node needs to determine whether to send the packet to its local or northward routing node; the bottom-right routing node needs to determine whether to send the packet to its local or northward routing node; and the remaining routing nodes also need to determine whether to send the packet to their local or northward routing node. When a leaf node sends an interrupt signal to the control center, the routing nodes on the vertical axis need to forward the interrupt signal to the southward routing node, and the routing nodes on the horizontal axis need to forward the interrupt signal to the westward routing node; the remaining routing nodes also need to forward the interrupt signal to the southward routing node. As can be seen from the above, different routing nodes receive data packets or interrupt signals in different directions, have different positions in the tree topology, and therefore have different next-hop routing nodes.

[0042] After receiving the data packet, the next-hop routing node executes steps 101-103 again. This process is repeated hop-by-hop at intermediate routing nodes until the data packet is sent to the target routing node. Once the target routing node receives the data packet, it stops forwarding it, parses the packet, extracts the configuration instructions or data carried in the packet, and executes the configuration instructions. For example, it sets register values.

[0043] In this embodiment, the configuration paths of each routing node in the on-chip network are designed as a tree topology. Each routing node is located as a leaf node in the tree topology. Packets transmitted along the configuration path travel from the root node to a leaf node and vice versa. By reducing unnecessary routing channels between leaf nodes, chip area overhead is reduced. When a routing node receives a data packet, it determines the target routing node corresponding to the data packet. Based on the receiving direction of the data packet and the position of the routing node in the tree topology, it transmits the data packet along the tree topology to the next-hop routing node, improving the real-time performance of data packet transmission.

[0044] Reference Figure 4 The diagram illustrates another data transmission method based on an on-chip network according to the present invention, applied to a routing node of an on-chip network, and specifically includes the following steps:

[0045] Step 201: Receive the data packet and determine the target routing node corresponding to the data packet.

[0046] For details of this step, please refer to step 101 above, which will not be repeated here.

[0047] Step 202: Determine the transmission method of the data packet;

[0048] Step 203: When the transmission method is unicast, determine the routing algorithm based on the position of the routing node in the tree topology and the receiving direction;

[0049] Step 204: According to the routing algorithm, determine the next-hop routing node from the first routing nodes connected in directions other than the receiving direction;

[0050] Step 205: If the transmission mode is broadcast, determine the first routing node as the next-hop routing node.

[0051] Regarding steps 202-205, it should be noted that the packet header carries a transmission mode identifier, for example, a 1-2 bit field. This identifier is set by the control module when generating the packet, explicitly indicating whether the packet's transmission mode is unicast or broadcast. Whether the packet's transmission mode is unicast or broadcast, the meaning of the target node and the next-hop selection logic are completely different.

[0052] The transmission mode identifier is located in the packet header and consists of one bit or a few bits. For example, an identifier of 0 indicates that the packet is transmitted via unicast, and an identifier of 1 indicates that the packet is transmitted via broadcast. In the case of unicast transmission, the packet has a specific, single destination routing node identifier, such as a specific leaf node or branch node address. The routing decision made by the routing node to determine the next-hop routing node strongly depends on this destination identifier. In the case of broadcast transmission, the packet's destination routing nodes are all routing nodes in the tree topology. The packet does not have a specific destination routing node identifier, and the routing decision does not depend on any specific destination node, but only on the network topology and the direction of reception.

[0053] When data packets are transmitted unicastly, the next-hop routing node for the current routing node is a specific neighbor node of that node. The selection of a neighbor node is based on the destination node's location, the packet's own location, the direction of reception, and the routing algorithm, excluding the direction of reception. The path from the root node to the destination routing node is deterministic and point-to-point. When data packets are transmitted broadcastly, the next-hop routing node is any of the other neighbor nodes except those in the direction of reception. The selection is based solely on the direction of reception and the neighbor list, independent of the destination routing node. Many homogeneous IP cores require broadcasting of the same configuration, thus necessitating a register configuration bus capable of performing broadcast functionality to improve the efficiency of configuring multiple IP cores.

[0054] In this context, the first routing node refers to the adjacent routing node directly connected by a physical link in the tree topology. A routing algorithm, in a communication network, refers to the rules or calculation methods used to determine the path of a data packet from its source node to its destination routing node. Each routing node determines only the next-hop routing node, not the complete routing path, based on the routing algorithm. When the data packet transmission method is unicast, the current routing node needs to determine the routing algorithm it will execute based on the direction of the data packet reception and its position in the tree topology. Then, based on the destination address carried in the data packet and the routing algorithm, it determines the next-hop routing node. For example, Figure 2 A routing node topology is illustrated, with the entire topology placed in a coordinate system. The control center is located in the lower left corner, and the routing node directly connected to the control center is the (0,0) node in the tree topology. The (0,0) node uses the XY routing algorithm to determine the next-hop routing node for packets entering from all directions. Routing nodes on the horizontal axis use the XY routing algorithm to determine the next-hop routing node when receiving packets from the west, and use the YX routing algorithm to determine the next-hop routing node for all packets entering from other directions. Routing nodes on the vertical axis use the YX routing algorithm for packets entering from all directions; the remaining routing nodes use the YX routing algorithm for packets entering from all directions. Packets can be data packets sent by the control center, interrupt signals generated by leaf nodes, or responses generated in response to data packets.

[0055] It should be noted that, Figure 2 This only shows one type of routing node topology. The control center can be located not only in the lower left corner, but also in the upper left corner, upper right corner, and lower right corner. The coordinate system will change accordingly. However, the routing nodes are still divided into three categories: routing nodes on the horizontal axis, routing nodes on the vertical axis, and other routing nodes. Each routing node still selects a routing algorithm from the XY routing algorithm and the YX routing algorithm based on its position in the tree topology and the direction of data packet reception.

[0056] It should be noted that routing nodes in a tree-like topology incur corresponding hardware overhead depending on the routing algorithm used. For example... Figure 5 The diagram illustrates how different hardware components are generated by the Generate module based on the routing node coordinates and the input direction. Specifically, based on the routing node coordinates and the input direction of the data packet, one of the hardware components implementing the XY routing algorithm and the hardware component implementing the YX routing algorithm is selected. No other hardware components are needed or involved, and no redundant resource overhead is introduced.

[0057] It's important to note that determining the next-hop routing node in directions other than the receiving direction is primarily aimed at preventing loops and duplicate reception. In unicast transmission, this prevents data packets from being sent back to the upstream node that sent them, thus avoiding ping-pong or loops. In broadcast transmission, by excluding the receiving direction, it ensures that broadcast packets do not return to the upstream node that sent them, preventing broadcast packets from looping infinitely through the network.

[0058] Optionally, sending the data packet to the next-hop routing node may specifically include:

[0059] Step S11: If the transmission mode is broadcast, the data packet is copied according to the number of next-hop routing nodes;

[0060] Step S12: Send the copied data packets to the next-hop routing nodes respectively.

[0061] For steps S11 and S12, when the data packet is transmitted in broadcast mode, a list of next-hop routing nodes containing N neighboring nodes to be forwarded has been determined.

[0062] Since the upstream route only sends one data packet to the current routing node, when the current routing node has at least two next-hop routing nodes, the current routing node needs to copy the data packet. The number of copies is equal to the number of next-hop nodes. For example, if the current routing node is a routing node on the horizontal axis with two next-hop routing nodes, namely routing nodes S1 and S2 in the east and north directions respectively, then two copies of the data packet are copied. N copies of the data packet are generated that are completely identical to the original received packet. The hardware implementation is a dedicated copying circuit. The copying logic is designed in the router hardware, such as using a state machine and buffer management, or a shared buffer and multiple pointers approach. The shared buffer and multiple pointers approach directly generates multiple copies. The shared buffer and multiple pointers approach involves storing the original packet in shared memory, creating N virtual copies pointing to the same data, and reading them as needed during physical transmission.

[0063] It should be noted that when sending N data packets, N data packets can be sent to the corresponding N next-hop routing nodes simultaneously.

[0064] For example, a routing node can set a request flag for each transmission direction, setting it to 1 before the data packet is completely sent in that direction and setting it to 0 after the data packet is completely sent in that direction. For example, in Figure 2In the topology shown, when node (0,0) receives a multicast data packet from the control center, it can set the request flag for all transmittable directions to 1. [1 (local), 0 (south), 1 (north), 0 (west), 1 (east)]; when a node on the horizontal axis receives a multicast data packet from the west, it sends data packets to the local, north, and east directions, setting the request flag for that direction to 0 after each direction is output. After a data packet has been sent from all transmittable directions, the next data packet is passed on.

[0065] Step 206: Divide the data packet into at least two first flow control units according to the bandwidth of the configured path;

[0066] Step 207: Send the at least two first flow control units sequentially to the next-hop routing node.

[0067] Regarding steps 206 and 207, this application embodiment provides a core fragmentation mechanism for transmitting data packets in a low-bandwidth configuration path, based on flow control transmission using a first flow control unit (Flit). The configuration path bandwidth refers to the single-cycle transmission bit width supported by the physical link, such as 4-bit or 8-bit. The original data packet is the complete configuration packet to be sent, which may be as long as 32-bit, 64-bit, or even longer. It should be noted that the number of bits in a Flit is less than or equal to the bandwidth of the physical link, and the bandwidth of the physical link is usually an integer multiple of the Flit. For example, if the single-cycle transmission bit width supported by the physical link is 8 bits, the number of bits in a Flit can be 8 bits or 4 bits.

[0068] The number of first flow control units is obtained by dividing the number of bits in the data packet by the number of bits in the first flow control unit. The size of the data packet is determined by the operation performed by the system and the size of the data. For example, when the number of flit bits is 24 bits, a read operation needs to carry the address in the data packet, which only requires 48 bits and 2 flits; a write operation needs both address and data, which requires 114 bits, so more flits are needed.

[0069] When a data packet is divided into at least two first flow control units, the complete data packet is sent to the next-hop routing node by sending at least two first flow control units to the next-hop routing unit.

[0070] It should be noted that when determining the first flow control unit, it is necessary not only to consider the physical bandwidth of the configured path, but also to align with the software data and ensure compatibility with the CPU word length. After a data packet is divided into at least two first flow control units, at least two first flow control units should be able to be reassembled into a complete CPU word length. For example, to ensure compatibility with 32-bit software, an 8-bit first flow control unit is used, and every 4 flits can form a complete 32-bit word.

[0071] Optionally, step 207 may specifically include:

[0072] Step S21: For each first flow control unit, after the first flow control unit is sent to the next-hop routing node, the first flow control unit is deleted from the input buffer of the routing node;

[0073] Step S22: Read the next first flow control unit from the input buffer and send the next first flow control unit to the next hop routing node until all first flow control units have been sent to the next hop routing node.

[0074] Regarding steps S21 and S22, this application embodiment provides a core mechanism for flow control unit-level buffer management to ensure reliable transmission and efficient resource utilization of data packets in the bandwidth configuration path. The buffer is released immediately after a Flit is sent, ensuring that the current routing node has successfully sent a Flit to the physical link of the next-hop routing node, preventing previously sent data from lingering and occupying valuable buffer space, and ensuring that newly arriving Flits can immediately use free buffer slots. It should be noted that zero-idle transmission can be achieved in this application embodiment; the next Flit is started immediately after the current Flit is sent, and the physical layer sending circuit and buffer reading circuit operate in parallel on the hardware side.

[0075] It should be noted that when the transmission method is broadcast, if the current routing node has at least two next-hop routing nodes, the first flow control unit can be sent to at least two next-hop routing nodes simultaneously. A single router cycle can arbitrate packets in all directions simultaneously. Only after all transmittable directions of the first FLIT have output the packet will the router's input buffer eject the FLIT and transmit the remaining FLIT packets of the data packet. Transmittable directions refer to directions pointing to the next-hop routing node.

[0076] Optionally, the first flow control unit carries a first identifier, which is used to indicate whether there is a first flow control unit with the same data packet after the first flow control unit; step S22 may specifically include:

[0077] Step S31: When the first identifier is 1, read the next first flow control unit from the input buffer and send the next first flow control unit to the next hop routing node;

[0078] Step S32: When the first identifier is 0, determine that all first flow control units corresponding to the data packet are sent to the next-hop routing node, and read the first flow control unit corresponding to the next data packet from the input buffer.

[0079] Regarding steps S31 and S32, embodiments of this application provide a flow control unit continuity identification mechanism for implementing control logic to ensure uninterrupted transmission of multi-Flit data packets. Specifically, as shown... Figure 6 The diagram illustrates a data packet structure where each packet is divided into at least two first flow control units. Each fragment includes a first identifier in the header and the original data content. The first identifier is either 1 or 0; only the last flow control unit in the packet has a first identifier of 0, while the remaining first flow control units have a first identifier of 1. The original data content is obtained by fragmenting the data packet, and the data consists of combinations of bits. A 1-bit flag is reserved in the header of each fragment. A flag of 1 indicates that a subsequent fragment of the same data packet exists; a flag of 0 indicates that this fragment is the last unit of the data packet. The first identifier is set in the header of each fragment before the control module sends the data packet, when the packet is sliced ​​into at least two fragments. This identifier guides each routing point on when to switch data packets, preventing errors or anomalies caused by fragments within the same data packet being interrupted.

[0080] In this embodiment, each fragment is simultaneously sent to each next-hop routing node. After a fragment is output from each transmittable direction, it is removed from the input buffer. If a fragment of the same data packet exists after the first identifier of the fragment, the next fragment is read from the input buffer. If no fragment of the same data packet exists after the first identifier of the fragment, it means that the data packet has been transmitted completely, and the fragment of the next data packet can be read.

[0081] Optionally, the method further includes:

[0082] Step S41: Receive the response returned by the next-hop routing node;

[0083] Step S42: If there are at least two responses, arbitrate the at least two responses to determine the priority of each response.

[0084] Step S43: According to the priority, each response is sent to the upstream routing node in sequence; the upstream routing node is the routing node that sends data packets to the routing node.

[0085] Regarding steps S41-S43, it should be noted that the configuration path of the tree topology can transmit not only data packets sent from the root node to the leaf nodes, but also responses sent from the leaf nodes to the root node. A response refers to the feedback signal from the leaf node to the data packet sent by the root node, and can generally be divided into the following three categories: when the root node requests register reads, the leaf node returns the read data; after configuration based on the data packet is completed, the leaf node returns a status confirmation response to the root node; when the root node verifies the hardware, in the event of verification failure or hardware malfunction, the leaf node sends an error report to the root node.

[0086] like Figure 2 The illustrated routing node topology shows that a node on the horizontal axis may receive responses from multiple directions, such as north, east, and local. When multiple responses are received, they need to compete for a single uplink channel. Therefore, arbitration is performed to determine the transmission order of the responses, and each response is transmitted sequentially according to the transmission order to avoid collisions and congestion.

[0087] The core of arbitration is to resolve contention between multiple input sources and a single output channel. Specifically, different weights can be assigned to different types of responses; for example, interrupt signals have a weight of 3, error responses have a weight of 2, and data responses have a weight of 1. Dynamic adjustment factors, such as waiting time factors and leaf node criticality, can also be introduced. When the waiting time factor exceeds the latency threshold, the priority is automatically increased, with core modules or core IP cores receiving higher weights.

[0088] For example, such as Figure 2 The topology of the routing nodes shown and as follows Figure 3The diagram shown illustrates data transmission based on on-chip network. The control center sends data packets to directly connected routing nodes. When the data packet transmission method is unicast, the target routing node of the data packet is the (1,2) routing node. The directly connected (0,0) routing node is the routing node on the horizontal axis, and the data packet is received in the west direction. Therefore, the routing algorithm is the XY routing algorithm, which determines the next hop routing node as the (1,0) routing node. The (0,0) routing node then sends the data packet to the (1,0) routing node. The (1,0) routing node is also a routing node on the horizontal axis, and the direction of data packet reception is also westward. The routing algorithm is the XY routing algorithm, and there is no deviation between the X coordinate and the target routing node. Therefore, the next hop routing node is determined to be the (1,1) routing node, and the (1,0) routing node sends the data packet to the (1,1) routing node. The (1,1) routing node is not a routing node on either the horizontal or vertical axis. Regardless of the direction of data packet reception, the routing algorithm is the YX routing algorithm, and the next hop routing node is determined to be the (1,2) routing node. The (1,1) routing node sends the data packet to the (1,2) routing node. After receiving the data packet, the (1,2) routing node determines that it is the target routing node based on the destination address carried in the data packet, configures itself according to the data packet, and returns a response, which carries the address of the control center. If the (1,2) routing node is not a routing node on the horizontal or vertical axis, the routing algorithm is determined to be the YX routing algorithm, and the next-hop routing node is determined to be the (1,1) routing node. The response is sent to the (1,1) routing node. After receiving the response, if the (1,1) routing node is not a routing node on the horizontal or vertical axis, the routing algorithm is determined to be the YX routing algorithm, and the next-hop routing node is determined to be the (1,0) routing node, the response is sent to the (1,0) routing node. If the (1,0) routing node is a routing node on the horizontal axis, the direction of receiving the response is north, the routing algorithm is determined to be the YX routing algorithm, the Y-axis coordinates are without deviation, the next-hop routing node is determined to be the (0,0) routing node, and the response is sent to the (0,0) routing node. The (0,0) routing node then sends the response to the control center. After receiving the response, the control center determines that the configuration is complete.

[0089] The control center sends data packets to directly connected routing nodes. If the data packet transmission method is broadcast, the (0,0) routing node needs to send data packets to the north, east, and local directions in addition to the receiving direction. Therefore, the (0,0) routing node needs to copy the data packet twice, sending it to the north, east, and local directions respectively. Other routing nodes follow the same logic as the (0,0) routing node, copying the data packet based on the number of adjacent routing nodes in directions other than the receiving direction, and then sending the copied data packet to the next-hop routing node. Each routing node, upon receiving the data packet, configures itself according to the data packet and generates a response. Each routing node generates a response and returns it to the control center along the tree-like topology. For example, the (1,0) routing node will receive responses from the north, east, and local directions. However, the (1,0) routing node only has one uplink channel to send the response to the (0,0) routing node. Therefore, it is necessary to arbitrate the responses from the three directions to determine the sending order of the three responses. Each response is sent to the (0,0) routing node in turn. The (0,0) routing node then sends each response to the control center according to the same execution logic. The control center sets a counter. The counter is 0 when a data packet is sent. When a response is received, the counter is incremented by one until the value of the counter is the same as the number of routing nodes in the tree topology, at which point the configuration is considered complete.

[0090] Optionally, step S43 may specifically include:

[0091] Step S51: Based on the bandwidth of the configured path, divide each response into at least two second flow control units;

[0092] Step S52: For each response, send all the second flow control units of the response to the upstream routing node in sequence;

[0093] Step S53: Determine the next response according to the priority, and send all the second flow control units corresponding to the next response to the upstream routing node until all responses are sent to the upstream routing node.

[0094] Similar to the data packet transmission, steps S51-S53 in this application embodiment provide a core fragmentation mechanism for transmitting responses in a low-bandwidth configuration path, based on flow control transmission using second flow control units (Flit). The configuration path bandwidth refers to the single-cycle transmission bit width supported by the physical link, such as 4-bit or 8-bit. The original response may be as long as 32-bit or 64-bit or even longer, while the number of bits in a Flit is less than or equal to the bandwidth of the physical link, and the bandwidth of the physical link is usually an integer multiple of the Flit. For example, if the single-cycle transmission bit width supported by the physical link is 8 bits, the number of bits in a Flit can be 8 bits or 4 bits. Each response can also be divided into at least two second flow control units for transmission. The header of each second flow control unit also carries a second identifier, which is used to indicate whether there are subsequent second flow control units with data from the same response.

[0095] When a data packet acquires arbitration priority on the uplink channel, the route uses a second identifier to determine whether there are other flow control units (Flow Control Units) with the same response following the current Flow Control Unit. A second identifier of 1 indicates that there are other Flow Control Units with the same response following the current Flow Control Unit, while a second identifier of 0 indicates that there are no other Flow Control Units with the same response following the current Flow Control Unit. If there are other Flow Control Unit packets with the same response following the current Flow Control Unit, the arbitration priority on the uplink channel is exclusively held by the input port corresponding to that response. For example, for a routing node, if an eastbound response acquires arbitration priority on the northbound output port, then until the entire eastbound response is sent (i.e., before the second identifier of the Flow Control Unit is 0), other input ports cannot acquire arbitration priority for that output direction, and responses from other input ports cannot be output.

[0096] In summary, the data transmission method based on on-chip network provided in this application embodiment can design the configuration path of each routing node in the on-chip network as a tree topology. Each routing node is located as a leaf node in the tree topology. Messages transmitted on the configuration path travel from the root node to the leaf node and from the leaf node to the root node. By reducing unnecessary routing channels between leaf nodes, chip area overhead is reduced, decreasing the channel area of ​​the configuration path by more than 30%. Furthermore, data packets, responses, interrupts, and other messages can be efficiently transmitted from the control center to each IP core, or from each IP core to the control center, using a multi-flit method. Since the number of bits in a flit is lower than that of a data packet, the channel width can be reduced, further saving channel area, improving the bandwidth utilization of the configuration path, and enhancing the real-time performance of data transmission. In addition, the broadcast configuration method can reduce the latency of multiple IP cores performing the same configuration by more than 80%. As the scale of the on-chip network further expands, the gains brought by this broadcast configuration method will further increase. Furthermore, during chip startup, various modules need to be configured. It has high bandwidth utilization efficiency and supports broadcast configuration, which can effectively reduce the startup time of the entire chip system.

[0097] Reference Figure 7 The diagram illustrates a structural block diagram of a data transmission device based on an on-chip network according to the present invention, which is applied to a routing node in an on-chip network and may specifically include the following modules:

[0098] The receiving module 310 is used to receive data packets and determine the target routing node corresponding to the data packets;

[0099] The node determination module 320 is used to determine the next-hop routing node corresponding to the routing node from the tree topology structure based on the receiving direction of the data packet and the position of the routing node in the tree topology structure; the tree topology structure is a structure of configured paths connecting various routing nodes;

[0100] The sending module 330 is used to send the data packet to the next-hop routing node so that the next-hop routing node can determine the corresponding next-hop routing node until the next-hop routing node is the target routing node, and then send the data packet to the target routing node so that the target routing node can be configured according to the data packet.

[0101] Optionally, the node determination module includes:

[0102] The mode determination module is used to determine the transmission mode of the data packet;

[0103] The algorithm determination module is used to determine the routing algorithm based on the position of the routing node in the tree topology and the receiving direction when the transmission mode is unicast.

[0104] The first determining submodule is used to determine the next-hop routing node from the first routing nodes connected in directions other than the receiving direction, according to the routing algorithm.

[0105] The second determining submodule is used to determine the first routing node as the next-hop routing node when the transmission mode is broadcast.

[0106] Optionally, the sending module includes:

[0107] The replication module is used to replicate the data packets according to the number of next-hop routing nodes when the transmission mode is broadcast.

[0108] The first sending submodule is used to send the copied data packets to the next-hop routing nodes respectively.

[0109] Optionally, the sending module includes:

[0110] The first partitioning module is used to partition the data packet into at least two first flow control units according to the bandwidth of the configured path;

[0111] The second sending submodule is used to send the at least two first flow control units sequentially to the next-hop routing node.

[0112] Optionally, the second transmitting submodule includes:

[0113] The deletion module is used to delete each first flow control unit from the input buffer of the routing node after the first flow control unit is sent to the next-hop routing node;

[0114] The reading module is used to read the next first flow control unit from the input buffer and send the next first flow control unit to the next hop routing node, until all first flow control units have been sent to the next hop routing node.

[0115] Optionally, the reading module includes:

[0116] The first reading submodule is configured to read the next first flow control unit from the input buffer when the first identifier is 1, and send the next first flow control unit to the next hop routing node;

[0117] The second reading submodule is used to determine, when the first identifier is 0, that all first flow control units corresponding to the data packet have been sent to the next-hop routing node, and to read the first flow control unit corresponding to the next data packet from the input buffer.

[0118] Optionally, the device further includes:

[0119] A response receiving module is used to receive the response returned by the next-hop routing node;

[0120] The arbitration module is used to arbitrate at least two responses when the number of responses is at least two, and to determine the priority of each response.

[0121] The response sending module is used to send each response sequentially to the upstream routing node according to the priority; the upstream routing node is the routing node that sends data packets to the routing node.

[0122] Optionally, the response sending module includes:

[0123] The second partitioning module is used to partition each response into at least two second flow control units according to the bandwidth of the configured path;

[0124] The first response sending submodule is used to send all the second flow control units of each response to the upstream routing node in sequence;

[0125] The second response sending submodule is used to determine the next response according to the priority, and send all the second flow control units corresponding to the next response to the upstream routing node, until all responses are sent to the upstream routing node.

[0126] In summary, the data transmission device based on an on-chip network provided in this application embodiment can design the configuration path of each routing node in the on-chip network as a tree topology. Each routing node is located as a leaf node in the tree topology. Messages transmitted on the configuration path travel from the root node to the leaf node and from the leaf node to the root node. By reducing unnecessary routing channels between leaf nodes, chip area overhead is reduced, decreasing the channel area of ​​the configuration path by more than 30%. Furthermore, data packets, responses, interrupts, and other messages can be efficiently transmitted from the control center to each IP core, or from each IP core to the control center, using a multi-flit method. Since the number of bits in a flit is lower than that of a data packet, the channel width can be reduced, further saving channel area, improving the bandwidth utilization of the configuration path, and enhancing the real-time performance of data transmission. In addition, the broadcast configuration method can reduce the latency of multiple IP cores performing the same configuration by more than 80%. As the scale of the on-chip network further expands, the gains brought by this broadcast configuration method will further increase. Furthermore, during chip startup, various modules need to be configured. It has high bandwidth utilization efficiency and supports broadcast configuration, which can effectively reduce the startup time of the entire chip system.

[0127] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0128] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0129] Regarding the processor in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be elaborated here.

[0130] Reference Figure 8 This is a structural block diagram of an electronic device for data transmission based on an on-chip network, provided in an embodiment of the present invention. Figure 8 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store executable instructions, which cause the processor to execute the data transmission method based on the on-chip network of the aforementioned embodiment.

[0131] The processor can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0132] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 The symbol is represented by only one line, but this does not mean that there is only one bus or one type of bus.

[0133] The memory may be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it may be EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory), magnetic tape, floppy disk, and optical data storage devices, etc.

[0134] This invention also provides a non-transitory computer-readable storage medium that, when instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to perform... Figure 1 The data transmission method based on on-chip network is shown.

[0135] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0136] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0137] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0138] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0139] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0140] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0141] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0142] The present invention has provided a detailed description of a data transmission method, apparatus, electronic device, and readable storage medium based on on-chip network. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A data transmission method based on a network on chip, characterized in that, A method applied to a routing node in a network-on-chip, the method comprising: receiving a data packet and determining a target routing node corresponding to the data packet; determining a next-hop routing node corresponding to the routing node from a tree topology according to a receiving direction of the data packet and a position of the routing node in the tree topology; the tree topology is a structure of configuration channels connecting various routing nodes; the various routing nodes are leaf nodes in the tree topology, and a control module is a root node of the tree topology; the control module is configured to generate the data packet; sending the data packet to the next-hop routing node, so that the next-hop routing node determines a corresponding next-hop routing node until the next-hop routing node is the target routing node, and the data packet is sent to the target routing node, so that the target routing node performs configuration according to the data packet; the determining of the next-hop routing node from the tree topology according to the receiving direction of the data packet and the position of the routing node in the tree topology comprises: determining a transmission mode of the data packet; in a case where the transmission mode is a unicast mode, selecting a routing algorithm currently to be executed by the routing node from preset routing algorithms according to the position of the routing node in the tree topology and the receiving direction; the preset routing algorithms comprise XY routing algorithms and YX routing algorithms; determining the next-hop routing node from a first routing node connected in a direction other than the receiving direction according to the routing algorithm.

2. The method of claim 1, wherein, the determining of the next-hop routing node from the tree topology according to the receiving direction of the data packet and the position of the routing node in the tree topology comprises: in a case where the transmission mode is a broadcast mode, determining the first routing node as the next-hop routing node.

3. The method of claim 2, wherein, the sending of the data packet to the next-hop routing node comprises: in the case where the transmission mode is the broadcast mode, copying the data packet according to a quantity of the next-hop routing nodes; sending the copied data packets to the next-hop routing nodes respectively.

4. The method of claim 1, wherein, the sending of the data packet to the next-hop routing node comprises: dividing the data packet into at least two first flow control units according to a bandwidth of the configuration channel; sending the at least two first flow control units to the next-hop routing node in sequence.

5. The method of claim 4, wherein, the sending of the at least two first flow control units to the next-hop routing node in sequence comprises: for each first flow control unit, deleting the first flow control unit from an input buffer of the routing node after the first flow control unit is sent to the next-hop routing node; reading a next first flow control unit from the input buffer and sending the next first flow control unit to the next-hop routing node until all the first flow control units are sent to the next-hop routing node.

6. The method of claim 5, wherein, The first flow control unit carries a first identifier, and the first identifier is used to indicate whether there is a first flow control unit of the same data packet after the first flow control unit; The reading of the next first flow control unit from the input buffer comprises: In the case that the first identifier is 1, the next first flow control unit is read from the input buffer, and the next first flow control unit is sent to the next hop routing node; In the case that the first identifier is 0, it is determined that all first flow control units corresponding to the data packet are sent to the next hop routing node, and the first flow control unit corresponding to the next data packet is read from the input buffer.

7. The method of claim 1, wherein, The method further comprises: receiving responses returned by the next hop routing node; In the case that the number of responses is at least two, the at least two responses are arbitrated to determine the priority of each response respectively; According to the priority, each response is sent to an upstream routing node in turn; the upstream routing node is a routing node that sends a data packet to the routing node.

8. The method of claim 7, wherein, According to the priority, each response is sent to an upstream routing node in turn, comprising: According to the bandwidth of the configuration channel, each response is divided into at least two second flow control units respectively; For each response, all second flow control units of the response are sent to the upstream routing node in turn; According to the priority, the next response is determined, and all second flow control units corresponding to the next response are sent to the upstream routing node until all responses are sent to the upstream routing node.

9. A data transfer apparatus based on a network-on-chip, characterized by, A routing node applied to a network on chip, the device comprises: A receiving module is configured to receive a data packet and determine a target routing node corresponding to the data packet; A node determining module is configured to determine a next hop routing node corresponding to the routing node from a tree topology according to a receiving direction of the data packet and a position of the routing node in the tree topology; the tree topology is a structure of a configuration channel connecting each routing node; each routing node is a leaf node in the tree topology, and a control module is a root node of the tree topology; the control module is configured to generate the data packet; A sending module is configured to send the data packet to the next hop routing node, so that the next hop routing node determines a corresponding next hop routing node until the next hop routing node is the target routing node, and the data packet is sent to the target routing node so that the target routing node configures according to the data packet; The node determining module is specifically configured to: determine a transmission mode of the data packet; In the case that the transmission mode is a unicast mode, a routing algorithm currently to be executed by the routing node is selected from a preset routing algorithm according to the position of the routing node in the tree topology and the receiving direction; the preset routing algorithm comprises an XY routing algorithm and a YX routing algorithm; The next hop routing node is determined from a first routing node connected in a direction other than the receiving direction according to the routing algorithm.

10. An electronic device, comprising: comprise: a processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method of any one of claims 1-8.

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