Display device and manufacturing method thereof

Abstract

A TFT layer (20a) on a base substrate (10) has a polycrystalline silicon semiconductor layer (12) formed of a polycrystalline silicon film, first TFTs (9aa) electrically connected to each other via source lines (18f) in conductor regions (12b, 12c) of the polycrystalline silicon semiconductor layer (12) are provided corresponding to a plurality of sub-pixels (P) constituting a display region (D), and a transmissive back gate layer (BGa) formed of an oxide semiconductor film is provided below the TFT layer (20a). The back gate layer (BGa) has a conductor portion (BGac) in which at least a portion of the oxide semiconductor film is made into a conductor, and the conductor portion (BGac) overlaps at least the channel region (12a) in plan view and is electrically connected to the source line (18f).

Description

Technical Field

[0001] The present invention relates to a display device and a method for manufacturing the same. Background Art

[0002] In recent years, self-luminous organic EL display devices using organic electroluminescence (hereinafter referred to as "EL") elements have attracted much attention as an alternative to liquid crystal display devices. Among organic EL display devices, for example, a flexible organic EL display device has been proposed. This device includes a TFT layer on a flexible resin substrate serving as a base substrate. This TFT layer includes multiple thin-film transistors (hereinafter referred to as "TFTs") for driving the organic EL elements in each sub-pixel constituting the display area. Semiconductor layers constituting TFTs include, for example, polycrystalline semiconductor layers composed of high-mobility polycrystalline silicon and oxide semiconductor layers composed of oxide semiconductors such as In-Ga-Zn-O, which have low leakage current.

[0003] In flexible organic EL display devices, TFTs comprising a polysilicon semiconductor layer (hereinafter referred to as "polysilicon TFTs"), particularly those with a top-gate structure in which a gate electrode is formed above the polysilicon semiconductor layer, sometimes experience unstable threshold (Vth) characteristics due to polarization of the resin substrate. To stabilize the threshold of polysilicon TFTs, it is known to form a metal film, for example, beneath the polysilicon TFT via an inorganic film, and use this metal film as a back gate. For example, in the display device described in Patent Document 1, an additional film is disposed beneath the polysilicon TFT (switching element) to suppress characteristic variations caused by light intrusion from the back of the channel or to impart a back-gate effect.

[0004] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application Laid-Open No. 2020-27862 Summary of the Invention Problems to be solved by the invention However, in a flexible organic EL display device, when a fingerprint sensor, camera, etc. are configured under its panel, a high panel aperture ratio (transmittance) is required. However, in order to suppress the characteristic changes caused by the metal film, the additional film with light-shielding properties described in Patent Document 1 causes the panel transmittance to decrease due to these films, and therefore is not suitable as a material for forming the back gate.

[0005] The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to achieve both stabilization of the threshold value of a TFT including a polycrystalline silicon semiconductor layer provided on a base substrate, particularly a resin substrate, and maintenance of the panel transmittance.

[0006] Solutions to the Problem In order to achieve the above-mentioned purpose, the display device involved in the present invention comprises a base substrate and a thin film transistor layer arranged on the base substrate, in which a plurality of thin film transistors are arranged corresponding to a plurality of sub-pixels constituting a display area, and the plurality of thin film transistors have a polycrystalline silicon semiconductor layer, which is formed by a polycrystalline silicon film and defines a channel region and a conductor region, and the plurality of thin film transistors are electrically connected to each other via signal wiring in the conductor region, and a back gate layer formed by an oxide semiconductor film and having transparency is arranged under the thin film transistor layer, and the back gate layer has a conductive portion, which is formed by conductively converting at least a portion of the oxide semiconductor film, and the conductive portion overlaps with at least the channel region when viewed from above and is electrically connected to the signal wiring.

[0007] A method for manufacturing a display device according to an embodiment of the present invention includes: providing a base substrate and a thin film transistor layer provided on the base substrate; in the thin film transistor layer, a plurality of thin film transistors are provided corresponding to a plurality of sub-pixels constituting a display area; the plurality of thin film transistors have a polycrystalline silicon semiconductor layer, the polycrystalline silicon semiconductor layer is formed of a polycrystalline silicon film and defines a channel region and a conductor region; the plurality of thin film transistors are electrically connected to each other via signal wiring in the conductor region; a back gate layer is provided below the thin film transistor layer and is formed of an oxide semiconductor film and has translucency; the back gate layer has a conductive portion, the conductive portion is formed by the At least a portion of the oxide semiconductor film is conductive, and the thin film transistor layer forming process for forming the thin film transistor layer includes: a first primer film forming process, forming a first primer film on the base substrate; a back gate layer forming process, after the oxide semiconductor film is formed on the surface of the substrate with the first primer film formed, the oxide semiconductor film is patterned to form the back gate layer; a second primer film forming process, forming a second primer film on the surface of the substrate with the back gate layer formed; a polycrystalline silicon semiconductor layer forming process, after the polycrystalline silicon film is formed on the surface of the substrate with the second primer film formed, the polycrystalline silicon film is patterned to form the polycrystalline silicon semiconductor layer; a gate insulating film A gate film forming step is performed to form a gate insulating film on the surface of the substrate on which the polycrystalline silicon semiconductor layer is formed in a manner covering the polycrystalline silicon semiconductor layer; a gate electrode forming step is performed to form a lower metal film on the surface of the substrate on which the gate insulating film is formed, and then the lower metal film is patterned to form a plurality of gate electrodes; a doping step is performed to perform doping using the gate electrodes as masks to form the channel region and the conductor region of the polycrystalline silicon semiconductor layer; an interlayer insulating film forming step is performed to form at least one interlayer insulating film on the surface of the substrate on which the plurality of gate electrodes are formed; a contact hole forming step is performed to form contact holes on the surface of the substrate on which the at least one interlayer insulating film is formed, wherein the contact holes Exposing at least a portion of the conductor region in the polysilicon semiconductor layer and the conductorized portion in the back gate layer; and a signal wiring forming step, after forming an upper metal film on the surface of the substrate where the contact hole is formed, patterning the upper metal film to form the signal wiring, the signal wiring covering the exposed surface of the conductorized portion exposed in the contact hole, in the second primer film forming step, by heat treatment after the second primer film is formed, the region of the back gate layer that at least overlaps with the channel region when viewed from above is conductorized to form the conductorized portion; in the signal wiring forming step, the conductorized portion is electrically connected to the signal wiring.

[0008] Effects of the Invention According to the present invention, it is possible to achieve both stabilization of the threshold value of a TFT including a polycrystalline silicon semiconductor layer provided on a base substrate, particularly a resin substrate, and maintenance of the panel transmittance. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a plan view schematically showing the configuration of an organic EL display device according to the first embodiment of the present invention.

[0010] Figure 2 It is a plan view of a display area of ​​the organic EL display device according to the first embodiment of the present invention.

[0011] Figure 3 This is an equivalent circuit diagram showing a pixel circuit of the organic EL display device according to the first embodiment of the present invention.

[0012] Figure 4 It is a schematic plan view schematically showing the arrangement of pixel circuits of the organic EL display device according to the first embodiment of the present invention.

[0013] Figure 5 FIG. 1 is a diagram showing the first TFT constituting the pixel circuit of the organic EL display device according to the first embodiment of the present invention. Figure 4 The enlarged top view within the double-dotted line in FIG.

[0014] Figure 6 This is a diagram showing a modification of the first TFT constituting the pixel circuit of the organic EL display device according to the first embodiment of the present invention. Figure 4 The enlarged plan view in the double-dotted line is the same as Figure 5 The corresponding figure.

[0015] Figure 7 This is a diagram showing a modification of the first TFT constituting the pixel circuit of the organic EL display device according to the first embodiment of the present invention. Figure 4 The enlarged plan view in the double-dotted line is the same as Figure 5 The corresponding figure.

[0016] Figure 8 It is a cross-sectional view of a display area and a frame area of ​​an organic EL display device according to the first embodiment of the present invention.

[0017] Figure 9 It is a cross-sectional view showing an organic EL layer constituting the organic EL display device according to the first embodiment of the present invention.

[0018] Figure 10 is a cross-sectional view of a display region and a frame region of an organic EL display device according to a second embodiment of the present invention, and is similar to Figure 8The corresponding figure.

[0019] Figure 11 is a cross-sectional view of a display region and a frame region of an organic EL display device according to a third embodiment of the present invention, and is equivalent to Figure 8 Picture.

[0020] Figure 12 is a plan view schematically showing the arrangement of pixel circuits of an organic EL display device according to a fourth embodiment of the present invention, and is Figure 4 The corresponding figure.

[0021] Figure 13 FIG. 1 is a diagram showing the first TFT constituting the pixel circuit of the organic EL display device according to the fourth embodiment of the present invention. Figure 12 The enlarged top view within the double-dotted line in FIG.

[0022] Figure 14 The organic EL display device according to the fourth embodiment of the present invention is Figure 13 A cross-sectional view of the display area along line XIV-XIV in FIG.

[0023] Figure 15 FIG. 1 is a diagram showing a first TFT constituting a pixel circuit of an organic EL display device according to a fifth embodiment of the present invention. Figure 12 The enlarged top view within the double-dotted line in FIG.

[0024] Figure 16 The organic EL display device according to the fifth embodiment of the present invention is Figure 15 A cross-sectional view of the display area along line XVI-XVI in FIG. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0026] First Implementation Method Figures 1 to 9 The first embodiment of the display device according to the present invention is shown. In addition, as a display device having a light-emitting element, an organic EL display device having an organic EL element is exemplified in the following embodiments. Figure 1 It is a plan view showing a schematic configuration of an organic EL display device 50 a according to this embodiment. Figure 2 3 is a plan view of the display area D of the organic EL display device 50 a . Figure 3 : is an equivalent circuit diagram showing a pixel circuit C of the organic EL display device 50a. Figure 4 1 is a schematic plan view schematically showing the arrangement of pixel circuits C of the organic EL display device 50 a . Figure 5 FIG. 1 is a diagram showing the first TFT 9aa constituting the pixel circuit C of the organic EL display device 50a. Figure 4 The enlarged top view within the double-dotted line in FIG. Figure 6 FIG. 1 is a diagram showing a modified example of the first TFT 9aa constituting the pixel circuit C of the organic EL display device 50a. Figure 4 The enlarged top view within the double-dotted line in Figure 5 The corresponding figure. Figure 7 FIG. 1 is a diagram showing a modified example of the first TFT 9aa constituting the pixel circuit C of the organic EL display device 50a. Figure 4 The enlarged top view within the double-dotted line in Figure 5 The corresponding figure. Figure 8 3 is a cross-sectional view of a display region D and a frame region F of an organic EL display device 50 a . Figure 9 2 is a cross-sectional view of the organic EL layer 23 constituting the organic EL display device 50a. Figures 5 to 7 , the upper layer of the gate electrode 14a is omitted.

[0027] like Figure 1 As shown, the organic EL display device 50a includes, for example, a display area D that is provided in a rectangular shape and displays an image, and a frame area F that is provided around the display area D and is provided in a frame shape. In this embodiment, the rectangular display area D is exemplified, but the rectangle also includes substantially rectangular shapes such as shapes with arc-shaped sides, shapes with arc-shaped corners, and shapes with notches on part of the sides.

[0028] like Figure 2 As shown in FIG. 1 , in the display area D, a plurality of sub-pixels P are arranged in a matrix. Figure 2 As shown, in the display area D, for example, a subpixel P having a red light-emitting region Lr for displaying red, a subpixel P having a green light-emitting region Lg for displaying green, and a subpixel P having a blue light-emitting region Lb for displaying blue are arranged adjacent to each other. Furthermore, in the display area D, three adjacent subpixels P having the red light-emitting region Lr, the green light-emitting region Lg, and the blue light-emitting region Lb constitute a single pixel. The arrangement of the subpixels P is not particularly limited; examples include a diamond arrangement and a stripe arrangement.

[0029] At one end of the frame area F (at Figure 1 The terminal portion T is along one direction ( Figure 1 In addition, if Figure 1 As shown, in the frame area F between the terminal portion T and the display area D, Figure 1The longitudinal direction is the bending axis, for example, the bending portion B can be bent at 180 degrees (U-shaped) to bend in one direction ( Figure 1 The method is set in a longitudinal (longitudinal) extension manner.

[0030] like Figure 8 As shown, the organic EL display device 50 a includes a flexible resin substrate 10 provided as a base substrate, and a TFT layer 20 a provided on the resin substrate 10 .

[0031] The resin substrate 10 is made of an organic resin material such as polyimide resin, etc. The base substrate is not limited to the resin substrate 10, and may be a glass substrate, etc., for example.

[0032] like Figure 3 As shown, in the TFT layer 20a, in each sub-pixel P, a first TFT 9aa, a second TFT 9b, and a capacitor 9c are provided as a pixel circuit C. Figure 4 As shown, the pixel circuits C are arranged in a matrix corresponding to the sub-pixels P. Figure 3 and Figure 4 The black circles (●) shown represent nodes.

[0033] like Figure 8 As shown, the TFT layer 20a includes: a first primer film 11a and a second primer film 11b provided on the resin substrate 10; a plurality of first TFTs 9aa and a plurality of second TFTs 9b provided for each sub-pixel P on the second primer film 11b (see FIG. Figure 3 ) and a plurality of capacitors 9c (refer to Figure 3 ); and a planarization film 19 provided on each first TFT9aa, each second TFT9b and each capacitor 9c. Here, as Figures 2 to 4 As shown, a plurality of gate lines 14 are provided in the TFT layer 20a as signal wirings, and the plurality of gate lines 14 extend parallel to each other in the horizontal direction in the figure. Figures 2 to 4 As shown, in the TFT layer 20a, a plurality of source lines 18f are provided as signal wirings in a direction intersecting (orthogonal) with the plurality of gate lines 14, that is, in a manner extending parallel to each other in the longitudinal direction in the figure. Figure 2 as well as Figure 3 As shown in FIG. 1 , in the TFT layer 20a, a plurality of power supply lines 18g are provided so as to extend parallel to each other in the longitudinal direction of the drawing. Figure 2 As shown in FIG. 1 , each power supply line 18g is provided adjacent to each source line 18f. Figure 4 As shown, each source line 18f is connected to, for example, a source driver SD.

[0034] In addition, if Figure 8As shown, in the TFT layer 20a, the first primer film 11a and the second primer film 11b, the semiconductor film to be the semiconductor layer, the gate insulating film 13, the gate line 14 (see Figures 2 to 4 ), gate electrode 14a, first metal film (lower metal film) constituting first wiring layer such as lower conductive layer, first interlayer insulating film 15, second metal film constituting second wiring layer such as upper conductive layer, second interlayer insulating film 17, source line 18f (refer to Figures 2 to 4 ), the source electrode 18a, the drain electrode 18b, the third metal film (upper metal film) constituting the third wiring layer such as the power line 18g, and the planarization film 19 are sequentially stacked on the resin substrate 10.

[0035] The first undercoat film 11a, the second undercoat film 11b, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are composed of, for example, single-layer films or stacked films of inorganic insulating films such as silicon nitride (SiNx (x is a positive number)), silicon oxide (SiO2), or silicon oxynitride (SiON). The first undercoat film 11a is preferably composed of a stacked film such as SiNx (upper layer) / SiO2 (lower layer). The second undercoat film 11b is preferably composed of a stacked film such as SiO2 (upper layer) / SiNx (lower layer).

[0036] The first metal film, the second metal film and the third metal film are composed of, for example, metal single-layer films such as molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), and tungsten (W), or metal stacked films such as Mo (upper layer) / Al (middle layer) / Mo (lower layer), Ti / Al / Ti, Al (upper layer) / Ti (lower layer), Cu / Mo, and Cu / Ti.

[0037] like Figure 3 As shown, in each sub-pixel P, the first TFT 9aa is electrically connected to the corresponding gate line 14 and source line 18f (signal wiring). Figure 8 As shown, first TFT 9aa includes a polycrystalline silicon semiconductor layer 12 (first semiconductor layer), a gate insulating film 13, a gate electrode 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, and source and drain electrodes 18a and 18b, which are sequentially provided on second undercoat film 11b. In other words, first TFT 9aa can be considered a top-gate polycrystalline silicon TFT.

[0038] The polysilicon semiconductor layer 12 is composed of a low temperature polysilicon film such as LTPS (low temperature polysilicon). Figure 8As shown, the polycrystalline silicon semiconductor layer 12 is provided in an island shape on the second undercoat film 11b in a plan view. The polycrystalline silicon semiconductor layer 12 is doped with impurity ions, rendering a portion of the layer conductive. As a result, the polycrystalline silicon semiconductor layer 12 includes a source region 12b and a drain region 12c, each defined as a separate conductive region, and a channel region 12a defined between the source region 12b and the drain region 12c. The source region 12b and the drain region 12c are electrically connected to the plurality of first TFTs 9aa via corresponding gate lines 14 and source lines 18f (signal wiring).

[0039] like Figure 8 As shown, the gate insulating film 13 is provided so as to cover the polycrystalline silicon semiconductor layer 12 .

[0040] like Figure 8 As shown, gate electrode 14a (first wiring layer) is provided on gate insulating film 13 so as to overlap channel region 12a of polycrystalline silicon semiconductor layer 12. Gate electrode 14a is configured to control conduction between source region 12b and drain region 12c of polycrystalline silicon semiconductor layer 12. Gate electrode 14a is formed of a first metal film.

[0041] like Figure 8 As shown, the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially provided so as to cover the gate electrode 14 a .

[0042] like Figure 8 As shown in FIG. 1 , the source electrode 18 a and the drain electrode 18 b (third wiring layer) are provided on the second interlayer insulating film 17 in a manner separated from each other. Figure 8 As shown, source electrode 18a and drain electrode 18b are connected to source region 12b and drain region 12c of polycrystalline silicon semiconductor layer 12 via contact holes Ha and Hb formed in the stacked film of gate insulating film 13, first interlayer insulating film 15, and second interlayer insulating film 17. Source electrode 18a and drain electrode 18b are formed of a third metal film.

[0043] Here, if Figures 4 to 8 As shown, in an organic EL display device 50a, a back gate layer BGa is provided below the first TFT 9aa that constitutes the TFT layer 20a. Specifically, the back gate layer BGa is provided between the first undercoat film 11a and the second undercoat film 11b that constitute the first TFT 9aa. Furthermore, the back gate layer BGa can be provided in the display area D and the frame area F to cover the entire surface of the TFT layer 20a, or it can be provided only in areas necessary for the conductive portion BGac described later. The thickness of the back gate layer BGa is, for example, approximately 10 to 100 nm.

[0044] The back gate layer BGa is composed of the aforementioned In—Ga—Zn—O oxide semiconductor film and has translucency (transparency). Therefore, in the organic EL display device 50a, when a fingerprint sensor, camera, or the like is disposed below the panel (display area D), the back gate layer BGa (and its conductive portion BGac) has little effect on the panel's transmittance, making it difficult to reduce the panel's transmittance.

[0045] In-Ga-Zn-O oxide semiconductors are ternary oxides of In (indium), Ga (gallium), and Zn (zinc). The ratio (composition ratio) of In, Ga, and Zn is not particularly limited. In-Ga-Zn-O semiconductors can be amorphous or crystalline. Crystalline In-Ga-Zn-O semiconductors are preferably those with a c-axis oriented approximately perpendicular to the planes. Other oxide semiconductors may be used in place of In-Ga-Zn-O semiconductors. For example, In-Sn-Zn-O semiconductors (e.g., In2O3-SnO2-ZnO; InSnZnO) may be used as other oxide semiconductors. Here, In-Sn-Zn-O semiconductors are ternary oxides of In (indium), Sn (tin), and Zn (zinc). In addition, other oxide semiconductors may include In-Al-Zn-O semiconductors, In-Al-Sn-Zn-O semiconductors, Zn-O semiconductors, In-Zn-O semiconductors, Zn-Ti-O semiconductors, Cd-Ge-O semiconductors, Cd-Pb-O semiconductors, CdO (cadmium oxide), Mg-Zn-O semiconductors, In-Ga-Sn-O semiconductors, In-Ga-O semiconductors, Zr-In-Zn-O semiconductors, Hf-In-Zn-O semiconductors, Al-Ga-Zn-O semiconductors, Ga-Zn-O semiconductors, In-Ga-Zn-Sn-O semiconductors, InGaO3 (ZnO)5, magnesium zinc oxide (Mg x Zn 1-x O), cadmium zinc oxide (Cd x Zn 1-x O), etc. Furthermore, as the Zn-O-based semiconductor, ZnO in an amorphous (amorphous) state, a polycrystalline state, a microcrystalline state in which an amorphous state and a polycrystalline state are mixed, or a semiconductor without any impurity element added can be used, to which one or more impurity elements selected from Group 1 elements, Group 13 elements, Group 14 elements, Group 15 elements, and Group 17 elements are added.

[0046] In addition, if Figures 4 to 8As shown, the back gate layer BGa includes a conductive portion BGac formed by converting the oxide semiconductor film into a conductive layer. The conductive portion BGac can be referred to as a transparent conductive layer. Furthermore, at least a portion of the back gate layer BGa can be the conductive portion BGac, or the entire back gate layer BGa can be the conductive portion BGac.

[0047] like Figure 4 As shown, the conductive portion BGac (back gate layer BGa) is provided integrally (in a stripe shape) along the extending direction of the source line 18 f (signal wiring) in a plan view so as to span across the plurality of sub-pixels P (the pixel circuits C constituting the plurality of sub-pixels P).

[0048] Here, if Figure 8 As shown in FIG. 1 , in the organic EL display device 50a, the conductive portion BGac overlaps with the channel region 12a of the polysilicon semiconductor layer 12 constituting the first TFT 9aa in a plan view. Furthermore, the conductive portion BGac only needs to overlap with the channel region 12a of the polysilicon semiconductor layer 12 in a plan view. For example, Figure 5 and Figure 6 As shown, in a plan view, the back gate layer BGa and its conductive portion BGac (the dotted portion in the figure) may also be arranged in a grid pattern corresponding to the pattern shape of the polysilicon semiconductor layer 12. In this case, the conductive portion BGac may be formed in at least a portion of the grid pattern of the back gate layer BGa (see FIG. Figure 5 ), can also be formed in the entire pattern (refer to Figure 6 ). On the other hand, Figure 7 As shown, in a plan view, the back gate layer BGa and its conductive portion BGac may also be provided to cover the entire sub-pixel P (the pixel circuit C constituting the sub-pixel P). In this case, the conductive portion BGac may be formed as at least a portion of the pattern of the back gate layer BGa, or may be formed as the entire pattern (see FIG. Figure 7 ).

[0049] The first TFT 9aa configured as described above can be a p-channel TFT such as a writing TFT, a driving TFT, a power supply TFT, or a light-emission control TFT. The writing TFT is configured to apply the voltage of the source line 18f to one terminal electrode of the driving TFT (hereinafter referred to as the "first terminal electrode") in response to selection of the gate line 14. The driving TFT is configured to apply a driving current corresponding to the voltage applied between the gate electrode and the first terminal electrode to one terminal electrode of the light-emission control TFT. The driving TFT is configured to control the current of the organic EL element 25, described later. The power supply TFT applies the voltage of the power line 18g to the first terminal electrode of the driving TFT. The light-emission control TFT is configured to apply the driving current to the organic EL element 25. The first TFT 9aa is preferably a driving TFT. In other words, the driving TFT affects the brightness of the organic EL element 25, and therefore is preferably configured as a first TFT 9aa having a back gate layer BGa having a conductive portion BGac. Furthermore, since the writing TFT, the power supply TFT, and the light emission control TFT other than the driving TFT are switching TFTs, they may or may not include the back gate layer BGa.

[0050] like Figure 3 As shown, in each subpixel P, the second TFT 9b is electrically connected to the corresponding first TFT 9aa and the power supply line 18g. Furthermore, the second TFT 9b has the same structure as the first TFT 9aa, including a second semiconductor layer, a gate insulating film 13, a gate electrode, a first interlayer insulating film 15, a second interlayer insulating film 17, and source and drain electrodes. The second semiconductor layer is formed, for example, of a low-temperature polysilicon film or an In-Ga-Zn-O-based oxide semiconductor film. The In-Ga-Zn-O-based oxide semiconductor can be the same oxide semiconductor as the In-Ga-Zn-O-based oxide semiconductor described above.

[0051] The second TFT 9b configured as described above may be, for example, an n-channel TFT such as an initialization TFT, a compensation TFT, or an anode discharge TFT. The initialization TFT initializes the voltage applied to the gate electrode of the driving TFT. The compensation TFT is configured to place the driving TFT in a diode connection state based on the selection of the gate line 14, thereby compensating for the threshold voltage of the driving TFT. The anode discharge TFT is configured to reset the charge accumulated on the first electrode 21 of the organic EL element 25, described later, based on the selection of the gate line 14. Furthermore, since the initialization TFT, the compensation TFT, and the anode discharge TFT are switching TFTs, they may or may not include a back gate layer BGa.

[0052] In addition, in this embodiment, although the first TFT 9aa and the second TFT 9b are top-gate type TFTs, the first TFT 9aa and the second TFT 9b may be bottom-gate type TFTs. The first TFT 9aa is preferably a top-gate type TFT.

[0053] like Figure 3 As shown, in each subpixel P, capacitor 9c is electrically connected to the corresponding first TFT 9aa and power line 18g. Capacitor 9c includes, for example, a lower conductive layer (first wiring layer) formed of a first metal film; a first interlayer insulating film 15 provided to cover the lower conductive layer; and an upper conductive layer (second wiring layer) formed of a second metal film and provided on the first interlayer insulating film 15 to overlap the lower conductive layer. Furthermore, upper conductive layer 16 is electrically connected to power line 18g via, for example, a contact hole formed in second interlayer insulating film 17.

[0054] Here, if Figure 8 As shown, in the organic EL display device 50a, not only a region of multiple sub-pixels P (hereinafter also referred to as "active region") is arranged in the display region D, but also a back gate layer BGa and its conductive portion BGac are arranged in the frame region F.

[0055] Moreover, if Figure 4 and Figure 8 As shown, in the organic EL display device 50a, the conductive portion BGac is electrically connected to the source line 18f (signal wiring) in the region where no sub-pixels P are arranged in the frame region F (hereinafter also referred to as the "inactive region"). Specifically, Figure 8 As shown, conductive portion BGac is electrically connected to source line 18f via contact hole Hf formed in the laminated film of second undercoat film 11b, gate insulating film 13, first interlayer insulating film 15, and second interlayer insulating film 17, which are at least one inorganic insulating film layer provided between conductive portion BGac and source line 18f. Thus, conductive portion BGac is fixed to the potential of source line 18f.

[0056] However, in flexible organic EL display devices featuring a back gate formed by separating an inorganic insulating film (primer film) from a top-gate polysilicon TFT, conventional display devices electrically connecting the back gate to a potential-fixing wiring (signal wiring) within the pixel circuit C (active region) via a contact hole formed in the inorganic insulating film have a problem with unstable TFT threshold characteristics due to impurities from the resin substrate located directly below the back gate. This is believed to be due to the presence of a contact hole near the TFT, allowing hydrogen atoms generated from the primer film to pass through the opening of the contact hole and adhere to the TFT channel.

[0057] In contrast, in the organic EL display device 50 a , the conductive portion BGac in the back gate layer BGa is electrically connected to the source line 18 f through the contact hole Hf outside the pixel circuit C (in the inactive region), so the above-mentioned problem is less likely to occur.

[0058] The planarizing film 19 has a flat surface in the display region D and is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (spin on glass) material.

[0059] like Figure 8 As shown, the organic EL display device 50 a includes an organic EL element layer 31 provided as an upper layer of the TFT layer 20 a and serving as a light-emitting element layer constituting the display region D, and a sealing film 35 provided on the organic EL element layer 31 .

[0060] like Figure 8 As shown, the organic EL element layer 31 includes a plurality of organic EL elements 25 as a plurality of light-emitting elements arranged in a matrix corresponding to a plurality of sub-pixels P.

[0061] like Figure 8 As shown, the organic EL element 25 includes a plurality of first electrodes 21, a plurality of organic EL layers 23, and a second electrode 24 sequentially provided on the planarization film 19. The plurality of organic EL layers 23 are provided on the first electrodes 21, and the second electrode 24 is provided on the organic EL layer 23 in common in the plurality of sub-pixels P. Figure 8 As shown, the organic EL element 25 is covered with a sealing film 35 .

[0062] like Figure 8 As shown in FIG. 1 , the first electrodes 21 are arranged in a matrix on the planarization film 19 in a manner corresponding to the plurality of sub-pixels P. Figure 8As shown, each first electrode 21 is electrically connected to the drain electrode 18d (or source electrode 18c) of each second TFT 9b via a contact hole formed in the planarizing film 19. The first electrode 21 also functions to inject holes into the organic EL layer 23. To improve the efficiency of hole injection into the organic EL layer 23, the first electrode 21 is preferably formed of a material with a high work function. Examples of materials for the first electrode 21 include metal materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), Yb, lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). Alternatively, the first electrode 21 may be formed of an alloy such as astatine (At) / astatine oxide (AtO2). Furthermore, the material constituting the first electrode 21 may be a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). Alternatively, the first electrode 21 may be formed by stacking multiple layers of the above materials. Examples of compound materials with a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).

[0063] The peripheral end of the first electrode 21 is covered by an edge cover 22 provided in a grid pattern in common to the plurality of sub-pixels P. Here, as a material constituting the edge cover 22, for example, a positive photosensitive resin material such as polyimide resin, acrylic resin, polysiloxane resin, or novolac resin, or a polysiloxane-based SOG material can be cited. Figure 8 As shown, a portion of the surface of the edge cover 22 serves as a pixel photo spacer that protrudes upward in the figure and is provided in an island shape.

[0064] like Figure 8 As shown in FIG. 1 , the organic EL layer 23 is disposed on each first electrode 21 and is arranged in a matrix in a manner corresponding to a plurality of sub-pixels P. Figure 9 As shown, each organic EL layer 23 includes a hole injection layer 1 , a hole transport layer 2 , a light emitting layer 3 , an electron transport layer 4 and an electron injection layer 5 which are sequentially arranged on the first electrode 21 .

[0065] The hole injection layer 1, also called an anode buffer layer, brings the energy levels of the first electrode 21 and the organic EL layer 23 closer together, thereby improving the efficiency of hole injection from the first electrode 21 to the organic EL layer 23. Examples of materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0066] The hole transport layer 2 has a function of improving the efficiency of hole transport from the first electrode 21 to the organic EL layer 23. Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, phenylethylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, aromatic amine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.

[0067] The light-emitting layer 3 is a region into which holes and electrons are injected from the first electrode 21 and the second electrode 24, respectively, when a voltage is applied to the first electrode 21 and the second electrode 24, and the holes and electrons recombine. The light-emitting layer 3 is formed of a material with high luminous efficiency. Examples of materials constituting the light-emitting layer 3 include metal hydroxyquinoline compounds [8-hydroxyquinoline metal complexes], naphthalene derivatives, anthracene derivatives, distyrene derivatives, vinyl acetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazole derivatives, styryl derivatives, styrylamine derivatives, distyrylbenzene derivatives, tristyrylbenzene derivatives, perylene derivatives, pyrenone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, acridine derivatives, phenoxazinones, quinacridone derivatives, rubrene, poly(p-phenylene vinylene), and polysilane.

[0068] The electron transport layer 4 has the function of efficiently transferring electrons to the light-emitting layer 3. Examples of materials constituting the electron transport layer 4 include organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, fluorenone derivatives, silole derivatives, and metal hydroxyquinoline compounds.

[0069] The electron injection layer 5 is close to the energy level of the second electrode 24 and the organic EL layer 23, and has the function of improving the efficiency of electron injection from the second electrode 24 to the organic EL layer 23. Through this function, the driving voltage of the organic EL element 25 can be reduced. In addition, the electron injection layer 5 is also called a cathode buffer layer. Here, as a material constituting the electron injection layer 5, for example, inorganic base compounds such as lithium fluoride (LiF), magnesium fluoride (MgF2), calcium fluoride (CaF2), strontium fluoride (SrF2), and barium fluoride (BaF2), aluminum oxide (Al2O3), strontium oxide (SrO), etc. can be mentioned.

[0070] like Figure 8 As shown, the second electrode 24 is provided to cover each organic EL layer 23 and the edge cover 22. The second electrode 24 also has the function of injecting electrons into the organic EL layer 23. To improve the efficiency of electron injection into the organic EL layer 23, the second electrode 24 is preferably made of a material with a low work function. Examples of materials for the second electrode 24 include silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), ruthenium (Ru), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). Alternatively, the second electrode 24 may be formed of, for example, an alloy of magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatine oxide (AtO2), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), or lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). Alternatively, the second electrode 24 may be formed of, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). Alternatively, the second electrode 24 may be formed by stacking multiple layers of the above materials. In addition, examples of materials with a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al).

[0071] like Figure 8 As shown, the sealing film 35 includes a first sealing inorganic film 32 provided to cover the second electrode 24; a sealing organic film 33 provided on the first sealing inorganic film 32; and a second sealing inorganic film 34 provided to cover the sealing organic film 33. The sealing film 35 protects the organic EL layer 23 from moisture, oxygen, and other factors. The first and second sealing inorganic films 32, 34 are composed of inorganic materials such as silicon oxide (SiO2), aluminum oxide (Al2O3), silicon nitride (SiNx (x is a positive number)) such as silicon tetranitride (Si3N4), or silicon carbonitride (SiCN). The sealing organic film 33 is composed of organic materials such as acrylic resin, polyurea resin, parylene resin, polyimide resin, or polyamide resin.

[0072] The above-described organic EL display device 50a is configured as follows: In each sub-pixel P, the gate signal is input to the first TFT 9aa via the gate line 14, causing the first TFT 9aa to be in an on state. By writing the data signal to the gate electrode of the second TFT 9b and the capacitor 9c via the source line 18f, the organic EL layer 23 is supplied with current from the power supply line 18g corresponding to the gate voltage of the second TFT 9b, so that the light-emitting layer 3 of the organic EL layer 23 emits light to perform image display. In addition, in the organic EL display device 50a, even when the first TFT 9aa is in an off state, since the gate voltage of the second TFT 9b is held by the capacitor 9c, the light emission of the light-emitting layer 3 is maintained until the gate signal of the next frame is input.

[0073] Next, a method for manufacturing the organic EL display device 50a of the present embodiment will be described. The method for manufacturing the organic EL display device 50a of the present embodiment includes a TFT layer formation process.

[0074] <TFT layer formation process> The TFT layer formation process is a process for forming the TFT layer 20a, and includes a first bottom coating film formation process, a back gate layer formation process, a second bottom coating film formation process, a polycrystalline silicon semiconductor layer formation process, a gate insulating film formation process, a gate electrode formation process, a doping process, an interlayer insulating film formation process, a contact hole formation process, and a signal wiring formation process.

[0075] (First bottom coating film formation process) First, on the resin substrate 10 formed on the glass substrate, for example, by using the plasma CVD (Chemical Vapor Deposition) method, a silicon oxide film (thickness of about 250 nm) and a silicon nitride film (thickness of about 50 nm) are sequentially formed to form a first bottom coating film 11a composed of a stacked film such as SiNx (upper layer) / SiO2 (lower layer).

[0076] (Back gate layer formation process) On the surface of the substrate on which the first bottom coating film 11a is formed, for example, an oxide semiconductor film composed of an InGaZnO4 film (thickness of about 30 nm) or the like is formed by sputtering, and then the oxide semiconductor film is patterned. Thus, a strip-shaped back gate layer BGa extending parallel to the extending direction of the source line 18f formed in the subsequent process is formed.

[0077] (Second bottom coating film formation process) On the surface of the substrate on which the back gate layer BGa is formed, a silicon nitride film (thickness of about 50 nm) and a silicon oxide film (thickness of about 250 nm) are sequentially formed, for example using a plasma CVD method, thereby forming a second basecoat film 11b composed of a stacked film such as SiO2 (upper layer) / SiNx (lower layer).

[0078] Here, in the method for manufacturing the organic EL display device 50a, a portion of the back gate layer BGa is made conductive by heat treatment after forming the second undercoat film 11b, thereby forming a conductive portion BGac. Specifically, the conductive portion BGac is formed in the region of the polycrystalline silicon semiconductor layer 12 formed in a subsequent step within the back gate layer BGa that overlaps at least with the channel region 12a when viewed from above.

[0079] (Polycrystalline Silicon Semiconductor Layer Formation Process) On the surface of the substrate on which the second base coat film 11b is formed, an amorphous silicon film (thickness of about 50nm) is formed by, for example, a plasma CVD method, and the amorphous silicon film is crystallized by laser annealing, etc. to form a polycrystalline silicon film composed of polycrystalline silicon. After that, the polycrystalline silicon film is patterned to form a polycrystalline silicon semiconductor layer 12.

[0080] (Gate Insulation Film Formation Step) After forming a silicon oxide film (about 100 nm thick) by plasma CVD on the substrate surface where the polysilicon semiconductor layer 12 is formed, the silicon oxide film is patterned to cover the polysilicon semiconductor layer to form the gate insulating film 13 .

[0081] (Gate Electrode Formation Process) On the surface of the substrate on which the gate insulating film 13 is formed, a first metal film (lower metal film) such as a molybdenum film (thickness of about 200 nm) is formed by sputtering, and then the first metal film is patterned to form a first wiring layer such as a gate electrode 14 a and a gate line 14 .

[0082] (Doping process) By doping the polycrystalline silicon semiconductor layer 12 with impurity ions using the gate electrode 14 a as a mask, a portion of the polycrystalline silicon semiconductor layer 12 is made conductive, thereby forming a source region 12 b , a drain region 12 c , and a channel region 12 a in the polycrystalline silicon semiconductor layer 12 .

[0083] (Interlayer Insulation Film Formation Step) On the surface of the substrate on which the gate electrode 14a is formed (the surface of the substrate where a part of the polysilicon semiconductor layer 12 is made conductive), at least one layer of interlayer insulating film is formed. On this substrate surface, for example, a silicon nitride film (with a thickness of about 150 nm) and a silicon oxide film (with a thickness of about 100 nm) are sequentially formed by plasma CVD method to form the first interlayer insulating film 15. Then, on the substrate surface on which the first interlayer insulating film 15 is formed, for example, a silicon oxide film (with a thickness of about 100 nm) is formed by plasma CVD method to form the second interlayer insulating film 17.

[0084] (Contact hole forming process) In the display region D (active region) of the substrate surface on which the second interlayer insulating film 17 is formed, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are appropriately patterned by, for example, dry etching to form contact holes Ha and Hb that expose at least a part of the surfaces of the source region 12b and the drain region 12c in the polysilicon semiconductor layer 12. In addition, in the frame region F (non-active region) of this substrate surface, the second undercoat film 11b, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are appropriately patterned by, for example, dry etching to form a contact hole Hf that exposes at least a part of the surface of the conductive portion BGac in the back gate layer BGa.

[0085] (Signal wiring forming process) On the substrate surface on which the above contact holes Ha, Hb, and Hf are formed, for example, a titanium film (with a thickness of about 50 nm), an aluminum film (with a thickness of about 400 nm), and a titanium film (with a thickness of about 200 nm) are sequentially formed by sputtering method to form a third metal film (upper metal film), and then this third metal film is patterned to form a third wiring layer such as a source line 18f, a source electrode 18a, a drain electrode 18b, and a power supply line 18g.

[0086] Thus, in the manufacturing method of the organic EL display device 50a, in the signal wiring forming process, the conductive portion BGac is electrically connected to the source line 18f.

[0087] <Other processes in the TFT layer forming process> The TFT layer forming process may include a second wiring layer forming process, a planarizing film forming process, etc. as required.

[0088] (Second wiring layer forming process) On the substrate surface on which the first interlayer insulating film 15 is formed in the interlayer insulating film forming process, for example, a second metal film such as a molybdenum film (with a thickness of about 200 nm) is formed by sputtering method, and then this second metal film is patterned to form a second wiring layer such as an upper conductive layer.

[0089] (Planarization Film Formation Process) An acrylic photosensitive resin film (about 2µm thick) is applied to the surface of the substrate on which the source line 18f is formed, for example, by spin coating or slit coating, and then the coated film is pre-baked, exposed, developed, and post-baked to form a planarization film 19.

[0090] The method for manufacturing the organic EL display device 50 a includes an organic EL element layer forming step and a sealing film forming step.

[0091] <Organic EL Element Layer Formation Step> The organic EL element layer 31 is formed by forming a first electrode 21, an edge cover 22, an organic EL layer 23 (a hole injection layer 1, a hole transport layer 2, a light-emitting layer 3, an electron transport layer 4, and an electron injection layer 5) and a second electrode 24 on the planarization film 19 of the TFT layer 20a formed in the TFT layer formation process using a known method to form an organic EL element 25.

[0092] <Sealing Film Forming Step> First, on the substrate surface where the organic EL element layer 31 is formed in the organic EL element layer formation step, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is deposited by plasma CVD, for example, using a CMM as an evaporation mask, so as to cover each organic EL element 25, thereby forming a first sealing inorganic insulating film 32. Next, an organic resin material such as an acrylic resin is deposited on the first sealing inorganic insulating film 32 by, for example, an inkjet method, to form a sealing organic film 33. Then, using a CMM as an evaporation mask, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is deposited by plasma CVD, for example, to cover the sealing organic film 33, thereby forming a second sealing inorganic insulating film 34. Through the above steps, a sealing film 35 is formed in the display area D, which is a stack of the first sealing inorganic insulating film 32, the sealing organic film 33, and the second sealing inorganic insulating film 34.

[0093] Finally, after attaching a protective sheet (not shown) to the substrate surface, laser light is irradiated from the glass substrate side of the resin substrate 10 to peel the glass substrate from the lower surface of the resin substrate 10. A protective sheet (not shown) is then attached to the lower surface of the resin substrate 10 from which the glass substrate has been peeled. In this manner, the organic EL display device 50a can be manufactured.

[0094] <Effect> As described above, according to the organic EL display device 50 a of this embodiment, the following effects can be obtained.

[0095] In the organic EL display device 50a, a back gate layer BGa is provided between the resin substrate 10 and the TFT layer 20a, with a second primer film 11b interposed therebetween. In the TFT layer 20a, top-gate first TFTs 9aa (polysilicon TFTs) comprising a polysilicon semiconductor layer 12 are provided corresponding to the plurality of subpixels P. This back gate layer BGa includes a conductive portion BGac. The conductive portion BGac is integrally provided along the direction of extension of the source line 18f (signal wiring) in a plan view, spanning the plurality of subpixels P (constituting the pixel circuit C thereof). The conductive portion BGac overlaps at least with the channel region 12a in a plan view and is electrically connected to the source line 18f. This prevents threshold (Vth) deviation of the first TFTs 9aa caused by polarization of the resin substrate 10, resulting in stable threshold characteristics.

[0096] In the organic EL display device 50a, the back gate layer BGa is formed of a transparent oxide semiconductor film, and at least a portion of the oxide semiconductor layer is made conductive, forming the conductive portion BGac. This ensures panel transmittance.

[0097] Thus, the organic EL display device 50a achieves both stabilization of the threshold of the TFT (particularly top-gate polysilicon TFT) and maintenance of the panel transmittance. Furthermore, in the organic EL display device 50a, the conductive portion BGac is electrically connected to the source line 18f via the contact hole Hf outside the pixel circuit C (in the inactive region). This prevents hydrogen atoms generated from the first undercoat film 11a from adhering to the channel region 12a, further stabilizing the threshold characteristics of the first TFT 9aa.

[0098] Second Implementation Method Next, use Figure 10 A second embodiment of the present invention will be described. Figure 10 is a cross-sectional view of the display area D and the frame area F of the organic EL display device 50b of this embodiment, and is Figure 8 The overall structure of the organic EL display device 50b is the same as that of the first embodiment except for the structure of the TFT layer 20b, so detailed description is omitted here. In addition, the same reference numerals are attached to the same components as those of the first embodiment, and their description is omitted.

[0099] like Figure 10 As shown, in an organic EL display device 50b, a metal layer M, which appears as an island when viewed from above, is provided in the frame region F (inactive region) between the lower end of the contact hole Hf and the conductive portion BGac. The metal layer M is disposed between the back gate layer BGa and the second undercoat film 11b. Thus, the conductive portion BGac and the source line 18f are electrically connected via the metal layer M.

[0100] The metal layer M is similar to the first metal film, the second metal film and the third metal film, and is composed of, for example, a metal single layer film of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), or a metal stacked film of Mo (upper layer) / Al (middle layer) / Mo (lower layer), Ti / Al / Ti, Al (upper layer) / Ti (lower layer), Cu / Mo, Cu / Ti, etc.

[0101] The organic EL display device 50b may be configured by adding the following metal layer forming step after the back gate layer forming step and before the second undercoat film forming step in the TFT layer forming step of the organic EL display device 50a described above.

[0102] (Metal layer formation process) The metal film is formed on the surface of the substrate on which the back gate layer BGa is formed by, for example, sputtering, and then the metal film is patterned to form the metal layer M.

[0103] <Effect> According to the organic EL display device 50 b described above, in addition to the effects of the organic EL display device 50 a described above, the following effects can be obtained.

[0104] In the organic EL display device 50b, a metal layer M is provided between the conductive portion BGac and the second primer film 11b in the frame region F (inactive region), specifically, in the region that overlaps with the contact hole Hf for electrically connecting the conductive portion BGac to the source line 18f when viewed from above. This metal layer M prevents the conductive portion BGac from penetrating when the contact hole Hf is formed.

[0105] Third Implementation Method Next, use Figure 11 A third embodiment of the present invention will be described. Figure 11 is a cross-sectional view of the display area D and the frame area F of the organic EL display device 50c of this embodiment, and is Figure 8 The overall structure of the organic EL display device 50c is the same as that of the first embodiment except for the structure of the TFT layer 20c, so detailed description is omitted here. In addition, the same reference numerals are attached to the same components as those of the first embodiment, and their description is omitted.

[0106] like Figure 11 As shown, in the organic EL display device 50 c , in the display region D (active region), the back gate layer BGc has a non-conductive portion BGcn where the oxide semiconductor film is not conductive.

[0107] The non-conductive portion BGcn is provided as a signal wiring in the extending direction of the source line 18f (see Figure 4) between a plurality of adjacent sub-pixels P. In other words, Figure 11 As shown, in the display area D (active area), the conductive portion BGcc of the back gate layer BGc is separated for each sub-pixel P. When viewed from above, the conductive portion BGcc overlaps the entire first TFT 9ac (the entire surface of the polycrystalline silicon semiconductor layer 12 that constitutes it). Thus, in the organic EL display device 50c, the conductive portions BGcc and the non-conductive portions BGcn are alternately arranged along the extending direction of the source line 18f.

[0108] Furthermore, the organic EL display device 50 c may also be configured to include a metal layer M, similar to the organic EL display device 50 b described above.

[0109] In the organic EL display device 50c, the second undercoat film forming step in the TFT layer forming step of the organic EL display device 50a described above can be modified as follows. For example, a heat treatment after forming the second undercoat film 11b can be performed so that the back gate layer BGc in the region between a plurality of adjacent sub-pixels P (first TFTs 9ac) in the direction in which the source line 18f extends is not affected by heat, or is less affected by heat.

[0110] <Effect> According to the organic EL display device 50 c described above, in addition to the effects of the organic EL display device 50 a described above, the following effects can be obtained.

[0111] In the organic EL display device 50c, a non-conductive portion BGcn is provided in the back gate layer BGc of the display region D (active region) between adjacent sub-pixels P (first TFTs 9ac) in the direction in which the source line 18f extends. This non-conductive portion BGcn separates the conductive portion BGcc from each sub-pixel P, thus minimizing the potential difference between the conductive portion BGcc and the polycrystalline silicon semiconductor layer 12. As a result, the stability of the threshold characteristics of the first TFTs 9ac can be improved.

[0112] Fourth Implementation Method Next, use Figures 12 to 14 A fourth embodiment of the present invention will be described. Figure 12 is a schematic plan view schematically showing the arrangement of pixel circuits C of the organic EL display device 50d of this embodiment, and is similar to Figure 4 The corresponding figure. Figure 13 FIG. 1 is a diagram showing the first TFT 9ad constituting the pixel circuit C of the organic EL display device 50d. Figure 12 The enlarged top view within the double-dotted line in FIG. Figure 14 It is along Figure 13A cross-sectional view of the display region D of the organic EL display device 50d along line XIV-XIV in FIG. Figure 13 In the figure, the upper layer of the gate electrode 14a is omitted. The overall structure of the organic EL display device 50d is the same as that of the first embodiment, except for the structure of the TFT layer 20d, and therefore a detailed description thereof is omitted here. Components identical to those in the first embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0113] like Figures 12 to 14 As shown in FIG. 5 , in the organic EL display device 50 d , the conductive portion BGdc (back gate layer BGd) is provided in an island shape for each sub-pixel P so as to cover the entire sub-pixel P when viewed from above. Specifically, Figure 13 and Figure 14 As shown, the island-shaped conductive portion BGdc overlaps the entire first TFT 9ad (the entire surface of the polycrystalline silicon semiconductor layer 12 constituting the first TFT 9ad) in a plan view.

[0114] Here, if Figure 14 As shown, in the organic EL display device 50 d , in the display region D (active region), the conductive portion BGdc is electrically connected to the source line 18 f via the contact hole Hf.

[0115] Furthermore, the organic EL display device 50 d may also be configured to include a metal layer M, similar to the organic EL display device 50 b described above.

[0116] The organic EL display device 50d can be formed by modifying the back gate layer formation and contact hole formation steps in the TFT layer formation process of the aforementioned organic EL display device 50a as follows. For example, in the back gate layer formation step, the oxide semiconductor film pattern is modified to form an island-shaped back gate layer BGd that overlaps the entire surface of the polysilicon semiconductor layer 12 (the entire first TFT 9ad) formed in a subsequent step when viewed from above. In the contact hole formation step, a contact hole Hf is formed in the second primer film 11b, gate insulating film 13, first interlayer insulating film 15, and second interlayer insulating film 17 in the display region D (active region), exposing at least a portion of the surface of the conductive portion BGdc.

[0117] <Effect> According to the organic EL display device 50 d described above, the same effects as those of the organic EL display device 50 a can be obtained.

[0118] Fifth Implementation Method Next, use Figures 15 and 16 A fifth embodiment of the present invention will be described. Figure 15 FIG. 1 is a diagram showing the first TFT 9ae of the pixel circuit C constituting the organic EL display device 50e of this embodiment. Figure 12 The enlarged top view within the double-dotted line in FIG. Figure 16 It is along Figure 15 A cross-sectional view of the display region D of the organic EL display device 50e taken along line XVI-XVI in FIG. Figure 15 In the figure, the upper layer of the gate electrode 14a is omitted. The overall structure of the organic EL display device 50e is the same as that of the fourth embodiment, except for the structure of the TFT layer 20e, and therefore a detailed description thereof is omitted here. Components identical to those in the fourth embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0119] like Figures 15 and 16 As shown, in the organic EL display device 50e, similar to the organic EL display device 50d described above, the conductive portion BGec (back gate layer BGe) is provided in an island shape for each sub-pixel P so as to cover the entire sub-pixel P when viewed from above. Specifically, the conductive portion BGec overlaps the entire surface of the polycrystalline silicon semiconductor layer 12 (the entire first TFT 9ae) when viewed from above.

[0120] Here, the organic EL display device 50 e is similar to the organic EL display device 50 c described above. In the display region D (active region), the back gate layer BGe has a non-conductive portion BGen where the oxide semiconductor film is not conductive.

[0121] In a plan view, the non-conductive portion BGen is arranged in a frame-like pattern around the island-shaped conductive portion BGec. This frame-like non-conductive portion BGen ensures that the conductive portion BGec in the back gate layer BGe is isolated for each sub-pixel P in the display area D (active area).

[0122] Furthermore, the organic EL display device 50e may also be configured to include a metal layer M, similar to the organic EL display device 50b described above.

[0123] In the organic EL display device 50e, the second undercoat film forming step in the TFT layer forming step of the organic EL display device 50d described above can be modified as follows. For example, in order to protect or reduce the thermal effects on the back gate layer BGe surrounding each subpixel P (first TFT 9ae), a heat treatment may be performed after forming the second undercoat film 11b.

[0124] <Effect> According to the organic EL display device 50 e described above, in addition to the effects of the organic EL display device 50 a described above, the following effects can be obtained.

[0125] In the organic EL display device 50e, a frame-shaped non-conductive portion BGen is provided in the back gate layer BGe around the subpixels P (first TFTs 9ae). Because the frame-shaped non-conductive portion BGen separates the conductive portion BGec from each subpixel P, a potential difference is less likely to occur between the conductive portion BGec and the polycrystalline silicon semiconductor layer 12. As a result, the stability of the threshold characteristics of the first TFTs 9ae can be improved.

[0126] Other Implementation Methods In the above embodiments, the conductive portion is integrally provided as a signal wiring along the direction in which the source line extends, spanning multiple sub-pixels. However, this is not limiting. The conductive portion may also be integrally provided as a signal wiring along the direction in which the gate line extends, spanning multiple sub-pixels. In this case, the conductive portion may be electrically connected to the gate line.

[0127] In the above embodiments, an organic EL layer having a five-layer stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer is exemplified, but the organic EL layer may also be a three-layer stacked structure of, for example, a hole injection layer serving as a hole transport layer, a light-emitting layer, and an electron transport layer serving as an electron injection layer.

[0128] In addition, in the above-mentioned embodiments, an organic EL display device in which the first electrode is set as the anode and the second electrode is set as the cathode is illustrated, but the present invention can also be applied to an organic EL display device in which the stacked structure of the organic EL layer is reversed, and the first electrode is set as the cathode and the second electrode is set as the anode.

[0129] In the above embodiments, an organic EL display device in which the electrode of the TFT connected to the first electrode is a drain electrode is exemplified. However, the present invention is also applicable to an organic EL display device in which the electrode of the TFT connected to the first electrode is a source electrode.

[0130] In each of the above-described embodiments, the display device is an organic EL display device. However, the present invention is also applicable to display devices such as an active matrix driven liquid crystal display device.

[0131] While the above embodiments illustrate an organic EL display device as an example, the present invention is not limited to organic EL displays and is applicable to any flexible display device. For example, it can be applied to flexible display devices such as QLEDs (quantum-dot light emitting diodes) that use light-emitting elements containing quantum dot layers.

[0132] Industrial applicability As described above, the present invention can be used in a flexible display device.

[0133] Description of Reference Numerals BGa, BGc, BGd, BGe back gate layer BGac, BGcc, BGdc, BGec Conductor BGcn, BGen non-conductive part D Display area F Border area M Metal Layer P sub-pixel 9aa, 9ac, 9ad, 9ae first TFT 10 Resin substrate (base substrate) 11a First primer film 11b Second base coating film 12 Polycrystalline silicon semiconductor layer 12a Channel region 12b Source region (conductor region) 12c Drain region (conductor region) 18f Source line (signal wiring) 20a, 20b, 20c, 20d, 20e TFT (thin film transistor) layer 25 Organic EL elements (organic electroluminescent elements, light-emitting elements) 31 Organic EL element layer (light-emitting element layer) 35 Sealing film 50a, 50b, 50c, 50d, 50e are organic EL display devices.

Claims

1. A display device comprising a base substrate and a thin film transistor layer provided on the base substrate, In the thin film transistor layer, a plurality of thin film transistors are provided corresponding to a plurality of sub-pixels constituting a display area. The plurality of thin film transistors include a polycrystalline silicon semiconductor layer formed of a polycrystalline silicon film and defining a channel region and a conductor region. The plurality of thin film transistors are electrically connected to each other via signal wiring in the conductor region. A transmissive back gate layer formed of an oxide semiconductor film is provided under the thin film transistor layer. The back gate layer has a conductive portion formed by conductively converting at least a portion of the oxide semiconductor film. The display device is characterized in that The conductive portion overlaps at least the channel region in a plan view and is electrically connected to the signal wiring.

2. The display device according to claim 1, wherein The conductive portion is integrally provided so as to span across the plurality of sub-pixels along the extending direction of the signal wiring in a plan view.

3. The display device according to claim 2, wherein: A frame area is provided around the display area. The conductive portion is arranged in the frame area. In a region of the frame region where the plurality of sub-pixels are not arranged, the conductive portion is electrically connected to the signal wiring.

4. The display device according to claim 2 or 3, characterized in that The back gate layer in the display region has a non-conductive portion where the oxide semiconductor film is not conductive. The non-conductive portion is provided between the plurality of adjacent sub-pixels.

5. The display device according to claim 1, wherein The conductive portion is provided in an island shape for each sub-pixel in a plan view.

6. The display device according to claim 5, wherein: The back gate layer in the display region has a non-conductive portion where the oxide semiconductor film is not conductive. The non-conductive portion is provided in a frame shape along the periphery of the island-shaped conductive portion in a plan view.

7. The display device according to claim 5 or 6, characterized in that: In the display area, the island-shaped conductive portion is electrically connected to the signal wiring.

8. The display device according to any one of claims 1 to 7, characterized in that The conductive portion and the signal wiring are connected via a contact hole formed in at least one inorganic insulating film provided between the conductive portion and the signal wiring.

9. The display device according to claim 8, wherein A metal layer having an island shape in a plan view is provided between the lower end of the contact hole and the conductive portion.

10. The display device according to any one of claims 1 to 9, characterized in that The conductive portion in the display area is provided in a mesh pattern so as to correspond to a shape of the polycrystalline silicon semiconductor layer in a plan view.

11. The display device according to any one of claims 1 to 9, characterized in that The conductive portion in the display area is provided so as to entirely cover each sub-pixel in a plan view.

12. The display device according to any one of claims 1 to 11, characterized in that The back gate layer is disposed on the entire surface of the thin film transistor layer.

13. The display device according to any one of claims 1 to 12, characterized in that: The signal wiring is a source wiring or a gate wiring.

14. The display device according to any one of claims 1 to 13, characterized in that The thin film transistor layer includes a first primer film and a second primer film sequentially stacked on the base substrate. The back gate layer is provided between the first primer film and the second primer film.

15. The display device according to claim 14, wherein: The thin film transistor layer includes: a polycrystalline silicon semiconductor layer, disposed on the second primer film; a gate insulating film provided to cover the polycrystalline silicon semiconductor layer; and A plurality of gate electrodes are provided on the gate insulating film.

16. The display device according to any one of claims 1 to 15, characterized in that include: a light-emitting element layer, which is disposed on the thin film transistor layer and has a plurality of light-emitting elements arranged corresponding to the plurality of sub-pixels; as well as A sealing film is provided to cover the light emitting element layer.

17. The display device according to claim 16, wherein: Each of the light-emitting elements is an organic electroluminescent element.

18. The display device according to claim 16 or 17, characterized in that: The plurality of thin film transistors are driving thin film transistors configured to control current of each of the light emitting elements.

19. The display device according to any one of claims 1 to 18, characterized in that The base substrate is a resin substrate.

20. A method for manufacturing a display device, The display device includes a base substrate and a thin film transistor layer provided on the base substrate. In the thin film transistor layer, a plurality of thin film transistors are provided corresponding to a plurality of sub-pixels constituting a display area. The plurality of thin film transistors include a polycrystalline silicon semiconductor layer formed of a polycrystalline silicon film and defining a channel region and a conductor region. The plurality of thin film transistors are electrically connected to each other via signal wiring in the conductor region. A transmissive back gate layer formed of an oxide semiconductor film is provided under the thin film transistor layer. The back gate layer has a conductive portion formed by conductively converting at least a portion of the oxide semiconductor film. The method for manufacturing the display device is characterized in that the thin film transistor layer forming step for forming the thin film transistor layer includes: a first primer film forming step of forming a first primer film on the base substrate; a back gate layer forming step of forming the oxide semiconductor film on the surface of the substrate on which the first primer film is formed, and then patterning the oxide semiconductor film to form the back gate layer; a second primer film forming step of forming a second primer film on the surface of the substrate on which the back gate layer is formed; a polycrystalline silicon semiconductor layer forming step of forming the polycrystalline silicon film on the surface of the substrate on which the second primer film is formed, and then patterning the polycrystalline silicon film to form the polycrystalline silicon semiconductor layer; a gate insulating film forming step of forming a gate insulating film on a surface of the substrate on which the polycrystalline silicon semiconductor layer is formed so as to cover the polycrystalline silicon semiconductor layer; a gate electrode forming step of forming a lower metal film on the surface of the substrate on which the gate insulating film is formed, and then patterning the lower metal film to form a plurality of gate electrodes; a doping step of performing doping using the gate electrodes as masks to form the channel region and the conductor region of the polysilicon semiconductor layer; an interlayer insulating film forming step of forming at least one interlayer insulating film on the surface of the substrate on which the plurality of gate electrodes are formed; a contact hole forming step of forming a contact hole on the surface of the substrate on which the at least one interlayer insulating film is formed, wherein the contact hole exposes at least a portion of the conductive region in the polycrystalline silicon semiconductor layer and the conductive portion in the back gate layer; as well as A signal wiring forming step comprises forming an upper metal film on the surface of the substrate where the contact hole is formed, and then patterning the upper metal film to form the signal wiring, wherein the signal wiring covers the exposed surface of the conductive portion exposed in the contact hole. In the second primer film forming step, a region of the back gate layer at least overlapping with the channel region in a plan view is made conductive by heat treatment after the second primer film is formed, thereby forming the conductive portion; In the signal wiring forming step, the conductive portion and the signal wiring are electrically connected.

21. The method for manufacturing a display device according to claim 20, wherein: The thin film transistor layer forming step includes a metal layer forming step after the back gate layer forming step and before the second primer film forming step. In the metal layer forming step, after forming a metal film on the substrate surface where the back gate layer is formed, the metal film is patterned to form an island-shaped metal layer between the lower end of the contact hole and the conductive portion in a plan view.

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