Fully balanced error code correction without increasing correction power

Abstract

In some aspects, the technology described herein relates to a method that includes receiving a standard error code correction (ECC) matrix that includes a portion for checking a payload and a portion for checking a parity of the payload; and extending the ECC matrix to form an extended matrix by adding a plurality of rows and a plurality of columns to form an upper matrix and a lower matrix, wherein the plurality of rows and columns include at least one all-zero portion, at least one portion for checking a quantized Adades-Na (QK) index, and a portion for checking a parity of the QK index.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to and the benefit of U.S. patent application serial number 18 / 443,883, filed on February 16, 2024, which claims the benefit of U.S. Provisional Patent Application No. 63 / 486,562, filed on February 23, 2023, the entire disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] At least some embodiments disclosed herein relate generally to memory systems, and more particularly, but not limited to, techniques for balancing and performing error correction on codewords stored in such memory devices. Background Art

[0004] The memory subsystem may include one or more memory devices that store data. For example, the memory devices may be non-volatile memory devices and volatile memory devices. Generally speaking, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices.

[0005] A memory device may include a memory integrated circuit having one or more memory cell arrays formed on an integrated circuit die of semiconductor material. A memory cell is the smallest memory unit that can be individually used or operated to store data. Generally, a memory cell can store one or more bits of data.

[0006] Different types of memory cells have been developed for memory integrated circuits, such as random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), NOR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), flash memory, etc.

[0007] Some integrated circuit memory cells are volatile and require power to maintain the data stored in the cell. Examples of volatile memory include dynamic random access memory (DRAM) and static random access memory (SRAM).

[0008] Some integrated circuit memory cells are nonvolatile and retain stored data even when power is not supplied. Examples of nonvolatile memory include flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM). Flash memory includes NAND-type flash memory or NOR-type flash memory. NAND memory cells are based on NAND logic gates, and NOR memory cells are based on NOR logic gates.

[0009] Cross-point memory (such as 3D XPoint memory) uses an array of non-volatile memory cells. The memory cells in cross-point memory are transistor-free. Each of such memory cells may have a selector device and optionally a phase change memory device, which are stacked together as a column in an integrated circuit. The memory cells of such a column are connected in the integrated circuit via two layers of wires extending in directions perpendicular to each other. One of the two layers is above the memory cell; and the other layer is below the memory cell. Thus, each memory cell can be individually selected at the intersection of two wires extending in different directions in the two layers. Cross-point memory devices are fast and non-volatile and can be used as a unified memory pool for processing and storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

[0011] Figure 1 is a diagram illustrating the quantized Gnu transform.

[0012] Figure 2 is a block diagram illustrating the decoding process using a dedicated error correction code matrix.

[0013] Figure 3 is a flow chart illustrating a method for decoding codewords and processing syndromes according to some of the disclosed embodiments.

[0014] Figure 4 is a block diagram illustrating a memory system according to some embodiments of the present disclosure.

[0015] Figure 5 is a block diagram illustrating a computing device showing an example of a client or server device used in various embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] The disclosed embodiments relate to performing error correction on codewords stored in a memory device or similar type of storage device. The disclosed embodiments utilize an extended error code correction (ECC) matrix that exploits properties of codewords balanced using a Quantized Knuth (QK) procedure.

[0017] In some aspects, the technology described herein relates to a method comprising: receiving a standard error code correction (ECC) matrix, the standard ECC matrix comprising a portion for checking a payload and a portion for checking a parity check of the payload; and extending the ECC matrix to form an extended matrix by adding multiple rows and multiple columns to form an upper matrix and a lower matrix, wherein the multiple rows and columns comprise at least one all-zero portion, at least one portion for checking a quantized Knuth (QK) index, and a portion for checking a parity check of the QK index.

[0018] In some aspects, the technology described herein relates to a method wherein the at least one all-zero portion comprises three all-zero portions, wherein a first all-zero portion and a second all-zero portion are included in the upper matrix and a third all-zero portion is included in the lower matrix.

[0019] In some aspects, the techniques described herein relate to a method wherein the at least one portion for checking QK indices includes an upper portion for checking the QK indices in the upper matrix and a lower portion for checking the QK indices in the lower matrix.

[0020] In some aspects, the techniques described herein relate to a method wherein the portion used to check parity of the QK index is included in the upper matrix.

[0021] In some aspects, the technology described herein relates to a method in which an expansion matrix has the form: Wherein All01 represents the first all-zero part, All02 represents the second all-zero part, All03 represents the third all-zero part, QKU represents the upper part for checking the QK index, QKL represents the lower part for checking the QK index, QKP represents the part for checking the parity of the QK index, UD represents the part for checking the payload, and UDP represents the part for checking the parity of the payload and the QK index.

[0022] In some aspects, the techniques described herein relate to a method, further comprising inputting a codeword into the spreading matrix to generate a syndrome, the codeword comprising user data, a QK index, and parity bits, the syndrome comprising an upper portion generated based on the QK index and parity bits associated with the QK index, and a lower portion generated using the user data, the QK index, and parity bits associated with the user data.

[0023] In some aspects, the technology described herein relates to a method comprising: inserting a codeword into a parity-check matrix to obtain syndromes, the codeword comprising a payload, a quantized Knuth (QK) index, and parity bits, the syndromes comprising an upper syndrome and a lower syndrome; determining, based on the upper syndrome and the lower syndrome, that there is an error in the QK index; iteratively updating the QK index to produce a new codeword; inserting the new codeword into the parity-check matrix until an error is detected only in the payload or in a portion of the parity bits associated with the payload; correcting the error; reversing grouping of the payload based on the corrected QK index; and returning a corrected payload.

[0024] In some aspects, the techniques described herein relate to a method that further includes generating the QK index by generating an all-zero value.

[0025] In some aspects, the techniques described herein relate to a method wherein the QK index comprises one-hot encoded packet positions relative to a number of packets that are reversed.

[0026]

[0014] In some aspects, the techniques described herein relate to a method, wherein the reversed packet includes parity bits and QK index bits.

[0027] In some aspects, the technology described herein relates to a method wherein determining, based on the upper syndrome and the lower syndrome, that there is an error in the QK index comprises: determining that the syndrome comprises a plurality of non-zero values; determining that the upper syndrome contains a non-zero value; and determining that the error is not solely in the QK index.

[0028] In some aspects, the techniques described herein relate to a method in which iteratively updating the QK index to generate a new codeword includes iterating through a series of one-hot encoded values ​​starting from 1.

[0029] In some aspects, the technology described herein relates to a method in which determining that an error is only in the payload or in a portion of the parity bits associated with the payload includes determining that the upper syndrome contains all zeros.

[0030] In some aspects, the techniques described herein relate to a method comprising: receiving a payload and a parity portion; generating first quantized Knuth (QK) indices comprising one-hot encoded zero values; adding the QK indices to the payload and parity portion to generate a codeword; inserting the codeword into a parity-check matrix to generate syndromes, the syndromes comprising upper and lower syndromes; and correcting the codeword based on contents of the upper and lower syndromes.

[0031] In some aspects, the techniques described herein relate to a method in which correcting the codeword based on contents of the upper and lower syndromes includes determining that the syndrome contains all zeros and returning the codeword.

[0032] In some aspects, the technology described herein relates to a method wherein correcting the codeword based on contents of the upper and lower syndromes includes determining that the syndrome contains a single non-zero value, correcting errors in the parity portion using an ECC1 engine, and returning a corrected payload.

[0033] In some aspects, the technology described herein relates to a method wherein correcting the codeword based on contents of the upper and lower syndromes includes determining that the syndromes include a plurality of non-zero values ​​and the upper syndrome contains an all-zero value and correcting one or more errors in the payload or parity portion and returning a corrected payload.

[0034] In some aspects, the technology described herein relates to a method wherein correcting the codeword based on contents of the upper and lower syndromes includes determining that the syndromes include a plurality of non-zero values ​​and that the upper syndromes contain the non-zero values, correcting errors in the QK indices to obtain corrected QK indices, inverting a subset of the codeword based on the corrected QK indices, and returning a corrected payload.

[0035] In some aspects, the technology described herein relates to a method wherein correcting the codeword based on contents of the upper syndrome and lower syndrome includes determining that the syndrome includes multiple non-zero values, the lower syndrome contains at least one non-zero value, and the upper syndrome contains at least one non-zero value and iteratively updating the QK index to generate a new codeword.

[0036] In some aspects, the technology described herein relates to a method, further comprising: inserting the new codeword into the parity-check matrix until errors are detected only in bits of the payload or the parity portion associated with the payload; correcting the errors; and returning a corrected payload.

[0037] Figure 1This is a diagram illustrating the QK transformation.

[0038] In the QK transform, a given payload is quantized into packets. For example, Figure 1 The payload 102 in FIG. 1 is quantized into four packets: P0, P1, P2, and P3. Generally, the packets will have the same length, and if the payload is not divisible by the packet length, one or more packets may be padded with zeros. In some implementations, the packet size may be selected based on the properties of the ECC. For example, the Bose-Chaudhuri-Hocquenghem (BCH) code, which can correct up to two errors, has a Hamming distance of 5. In this scenario, a packet size equal to or greater than a Hamming distance of 5 may be used.

[0039] The goal of the QK transformation is to balance the 1s and 0s in the payload by sequentially inverting the bits of the packets until the ratio of 1s to 0s meets the error tolerance. To do this, the transformation begins with the uninverted payload 106. First, the QK algorithm inverts packet P0 and examines the resulting payload 108. If the ratio of 0s to 1s in payload 108 does not meet the required threshold, the algorithm inverts the next packet, P1, resulting in both packets P0 and P1 being inverted in payload 110. If the ratio of 0s to 1s in payload 110 does not meet the required threshold, the algorithm continues similarly, inverting packet P2 to obtain payload 112, inverting packet P3 to obtain payload 114, and so on.

[0040] Once the algorithm determines that the ratio of the payload meets the required threshold, the algorithm ends and outputs the position. This position represents the last reversed packet in the payload and is illustrated as a one-hot encoding 104. Thus, as illustrated, bits "0000" indicate that no packets are reversed, bits "1000" indicate that P0 is reversed, "0100" indicates that packets P0 and P1 are reversed, "0010" indicates that P0 through P2 are reversed, and so on.

[0041] It is important to note that an error margin or threshold is used because the ratio of 1s to 0s may not be exactly 1:1. Therefore, the threshold will define the tolerance that can be used to terminate the algorithm (e.g. 1:1.25).

[0042] When a system employing the QK algorithm writes a payload, it writes the inverted bits. Thus, although corresponding to the original payload 106, the payload 110 contains the inverted bits of P0 and P1 when it is written. Therefore, the QK index (represented in the one-hot encoding 104) should also be stored. This is because the reading algorithm must invert P0 and P1 of the payload 110 to obtain the payload 106. To do this, it must know which packets were inverted. Since the QK algorithm continuously inverts packets, it is sufficient to store the identity of the last inverted packet.

[0043] Balancing the number of ones and zeros in the payload of a NAND flash memory device can improve the reliability and lifespan of the device. In NAND flash memory, data is stored by creating and interrupting charges on memory cells. Furthermore, in some types of NAND flash memory devices, balancing will improve the reliability of the sensing technology used in such devices. Furthermore, a balanced payload can help improve the efficiency of error correction algorithms, which can further enhance the reliability and performance of the device. Furthermore, because the grouping is selected based on the Hamming distance of the ECC code, consistency between the parity bits and the QK-processed payload is maintained. It is worth noting that in the following examples, the ECC algorithm can be assumed to be invariant, as consistency is maintained regardless of whether the grouping bits are inverted. That is, the ECC algorithm will produce the same parity bits for the grouping or its inversion.

[0044] In some systems, the QK index data is not persisted in memory. For example, if the QK index is stored in a one-hot encoding, during a read operation, the QK index data can be assumed to be all zeros, and the ECC power can be increased to detect errors in the QK index data, if any. Since the one-hot encoding uses only one bit, the increased ECC power will enable the QK index encoding to be recreated at the expense of more complex and time-consuming processing.

[0045] Figure 2 is a block diagram illustrating the decoding process using a dedicated error correction code (ECC) matrix.

[0046] In the illustrated implementation, codeword 228 may be inserted into the ECC engine ( Figure 2 228, but described elsewhere). The ECC engine stores a parity check matrix 230. Briefly, the ECC engine uses the codeword 228 and the parity check matrix 230 to calculate a syndrome 232. The parity check matrix 230 represents a series of linear relationships (i.e., coefficients of the parity check equation) that define the ECC code. The details of calculating the syndrome are not described in detail herein, nor is any acceptable method for calculating the syndrome using the parity check matrix (e.g., performing a matrix multiplication between the parity check matrix 230 and the codeword 228 to generate the syndrome 232). If the syndrome is an all-zero value, then the codeword 228 contains no errors. In contrast, if the syndrome contains a non-zero value (i.e., 1), then the codeword 228 contains one or more errors.

[0047] In the illustrated implementation, the codeword 228 includes three parts: a payload 202, a quantized Knuth index (QK index 204), and a parity portion 206. In some implementations, the payload 202 and the parity 206 may be read from a memory device, while the QK index 204 may be synthesized and not stored in the memory device.

[0048] Payload 202 can contain any type of user data and the specific content of payload 202 is not intended to be limiting. Generally speaking, payload 202 will contain binary data of a given length. As a continuous example, payload 202 can contain 128 bits of binary data.

[0049] The QK index 204 may include an encoded QK index. Details of generating the QK index are given in Figure 1 The QK index 204 may be encoded using a one-hot coding scheme, a thermometric coding scheme, a binary coding scheme, a Gray coding scheme, or a similar type of coding scheme. For example, a one-hot coding value of "0000" may indicate that no inversion has been performed, while a value of "1000" may indicate that all packets of the payload 102 have been inverted. For further details on the QK algorithm, please refer to Figure 1 .

[0050] Parity check portion 206 may include a set of parity check bits calculated using a generator matrix. As with other ECCs, the generator matrix may include the matrix inverse of a parity check matrix 230. For brevity, the specific details of such a matrix are not expanded herein. The specific size of parity check portion 206 may be configured based on the needs of the system. In some embodiments, the ECC associated with parity check matrix 230 may include a Bose-Chaudhuri-Hokkewenheim (BCH) code, which may include a configurable number of parity check bits. In some embodiments, a specific ECC code may include an ECC1 code (i.e., a code that can correct a single error).

[0051] The illustrated parity check matrix 230 represents an extended parity check matrix. As an example, if the codeword 228 includes only the payload 202 and the parity check portion 206, then the standard parity check matrix may include only the payload check portion 216 and the parity check portion 220. These two portions, when combined, will form a standard parity check matrix for the standard codeword. However, since the codeword 228 includes the QK index 204, this standard parity check matrix is ​​extended to include additional coefficients for the QK index 204 (e.g., QK index lower 218). Furthermore, as will be discussed, additional rows are added to the parity check matrix in the form of an upper parity check matrix portion that includes an all-zero portion 208, a QK index upper 210, an all-zero portion 212, and a QK parity check portion 214. Herein, the all-zero portion 208, QK index upper 210, all-zero portion 212, and QK parity portion 214 are collectively referred to as the "upper matrix," while the payload check portion 216, QK index lower 218, and parity portion 220 are collectively referred to as the "lower matrix."

[0052] The specific contents of QK index upper 210, QK parity portion 214, payload check portion 216, QK index lower 218, and parity portion 220 will include coefficients based on the underlying ECC parity check equation. The specific values ​​of the matrix are not limiting. The contents of all zero portion 208, all zero portion 212, and all zero portion 222 will include the zero values ​​in parity check matrix 230.

[0053] As illustrated, the resulting syndrome 232 is divided into two parts: an upper syndrome 224 and a lower syndrome 226. The syndrome value of the upper syndrome 224 is calculated by multiplying the codeword 228 by the upper matrix, while the syndrome value of the lower syndrome 226 is calculated by multiplying the codeword 228 by the lower matrix. The use of all-zero portions (e.g., all-zero portion 208, all-zero portion 212, and all-zero portion 222) affects which portions of the codeword 228 will affect the syndrome 232. Specifically, due to the all-zero portion 208, any errors in the payload 202 will not affect the upper syndrome 224, and further due to the all-zero portion 212, the upper syndrome will not be affected by the user data entries in the parity portion 206. Specifically, the QK parity portion 214 may be associated with the parity bits generated for the QK index 204, while the parity portion 220 may be associated with the parity bits associated with the payload 202. As an example, if the parity portion 206 includes the bits "010101," then the first three may be generated for the payload 202, while the last three may be generated for the QK index 204. The specific size of each is not limiting.

[0054] In the illustrated embodiment, QK index upper 210 and QK index lower 218 may include parity check coefficients to check for errors within QK index 204. Specifically, in some embodiments, the generated QK index value may not be stored in persistent storage. In contrast, when one-hot encoding is used, QK index 204 may be set to an all-zero value. With this configuration, QK index 204 will contain no errors or one error (the one-hot position of the packet being the last inverted packet) if no packets are inverted. If an error occurs in payload 202, there may be two errors (one in QK index 204 and one in payload 202).

[0055] To accommodate the double error scenario, the parity check matrix 230 must meet two requirements. First, the matrix must be able to correct one error in the QK index bits and one error in the payload bits. Second, the matrix must be able to Figure 1 The QK algorithm described in

[15] is used for balancing.

[0056] Regarding the first requirement, when errors are detected in both payload and QK index, the resulting parity check matrix must distinguish this case from other errors in payload and QK index bits, from any single error case, and from error-free syndromes.

[0057] The parity check matrix achieves this by ensuring that a simple signature in syndrome 232 occurs when a QK inversion is performed. This is achieved by using an all-zero portion 208, which ensures that the column associated with the QK index in the parity check matrix is ​​not all zeros in the upper matrix. The upper matrix is ​​only affected by inversions (e.g., non-zero QK indices) and / or errors in the QK parity bits. In this way, a simple syndrome signature can be obtained when the upper portion of the syndrome is not all zeros.

[0058] In order to decode the syndrome that occurs when there is an error in the QK parity part and / or the QK index (referred to as the "reference syndrome" in the following paragraphs), a possible syndrome value must be different from other possible values.

[0059] Generally speaking, four error scenarios must be considered to ensure this differentiation. First, when one error is in the QK parity portion and the other error is in the QK index, any reference syndrome must be different from any other syndrome generated. This means that the columns associated with QK upper index 210 and QK lower index 218 must differ by at least three bits. Second, any reference syndrome must be different from any other single error that occurs only in the QK parity portion 214. This means that the columns associated with QK upper index 210 and QK lower index 218 must contain at least three bits set to 1. Third, any reference syndrome must be different from any other single error in the QK index 204. This means that the columns associated with QK upper index 210 and QK lower index 218 must contain at least two bits set to 1. Fourth, any reference syndrome must be different from any other single error in the payload 202. This means that the columns associated with the all-zero portion 208 must be all zeros.

[0060] As discussed above, the matrix must be such that Figure 1The QK algorithm described in

[15] is balanced. Under this requirement, the exclusive OR (XOR) of the columns associated with the constituent packets must be all zeros, and all bits of the message must be included in the packet. The use of the all-zero portion 208 imposes additional constraints on the parity check matrix. According to the QK procedure, assuming a packet size of five, a given packet will contain two QK index bits and three additional bits (payload bits or parity bits). If other packet sizes are used, there will still be two QK index bits, but the number of other bits may increase or decrease. Since the all-zero portion 208 is all zero, the QK index 210 should be compensated only with the QK parity bits from the parity portion 206. Therefore, each packet will contain two QK index bits, one or more QK index parity bits, and user data bits. Therefore, the QK index parity bits will be used by multiple packets and may be inverted multiple times during the QK process to obtain a balanced message.

[0061] If QK parity bits are included within a packet, this will increase the total number of packets for the codeword. Therefore, in some embodiments, the packets can be constructed in a specific way. First, each packet can contain two consecutive QK index bits. Second, the first QK index bit can be shared with the previous packet. Third, the columns of the parity check matrix associated with the second QK index bit should be as similar as possible to the columns of the first QK index bit. In other words, the QK index list and order must be selected to minimize the differences between the columns associated with consecutive QK indices. In general, the Hamming distance between the columns of two QK index bits in the same packet should be as low as possible. Furthermore, in some embodiments, if some bits are inverted multiple times through the packet, this number should be an odd number to ensure that they retain the inverted value in the final inversion.

[0062] Figure 3 is a flow chart illustrating a method for decoding codewords and processing syndromes according to some of the disclosed embodiments.

[0063] In step 302, the method may include reading a codeword. In some implementations, the codeword may include a payload and a set of parity bits. In some implementations, the payload may include any type of user data. In some implementations, the parity bits may include a value corresponding to a value in the codeword. Figure 2 In some implementations, the value of the QK index is not stored in a memory device.

[0064] In step 304, the method may include generating a blank QK index value. In some embodiments, the QK index value may be represented as a one-hot write code value. Thus, the method may use the value zero as the QK index value. Of course, in some cases, this may be a correct QK index if no inversion is performed on the payload during writing. However, if any inversion is performed, then the blank value zero will be incorrect. Due to the use of one-hot encoding, this will mean that the blank QK index will only contain one error. Therefore, in step 304, either no errors are introduced into the codeword, or only one error is introduced into the codeword. However, as will be discussed, errors may also occur in the payload, the parity bits associated with the payload, and the parity bits associated with the correct QK index.

[0065] In step 306, the method may include using Figure 2 The parity check matrix described in

[15] is used to generate the syndrome. As discussed, a codeword (including a QK index) can be input into the parity check matrix, and the product of the codeword and the parity check equation can be calculated to output a syndrome. The syndrome will include an upper portion and a lower portion. The upper portion can be calculated by multiplying a blank QK index value with the upper portion of the QK index of the parity check matrix, and by multiplying the QK parity bit with the QK parity portion. Since all other portions of the matrix are all zero, the upper syndrome is only affected by the QK index and its corresponding parity check. In contrast, the lower syndrome is calculated by calculating three products: one between the payload and the payload check portion, one between the QK index and the lower half of the QK index, and one between the payload and the QK index parity bit and the parity check portion. Thus, the lower syndrome is affected by the payload and the payload and QK index parity check, as well as the QK index itself. As with other ECC systems, the syndrome will comprise a one-dimensional vector representing errors in the codeword.

[0066] In step 308, the method may include first determining whether the syndrome contains an all-zero value. If so, the method may determine that the codeword is valid and contains no errors. Thus, in step 310, the method may return the payload. Since a blank QK index is used, the method may assume that no inversion was performed during the QK procedure, and therefore no inversion is required before returning the payload.

[0067] In step 312, if the syndrome includes at least one non-zero value (i.e., 1), the method may then count the number of non-zero values ​​and first determine if only one non-zero value occurs. If so, the method proceeds to step 314. In step 314, the method may determine that an error occurred in the parity bit (due to the constraints discussed above) and may use standard ECC1 correction methods to correct the error. After correcting the error, the method may include returning the payload.

[0068] In contrast, if more than one non-zero value appears in the syndrome, the method proceeds to step 316, where it determines whether the upper syndrome contains a non-zero value. If the method determines that the upper syndrome is all zero, the method may assume that no inversion is applied because the product of the QK index and the upper portion of the QK index is zero, and the product of the QK parity and the QK parity portion is also zero. Since a blank QK index is used, this means that a blank QK index (indicating no inversion) is valid. Therefore, any error must have occurred in the user data or parity portion. Therefore, in step 318, the method may correct the error in the user data or parity portion and return the correct payload. As discussed, since ECC1 may be used, step 318 may include correcting a single error in the user data.

[0069] In contrast, if the method determines that the upper syndrome is not all zeros, then the method proceeds to step 320 where it determines whether the syndrome represents an error only in the QK index (a "pure" QKI error).

[0070] As discussed above, this determination can be ensured by a first constraint, namely that the columns associated with the QK upper index and the QK lower index differ by at least three bits. Thus, the method can determine whether at least one bit appears in the upper syndrome. If so, the method can determine that the user data is valid and that the error occurred only in the QK index portion or the QK index itself. In this case, in step 322, the method can use the ECC correction power to correct the QK index value and / or parity bits and then return the payload. Since the QK index is blank and an error is detected in the QK index area, this means that the actual QK index is non-zero. Therefore, in some embodiments, the method may further include performing a QK inversion on the payload based on the corrected QK index to obtain the correct payload before returning the payload.

[0071] On the other hand, if the error is not a pure QKI error, the method proceeds to step 324 where the method attempts to correct one QK index at a time and checks whether the resulting syndrome equals a user data error or a parity bit error.

[0072] In step 324, the method cannot determine whether the syndrome indicates an error in the QK index alone, in the payload or parity alone, or in both the QK index and the payload or parity. Because the QK index is synthesized as a blank value, the method can re-execute itself, synthesizing and incrementing the QK index value and executing the above steps until a decision is reached, until one of steps 310, 314, 318, or 322 is executed. For example, given a four-bit QK index, the method can re-execute setting the QK index to 0001, then to 0010, then to 0100, and then to 1000. At least one of these permutations will clear the error in the QK index portion and reveal whether any errors still exist in the user data or parity portion of the codeword. Once the method reveals this error, it can use the ECC1 correction function to correct the error and return a valid codeword.

[0073] Figure 4 is a block diagram illustrating a memory system according to some embodiments of the present disclosure.

[0074] As in Figure 4 , computing system 400 includes a host processor 402 communicatively coupled to a memory system 404 via a bus 418. Memory system 404 includes a controller 406 communicatively coupled to one or more memory banks 414A-414N forming a memory array via a bus / interface 416. As illustrated, controller 406 includes a local cache 405, firmware 410, and an error correction code (ECC) module 412.

[0075] In the illustrated embodiment, the host processor 402 may comprise any type of computer processor, such as a central processing unit (CPU), a graphics processing unit (GPU), or other type of general-purpose or special-purpose computing device. The host processor 402 includes one or more output ports that allow address, user, and control data to be transferred between the host processor 402 and the memory system 404. In the illustrated embodiment, this communication is performed over a bus 418. In one embodiment, the bus 418 comprises an input / output (I / O) bus or a similar type of bus.

[0076] Memory system 404 is responsible for managing one or more memory banks 414A to 414N. In one embodiment, memory banks 414A to 414N include NAND flash dies or other configurations of non-volatile memory. In one embodiment, memory banks 414A to 414N include memory arrays.

[0077] Memory banks 414A through 414N are managed by controller 406. In some embodiments, controller 406 comprises a computing device configured to mediate access to and from memory banks 414A through 414N. In one embodiment, controller 406 comprises an ASIC or other circuitry mounted on a printed circuit board housing memory banks 414A through 414N. In some embodiments, controller 406 may be physically separate from memory banks 414A through 414N. Controller 406 communicates with memory banks 414A through 414N via interface 416. In some embodiments, this interface 416 comprises a physical wiring (e.g., trace) interface. In other embodiments, interface 416 comprises a standard bus for communicating with memory banks 414A through 414N.

[0078] Controller 406 includes various modules 405 to 412. In one embodiment, various modules 405 to 412 include various physically distinct modules or circuits. In other embodiments, modules 405 to 412 may be fully (or partially) implemented in software or firmware.

[0079] As illustrated, firmware 410 comprises the core of the controller and manages all operations of controller 406. Firmware 410 may implement some or all of the methods described above.

[0080] Figure 5 is a block diagram illustrating a computing device showing an example of a client or server device used in various embodiments of the present disclosure.

[0081] The computing device 500 may include Figure 5 The components shown may be greater or fewer components depending on the deployment or use of device 500. For example, a server computing device (e.g., a rack-mount server) may not include audio interface 552, display 554, keyboard 556, illuminator 558, tactile interface 562, global positioning service (GPS) receiver 564, or camera / sensor 566. Some devices may include additional components not shown, such as a graphics processing unit (GPU) device, a cryptographic coprocessor, an artificial intelligence (AI) accelerator, or other peripheral devices.

[0082] As shown in the figure, the device 500 includes a central processing unit (CPU) 522, which communicates with a mass storage device 530 via a bus 524. The computing device 500 also includes one or more network interfaces 550, an audio interface 552, a display 554, a keyboard 556, an illuminator 558, an input / output interface 560, a tactile interface 562, an optional global positioning system (GPS) receiver 564, and a camera or other optical, thermal, or electromagnetic sensor 566. The device 500 may include one camera / sensor 566 or multiple cameras / sensors 566. The location of the camera / sensor 566 on the device 500 may vary depending on the device 500 model, the device 500 capabilities, and the like, or some combination thereof.

[0083] In some embodiments, CPU 522 may include a general-purpose CPU. CPU 522 may include a single-core or multi-core CPU. CPU 522 may include a system on chip (SoC) or a similar embedded system. In some embodiments, a GPU may be used instead of CPU 522, or used in combination with CPU 522. Mass storage 530 may include a dynamic random access memory (DRAM) device, a static random access memory device (SRAM) or a flash (e.g., NAND flash) memory device. In some embodiments, mass storage 530 may include a combination of such memory types. In one embodiment, bus 524 may include a peripheral component interconnect express (PCIe) bus. In some embodiments, bus 524 may include multiple buses instead of a single bus.

[0084] Mass storage 530 illustrates another example of a computer storage medium for storing information such as computer-readable instructions, data structures, program modules, or other data. Mass storage 530 stores a basic input / output system ("BIOS") 540 for controlling low-level operations of computing device 500. In the illustrated embodiment, BIOS 540 may be stored in a read-only memory (ROM), such as ROM 534. Mass storage also stores an operating system 541 for controlling the operation of computing device 500.

[0085] The application 542 may include computer-executable instructions that, when executed by the computing device 500, perform any of the methods (or portions of methods) previously described in the description of the preceding figures. In some embodiments, software or programs implementing method embodiments may be read from a hard drive (not illustrated) and temporarily stored in the RAM 532 by the CPU 522. The CPU 522 may then read the software or data from the RAM 532, process it, and store it again in the RAM 532.

[0086] Computing device 500 may optionally communicate with a base station (not shown) or directly with another computing device.Network interface 550 is sometimes called a transceiver, transceiver device, or network interface card (NIC).

[0087] Audio interface 552 generates and receives audio signals such as sounds of human speech. For example, audio interface 552 may be coupled to a speaker and microphone (not shown) to enable remote communication with others or to generate audio confirmation of an action. Display 554 may be a liquid crystal display (LCD), gas plasma, light emitting diode (LED), or any other type of display used with a computing device. Display 554 may also include a touch-sensitive screen arranged to receive input from an object such as a stylus or digits from a human hand.

[0088] Keypad 556 may include any input device arranged to receive input from a user. Illuminator 558 may provide a status indication or provide light.

[0089] The computing device 500 also includes a computer for using, for example, USB, infrared, An input / output interface 560 for communicating with external devices using a communication technology such as ATTACH® or similar. A tactile interface 562 provides tactile feedback to a user of the client device.

[0090] The optional GPS receiver 564 can determine the physical coordinates of the computing device 500 on the Earth's surface, typically outputting the location as latitude and longitude values. The GPS receiver 564 can also employ other geolocation mechanisms, including but not limited to triangulation, assisted GPS (AGPS), E-OTD, CI, SAI, ETA, BSS, or the like, to further determine the physical location of the computing device 500 on the Earth's surface. However, in one embodiment, the computing device 500 can communicate through other components that provide other information that can be used to determine the device's physical location, including, for example, a MAC address, an IP address, or the like.

[0091] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0092] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0093] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of magnetic disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0094] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the methods. The structure of various such systems will appear as set forth in the appended claims. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0095] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0096] In this description, various functions and operations are described as being performed or caused by computer instructions to simplify the description. However, those skilled in the art will recognize that such expressions mean that the functions are generated by one or more controllers or processors (e.g., microprocessors) executing computer instructions. Alternatively, or in combination, the functions and operations may be implemented using dedicated circuitry with or without software instructions, such as using an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Embodiments may be implemented using hard-wired circuitry without or in combination with software instructions. Thus, the technology is not limited to any specific combination of hardware circuitry and software, nor to any specific source of instructions executed by the data processing system.

[0097] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A method comprising: Receive error code correction (ECC) matrix; and The ECC matrix is ​​extended to form an extended matrix including an all-zero portion, a portion for checking a quantized Knuth (QK) index, and a portion for checking a parity of the QK index.

2. The method of claim 1, wherein the all-zero portion comprises three all-zero portions, wherein a first all-zero portion and a second all-zero portion are included in an upper matrix of the extended matrix, and a third all-zero portion is included in a lower matrix of the extended matrix.

3. The method of claim 2, wherein the portion for checking QK indices comprises an upper portion for checking the QK indices in the upper matrix and a lower portion for checking the QK indices in the lower matrix. 4 . The method of claim 3 , wherein the portion for checking parity of the QK index is included in the upper matrix.

5. The method according to claim 4, wherein the expansion matrix has the following form: in All01 represents the first all-zero part, All02 represents the second all-zero part, All03 represents the third all-zero part, QKU represents the upper part for checking the QK index, QKL represents the lower part for checking the QK index, QKP represents the part for checking the parity of the QK index, ID represents a part for checking the payload, and UDP represents a part for checking the parity of the payload and the QK index.

6. The method of claim 1 , further comprising inputting a codeword into the spreading matrix to generate a syndrome, the codeword comprising user data, a QK index, and parity bits, the syndrome comprising an upper portion generated based on the QK index and parity bits associated with the QK index, and a lower portion generated using the user data, the QK index, and parity bits associated with the user data.

7. A method comprising: Inserting a codeword into a parity check matrix to obtain an upper syndrome and a lower syndrome, the codeword comprising a payload, a quantized Knuth (QK) index, and a parity bit; Updating the QK index to generate a new codeword; inserting the new codeword into the parity check matrix until an error is detected only in the payload or in a portion of the parity bits associated with the payload; correcting the error; reversing grouping of the payload based on the corrected QK index; and Returns the corrected payload.

8. The method of claim 7, further comprising generating the QK index by generating an all-zero value.

9. The method of claim 7, wherein the QK index comprises one-hot encoded group positions relative to a number of groups that are reversed.

10. The method of claim 9, wherein the reversed packet includes parity bits and QK index bits.

11. The method of claim 7, wherein determining that an error exists in the QK index based on the upper syndrome and the lower syndrome comprises: Determining that the syndrome includes a plurality of non-zero values; Determining that the upper syndrome contains a non-zero value; and It is determined that the error is not only in the QK index.

12. The method of claim 7, wherein iteratively updating the QK index to generate a new codeword comprises iterating through a series of one-hot encoded values ​​starting from 1.

13. The method of claim 7, wherein determining that errors are only in the payload or in a portion of the parity bits associated with the payload comprises determining that the upper syndrome contains all zeros.

14. A method comprising: Receive the payload and parity part; generating a first quantitative Gartner (QK) index; Adding the QK index to the payload and parity portion to generate a codeword; Inserting the codeword into a parity check matrix to generate an upper syndrome and a lower syndrome; and The codeword is corrected based on the upper syndrome and the lower syndrome.

15. The method of claim 14, wherein correcting the codeword based on the contents of the upper and lower syndromes comprises determining that the syndrome contains all zeros and returning the codeword.

16. The method of claim 14, wherein correcting the codeword based on the contents of the upper and lower syndromes comprises determining that the syndrome contains a single non-zero value, correcting errors in the parity portion using an ECC1 engine, and returning a corrected payload.

17. The method of claim 14, wherein correcting the codeword based on the contents of the upper and lower syndromes comprises determining that the syndromes include a plurality of non-zero values ​​and the upper syndrome contains an all-zero value and correcting one or more errors in the payload or parity portion and returning a corrected payload.

18. The method of claim 14 , wherein correcting the codeword based on contents of the upper and lower syndromes comprises determining that the syndromes include a plurality of non-zero values ​​and that the upper syndromes contain the non-zero values, correcting errors in the QK indexes to obtain corrected QK indexes, inverting a subset of the codeword based on the corrected QK indexes, and returning a corrected payload.

19. The method of claim 14, wherein correcting the codeword based on contents of the upper syndrome and the lower syndrome comprises determining that the syndrome includes a plurality of non-zero values, the lower syndrome contains at least one non-zero value, and the upper syndrome contains at least one non-zero value and iteratively updating the QK index to generate a new codeword.

20. The method of claim 19, further comprising: inserting the new codeword into the parity check matrix until errors are detected only in bits of the payload or the parity portion associated with the payload; correcting the error; and Returns the corrected payload.

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