Real-time circuit line resistance-capacitance detection

Abstract

The invention relates to real-time circuit line resistance-capacitance detection. A resistance-capacitance (RC) sensor circuit is provided. The circuit includes: a regulator configured to drive a circuit line; one or more current mirrors coupled to the regulator to obtain a representative copy of the current of the circuit line; and an integrator including an analog-to-digital converter (ADC). The ADC is coupled to the one or more current mirrors to receive the representative replica of the current of the circuit line and is configured to: integrate the representative replica of the current of the circuit line over a plurality of time intervals to obtain a plurality of charges associated with the respective time intervals; and outputting digital data for calculating the RC time constant. The plurality of time intervals are within a first ramp period that ramps a distal voltage of the circuit line from a first voltage value to a second voltage value.

Description

[0001] This application claims priority to U.S. Provisional Application No. 63 / 569,014, filed on March 22, 2024, entitled “REAL-TIME CIRCUIT LINE RESISTOR-CAPACITOR DETECTION,” the contents of which are incorporated by reference in their entirety for all purposes. Technical Field

[0002] The present disclosure relates to one or more systems for memory, including techniques for real-time sensing of resistance-capacitance (RC) time constants of circuit lines. Background Art

[0003] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell. Information can also be erased from a memory cell and new information can be stored in the memory cell.

[0004] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described in terms of either a volatile configuration or a non-volatile configuration. Memory cells configured in a non-volatile configuration can maintain a stored logic state for an extended period of time, even in the absence of external power. Memory cells configured in a volatile configuration lose their stored state when disconnected from external power. Summary of the Invention

[0005] In one aspect, the present disclosure provides a resistance-capacitance (RC) sensor circuit, comprising: a regulator configured to drive a circuit line; one or more current mirrors coupled to the regulator to obtain a representative copy of a current of the circuit line; and an integrator comprising an analog-to-digital converter (ADC), the ADC coupled to the one or more current mirrors to receive the representative copies of the current of the circuit line and configured to: integrate the representative copies of the current of the circuit line over a plurality of time intervals to obtain a plurality of charges associated with respective time intervals, wherein the plurality of time intervals are within a first ramping period for ramping a far-end voltage of the circuit line from a first voltage value to a second voltage value, and output digital data for calculating an RC time constant of the circuit line, wherein the digital data is a representation of the plurality of charges.

[0006] In another aspect, the present disclosure further provides a memory device comprising: a memory array; the resistor-capacitor (RC) sensor circuit described above; and a memory controller.

[0007] On the other hand, the present disclosure further provides a memory device comprising: a memory array; a regulator; a resistance-capacitance (RC) sensor circuit configured to sense the RC time constant of a circuit line in the memory device; and a memory controller configured to: cause a proximal voltage of the circuit line to change from a first voltage value to a second voltage value and maintain the proximal voltage of the circuit line at the second voltage value during at least a first ramp period; obtain the RC time constant of the circuit line during the first ramp period; determine a second ramp period based on the RC time constant; and cause the proximal voltage of the circuit line to change from the second voltage value to a third voltage value and maintain the proximal voltage of the circuit line at the third voltage value during the second ramp period, wherein the second ramp period is less than the first ramp period.

[0008] In another aspect, the present disclosure further provides a system comprising: a processor; a circuit; a memory device coupled to the processor, the memory device being any of the memory devices described above.

[0009] On the other hand, the present disclosure further provides a method for detecting defects in a target circuit line, the method being performed at least in part using a memory device including a memory array, a resistor-capacitor (RC) sensor circuit, and a memory controller, the method comprising: obtaining a representative copy of the current of the circuit line by the RC sensor circuit; integrating the representative copy of the current of the circuit line over multiple time intervals to obtain multiple charges associated with the multiple time intervals; obtaining digital data associated with the circuit line, the digital data being a representation of the multiple charges associated with the multiple time intervals; and determining whether the circuit line is defective based on the digital data. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A and 1B Examples of a host system and a memory system supporting techniques for real-time sensing of RC time constants of circuit lines according to examples disclosed herein are described.

[0011] Figure 1C is a block diagram of a memory device in communication with a memory system controller of a memory system according to examples disclosed herein.

[0012] Figures 2A to 2C is an illustrative schematic diagram of a portion of a memory cell array in a memory device according to examples disclosed herein.

[0013] Figure 2D An example of a memory device including multiple memory cell blocks according to examples disclosed herein is described.

[0014] Figure 3 is a block diagram of an example device for implementing one or more systems and for performing one or more methods described herein according to examples disclosed herein.

[0015] Figure 4 is a block diagram of an example memory system supporting techniques for real-time sensing of RC time constants of circuit lines according to examples disclosed herein.

[0016] Figure 5A is a schematic diagram of an example word line regulator driving a word line according to examples disclosed herein.

[0017] Figure 5B is an example relationship between word line current and time for the same time constant with different resistance and capacitance values ​​according to examples disclosed herein.

[0018] Figure 5C is a schematic diagram of an example word line regulator according to examples disclosed herein.

[0019] Figure 6A is a schematic diagram of an example word line regulator and an example current mirror for obtaining representative copies of pull-up and pull-down currents according to examples disclosed herein.

[0020] Figure 6B is a schematic diagram of an example word line regulator and another example current mirror for obtaining a representative copy of the pull-up current according to examples disclosed herein.

[0021] Figure 6C is a schematic diagram of an example word line regulator and an example current mirror for obtaining a representative copy of a resistor divider current according to examples disclosed herein.

[0022] Figure 6D is a schematic diagram of an example word line regulator and an example current source for obtaining a representative copy of a resistor divider current according to examples disclosed herein.

[0023] Figure 7A is a schematic diagram of an example RC sensor circuit including a regulator, a current mirror, and an integrator according to examples disclosed herein.

[0024] Figure 7B is an example relationship between word line current and digital data representing the word line current according to examples disclosed herein.

[0025] Figure 8A is an example relationship of proximal word line voltage, distal word line voltage, and word line current with respect to time in a read operation according to examples disclosed herein.

[0026] Figure 8B is an example relationship of proximal word line voltage and distal word line voltage with respect to time in a programming operation according to examples disclosed herein.

[0027] Figure 9 The description shows a flow chart showing one or several methods supporting techniques for optimizing access operations using real-time RC time constant measurements according to examples disclosed herein.

[0028] Figure 10A and 10B The description shows a flow chart showing one or several methods supporting techniques for detecting defects in target circuit lines according to examples disclosed herein. DETAILED DESCRIPTION

[0029] In a memory device or any semiconductor device, circuit lines are present. These lines are used to conduct voltage and / or current signals. They can be made of metals, alloys, or semiconductor materials (e.g., doped polysilicon). For example, circuit lines in a memory device include word lines, bit lines, select lines (e.g., source select lines or SGS lines, drain select lines or SGD lines), common source (e.g., SRC) lines, and the like. The description herein uses word lines in a memory device as an example, but it should be understood that the concepts are applicable to other types of circuit lines in a memory device or any other semiconductor device.

[0030] A circuit line can also be referred to as a transmission line for transmitting signals. A circuit line can be loaded and therefore associated with resistance and capacitance. Therefore, the time required for a signal to ramp up or down at the near end of the circuit line may be different from the time required for the signal to ramp up or down at the far end of the circuit line. This is called the propagation delay of the circuit line. The propagation delay of a circuit line is related to the resistance (R) and capacitance (C) of the circuit line and can be measured by the RC time constant, which is the product of resistance and capacitance. A memory device has many circuit lines, such as word lines. Using word lines as an example, the circuit configuration and manufacturing process inevitably cause word lines to differ in many ways. Therefore, the RC time constant of a word line can vary depending on the semiconductor die, block, and / or word line. These variations in the RC time constant of a word line, in turn, change the propagation delay of the word line. As a result, memory device operations (such as reading, programming, and erasing) can be negatively affected (e.g., slowed down).

[0031] In addition to variations in wordline RC time constants, the manufacturing process of a memory device can lead to wordline defects, including open wordline defects and short wordline defects. An open wordline defect (or any circuit line defect) has a discontinuity or interruption in the conduction path, preventing current from flowing. A short wordline defect (or any circuit line defect) occurs when an unintended connection exists between two points on a wordline and another part of the circuit with very low or negligible resistance (e.g., another wordline), thereby bypassing the intended load or resistance or bypassing the intended insulation. Both open and short wordline defects are undesirable and can be costly. If too many wordline defects exist, a memory device can become excessively leaky, unreliable, nonfunctional, prone to data loss, or completely inoperable.

[0032] To characterize or detect wordline RC time constant variations and / or wordline defects as described above, measuring the wordline RC time constant is desirable or advantageous. For example, measuring the RC time constant of each of many wordlines in a memory device can provide an estimate of the propagation delay or ramp-up / down rate of different wordlines. Measuring the RC time constant can also provide an indication of whether any particular wordline may be open or shorted. In some implementations, RC time constant measurements can be performed in real time to improve efficiency. As described in this disclosure, real-time measurements are integrated into or become part of memory operations (e.g., read, write, or erase operations). Real-time measurements can be used to optimize the timing of the same operation or subsequent operations. Real-time measurement of wordline RC time constants can be used to compensate for wordline RC time constant variations across different wordlines, thereby optimizing or improving the time allocated for memory device operations (e.g., read, program, erase). Currently, without using the real-time RC time constant measurement techniques described herein, firmware assumes that all wordlines have a worst-case (e.g., maximum) RC time constant for each memory device operation (e.g., read, program, erase). That is, all word lines are assumed to propagate signals as slowly as the word line with the largest RC time constant. This assumption is made to ensure that sufficient time is allocated to complete operations on all word lines. However, some or most word lines may not have the worst-case RC time constant, and thus assuming that all word lines have the worst-case RC time constant results in slow and inefficient operation of some or most word lines. As described in more detail below, using the techniques disclosed herein, the RC time constant of a word line can be measured in the first strobe of an operation and can be used to calculate the time that needs to be allocated to subsequent strobes for the same operation (e.g., read or program), potentially resulting in faster operation (e.g., if the word line does not have the worst-case RC time constant).

[0033] Furthermore, measuring the RC time constant of a wordline can be used to detect defective wordlines. For example, an open wordline may have an abnormally small wordline RC time constant because it is disconnected and therefore has no or a small load on the wordline. Furthermore, when a shorted wordline charges or discharges due to leakage or a short circuit, the wordline may have an abnormal current distribution. For example, the current in the wordline may not reach zero, but may instead have a constant small leakage. Consequently, even after a sufficiently long time, the wordline may not stabilize or reach zero. Furthermore, if a severe short circuit exists between the wordline and other parts of the circuit, the current may be abnormally large. Real-time identification of defective wordlines can therefore help prevent defective memory devices from being used or provided to customers, which in turn prevents potential data loss.

[0034] Figure 1AAn example of a system 100 supporting techniques for real-time sensing of RC time constants according to examples disclosed herein is illustrated. The system 100 includes a host system 105 coupled to a memory system 110. The system 100 can be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (such as an airplane, drone, train, car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0035] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other devices.

[0036] System 100 may include a host system 105 that may be coupled to memory system 110. In some examples, this coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause host system 105 to perform various operations according to the examples described herein. Host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. Host system 105 may be comprised of, for example, Figure 3 300 is implemented as shown in FIG. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). For example, the host system 105 may use the memory system 110 to write data to the memory system 110 and read data from the memory system 110. Although Figure 1A One memory system 110 is shown in FIG. 1 , but the host system 105 can be coupled to any number of memory systems 110 .

[0037] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a Graphics Double Data Rate (GDDR) interface, a DIMM interface (e.g., a DDR-capable DIMM slot interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0038] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory device 130 may include one or more memory arrays of any type of memory cells, such as non-volatile memory cells, volatile memory cells, or any combination thereof. Figure 1A , two memory devices 130-a and 130-b are shown in the example of , but memory system 110 may include any number of memory devices 130. Furthermore, if memory system 110 includes more than one memory device 130, different memory devices 130 within memory system 110 may include the same or different types of memory cells.

[0039] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory devices 130 to perform operations such as reading data, writing data, erasing data, or refreshing data, and other such operations at the memory devices 130, which can be collectively referred to as access operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0040] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (e.g., error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0041] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP), or any other suitable processor or processing circuitry.

[0042] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or computations related to the functions attributed herein to the memory system controller 115.

[0043] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0044] In some examples, the memory devices 130 may include (e.g., on the same semiconductor die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1A As described in the examples of the present disclosure (e.g., Figure 1CIn the example shown in FIG, local controller 135 is disposed on the same semiconductor die as the memory array (e.g., array 104), and separate memory system controller 115 is disposed on a different die. In other examples, some portions of memory device 130 may be disposed on a first die, and other portions of memory device 130 may be disposed on a second die different from the first die. For example, the first die may include memory cell array 104 and its associated circuitry, such as column decoder 111 and row decoder 108. The second die may include logic circuitry, power circuitry, or other circuitry of device 130. Thus, the second die may include system controller 115, I / O control 112, etc. In this example, the first die does not have a local controller, and the second die includes system controller 115. The first and second dies may be hybrid-bonded together using, for example, through-hole vias (TSVs) to electrically connect them. The first and second dies may also be wafer-bonded using flip-chip bonding techniques, etc. In this disclosure, both the memory system controller 115 and the local controller 135 may be referred to as memory controllers or simply as the first memory controller and the second memory controller. It should be understood that although they may be different controllers, unless otherwise specified, certain operations disclosed herein may be caused or performed by either or both memory controllers.

[0045] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding memory blocks 170, where each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0046] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as single-level cells (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLC) when configured to each store two bits of information, triple-level cells (TLC) when configured to each store three bits of information, quad-level cells (QLC) when configured to each store four bits of information, or more generally, multi-level memory cells. Multi-level memory cells may provide greater storage density relative to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0047] In some cases, a plane 165 may refer to several groups of memory blocks 170, and in some cases, concurrent operations may be performed on different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual memory blocks 170 may be referred to as physical blocks, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, and so on). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells in different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0048] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., be coupled to a common word line), and memory cells in the same string may share a common digit line (which may alternatively be referred to as a bit line) (e.g., be coupled to a common digit line). Example memory cell structures are shown in more detail below using illustrative schematics.

[0049] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity (e.g., at a page granularity or portions thereof) but can be erased at a second granularity (e.g., at a block granularity). That is, a page 175 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., concurrently programmed or read as part of a single program or read operation), and a memory block 170 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., concurrently erased as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 cannot be updated until the entire block 170 containing the page 175 is erased.

[0050] In some cases, an L2P (logical to physical) mapping table may be maintained and data may be marked as valid or invalid at a page granularity level, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be data that may be outdated because a newer or updated version of the data is stored in a different page 175 of the memory device 130. Invalid data may have been previously programmed to an invalid page 175 but may no longer be associated with a valid logical address, such as a logical address referenced by the host system 105. Valid data may be the latest version of this data stored on the memory device 130. A page 175 that contains no data may be a page 175 that has never been written to or has been erased.

[0051] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0052] The system 100 may include any number of non-transitory computer-readable media that support techniques for logical-to-physical table compression. For example, the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware, logic, code) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, such instructions, when executed by the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions described herein.

[0053] In some cases, memory system 110 may compress the L2P map to expand the number of physical addresses mapped by the L2P map. For example, if a group of consecutive entries of an uncompressed L2P map include consecutive physical addresses, memory system 110 may compress the consecutive entries into a single entry that includes the starting physical address of the consecutive physical addresses. Additionally, memory system 110 may include an indication of a starting logical address corresponding to the starting physical address in the compressed entry. To identify a physical address within the compressed entry, memory system 110 may use the indication to determine an offset between a logical address corresponding to the physical address (e.g., a logical address included in a read command for data stored at the physical address) and the starting physical address, and may apply the offset to the starting physical address to determine the physical address. Compressing the L2P map may allow the L2P map to cover an expanded range of the physical address space without increasing the size of the L2P map.

[0054] Figure 1B An example of a system diagram 101 illustrating communication between a host system 105 and a memory system 110 using a kernel and firmware according to examples disclosed herein is shown. System diagram 101 may include memory system 110, kernel 107, and application 109. Memory system 110 may include firmware 119. Firmware 119 may be provided by a controller and / or other circuitry (e.g., a processor) of the memory system. Figure 1A 10 and / or local controller 135). In some examples, as described herein, system 123 may include memory system 110 and kernel 107. Additionally, host system 105 may include kernel 107 and application 109.

[0055] As described above, the memory system 110 may include multiple memory devices configured to store and retrieve data, including non-volatile memory devices and volatile memory devices (such as local memory 120). Firmware 119 may refer to the firmware stored in Figure 1A 10 (e.g., non-volatile memory devices within the memory system 110) and / or the memory array within the local memory 120 shown in FIG. 10. The firmware 119 may provide low-level control functions for the memory system 110. For example, the firmware 119 may serve as an interface between the memory system 110 and other components of the system 123, and the host system 105 may issue access operations to the memory system 110 by interfacing with the firmware 119. In some examples, the firmware 119 may be or be included within or implemented by the memory system controller 115, as described herein with reference to FIG. Figure 1A Description. In some examples, the memory system 110 may store a logical-to-physical mapping that maps logical addresses to physical addresses within a non-volatile memory device (e.g., in a logical-to-physical table). To perform a memory access operation, the memory system 110 may move a portion of the logical-to-physical mapping corresponding to one or more logical addresses (e.g., as indicated by the kernel 107) from a non-volatile memory device to a volatile memory device.

[0056] The kernel 107 may serve as an interface between the host system 105 and components associated with the host system 105, such as the operating system of the host system 105. Furthermore, the kernel 107 may perform resource allocation and file management, among other operations, for the host system 105. For example, an application 109 running within the host system 105 may access information stored within the memory system 110 by issuing a command to the kernel 107 indicating a file to be accessed. The kernel 107 may store mapping information associated with the file. For example, a file may be associated with a file name and may correspond to a range of logical block addresses. The kernel 107 may store mapping information (e.g., a mapping table) that tracks the logical block addresses corresponding to files on the host system 105. In some examples, the application 109 may issue an access command to the kernel 107 indicating the file name, offset, and length associated with the file to be accessed, and the kernel 107 may retrieve one or more logical block addresses corresponding to the file to be accessed. The kernel 107 may then communicate with the firmware 119 to indicate the one or more logical block addresses to the memory system 110, and the memory system 110 may perform access operations based on the one or more logical block addresses.The memory system 110 may communicate the access information to the kernel 107 (eg, via the firmware 119).

[0057] In some examples, kernel 107 may communicate with firmware 119 using information units, such as UFS Protocol Information Units (UPIUs). For example, kernel 107 may issue or receive commands, responses, data, or other information via information units exchanged with firmware 119. An information unit may refer to a data packet that may contain a header segment and one or more transaction-specific fields. In some examples, an information unit may additionally include one or more extended header segments, one or more data segments, or a combination thereof. The header segment of an information unit may indicate information associated with the destination of the information unit, the source of the information unit, a function request, whether additional data or parameters will be transmitted, whether the additional data or parameters are included within the information unit or will be sent in the next information unit, or any combination thereof. Transaction-specific fields may be used for additional fields depending on the operation associated with the information unit. The data segment may be used to include data to be transferred from one device to another.

[0058] In some examples, a command information unit (e.g., a command UPIU) may be an example of an information unit associated with the transmission of a command (e.g., a SCSI command) and may instruct a device to perform a certain operation indicated by the command information unit. For example, the command information unit may include a block descriptor (e.g., a command descriptor block) that may indicate information related to the operation indicated by the command information unit. In some examples, the kernel 107 may transmit the command information unit to the memory system 110 to indicate to the memory system 110 the operation to be performed by the memory system 110.

[0059] In some examples, to perform an access operation, the memory system 110 may load an L2P map associated with the information to be accessed. For example, the memory system 110 may transfer a portion of a logical-to-physical map associated with the information to be accessed from a non-volatile memory device (e.g., NAND memory) of the memory system 110 to a volatile memory device (e.g., SRAM) of the memory system 110. In another example, the host system 105 may notify the memory system 110 of a logical block address range corresponding to an upcoming access operation (e.g., before issuing an access command). The memory system 110 may use the logical block address range to load (e.g., preload, prefetch) the associated portion of the L2P map (e.g., from the non-volatile memory device to the volatile memory device) before receiving an access command instructing the memory system 110 to perform the access operation. Additionally, after the host system 105 issues an access command, the memory system 110 may issue a response to the host system 105 more quickly because the memory system 110 has already loaded the relevant portion of the L2P map associated with the access operation.

[0060] The above description of system diagram 101 is an illustrative example of communication between host system 105 and memory system 110 using kernel 107, application 109, and firmware 119. It should be understood that additional communication methods including function calls, commands, responses, messages, etc. can be implemented using host system 105 and memory system 110 and / or additional systems or components.

[0061] Figure 1C is in accordance with an embodiment with a memory system (e.g. Figure 1A and 1B A simplified block diagram of a memory device 130 communicating with a memory system controller 115 of a memory system 110. Figure 1C As shown in FIG and described in more detail below, memory device 130 includes a memory cell array 104 that is logically arranged into rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., a word line), while memory cells of a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line can be associated with more than one logical row of memory cells and a single data line can be associated with more than one logical column. Memory cells of at least a portion of memory cell array 104 ( Figure 1C ) can be programmed into one of at least two target data states for storing any number of bits of information.

[0062] Continue to refer Figure 1C , row decoding circuitry 108 and column decoding circuitry 111 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 112 for managing the input of commands, addresses, and data to memory device 130, as well as the output of data and status information from memory device 130. Address registers 144 communicate with I / O control circuitry 112 and row decoding circuitry 108 and column decoding circuitry 111 to latch address signals prior to decoding. Row decoding circuitry 108 and column decoding circuitry 111 may be referred to simply as row decoder 108 and column decoder 111, respectively. Command register 124 communicates with I / O control circuitry 112 and local controller 135 to latch incoming commands.

[0063] A memory controller (e.g., a local controller 135 within the memory device 130) controls access to the memory cell array 104 in response to commands and generates status information for the external memory system controller 115. That is, the local controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the memory cell array 104. The local controller 135 communicates with the row decoding circuitry 108 and the column decoding circuitry 111 to control the row decoding circuitry 108 and the column decoding circuitry 111 according to addresses.

[0064] Local controller 135 also communicates with cache registers 118 and data registers 121. In some embodiments, one or more cache registers 118 may collectively form at least a portion of a cache buffer. Cache registers 118, under the direction of local controller 135, latch or buffer incoming or outgoing data to temporarily store data while memory cell array 104 is busy writing or reading other data, respectively. During a programming operation (e.g., a write operation), data may be transferred from cache register 118 to data register 121 for transmission to memory cell array 104; then, the new data may be latched into cache register 118 from I / O control circuitry 112. During a read operation, data may be transferred from cache register 118 to I / O control circuitry 112 for output to memory system controller 115; then, the new data may be transferred from data register 121 to cache register 118. In some embodiments, cache register 118 and / or data register 121 may form at least a portion of page buffer 152 of memory device 130. Page buffer 152 may further include a sensing device, such as a sense amplifier, for sensing the data state of a memory cell in memory cell array 104, for example, by sensing the state of a data line connected to the memory cell. Status register 122 may communicate with I / O control circuitry 112 and local media controller 135 to latch status information for output to memory system controller 115.

[0065] like Figure 1C , memory device 130 receives various control signals from memory system controller 115 via local controller 135 via control link 132. For example, the control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protect signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received via control link 132. In one embodiment, memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from memory system controller 115 via multiplexed input / output (I / O) bus 134 and outputs the data to memory system controller 115 via I / O bus 134.

[0066] For example, a command may be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then may be written into command register 124. An address may be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then may be written into address register 144. Data may be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device and then may be written into cache register 118. The data may then be written into data register 121 for programming memory cell array 104.

[0067] In an embodiment, cache register 118 may be omitted and data may be written directly to data register 121. Data may also be output via input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device. Although reference may be made to I / O pins, these may include any conductive node, such as a conventional conductive pad or conductive bump, that provides an electrical connection to memory device 130 by an external device (e.g., memory system controller 115). Although the above description uses a 16-bit I / O bus 134 as an example, it should be understood that bus 134 may be configured for any number of bits (e.g., 64 bits).

[0068] It will be appreciated by those skilled in the art that additional circuitry and signals may be provided, and Figure 1C The memory device 130 has been simplified. It should be recognized that the reference Figure 1C The functionality of the various block components described is not necessarily separated into distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform Figure 1C Alternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1C Additionally, while specific I / O pins are described according to general conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0069] Figures 2A to 2B FIG. 2 is an example schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array. The memory cell array 200A may be a reference array according to an embodiment of the present invention. Figure 1C 1. An example of a memory array 104 of a memory device 130 is depicted. Memory array 200A includes access lines (e.g., word lines 2020 through 202 N) and data lines (eg, bit lines 2040 to 204 M ). The word lines 202 may be connected to global access lines (eg, global word lines) in a many-to-one relationship ( Figure 2A For some embodiments, memory array 200A may be formed over a semiconductor, which may be doped to have a conductivity type, such as p-type conductivity, such as for forming a p-well, or n-type conductivity, such as for forming an n-well.

[0070] The memory array 200A may be arranged into rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column may include a string of memory cells (eg, nonvolatile memory cells) connected in series, such as NAND strings 2060-206 M Each NAND string 206 can be connected (eg, selectively connected) to a common source (SRC) 216 and can include memory cells 2080-208 N The memory cells 208 may represent non-volatile memory cells for data storage. The memory cells 208 of each NAND string 206 may be connected in series to a select gate 210 (eg, a field effect transistor) (eg, select gates 2100 to 2101). M One of the transistors (eg, which may be a source select transistor, often referred to as a select gate source) and a select gate 212 (eg, a field effect transistor) (eg, select gates 2120 to 212 M One of the select gates 2100 to 210 is connected to the drain select transistor 2100. M The gates 2120 to 2121 may be connected in common to a select line 214 (eg, a source select line (SGS)). M 2 and 3. The select gates 210 and 212 may be commonly connected to a select line 215 (e.g., a drain select line (SGD)). Although depicted as conventional field effect transistors, the select gates 210 and 212 may utilize a similar (e.g., identical) structure as the memory cell 208. The select gates 210 and 212 may represent a plurality of select gates connected in series, wherein each select gate in the series is configured to receive the same or an independent control signal.

[0071] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 of a corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 of a corresponding NAND string 2060. Thus, each select gate 210 can be configured to selectively connect a corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0072] The drain of each select gate 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 may be connected to the memory cell 208 of the corresponding NAND string 2060. N Thus, each select gate 212 can be configured to selectively connect a corresponding NAND string 206 to a corresponding bit line 204 . The control gate of each select gate 212 can be connected to a select line 215 .

[0073] Figure 2A The memory array 200A in can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, where the common source 216, NAND strings 206, and bit lines 204 extend in substantially parallel planes. Alternatively, Figure 2A The memory array 200A in FIG. 2 can be a three-dimensional memory array, for example, where the NAND strings 206 can extend substantially perpendicular to a plane containing the common source 216 and can extend substantially parallel to a plane containing the bit lines 204 .

[0074] The typical structure of the memory cell 208 includes a data storage structure 234 (e.g., a floating gate, a charge trap, and the like) that can determine the data state of the memory cell (e.g., by a change in threshold voltage) and a control gate 236, such as Figure 2A 2. The data storage structure 234 may include both conductive and dielectric structures, with the control gate 236 typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. The memory cell 208 has its control gate 236 connected to (and in some cases forming) the word line 202.

[0075] A column of memory cells 208 may be one NAND string 206 or several NAND strings 206 that are selectively connected to a given bit line 204. A row of memory cells 208 may be the memory cells 208 that are commonly connected to a given word line 202. A row of memory cells 208 may, but need not, include all of the memory cells 208 that are commonly connected to a given word line 202. Rows of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically includes every other memory cell 208 that is commonly connected to a given word line 202. For example, a row of memory cells 208 may be commonly connected to a word line 202. NThe memory cells 208 selectively connected to the even bit lines 204 (eg, bit lines 2040, 2042, 2044, etc.) may be a physical page of memory cells 208 (eg, even memory cells) and are commonly connected to the word line 202. N And the memory cells 208 selectively connected to the odd bit lines 204 (eg, bit lines 2041 , 2043 , 2045 , etc.) may be another physical page of memory cells 208 (eg, odd memory cells).

[0076] Despite Figure 2A The bit lines 2043 to 2045 are not explicitly depicted in the figure, but it is obvious from the figure that the bit lines 204 of the memory cell array 200A can be numbered consecutively from bit line 2040 to bit line 204. M . Other groupings of memory cells 208 commonly connected to a given word line 202 may also define a physical page of memory cells 208. For a particular memory device, all of the memory cells commonly connected to a given word line may be considered a physical page of memory cells. A portion (which may still be an entire row in some embodiments) of a physical page of memory cells (e.g., an upper page or lower page of memory cells) that is read during a single read operation or programmed during a single program operation may be considered a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as those connected to word lines 2020 through 202. N All memory cells of a common word line 202 (e.g., all NAND strings 206 that share a common word line 202). Unless explicitly distinguished, references herein to a page of memory cells refer to memory cells of a logical page of memory cells. A logical page may or may not be the same as a physical page. Although Figure 2A The examples are discussed in conjunction with NAND flash, but the embodiments and concepts described herein are not limited to a particular array architecture or structure, but may include other structures (such as SONOS, phase change, ferroelectric, etc.) and other architectures (such as AND arrays, NOR arrays, etc.).

[0077] Figure 2B Can be used for reference Figure 1B Another schematic diagram of a portion of a memory cell array 200B in a memory device (eg, as part of memory cell array 104) is depicted. Figure 2B Like numbered elements in FIG. 1 correspond to those in FIG. 1 and FIG. 2 . Figure 2A Provide a description. Figure 2BAdditional details are provided for one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B can incorporate a vertical structure that can include semiconductor pillars, where a portion of the pillars can serve as channel regions for memory cells of a NAND string 206. The NAND strings 206 can each be selectively connected to bit lines 2040 through 204 through select transistors 212 (e.g., which can be drain select transistors, often referred to as select gate drains). M The NAND strings 206 are connected to a common source 216 through a select transistor 210 (e.g., which may be a source select transistor, often referred to as a select gate source). Multiple NAND strings 206 may be selectively connected to the same bit line 204. A subset of the NAND strings 206 may be selected by biasing select lines 2150 to 2155. K Each word line 202 is connected to its corresponding bit line 204 to selectively activate a particular select transistor 212 located between each NAND string 206 and the bit line 204. The select transistors 210 can be activated by biasing the select line 214. In some embodiments, each sub-block or string of memory cells has a separate select line 214 from the other sub-blocks or strings. In some embodiments, a pair of sub-blocks share a single select line 214. Each word line 202 can be connected to multiple rows of memory cells in the memory array 200B. The rows of memory cells commonly connected to each other by a particular word line 202 can be collectively referred to as a tier.

[0078] The three-dimensional NAND memory array 200B may include multiple stacked layers of memory cell hierarchies connected using vertical channels (e.g., semiconductor pillars). For example, the number of layers in the three-dimensional NAND memory array 200B may be 32, 48, 64, 96, 112, or any other number of layers. In some examples, groups of layers may be collectively referred to as layers. Layers in a three-dimensional NAND memory array may be processed together (e.g., etched together to form a portion of a semiconductor pillar). A memory device having a three-dimensional NAND memory array may provide more memory cells on a single chip than a memory device formed with a two-dimensional NAND array, and thus provide higher storage capacity. Furthermore, in a memory device having a three-dimensional NAND memory array, the transistors in the memory cells are spaced apart, thereby reducing interference and electron leakage.

[0079] As described above, memory cells can be grouped into memory blocks. Figure 2C Depicts the grouping of NAND strings 206 into memory cell blocks 250, such as memory cell blocks 2500 through 250. L. A memory cell block 250 can be a grouping of memory cells 208 that can be erased together in a single erase operation. A group of memory cells that can be erased together is also referred to as an erase block. Each memory cell block 250 can represent those NAND strings 206 that are typically associated with a single select line 215 (e.g., select line 2150). The common source 216 of a memory cell block 2500 can be the same as the common source 216 of the memory cell block 250. L For example, each memory cell block 2500 to 250 L The access line 202 and the select lines 214 and 215 of one memory cell block 250 may not be directly connected to the memory cell blocks 2500 to 2500, respectively. L The access line 202 and select lines 214 and 215 of any other memory cell block in the memory cell block.

[0080] Bit lines 2040 to 204 M The buffer portion 240 may be connected (eg, selectively connected) to the buffer portion 240, which may be part of the page buffer 152 of the memory device 130. The buffer portion 240 may correspond to a memory plane (eg, memory cell blocks 2500 to 250 L Buffer portion 240 may include sensing circuitry (which may include sense amplifiers) for sensing the data value indicated on the corresponding bit line 204.

[0081] Figure 2D is a block diagram of a portion of an example memory cell array 260. The memory cell array 260 may be used as a reference. Figure 1C 1. The memory cell array 260 is depicted as having four memory planes 261 (eg, memory planes 261a through 261d). Each of the memory planes 261 may correspond to Figure 1A Each memory plane 261 can communicate with a corresponding buffer portion 240 that can collectively form a page buffer 262. The page buffer 262 can be used to implement Figure 1C 1. Although four memory planes 261 are depicted, other numbers of memory planes 261 may collectively communicate with the page buffers 262. Each memory plane 261 is depicted as including L+1 memory cell blocks 250 (e.g., memory cell blocks 2500 to 2501). L ).

[0082] Continue to refer Figure 1C and 2A To 2C, during a true erase operation (during which the memory cells are actually erased), the local controller 135 (eg, using the erase operation manager 137) may cause the common source voltage line (eg, SRC 216 ( Figure 2A )) Select gate 2100 to 210 M (SGS transistor) is turned on by the erase pulse ramping to the erase voltage (VERA). Ramping to this high bias erase voltage and then ramping back from this voltage requires a significant amount of time. Concurrently, the erase operation manager 137 may cause the select gates 2120 to 212 m ( Figure 2A ) is disconnected to select gates 2120 to 212 m The drain of the bit line 2040 to 204 is able to float, which causes the bit line 2040 to 204 M Also floated. In addition, the erase operation manager 137 can Figure 2A ) is coupled to ground (eg, 0 volts) or word line 202 is held at a low voltage. This set of voltage levels at memory array 200A can produce an erase potential that causes memory cells 2080-208 N is erased, for example, by forcing electrons to exit through the body of each memory cell and off the floating bit lines 2040 to 204 M In other embodiments, the selection gates 2100 to 210 M disconnected, causing the SRC line 216 to float, while the select gates 2120 to 212 M When turned on, the voltage of the bit line is ramped to Vera. As mentioned earlier, in 3D NAND, one of the channel region, pillar, or bit line can also be ramped to cause the erase of the attached memory cell. Therefore, for simplicity herein, reference to a "memory line" should be understood as reference to any of the SRC line or bit line in 2D NAND or any of the channel, pillar, or bit line in 3D NAND. In some embodiments, one or more sub-blocks (including physical blocks) of memory cells are erased during the same true erase operation. A block of memory cells can generally be understood to include four or more sub-blocks, where each sub-block includes a separate string of memory cells.

[0083] A high-level block diagram of an example device 300 that can be used to implement the systems, devices, and methods described herein is provided in Figure 3 It will be understood that the various systems, apparatus, and methods described herein can be implemented using analog and / or digital circuitry or using one or more computers utilizing well-known computer processors, memory systems, storage devices, computer software, and other components. Typically, a computer includes a processor for executing instructions and one or more memory devices for storing instructions and data. A computer may also include or be coupled to one or more mass storage devices, such as one or more magnetic disks, internal hard disks and removable disks, magneto-optical disks, optical disks, and the like.

[0084] The various systems, devices, and methods described herein can be implemented using computers operating in a client-server relationship. Typically, in such a system, a client computer is remotely located from a server computer and interacts via a network. The client-server relationship can be defined and controlled by computer programs running on the respective client and server computers. Examples of client computers can include desktop computers, workstations, laptop computers, cellular smartphones, tablet computers, or other types of computing devices.

[0085] The various systems, apparatuses, and methods described herein may be implemented using a computer program product tangibly embodied in an information carrier (e.g., in a non-transitory machine-readable storage device) for execution by a programmable processor; and the method procedures and steps described herein (including Figures 1A to 10B One or more of at least some of the steps in the process of performing the present invention may be implemented using one or more computer programs that can be executed by the processor. A computer program is a set of computer program instructions that can be used directly or indirectly in a computer to perform a specific activity or cause a specific result. A computer program can be written in any form of programming language (including compiled or interpreted languages), and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0086] like Figure 3 As shown in FIG, apparatus 300 may be used to implement a system comprising, coupled to, or utilizing a memory system (e.g., Figure 1A A host system (eg, a memory system 110) Figure 1A The device 300 can be used to execute the operations of the controller (e.g., to execute an operating system to execute the corresponding Figure 1A operation of the host system controller 106 and / or local controller 135).

[0087] In some embodiments, the apparatus 300 includes a processor 310 operatively coupled to a data storage device 320 and a main memory device 330. The processor 310 controls the overall operation of the apparatus 300 by executing computer program instructions 324 that define such operation. The instructions 324 include instructions for implementing the controller (e.g., Figure 1A The computer program instructions 324 may be stored in a data storage device 320 or other computer readable medium and loaded into a main memory device 330 when execution of the computer program instructions is desired. For example, the processor 310 may be used to implement one or more components and systems described herein, such as the host system controller 106 and / or the local controller 135 ( Figure 1A Therefore, Figures 1A to 10BAt least some of the method steps in the embodiment of the present invention may be defined by computer program instructions 324 stored in the main memory device 330 and / or the data storage device 320 and controlled by the processor 310 executing the computer program instructions 324. For example, the computer program instructions 324 may be implemented as computer executable code programmed by a person skilled in the art to perform the operations described herein. Figures 1A to 10B . Thus, by executing computer program instructions, processor 310 executes the algorithms defined by the method steps of these aforementioned figures to perform operations (e.g., reading, programming, erasing, etc.). Device 300 also includes one or more network interfaces 380 for communicating with other devices via a network. Device 300 may also include one or more input / output devices 390 (e.g., a display, keyboard, mouse, speaker, buttons, etc.) that enable user interaction with device 300.

[0088] The processor 310 may include both general-purpose and special-purpose microprocessors and may be the sole processor of the apparatus 300 or one of multiple processors. The processor 310 may include one or more central processing units (CPUs) and one or more graphics processing units (GPUs). For example, a GPU may operate separately from and / or multitask with one or more CPUs to accelerate processing, such as for the various image processing applications described herein. The processor 310, the data storage device 320, and / or the main memory device 330 may include, be supplemented by, or be incorporated into one or more application-specific integrated circuits (ASICs) and / or one or more field-programmable gate arrays (FPGAs).

[0089] The data storage device 320 and the main memory device 330 each include a tangible, non-transitory computer-readable storage medium. The data storage device 320 and the main memory device 330 may each include a high-speed random access memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), double data rate synchronous dynamic random access memory (DDR RAM), or other random access solid-state memory devices), and may include non-volatile memory, such as one or more magnetic disk storage devices (e.g., internal hard disk and removable disk), magneto-optical disk storage devices, optical disk storage devices, flash memory devices (NAND memory devices, NOR memory devices), semiconductor memory devices (e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM), digital versatile disk read-only memory (DVD-ROM) disks), or other non-volatile solid-state storage devices. For example, the data storage device 320 may use the memory system 110 ( Figure 1A) implementation. In some examples, the data storage device 320 and the main memory device 330 may include one or more memory devices 130 ( Figure 1A ).

[0090] Input / output devices 390 may include peripheral devices such as printers, scanners, display screens, etc. For example, input / output devices 390 may include a display device such as a cathode ray tube (CRT), a plasma or liquid crystal display (LCD) monitor for displaying information to a user, a keyboard, and a pointing device (such as a mouse or trackball) through which a user can provide input to apparatus 300.

[0091] Any or all of the functionality of the systems and devices discussed herein may be performed by processor 310 and / or incorporated into a device or system, such as system 100. Furthermore, system 100 and / or device 300 may utilize one or more neural networks or other deep learning techniques performed by processor 310 or other systems or devices discussed herein.

[0092] Those skilled in the art will recognize that actual computer or computer system implementations may have other structures and may contain other components, and Figure 3 is a high-level representation of some of this computer's components for illustration purposes.

[0093] Figure 4 is a block diagram of an example memory system 400 supporting techniques for real-time sensing of RC time constants of circuit lines according to examples disclosed herein. Figure 4 , memory system 400 corresponds to memory system 110 described above. Similar to memory system 110, system 400 also includes a memory system controller 415 that communicates with a memory device 430. Controller 415 and memory device 430 may be the same as or substantially similar to controller 115 and memory device 130 described above. For example, memory device 430 may include some or all of the same components or functional blocks as memory device 130 described above, such as local controller 135, row decoder 108, memory cell array 104, and column decoder 111. Therefore, descriptions of these blocks will not be repeated.

[0094] In some embodiments, the memory device 430 includes an RC sensor circuit 402 configured to drive a circuit line (eg, a word line). The RC sensor circuit 402 can output digital data that is used to measure the RC time constant of the circuit line. Figure 4, in one example, RC sensor circuit 402 includes a regulator 420 that can be configured to drive a circuit line having an RC time constant. It further includes one or more current mirrors 440 coupled to regulator 420. Current mirror 440 is configured to obtain a representative copy of the current of the circuit line. RC sensor circuit 402 further includes an integrator 460 that integrates the representative copy of the current of the circuit line over multiple time intervals. Based on the integration result, a digital data output can be provided to calculate the RC time constant of the circuit line. In some examples, RC sensor circuit 402 may also include a voltage or current source 480 that can be used to measure the representative copy of the current of the circuit line and optionally obtain a lookup table or its equivalent. Regulator 420, current mirror 440, integrator 460, and voltage or current source 480 are described in more detail below.

[0095] exist Figure 4 , RC sensor circuit 402 is shown as a separate block from other components of memory device 430. It may also be integrated or grouped into other components. For example, it may be part of local controller 135, memory cell array 104, or one or both of decoders 108 and 111. In some examples, one or both of local controller 135 and memory system controller 415 may also include RC constant manager 410. RC constant manager 410 may be used to manage and / or control the operation of RC sensor circuit 402. For example, it may be part of controller 415 or 135, such that RC sensor circuit 402 receives commands or instructions from one or both controllers to sense the RC time constant in real time (e.g., when memory cell array 104 is accessed through a read operation or a program operation). RC constant manager 410 is described in more detail below.

[0096] Turning to the first component of the RC sensor circuit 402 and using a word line as an example of a circuit line, Figure 5A is a schematic diagram of an example word line regulator 420 driving a word line 520 according to examples disclosed herein. Figure 5A The word line regulator 420 is shown configured such that its output terminal 513 is connected to the negative input terminal 505. Its positive input terminal 503 can receive a reference voltage signal for generating a drive voltage at the output terminal 513. The output terminal 513 of the regulator 420 is coupled to the word line 520. The word line 520 is shown by a simplified equivalent circuit in which a resistor 522 (represented by R wl ) coupled to two capacitors 524 and 526 (represented by C wldenoted). Each of capacitors 524 and 526 represents half the capacitance of word line 520. And resistor 522 represents the resistance of word line 520. Word line 520 has a proximal end and a distal end. The proximal end is directly coupled to output terminal 513 of regulator 420 for receiving a drive voltage signal. The distal end of word line 520 represents a location relatively far from output terminal 513 of regulator 420. For example, the distal end may be at the control gate of a particular memory cell (e.g., Figure 2A Certain memory cells may be located far from the output terminal 513 of the regulator 420 and generally unavailable for voltage measurement. Figure 5A As shown in FIG, therefore, for word line 520, there is a near-end voltage (given by V wl_near ) and the remote voltage (denoted by V wl_far To measure the RC time constant of word line 520, the remote voltage should be used, but it is not available. Therefore, the technique described herein measures the word line current (denoted by I wl ) or a representative copy thereof to determine the RC time constant of word line 520.

[0097] Figure 5B is an example relationship between word line current and time for the same time constant with different resistance and capacitance values ​​according to the examples disclosed herein. Figure 5B In FIG. 1 , the horizontal axis represents time, and the vertical axis represents word line current (denoted by I wl ). Curve 523 and curve 525 both show that the wordline current decreases and should approach zero within a sufficient time. Curve 523 and curve 525 may represent two different wordlines with the same RC time constant. For example, the wordline corresponding to curve 523 may have a high resistance (e.g., 200K ohms) and a low capacitance (e.g., 10pF); while the wordline corresponding to curve 525 may have a low resistance (e.g., 100K ohms) and a high capacitance (e.g., 20pF). The RC time constants of the two wordlines are therefore the same. However, the wordline currents I wl Different, such as Figure 5B 5. As shown in FIG. 5(a), the word line corresponding to curve 525 may have a higher word line current at any given time.

[0098] To measure the word line RC time constant, in some instances, two or more time intervals are selected. Figure 5B In FIG, the first time interval is from time 0 to T1 and the second time interval is from time 0 to T2. Then, the word line current I is calculated in the two time intervals (ie, from 0 to T1 and from 0 to T2). wl The integral of the current results in the total charge for the time interval. Therefore, the word line current I wl The integration from time 0 to time T1 results in charge Q1; and the word line current Iwl Integration from time 0 to time T2 results in charge Q2. The ratio of charge Q1 to Q2 can be calculated as follows [1].

[0099]

[0100] In the above equation [1], Q1 and Q2 represent the current from the word line I wl The charge obtained by integration over two time intervals T1 and T2 (both starting from time 0); e represents the Euler number or natural base and is the irrational number 2.718281828459...; τ represents the RC time constant of the word line. Therefore, by measuring the word line current and then obtaining the charge over two or more time intervals, the RC time constant τ can be calculated. For the word line current corresponding to Figure 5B For the two word lines in the two curves 523 and 525, the RC time constants are the same, even though the word line currents are different.

[0101] As described above, by measuring the wordline current rather than the unavailable remote wordline voltage, the RC time constant of the wordline can be calculated. In some instances, the wordline current measurement needs to be accurate (e.g., with an uncertainty of less than 1%). An accurate measurement of the wordline current translates into an accurate measurement of the RC time constant (e.g., if the uncertainty of the wordline current measurement is less than 1%, the uncertainty of the RC time constant can be less than 3%). Furthermore, the measurement speed needs to be fast to enable real-time measurement. For example, the RC time constant measurement speed needs to be fast enough to complete within 0.5 μs, or within any time requirement for real-time operation. Measuring the wordline current presents certain challenges. For example, it cannot be measured directly, and therefore a current mirror is used to obtain a representative copy of the wordline current and measure the representative copy. Therefore, the current mirror (e.g., current mirror 440) needs to be configured so that the representative copy of the current is sufficiently accurate and matches the wordline current. Additionally, the integrator (e.g., integrator 460) needs to be configured so that the wordline current can be converted from an analog value to a digital value for calculating the charge ratio and obtaining the RC time constant. Examples of circuits for RC sensor circuit 402 are described in more detail below.

[0102] Figure 5C is a schematic diagram of an example word line regulator 420 according to examples disclosed herein. Figure 5C As illustrated in FIG. 4 , the regulator 420 may include one or more operational amplifiers (e.g., operational amplifiers 532 and 548), a resistor divider (e.g., including resistors 544 and 546 connected in series) coupled to the one or more operational amplifiers, and a plurality of transistors coupled to the one or more operational amplifiers. The operational amplifiers 532 and 548 receive certain reference voltages as input signals. For example, the operational amplifier 532 receives a reference voltage at its negative input terminal 533, which is a voltage supplied by V dac_vwlrvThe positive input terminal 535 is connected to the node between the resistors 544 and 546. The resistor divider includes a resistor 544 (denoted as R1) and a resistor 546 (denoted as R2), which is configured to provide a resistor divider current (denoted by I res or I_ RES In some examples, another operational amplifier 548 is used. The operational amplifier 548 receives the voltage supplied by V dac_vpos_ref Its negative input terminal 547 is connected to the node between the resistor 546 (denoted as R2) and the transistor 552. This node is also connected to the output terminal 549 of the operational amplifier 548. Using the operational amplifier 548 and using V dac_vpos_ref The voltage at output terminal 549 of operational amplifier 548 can be set to any value, including a negative voltage, by using an appropriate reference voltage value. If the voltage at output terminal 549 is set to a negative voltage, transistor 552 is turned off, disconnecting the resistor divider of the regulator circuit from electrical ground 554 (which is typically at 0V). Thus, using operational amplifier 548, the bottom node of resistor 546 (represented by R2) can be set to a negative voltage (compared to 0V at electrical ground 554), thereby expanding the operating range of regulator 420.

[0103] Figure 5C Further shown are a plurality of transistors 536, 538, 542 and another resistor 534. For illustrative purposes, transistors 536, 538, and 542 are shown as NMOS transistors (N-type metal oxide semiconductor). However, it should be understood that other types of transistors (e.g., PMOS transistors, bipolar transistors, etc.) may also be used. The output terminal 537 of the operational amplifier 532 is coupled to the gate terminal of the transistor 536 and the gate terminal of the transistor 542. The source terminal of the transistor 536 may be connected to the gate terminal of the transistor 542. N The drain terminal of transistor 536 may be coupled to the first terminal 553 of resistor 534, and the second terminal of transistor 534 may be coupled to power supply 531. The drain terminal of transistor 538 may also be coupled to power supply 531, and the gate terminal of transistor 538 may be coupled to the first terminal 553 of resistor 534. The current generated by transistor 538 is referred to as the pull-up current (denoted as I pu or I_ PU ). The source terminal of transistor 538 is coupled to the drain terminal of transistor 542. The source terminal of transistor 542 is coupled to the drain terminal of transistor 542. N The drain terminal of transistor 542 is the output terminal 543 of regulator 420 and is also coupled to the word line driven by regulator 420. Output terminal 543 is also coupled to a Figure 5CThe resistor divider of resistors 544 and 546 is shown in FIG. Therefore, the current generated by or through transistor 542 is called the pull-down current (denoted as I pd or I_ PD The current through the resistor divider (including resistors 544 and 546) is called the resistor divider current (denoted by I res or I_ RES express).

[0104] based on Figure 5C configuration, the word line current (given by I wl ) is therefore a function of the pull-up current, pull-down current, and resistor divider current, as described in the following equation [2].

[0105] I wl =I pu -I pd -I res [2]

[0106] Word line voltage (V wlrv It can also be calculated based on the following equation [3].

[0107]

[0108] In the above equation [3], V dac_vwlrv represents the reference voltage supplied to the input terminal of the operational amplifier 532, and V dac_vpos_ref = represents the reference voltage provided to the input terminal of the operational amplifier 548. R1 and R2 represent the resistance of the resistors 544 and 546 used in the resistor divider. Therefore, by controlling the two reference voltages V dac_vwlrv and V dac_vpos_ref By setting the appropriate values ​​R1 and R2 of resistors 544 and 546, the target word line voltage V wlrv . Word line current I wl (which is the net current charging the word line) can then be calculated based on the above equation [2].

[0109] As described above, wordline current cannot typically be measured directly because direct measurement would alter the current driving the wordline and thus potentially interfere with operations (e.g., read or program operations). Therefore, the wordline current needs to be "mirrored," meaning a representative copy is obtained for measurement. Current mirrors are commonly used to obtain a representative copy of the current. Figure 6A is a schematic diagram of an example word line regulator 420 and example current mirrors 440a-440b for obtaining representative copies of pull-up and pull-down currents, respectively, according to examples disclosed herein. Figure 5C The regulator 420 can generate the pu (or I_PU ) represents the pull-up current, represented by I pd (or I_ PD ) and the pull-down current represented by I res (or I_ RES ) represents the resistor divider current. The word line current (represented by I wl The word line current is calculated based on the pull-up current, the pull-down current, and the resistor divider current. Therefore, if a representative copy of each of the pull-up current, the pull-down current, and the resistor divider current is available, a representative copy of the word line current can be obtained.

[0110] refer to Figure 6A , current mirror 440a can be configured to obtain a representative copy of the pull-up current produced by the regulator. Figure 6A As shown in FIG, current mirror 440a is coupled to regulator 420 to obtain a pull-up current (I pu ). Current mirror 440a includes transistors to copy or "mirror" the current flowing in one branch of current mirror 440a to the other branch of current mirror 440a. Figure 6A In one example shown in FIG, current mirror 440a includes a left branch having one or more transistors, such as transistors 602, 606, and 612, and a right branch having corresponding one or more transistors, such as transistors 604, 608, and 614. PMOS transistors are used for illustration, but other types of transistors may also be used. In the left branch of current mirror 440a, the drain terminal of transistor 612 is coupled to the drain terminal of transistor 538 of regulator 420; the gate terminal of transistor 612 is connected to electrical ground (thus, PMOS transistor 612 is turned on); and the source terminal of transistor 612 is coupled to the drain terminal of transistor 606. The gate terminal of transistor 606 can be connected to an external bias circuit (not shown) to receive a bias voltage so that current mirror 440a has an appropriate operating point. The source terminal of transistor 606 is coupled to the drain terminal of transistor 602; the gate terminal and drain terminal of transistor 602 are coupled together and to the gate terminal of transistor 604 of the right branch; and the source terminal of transistor 602 is coupled to the power supply. Thus, the left branch includes three transistors 612, 606, and 602. The current flowing through the left branch of the first current mirror 440a is the pull-up current (given by I pu express).

[0111] Correspondingly, in the right branch of current mirror 440a, transistors 604, 608, and 614 are configured to replicate the pull-up current in the left branch. The source terminal of transistor 604 is coupled to the power supply; the gate terminal of transistor 604 is coupled to the gate terminal and drain terminal of transistor 602 in the left branch (forming a current mirror structure); and the drain terminal of transistor 604 is coupled to the source terminal of transistor 608. The gate terminal of transistor 608 is coupled to the gate terminal of transistor 606 in the left branch, and thus, transistor 608 also receives a bias voltage from the bias circuit. The drain terminal of transistor 608 is coupled to the source terminal of transistor 614. In some examples, an optional capacitor (denoted as V cap ) is also present at the drain terminal of transistor 608 / source terminal of transistor 614. The gate terminal of transistor 614 is coupled to electrical ground (so transistor 614 is turned on). Transistor pair 602 and 604 have their gate terminals coupled together and thus form a current mirror pair; and transistor pair 606 and 608 have their gate terminals coupled together and both receive a bias voltage, so they form a bias pair. The pull-up current I flowing through the left branch pu Thus copying or "mirroring" it to the right branch.

[0112] In some examples, transistor pair 602 and 604 have an M:1 ratio in terms of their area (e.g., if transistors 602 and 604 have the same length, their widths have an M:1 ratio), where M can be a positive number. The representative replica of the pull-up current in the right branch is therefore 1 / M of the pull-up current in the left branch. For measurement purposes, the representative replica of the pull-up current does not need to be as large as the true pull-up current, as long as the M:1 ratio is taken into account in the subsequent calculation of the RC time constant. Using a smaller current in the representative replica of the pull-up current can therefore reduce power consumption. In the above description of current mirror 440a, the right branch or a portion thereof can be referred to as a pull-up replica circuit.

[0113] Continue to refer Figure 6A , current mirror 440b can be configured to obtain a representative copy of the pull-down current from regulator 420. Figure 6A , in one example, the current mirror 440b includes a transistor 616, which is an NMOS transistor. Transistor 616 couples its gate terminal to the gate terminal of transistor 542, which generates a pull-down current (I pd). Transistor 616 has its source terminal coupled to electrical ground and its drain terminal coupled to the right branch of current mirror 440a. Thus, transistor 616 operates as a second current mirror to replicate or "mirror" the pull-down current flowing through transistor 542. Similarly, transistors 542 and 616 have an M:1 ratio in terms of their areas (e.g., if transistors 542 and 616 have the same length, then their widths have an M:1 ratio), where M can be a positive number. The representative replica of the pull-down current in current mirror 440b is therefore 1 / M of the pull-down current in regulator 420. For measurement purposes, the representative replica of the pull-down current does not need to be as large as the true pull-down current, as long as the M:1 ratio is taken into account in the subsequent calculation of the RC time constant. Using a smaller representative replica of the pull-down current thus reduces power consumption. In the above description of current mirror 440b, transistor 616 or some other circuit that can replicate the pull-down current may be referred to as a pull-down replica circuit.

[0114] Figure 6B FIG2 is a schematic diagram of an example word line regulator 420 and another example current mirror 440c for obtaining a representative copy of the pull-up current according to examples disclosed herein. The regulator 420 is the same as described above and therefore will not be described again. The current mirror 440c is configured to obtain the pull-up current (I pu ). Current mirror 440c is configured differently from current mirror 440a. Figure 6B , current mirror 440c includes a replica circuit and an operational amplifier 622. In one example, the replica circuit includes a transistor 624 and a transistor 626 (both of which can (but are not necessarily) NMOS transistors). Transistors 624 and 626 are coupled in series such that the source terminal of transistor 624 is coupled to the drain terminal of transistor 626. The drain terminal of transistor 624 is coupled to a power supply; and the source terminal of transistor 626 is coupled to electrical ground (connected by V N It should be understood that although the replica circuit in the current mirror 440c is only shown as Figure 6B , but any number of transistors in any other configuration may be used to form the replica circuit. Transistors 624 and 538 have a 1:M ratio in terms of their areas (e.g., the widths of transistors 624 and 538 have a 1:M ratio if they have the same length), similar to the case described above in current mirror 440a.

[0115] Operational amplifier 622 is coupled between regulator 420 and a replica circuit including transistors 624 and 626. Specifically, one input terminal (e.g., the negative terminal) of operational amplifier 622 is coupled to output terminal 543 of regulator 420; the other input terminal (e.g., the positive terminal) of operational amplifier 622 is coupled to node 545, which is also the source terminal of transistor 624 or the drain terminal of transistor 626. The output terminal of operational amplifier 622 is coupled to the gate terminal of transistor 626. The voltage at node 545 (also referred to as the source voltage, which is the voltage at the source terminal of transistor 624) is forced to be equal to the word line voltage V at the output terminal of regulator 420. wlrv , because operational amplifier 622 has a high gain. In this way, the pull-up current can be copied from regulator 420.

[0116] Figure 6C is a schematic diagram of an example wordline regulator 420 and an example current mirror 440d for obtaining a representative copy of the resistor divider current according to examples disclosed herein. In some examples, the current mirror 440d is coupled to an operational amplifier 548. As described above, in some examples, transistor 552 is turned off (e.g., by applying a low voltage or ground voltage to the gate terminal of transistor 552) and thus the resistor divider including resistors 544 and 546 is disconnected from ground 554. Therefore, the resistor divider current (given by I res or I_ RES 544). res A representative copy of the resistor divider current is shown as I res_replica .

[0117] Figure 6D is a schematic diagram of an example word line regulator 420 and an example current or voltage source 662 for obtaining a representative copy of a resistor divider current according to examples disclosed herein. Figure 6D Shows another way to get a representative copy of the resistor divider current in a test setup. Figure 6D, regulator 420 is not in operation (e.g., a read or program operation). Instead, the resistor divider (including resistors 544 and 546) is disconnected from regulator 420 at node 543 (which is the output terminal of regulator 420) and node 549 (which is the output terminal of operational amplifier 548). Disconnection of the resistor divider from the rest of regulator 420 can be implemented using switches (not shown) placed at nodes 543 and 549. These switches can be FET switches that can be controlled to: (1) disconnect the resistor divider from the rest of regulator 420 while measuring the current flowing through the resistor divider or the voltage at the output terminal of the regulator, respectively; and (2) reconnect the resistor divider to the rest of regulator 420 when the measurement is complete.

[0118] During the test, transistor 552 is turned on (e.g., by applying a sufficiently large positive voltage to its gate terminal). Current or voltage source 662 (at Figure 6D , 662 is shown as being made by I_ DC ) can be controlled (e.g., by test equipment or a tester) to provide a plurality of predetermined currents or voltages to the resistor divider. For example, if a known voltage is applied, the current flowing through the resistor divider including resistors 544 and 546 can be measured. This is because the resistor divider current I res is the voltage at node 543 (given by V wrlv If current is applied to the resistor divider, the voltage at node 543 (denoted by V wrlv During the test process, multiple known voltages or known currents can be applied to the resistor divider. A lookup table or V wrlv with I res Therefore, if the real-time measurement of V wrlv , then I res This can be easily obtained by using a lookup table or relationship. For example, the lookup table or relationship can be stored in the Figure 4 4. It is accessible by the controller using firmware commands.

[0119] The above description provides examples of the regulator 420 and the current mirror 440 . Figure 7A is a schematic diagram of an example RC sensor circuit including a regulator 420, a current mirror 440, and an integrator 460 according to examples disclosed herein. Current mirror 440 can be any one or more of current mirrors 440a through 440d described above. In some cases, the resistor divider current can be measured during testing or manufacturing, and a lookup table or curve can be established for faster calculations. Figure 7AIn FIG. 4 , the regulator 420 and the current mirror 440 are simplified for illustrative purposes. In one example, the integrator 460 includes an analog-to-digital converter (ADC). The ADC is coupled to one or more current mirrors 440. As described above, the current mirror 440 obtains representative copies of the pull-up current, the pull-down current, and the resistor divider current. Based on these representative copies, the word line current I wl It can be obtained based on the following equation [1]. Figure 7A In the example, the current flowing out of the current mirror 440 can be the word line current. When the loop between the current mirror 440 and the integrator 460 is stable, this current is equal to the ADC current from the integrator 460 (given by I adc express).

[0120] like Figure 7A , an integrator 460 (eg, ADC) includes a comparator 710 coupled to one or more current mirrors 440. The comparator 710 is configured to receive the output voltage of the one or more current mirrors 440 and a reference voltage (given by V ref The comparator 710 compares the output voltage of the current mirror 440 with the reference voltage V ref The output signal is provided to the oscillator 720. The oscillator 720 can be controlled by the output signal of the comparator 710 to generate pulses at a certain frequency to drive the charge pump 740. Depending on the voltage level of the output signal of the comparator 710, the pulse repetition rate (or pulse frequency, pulse time interval) of the output signal from the oscillator 720 can be changed.

[0121] Charge pump 740 may include a switched capacitor structure that uses switches 742a-742d to connect and disconnect capacitors in a particular manner (e.g., by C adc 743), thereby effectively transferring charge to, from, or between capacitors to form an output voltage or current. For illustration, Figure 7A 4 switches and 1 capacitor are shown, but it should be understood that other charge pump structures including more or fewer switches or capacitors or different configurations thereof may also be used. In this case, switches 742a to 742d of charge pump 740 are controlled by pulses generated by oscillator 720 to form a charge pump 740 composed of I adc Represents the ADC current. When the ADC current is controlled to be the same as the output current of the current mirror (which is the word line current I wl The feedback loop between the current mirror 440 and the integrator 460 is stable when the representative copy of the word line current I is the same. The oscillator 720 also provides its output pulse to the counter 730. Therefore, when the loop is stable, the digital output (e.g., digital count) of the counter 730 is a value representing the word line current I wl The following equation [4] provides the integral of a representative copy of the word line current (given by Imirror ), the count provided by counter 730 (represented by D adc ), the capacitance of the capacitor 743 in the charge pump 740 (denoted by C adc ), power supply voltage (denoted by V cc ) and the reference voltage of the comparator 710 (denoted by V ref Represents the mathematical relationship between.

[0122] ∫I mirror dt=D adc *C adc *(2V cc -V ref )[4]

[0123] The integration performed by integrator 460 may be applied to multiple time intervals. Figure 5B As shown in FIG, for example, the integration can be performed over a time interval between time 0 and T1 and another time interval between time 0 and T2. The result of the multiple integrations is a plurality of ADC counts. For example, a first ADC count can represent the integration of the word line current over a first time interval (from time 0 to T1), and a second ADC count can represent the integration of the word line current over a second time interval (from time 0 to T2). The current integration results in a charge. Thus, the first and second ADC counts represent a first charge and a second charge, respectively. The RC time constant can be calculated based on the first count (given by D adc1 ) and the second count (denoted by D adc2 denoted) is calculated as shown in the following equation [5].

[0124]

[0125] The above-described integrator 460 can operate at high speed and the loop can be stabilized in a short period of time. For example, by properly configuring capacitor 702, a dominant pole can be generated for stabilizing the ADC. Other techniques can also be used to create a stable loop for the ADC. Figure 7A The settling time of this ADC shown in FIG can be configured to be very short, thereby enabling real-time measurement of the RC time constant, as described in more detail below.

[0126] As described above, a representative copy of the word line current is obtained based on obtaining a representative copy of the pull-up current, the pull-down current, and the resistor divider current in the regulator. Figure 7A The output of the current mirror 440 is from Figure 6A 、 Figure 6B and Figure 6CThe current mirror 440 may provide a representative copy of the wordline current for the described method. Current mirror 440 may only provide a representative copy of the net current of the pull-up and pull-down currents. Current mirror 440 may have an offset in the net current of the wordline (e.g., due to transistor mismatch). Therefore, the output of integrator 460 needs to be adjusted using a resistor divider current that can be obtained from a lookup table or curve.

[0127] Although Figure 7A The RC sensor circuit shown in can operate in real time to provide the RC time constant of the word line, but in some examples, the current mirror die trim (TBD) technique can be used to improve the accuracy of the current mirror. Figure 6D For example, when TBD technology is applied, the regulator 420 can be disconnected from the word line (eg, using Figure 6D 4 and described above). An external current source, such as current source 662, can be used to apply a known DC current to node 543, which is the input node of current mirror 440 and integrator 460. Current mirror 440 produces a representative copy of the known DC current, and integrator 460 outputs a digital count representing the integral of the known DC current. Different values ​​of the DC current can be used, and a digital output from integrator 460 can be obtained for various DC current values.

[0128] Figure 7B is the word line current according to the examples disclosed herein (using a known DC current value, given by I wl ) and digital data representing the word line current (using the count output by the integrator 460, represented by D iwl Curve 750 can be obtained by forcing a plurality of known DC currents as described above and obtaining digital counts at the output of integrator 460. For example, this relationship can be stored as a lookup table or curve in Figure 4 In real-time operation, when the digital count is obtained at the output of integrator 460, the word line current can be quickly obtained using the stored lookup table or curve.

[0129] The RC sensor circuit described above can be used in real time to obtain the RC time constant. This RC time constant can, in turn, be used to determine the time delay for propagating the word line voltage from the near end to the far end. This time delay can then be used in subsequent steps or periods within the same operation. Figure 8A8 is an example relationship of the proximal word line voltage, the distal word line voltage, and the word line current with respect to time in a read operation according to the examples disclosed herein. Curves 802, 804, and 806 represent the proximal word line voltage waveform, the distal word line voltage waveform, and the word line current waveform, respectively, during the example read operation. During a read operation of a multi-level memory cell (e.g., MLC, TLC, QLC, etc.), a regulator applies a voltage at the proximal end of the selected word line (i.e., the end of the word line close to the regulator that drives the word line). This word line voltage is also referred to as the output voltage of the regulator, the proximal word line voltage, or the reference voltage. The following description uses the proximal word line voltage. The proximal word line voltage propagates to the distal end and becomes the distal word line voltage, which is compared to one or more of the multiple threshold voltage (Vt) levels of the multi-level memory cell. Using an MLC memory cell as an example, which has three threshold voltage levels (V t1 、V t2 and V t3 ). Therefore, during a read operation, different threshold voltage levels (V t1 、V t2 and V t3 ) is compared, the near word line voltage increases or decreases and therefore, the far word line voltage also increases or decreases to read the data stored in the memory cell. During a read operation of the memory cell associated with the selected word line, the other word lines are applied with a pass voltage (V pass ), which is usually higher than all threshold voltages.

[0130] refer to Figure 8A During this example read operation, a regulator (such as regulator 420) may first apply a low voltage to the proximal end of the selected word line. Thus, as shown by curve 802, the proximal word line voltage (V wl_near ) ramps down from a first voltage value (eg, a highest level) at time T0 to a second voltage value (eg, a lowest level) after a short time delay. Curve 804 shows the remote word line voltage (V wl_far ) is ramped down from a first voltage level at time T0 to a second voltage level at time T2. Due to the word line RC, the remote word line voltage (V wl_far ) ramp down is longer than the time delay for ramping down the near word line voltage. That is, there is a propagation delay between the near word line voltage and the far word line voltage. Curve 806 shows the word line current (I wl ) from an initial value at time T0 to a final value (eg, zero current).

[0131] As described above, during a read operation, the regulator drives the selected word line to different voltage levels in an incremental manner. Conventionally, the regulator cannot increase the word line voltage to the next value until a sufficiently long period has passed so that the remote word line voltage (V wl_far) has settled to its final value. The period that the regulator needs to keep the proximal word line voltage constant depends on the worst-case word line RC time constant. However, as described above, this results in a slower read operation because not all word lines have the worst-case RC time constant.

[0132] Figure 8A It is shown that during the first ramp period or first strobe period in a read operation, the RC time constant of the selected word line can be measured using the above-described techniques. Specifically, strobe corresponds to the period during which the regulator holds the proximal word line voltage (or its output voltage) constant. As shown by Figure 8A The curve 802 in FIG. 1 shows that the first gating corresponds to the period between time T0 (which is the time when the proximal word line voltage starts to change from the first voltage value to the second voltage value) and the time when the proximal word line voltage starts to change from the second voltage value to the third voltage value. Figure 8A Curve 804 of φ ... Figure 8A The period corresponding to the first strobe is shown to be longer than the first ramp period, which is simply the time required for the remote word line voltage to stabilize. The period corresponding to the first strobe may correspond to the time required for the remote word line voltage to stabilize for the word line with the worst-case RC time constant (e.g., the largest RC time constant among all word lines). Therefore, if the selected word line is not the worst-case word line, the timing of the first ramp period may be less than the period corresponding to the first strobe. If the selected word line is the worst-case word line, the first ramp period is the same as the period of the first strobe (i.e., the worst-case ramp period).

[0133] Using the above-described RC sensor circuit (eg, circuit 402 ), the word line current I wl Integration of the representative copy of the word line can be performed over multiple time intervals during the first ramp period (e.g., the time intervals between T0 and T1 and between T0 and T2). An RC time constant can be calculated based on the ratio of the charges obtained from the integration. This process for obtaining the RC time constant can be performed during the first ramp period of the first strobe. Thus, subsequent ramp periods allocated to the selected word line can be obtained.

[0134] refer to Figure 8A For the second ramp period (in the second strobe), the regulator adjusts the near-end word line voltage (V wl_near ) changes from a second voltage value (eg, the lowest voltage level) to a third voltage that is higher than the second voltage value (but not the highest level). Based on the RC time constant obtained during the first ramp period, the remote word line voltage (V wl_far) can be calculated based on the second and third voltage values. Thus, the regulator does not need to wait for a long period corresponding to the worst-case wordline RC time constant before it further ramps the near-end wordline voltage to the next value. Instead, because the precise time delay required in the second strobe is known, the regulator can be controlled (e.g., by local controller 135 or memory system controller 415) to increase the near-end wordline voltage to the next value upon completion of the second ramp period or shortly thereafter. In this case, the duration of the second strobe can be reduced to be substantially the same as the second ramp period, and little or no time is wasted in the read operation. The same process can be repeated for subsequent strobes. For example, the RC time constant obtained during the first or second ramp period can be used to calculate the third ramp period. After the regulator increases the near-end wordline voltage from the third voltage value to the fourth voltage value, it maintains the near-end wordline voltage at the fourth voltage value for approximately the third ramp period, just long enough for the far-end wordline voltage to stabilize. The regulator can then further increase or decrease the near-end wordline voltage for subsequent steps in the read operation. The period of the third gating can therefore also be reduced to be substantially the same as the third ramp period for ramping up and stabilizing the remote word line voltage. In short, the read operation can be performed in a short period.

[0135] exist Figure 8A In FIG, two time intervals are shown for calculating the RC time constant of a selected word line. The two time intervals are between time point T0 and time point T1 and between time point T0 and time point T2. The selection of time points T1 and T2 needs to be controlled so that a time point after the remote word line voltage stabilizes (e.g., after the remote word line voltage reaches a final value or is within a threshold of the final value) should not be selected. In addition, time points T1 and T2 cannot be too close to each other to improve the calculation accuracy. Although Figure 8A Only two time points, T1 and T2, are shown, but more time points, such as T3, T4, etc., may be used to integrate the word line current to obtain the RC time constant. Controlling the selection of time points for integration may be performed by a controller, such as local controller 135 or memory system controller 115.

[0136] As described above, the measurement of the RC time constant can also be used to assess whether a word line is defective. Thus, if the remote word line voltage (curve 804) does not stabilize and / or the word line current I wl If (curve 806) does not approach its final value (e.g., 0), it may mean that there is leakage current or a possible short circuit between the word line and the rest of the memory device. On the other hand, if the remote word line voltage settles to its final value in an unusually short period of time, it may mean that the word line is interrupted and, therefore, the device may have an open word line defect.

[0137] Additionally, real-time measurement of the RC time constant of a word line can be used to determine if the word line is overdriven. Overdriving a word line means that the regulator initially drives the word line to a voltage higher than the target voltage value and then reduces the voltage back to the target voltage value. For example, Figure 8A During the second strobe period, the regulator can initially apply a voltage slightly higher than the third voltage value and then reduce the voltage down to the third voltage value (which is the final voltage value of the second strobe). This allows the remote wordline voltage to stabilize more quickly. Real-time measurement of the RC time constant can also be used to assess the amount of overdrive required. For example, if the wordline has a relatively small RC time constant, a smaller overdrive can be applied; and if the wordline has a relatively high RC time constant, a larger overdrive is required.

[0138] also, Figure 8A This illustrates a regulator driving the near-end word line voltage (curve 802) from low to high during a read operation. The reverse operation can also be performed. That is, the regulator can drive the near-end word line voltage or another circuit line voltage from high to low. The same or substantially similar method for measuring the RC time constant can be performed, and the total duration of the read operation can be reduced.

[0139] Figure 8B is an example relationship of the near-end word line voltage and the far-end word line voltage with respect to time in a programming operation according to examples disclosed herein. Curve 822 represents the near-end word line voltage (V wl_near ) and curve 824 represents the word line voltage at the far end (V wl_far Programming a multi-level memory cell (e.g., MLC, TLC, QLC, etc.) involves storing data by adjusting the charge level within the memory cell to represent multiple bits per cell. Programming is typically controlled by a controller (e.g., local controller 135 and / or system controller 115). Programming a memory cell typically involves two phases, a data programming phase and a verification phase. Both phases are repeated to program the data into the memory cell. During the programming phase, the regulator drives programming pulses with increasing voltage values ​​because a multi-level memory cell has multiple levels of threshold voltage (e.g., V t1 、V t2 and V t3 During the verify phase, the controller verifies the program data and if the data is verified, the specific memory cell is programmed. If the data is not verified, additional programming pulses are used and these additional programming pulses may have higher or lower voltage levels.

[0140] Figure 8B is a simplified diagram illustrating the programming operation of a memory cell. Figure 8B As shown in FIG, the RC time constant of the selected word line for programming operation can also be obtained in a similar manner as described above. Figure 8BDuring the first programming pulse phase shown in FIG, the regulator can drive the proximal end of the selected word line to a different voltage value. Therefore, the RC time constant can be measured during the period in which the regulator maintains the word line voltage at the first voltage value. Next, the regulator changes the proximal word line voltage to a second voltage value. The RC time constant can be used to calculate the ramp-up or ramp-down time required for the remote word line voltage to stabilize at the second voltage value. Therefore, the regulator only needs to maintain the word line voltage at the second voltage value for the period of time allowed for the remote word line voltage to stabilize, and not longer (or slightly longer). The regulator can perform similar operations for subsequent steps in the first programming pulse phase.

[0141] In some examples, the RC time constant of the word line is measured during the program-verify phase rather than during the program pulse phase. This is because the read and program-verify operations use the same regulator, while the program (or write) operation may use a different regulator. Regardless of the regulator used, the real-time RC time constant of the word line can be measured using the above-described techniques and used to optimize subsequent steps in the program-verify phase. In this way, the total programming time of the programming operation can be reduced.

[0142] Figure 9 The illustration shows a flow chart showing one or more methods 900 supporting techniques for optimizing access operations using real-time RC time constant measurements according to examples disclosed herein. Figure 9 As shown in FIG, a memory controller (eg, memory system controller 115 and / or local controller 135) may store instructions and issue firmware commands to perform one or more steps in method 900. Figure 8A and 9 In step 902, the memory controller may cause the proximal voltage of the circuit line to change from a first voltage value to a second voltage value during at least a first ramp period (e.g., by Figure 8A The proximal voltage of the circuit line is maintained at the second voltage value within a period (shown by curves 802 and 804). In step 904, the memory controller obtains the RC time constant of the circuit line during the first ramp period. For example, using two time intervals from T0 to T1 and from T0 to T2, the RC time constant can be obtained based on the integration of the word line current, as described above. In step 906, the memory controller determines the second ramp period (e.g., by Figure 8A In step 908, the memory controller causes the proximal voltage of the circuit line to change from the second voltage value to the third voltage value and during the second ramping period (e.g., by Figure 8A The above steps can be applied to Figure 8A The read operation shown in or Figure 8Band described above. Furthermore, in both the read and program operations, the second voltage value may be greater than the first voltage value, and the third voltage value may be greater than the second voltage value, or vice versa. For the program operation, the first period may be within a programming pulse phase or a verify phase of the program operation.

[0143] Figure 10A The description shows a flow chart of one or more methods 1000 supporting techniques for detecting defects in a target circuit line according to examples disclosed herein. Method 1000 can be performed at least in part using a memory device including a memory array, a resistor-capacitor (RC) sensor circuit, and a memory controller. In method 1000, step 1002 obtains a representative copy of the current of the circuit line via an RC sensor circuit (e.g., circuit 402). Step 1004 integrates the representative copy of the current of the circuit line over multiple time intervals (e.g., via integrator 460) to obtain multiple charges associated with the multiple time intervals. Step 1006 obtains digital data associated with the circuit line (e.g., via an ADC of integrator 460). The digital data represents the multiple charges associated with the multiple time intervals. Step 1010 determines whether the circuit line is defective based on the digital data.

[0144] Figure 10B A flowchart illustrating details of one or more methods 1010 for determining whether a circuit line is defective based on digital data is described. Step 1022 compares the digital data associated with the circuit line with digital data associated with a known circuit line that is not defective. Step 1024 determines whether the digital data associated with the circuit line is defective based on the comparison result. For example, in step 1032, a determination is made (e.g., by a memory device, a memory system, or a host system) whether the comparison result indicates that the target circuit line has a constant leakage current compared to the known circuit line. If so, step 1034 flags the target circuit line as a shorted circuit line. In another example, in step 1036, a determination is made whether the comparison result indicates that the target circuit line has a current that is less than a current of the known circuit line by more than a threshold. If so, step 1038 flags the target circuit line as an open circuit line.

[0145] It should be noted that the described techniques include possible implementations, and that the operations and steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0146] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0147] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are said to be in electronic communication (or in conductive contact or connected or coupled) with each other if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact or connected or coupled) with each other may be open or closed based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (such as switches, transistors, or other components). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (such as switches or transistors).

[0148] The term "coupled" (e.g., "electrically coupled") may refer to a condition that transitions from an open-circuit relationship between components (where signals cannot currently pass between the components via a conductive path) to a closed-circuit relationship between the components (where signals can pass between the components via a conductive path). If a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components via a conductive path that previously prevented signal flow.

[0149] The term "isolation" refers to a relationship between components where signals are no longer able to flow between them. If an open circuit exists between the components, the components are isolated from each other. For example, if a switch located between two components is open, the components separated by the switch are isolated from each other. If a controller isolates two components, the controller causes a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0150] The terms "if," "when," "based on," or "based at least in part on" may be used interchangeably. In some instances, if the terms "if," "when," "based on," or "based at least in part on" are used to describe a connection between conditional actions, conditional processes, or portions of processes, the terms may be interchangeable.

[0151] The term "in response to" may refer to a condition or action occurring at least in part, if not entirely, as a result of a preceding condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least in part as a result of the preceding condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occurring after the first condition or action).

[0152] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or a subregion of the substrate, can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate, or by any other doping method.

[0153] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials (e.g., metals). The source and drain can be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor can be "switched on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor gate, the transistor can be "off" or "deactivated."

[0154] The description set forth herein, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" rather than "preferred" or "advantageous over other examples." The "Detailed Description" includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0155] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0156] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Figure 3 If the functionality is implemented in software executed by a processor 310 (e.g., a processor 310), the functionality may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the described functionality may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functionality may also be physically located at various locations, including being distributed such that portions of the functionality are implemented at different physical locations.

[0157] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of ..." or "one or more of ...") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0158] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications of the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A resistor-capacitor (RC) sensor circuit, comprising: a regulator configured to drive a circuit line; one or more current mirrors coupled to the regulator to obtain a representative copy of the current of the circuit line; and an integrator comprising an analog-to-digital converter (ADC) coupled to the one or more current mirrors to receive the representative copy of the current of the circuit line and configured to: integrating the representative replica of the current of the circuit line over a plurality of time intervals to obtain a plurality of charges associated with respective time intervals, wherein the plurality of time intervals are within a first ramping period for ramping the remote voltage of the circuit line from a first voltage value to a second voltage value, and Digital data for calculating an RC time constant of the circuit line is output, wherein the digital data is representative of the plurality of charges.

2. The RC sensor circuit of claim 1 , wherein the regulator comprises: one or more operational amplifiers configured to receive one or more reference voltages; and a resistor divider coupled to the one or more operational amplifiers, the resistor divider having a resistor divider current; and A plurality of transistors are coupled to at least one of the one or more operational amplifiers, the plurality of transistors being configured to generate a pull-up current and a pull-down current, wherein the current of the circuit line is obtained based on the pull-up current, the pull-down current, and the resistor divider current.

3. The RC sensor circuit of claim 1 , wherein the one or more current mirrors comprise: a first current mirror configured to obtain a representative copy of the pull-up current generated in the regulator; and A second current mirror is configured to obtain a representative copy of the pull-down current generated in the regulator.

4. The RC sensor circuit of claim 3 , wherein the first and second current mirrors are sized so that the representative replicas of the pull-up current and the pull-down current have a 1 / M ratio relative to the pull-up current and the pull-down current generated in the regulator, respectively, where M is a positive number. 5 . The RC sensor circuit of claim 3 , wherein the first current mirror and the second current mirror comprise pull-up replica circuitry and pull-down replica circuitry configured to obtain the representative replicas of the pull-up current and the pull-down current, respectively.

6. The RC sensor circuit of claim 3 , wherein the first current mirror comprises: replica circuit; and An operational amplifier is coupled between the regulator and the replica circuit.

7. The RC sensor circuit of claim 3, further comprising: A third current mirror is coupled to the regulator, the third current mirror being configured to obtain a representative copy of a resistor divider current generated in the regulator.

8. The RC sensor circuit of claim 3, further comprising: a voltage source or a current source controllable to provide a plurality of predetermined voltages or currents, respectively, to the resistor divider of the regulator; and One or more switches controllable to disconnect the resistor divider from the rest of the regulator when measuring current through the resistor divider or measuring voltage at the output of the regulator, respectively.

9. The RC sensor circuit of claim 1 , wherein the ADC comprises: a comparator coupled to the one or more current mirrors, the comparator configured to receive an output voltage of the one or more current mirrors and a reference voltage; an oscillator coupled to the output of the comparator; a charge pump coupled to the oscillator and the one or more current mirrors, wherein the charge pump, the comparator, and the oscillator form a feedback loop to output a digital output voltage pulse representing the integration of the representative copy of the current of the circuit line; and A counter is configured to generate the digital data based on the digital output voltage pulses.

10. The RC sensor circuit of claim 1, wherein the digital data comprises first and second ADC counts representing first and second charges, respectively, of the plurality of charges, and the RC time constant is a ratio of the first and second ADC counts.

11. The RC sensor circuit of claim 1 , wherein the circuit line is a word line in a memory device.

12. A memory device comprising: memory arrays; memory controller; and A resistor-capacitor RC sensor circuit comprising a regulator configured to drive a circuit line; one or more current mirrors coupled to the regulator to obtain a representative copy of the current of the circuit line; and an integrator comprising an analog-to-digital converter (ADC) coupled to the one or more current mirrors to receive the representative copy of the current of the circuit line and configured to: integrating the representative replica of the current of the circuit line over a plurality of time intervals to obtain a plurality of charges associated with respective time intervals, wherein the plurality of time intervals are within a first ramping period for ramping the remote voltage of the circuit line from a first voltage value to a second voltage value, and Digital data for calculating an RC time constant of the circuit line is output, wherein the digital data is representative of the plurality of charges.

13. A memory device comprising: memory arrays; Regulator; a resistor-capacitor (RC) sensor circuit configured to sense an RC time constant of a circuit line in the memory device; and A memory controller configured to: causing a proximal voltage of the circuit line to change from a first voltage value to a second voltage value and maintaining the proximal voltage of the circuit line at the second voltage value during at least a first ramping period; obtaining the RC time constant of the circuit line during the first ramping period; determining a second ramping period based on the RC time constant; and The proximal end voltage of the circuit line is caused to change from the second voltage value to a third voltage value and maintained at the third voltage value during a second ramping period, wherein the second ramping period is less than the first ramping period.

14. The memory device of claim 13, wherein the memory controller is configured to perform a read operation, and wherein the second voltage value is greater than the first voltage value, and wherein the third voltage value is greater than the second voltage value.

15. The memory device of claim 13, wherein the memory controller is configured to perform a programming operation, and wherein the first ramping period is within a verify phase of the programming operation.

16. The memory device of claim 13, wherein the memory controller is configured to perform a programming operation, and the first ramping period is within a programming pulse phase of the programming operation.

17. A method for detecting defects in a target circuit line, the method being performed at least in part using a memory device including a memory array, a resistor-capacitor (RC) sensor circuit, and a memory controller, the method comprising: obtaining a representative copy of the current of the circuit line from the RC sensor circuit; integrating the representative copy of the current of the circuit line over a plurality of time intervals to obtain a plurality of charges associated with the plurality of time intervals; obtaining digital data associated with the circuit line, the digital data being a representation of the plurality of charges associated with the plurality of time intervals; and A determination is made based on the digital data as to whether the circuit line is defective.

18. The method of claim 17, wherein determining whether the circuit line is defective comprises: comparing the digital data associated with the circuit line with digital data associated with a known circuit line that does not have a defect; and A determination is made based on the comparison result whether the digital data associated with the circuit line is defective.

19. The method of claim 18, wherein determining whether the digital data associated with the circuit line is defective based on the comparison result comprises: determining whether the comparison result indicates that the target circuit line has a constant leakage current compared to the known circuit line; and If the target circuit line has a constant leakage current compared to the known circuit line, then the target circuit line is flagged as a shorted circuit line.

20. The method of claim 18, further comprising: determining whether the comparison result indicates that the target circuit line has a current that is less than a current of the known circuit line by more than a threshold; and If the target circuit line has a current that is less than the current of the known circuit line by more than the threshold, then the target circuit line is flagged as an open circuit line.

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