SOPC time synchronization method based on FPGA

Abstract

The invention discloses an SOPC time synchronization method based on an FPGA, and relates to the technical field of time synchroniss.The method comprises the steps that an integrated time synchronization system is constructed in a single FPGA chip, and the time synchronization system comprises a data receiving unit, a time analysis unit, a time control unit and a man-machine interaction unit; an external time service signal is obtained through a data receiving unit, the time service signal comprises a time message and a synchronous pulse signal which are provided by a satellite time service module, the time message is analyzed by a time analysis unit, time information is extracted according to a preset rule, and reference source selection is carried out based on quality parameters of a plurality of time sources; according to the SOPC time synchronization method based on the FPGA, the reliability and synchronization precision of local time generation are improved, the method is suitable for the key fields of electric power, traffic, communication and the like with extremely high time consistency requirements, and the universality, expansibility and practical value of the system are enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of time synchronization, and in particular to a SOPC time synchronization method based on FPGA. Background Art

[0002] In the design of modern time synchronization systems, high-precision transmission and low-latency display of time information are crucial, directly impacting the system's reliability and real-time performance in practical applications. This is particularly true in scenarios requiring high time consistency, such as power, transportation, and communications. Time synchronization errors can lead to system failure or control deviations. Traditional time synchronization systems often utilize a multi-chip architecture, such as a separate embedded chip controlling a liquid crystal display (LCD) to provide a human-machine interface. However, while this architecture is functionally mature, its hardware implementation is complex, with functional modules distributed across different chips. This not only increases system size and cost, but also places higher demands on integrated design and wiring. Furthermore, because multiple chips must communicate via communication interfaces such as serial ports, I2C, or SPI, transmission delays and even errors can easily occur during this information exchange, impacting the accuracy and responsiveness of the time information display. During system operation, inter-chip communication delays can accumulate, causing the final time output to deviate from the true timing signal and reducing synchronization accuracy. Furthermore, the complexity of the system architecture also increases debugging and maintenance costs, posing challenges in product development cycles and ensuring stability. Summary of the Invention

[0003] The purpose of the present invention is to provide a SOPC time synchronization method based on FPGA to solve the problems existing in the prior art.

[0004] To achieve the above object, the present invention provides the following technical solution: a SOPC time synchronization method based on FPGA, the method comprising: An integrated time synchronization system is built in a single FPGA chip. The time synchronization system includes a data receiving unit, a time analysis unit, a time control unit, and a human-computer interaction unit. Obtain external timing signals through the data receiving unit, the timing signals include time messages and synchronization pulse signals provided by the satellite timing module; The time parsing unit parses the time message, extracts time information according to preset rules, and selects a reference source based on quality parameters of multiple time sources; The time control unit generates local standard time and multiple synchronous output signals based on the selected time reference source; The human-computer interaction unit uses a configurable soft-core processor embedded in the FPGA chip to read the human-computer interaction parameters in the configuration memory, control the display interface to output the current time information, and update the configuration parameters in response to user operations; Configuration parameters are saved in non-volatile external memory in power-off state and automatically loaded after the system is powered on to ensure the continuity and stability of the time synchronization system; The human-computer interaction unit, time analysis unit and time control unit are integrated into the FPGA chip, eliminating the communication delay between chips, reducing hardware complexity and cost, and improving the integration and response speed of the time synchronization system.

[0005] Preferably, the time parsing unit includes an IRIG-B signal parsing module for parsing the input pulse width coded signal and obtaining time information in a B code format by identifying logic bits and time delimiters.

[0006] Preferably, the time control unit supports the simultaneous output of synchronization signals in multiple formats, including pulses per second, pulses per minute, pulses per hour, TTL level signals, RS232 serial port signals and RS485 differential signals.

[0007] Preferably, the display interface controlled by the human-computer interaction unit is a graphic liquid crystal display LCD12864, and the soft-core processor implements instruction transmission and refresh operations on the LCD through a PIO interface, supporting graphical output of time information and menu-based interactive operations.

[0008] Preferably, the configuration parameters include display brightness, time format, synchronization signal type selection, user authority level and serial port baud rate setting.

[0009] Preferably, the non-volatile external memory is a flash chip, and the soft-core processor periodically stores the configuration parameters redundantly through an SPI interface.

[0010] Preferably, the data receiving unit includes a message cache module and a redundancy check mechanism, wherein the message cache module is used to temporarily store the satellite data sequence to be parsed, and the redundancy check mechanism uses a CRC algorithm to verify data integrity. If a data anomaly is detected, a re-request logic is triggered to prevent erroneous time information from participating in system time calculation.

[0011] Preferably, the soft-core processor and the FPGA logic area exchange key data through a shared memory mechanism. The shared memory realizes high-speed reading and writing of data through on-chip RAM, and sets a mutually exclusive access flag to ensure data consistency and access security in a synchronous state.

[0012] Preferably, the human-computer interaction unit further includes a key scanning module and a menu management module. The key scanning module detects user input in a periodic polling manner, and the menu management module performs content jumps, option highlights, and parameter confirmation actions according to the current page status.

[0013] Preferably, the time synchronization system further includes a remote access and update module, and the soft-core processor implements remote reading and updating of system firmware versions, configuration parameters and operation logs through an integrated Ethernet interface.

[0014] It can be seen from the above technical solution that the present invention has the following beneficial effects: This FPGA-based SOPC time synchronization method integrates multiple functional modules, including data reception, time analysis, time control, and human-computer interaction, into a single FPGA chip, avoiding the hardware redundancy and communication delay issues associated with traditional multi-chip architectures. This achieves a highly integrated system structure and significantly reduces hardware costs and development difficulty. The method utilizes a soft-core processor embedded within the FPGA, which not only enables direct control of the display interface, improving the real-time and accuracy of time information display, but also supports the storage of configuration parameters and power-off protection, ensuring the continuous and stable operation of the system. Furthermore, by evaluating and optimizing the quality parameters of multiple time sources, the reliability and synchronization accuracy of local time generation are improved. This method is suitable for critical sectors such as electricity, transportation, and communications, which have extremely high requirements for time consistency, enhancing the system's versatility, scalability, and practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Flow chart of the method of the present invention. DETAILED DESCRIPTION

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0017] like Figure 1 As shown, the present invention provides a technical solution: a SOPC time synchronization method based on FPGA, the method comprising: An integrated time synchronization system is built in a single FPGA chip. The time synchronization system includes a data receiving unit, a time analysis unit, a time control unit, and a human-computer interaction unit. Obtain external timing signals through the data receiving unit, the timing signals include time messages and synchronization pulse signals provided by the satellite timing module; The time parsing unit parses the time message, extracts time information according to preset rules, and selects a reference source based on quality parameters of multiple time sources; The time control unit generates local standard time and multiple synchronous output signals based on the selected time reference source; The human-computer interaction unit uses a configurable soft-core processor embedded in the FPGA chip to read the human-computer interaction parameters in the configuration memory, control the display interface to output the current time information, and update the configuration parameters in response to user operations; Configuration parameters are saved in non-volatile external memory in power-off state and automatically loaded after the system is powered on to ensure the continuity and stability of the time synchronization system; The human-computer interaction unit, time analysis unit and time control unit are integrated into the FPGA chip, eliminating the communication delay between chips, reducing hardware complexity and cost, and improving the integration and response speed of the time synchronization system.

[0018] This embodiment relates to a time synchronization system built within a single field-programmable gate array chip. The basic concept is to integrate the reception, analysis, control, and interaction of time signals onto a single chip platform to achieve high-precision, low-latency time synchronization. The system first receives an external timing signal via a data receiving unit. This signal typically consists of a time message input via a serial port or dedicated communication interface and a once-per-second synchronization pulse signal from an external satellite timing module, such as a Global Positioning System (GPS) timing module. The time message uses a standard format and typically contains time fields such as the current year, month, day, hour, minute, and second.

[0019] The data receiving unit integrates a serial port receiver and pulse input detection logic. The serial port receiver is responsible for identifying and buffering data frames from external modules, buffering the received data, and forwarding it to the time resolution unit. The pulse input detection logic receives the pulse-per-second signal corresponding to the time message to achieve time base alignment. After receiving the complete time message, the time resolution unit uses pre-defined field parsing rules to extract the time field from the message. Combined with the edge events of the synchronization pulse, it captures the timestamp and locks the synchronization moment, completing the standardized parsing of the time data.

[0020] After time resolution is complete, the time resolution unit feeds the resolved time information into the reference source evaluation module. Under preset logic control, this module compares and analyzes candidate time sources based on quality parameters such as stability, validity, and packet loss rate. Using an optimization algorithm, it selects the optimal time source as the reference source for the local system time.

[0021] The time control unit initiates the local clock generation process based on the selected reference source. This process generates a local clock signal using the system's internal timer and high-frequency reference crystal oscillator. It then uses phase adjustment logic to align the local clock with the selected reference time, achieving precise time synchronization. The unit also generates a variety of output signals, including standard one-second pulse output signals, millisecond synchronization pulses, and serial port time codes, for use in time synchronization with external devices or systems. All output signals are configurable, including level type, output port, and signal format.

[0022] The system also includes a human-computer interaction unit, implemented by a configurable soft-core processor embedded in an FPGA chip. This processor accesses control parameters stored in configuration memory via an internal bus, including display format, communication baud rate, and time correction offset. Based on these parameters, the processor controls the display interface to display real-time information such as the current synchronization time status, reference source information, and system operating mode. The processor also responds to user control commands input via external buttons, serial port commands, or the touch screen, enabling real-time updating and storage of configuration parameters.

[0023] These configuration parameters are written to a nonvolatile memory external to the FPGA chip, such as serial flash memory or electrically erasable read-only memory (EEROM), and are retained even after a system power outage. Upon system power-up, the soft-core processor automatically loads the parameters from this memory and restores the system to its pre-power-down state, ensuring continuity and consistency in the time synchronization system after an unexpected power outage or restart.

[0024] Because all units are integrated into the same FPGA chip, signals are transmitted internally via logical connections, eliminating the need for cross-chip communication. This avoids the degradation of synchronization accuracy caused by bus drivers, protocol switching, or signal delays, significantly improving response speed and system reliability. The overall system is based on a modular design concept, with each unit able to operate independently or collaboratively, achieving a complete functional chain of time acquisition, analysis, control, output, and interaction.

[0025] This implementation significantly improves the integration and response performance of the time synchronization system. By integrating all functional modules in a single FPGA chip, the delay and stability problems caused by multi-chip communication in traditional systems are avoided, reducing the complexity of the hardware system and manufacturing costs. The system adopts a multi-source time reference mechanism to enhance anti-interference and fault tolerance capabilities, ensuring high reliability and high-precision output of local time. The human-computer interaction module supports dynamic parameter configuration and status visualization, which improves the operability and user-friendliness of the system. Through the power-off retention mechanism, the system has the ability to operate continuously and can quickly recover to the established state even after a power outage, ensuring the uninterrupted and stable time synchronization function. It is suitable for industrial and military scenarios with high requirements for time accuracy and reliability.

[0026] The time parsing unit includes an IRIG-B signal parsing module, which is used to parse the input pulse width coded signal and obtain the time information in B code format by identifying the logic bit and time separator.

[0027] This embodiment further embeds an IRIG-B signal parsing module within the time parsing unit of the overall SOPC time synchronization system to identify and parse pulse-width encoded time signals from external timing equipment. IRIG-B signals are a standard time code format characterized by the use of pulses of varying widths to represent logical bit values ​​and time field boundaries, transmitting a complete time frame per second. They are widely used in aviation, power generation, and industrial automation scenarios.

[0028] In practical implementation, the input of the IRIG-B signal parsing module is connected to the high-speed digital input pins of the FPGA to receive continuous pulse-coded signals. The module first incorporates an edge capture circuit that performs high-precision sampling of the input pulse signal, detecting the time interval between the rising and falling edges of each pulse and converting this interval into a digital pulse width. Based on a pre-set pulse width threshold, the module identifies pulses within a specific time range as logical zeros, logical ones, or time separators. For example, pulses of short duration are identified as logical zeros, pulses of medium duration as logical ones, and pulses of the longest duration as field separators.

[0029] After pulse width identification, the system activates the state machine control logic to perform structured parsing of the identified logical bit stream. The state machine reads and marks each time field, including seconds, minutes, hours, Julian day, year, and control field, bit by bit, according to the IRIG-B standard time code sequence. To ensure parsing accuracy, the system incorporates a built-in cyclic check mechanism that automatically detects synchronization markers in key field locations, ensuring that the data stream correctly locks onto the start bit at any point in time.

[0030] The parsed time fields are reassembled into a complete standard time data format after structuring and sent to the time control unit as a local reference time source. If the system is set up for a multi-source input environment, the parsed time can also participate in the time source evaluation process and be used as the preferred synchronization benchmark after quality comparison with other time signals. In addition, the IRIG-B parsing module has a signal loss detection mechanism. Once reception is interrupted or the signal anomaly exceeds the set threshold, the module will immediately report the status to the upper-level control logic and switch to the backup timing source to ensure the continuity and stability of system operation.

[0031] The module's timing control and recognition logic are implemented using programmable logic units. This allows for parameterized adjustment of thresholds and recognition rules based on the electrical characteristics of specific IRIG-B variant signals (such as DC level and sinusoidal modulation), resulting in strong signal adaptability. The entire parsing process is completed within the FPGA, eliminating the need for an external decoding chip, significantly improving decoding speed and system reliability.

[0032] By integrating an IRIG-B signal parsing module into the time resolution unit, this implementation significantly improves the system's compatibility with a variety of timing signals, enabling it to not only parse serial-format messages but also process IRIG-B coded signals, which are widely used in industrial and military applications. This module utilizes pulse width recognition and state machine decoding to ensure high accuracy and reliability, while simplifying the need for an external IRIG-B decoder and further reducing the overall system hardware complexity. This approach also enhances the fault tolerance and scalability of the time synchronization system, enabling flexible switching of parsing modes for different signal sources and expanding the system's applicability.

[0033] The time control unit supports the simultaneous output of multiple formats of synchronization signals, including pulse per second, pulse per minute, pulse per hour, TTL level signal, RS232 serial port signal and RS485 differential signal.

[0034] This implementation incorporates control logic and interface conversion circuitry within the FPGA's integrated time control unit to support multi-format synchronization signal output, meeting the diverse synchronization signal types and communication interface requirements of various devices and systems. Its core function is to generate multiple synchronization pulse signals with strict time consistency and period accuracy based on local standard time, and output them in parallel as different physical signals.

[0035] First, the system uses the high-precision clock source embedded in the FPGA as the basic time signal, combined with timer and counter modules to build a local time series. This time series operates in milliseconds or microseconds as the minimum time unit, and can achieve progressive counting at the second, minute, and hour levels through configuration parameters. In specific implementation, the system uses a first-level timer to generate a second-second count signal. When the cumulative count reaches 60 times, it drives the second-level minute counter, which then controls the hour count logic to generate the hour synchronization signal. All of these timing modules are designed with the FPGA's synchronization logic to ensure the stability and consistency of their timing.

[0036] Based on this local time base, the system sets up synchronization signal output control logic to output pulse signals according to the specified trigger conditions. The second-of-second pulse signal is triggered by the timer's full-value interrupt signal and outputted via a designated pin as a single-cycle high-level pulse for one-second synchronization with external systems. Similarly, the minute-of-the-minute pulse is triggered when the second-of-the-second counter reaches full value, outputting a relatively longer-duration synchronization signal to facilitate device differentiation. The hourly pulse is driven by the minute counter in conjunction with the hour counting logic to ensure it precisely falls on the hour.

[0037] To achieve compatible output across various electrical interfaces, the time control unit integrates multiple driver modules. For TTL-level output, the FPGA's general-purpose input / output ports are directly used to output logic high and low-level signals. Output levels can be configured to various standards, such as 3V, 3V, and 5V, through the FPGA chip's power supply configuration. For RS232 serial port output, the system has an embedded serial communication controller module, which uses a standard asynchronous communication protocol to encode the current time in data frames and output them through the serial port pins. Parameters such as the serial port baud rate, stop bits, and parity bit are configurable through the human-computer interface during system initialization.

[0038] For applications requiring long-distance, highly interference-resistant transmission, the time control unit includes a reserved RS485 output path. This path's signals are generated by the FPGA logic as differential pulse pairs, converted to RS485 levels by an external differential driver chip, and transmitted to external devices via a two-wire bus structure. This differential output offers strong immunity to electromagnetic interference, making it suitable for long-distance transmission of synchronization signals in complex environments such as industrial control and power dispatch.

[0039] All synchronization signal output ports are enabled and parameterized through a unified configuration storage area. Users can use the human-computer interaction module to select which synchronization signals to enable and set parameters such as output period, pulse width, pin number, and signal level type. Dynamic configuration modification is also supported during system operation, enabling adaptive adjustments based on application environment requirements, improving system maintainability and adaptability.

[0040] This implementation significantly enhances the time synchronization system's adaptability to a variety of usage scenarios. By supporting the simultaneous output of synchronization pulses at multiple time granularities, such as seconds, minutes, and hours, the time control unit can simultaneously serve downstream application devices requiring different time accuracies. The integration of multiple interface standards, including TTL, RS232, and RS485, meets the diverse physical layer requirements, from low-level signals to long-distance differential communications, greatly enhancing the system's versatility and ease of deployment. Each interface output is uniformly controlled by an FPGA, offering fast response speed and high precision. Users can flexibly configure output strategies, simplifying the system structure and reducing overall costs.

[0041] The display interface controlled by the human-computer interaction unit is a graphic liquid crystal display LCD12864. The soft-core processor realizes instruction transmission and refresh operation on the LCD through the PIO interface, and supports graphical output of time information and menu-based interactive operation.

[0042] This embodiment configures a graphical LCD interface within the human-computer interaction unit, using an LCD12864 as the primary display device to output information such as the time synchronization system's current operating status, time information, synchronization source selection results, and user menus. The LCD12864 is a graphic display using a liquid crystal dot matrix structure, boasting a resolution of 128 columns and 64 rows. It supports the simultaneous display of text and graphics, offering a large viewing area and strong compatibility.

[0043] The display module is connected to the soft-core processor within the FPGA chip via parallel control. The soft-core drives and controls the LCD module via a general-purpose input / output interface. During system initialization, the soft-core processor sends startup commands to the LCD12864 module via the general-purpose input / output interface. These commands include reset commands, display mode settings, dot matrix mode selection, cursor hiding commands, and clearing the display cache. After initialization, the LCD module enters a standby display state, awaiting data refresh commands.

[0044] During normal system operation, the soft-core processor uses a periodic scheduling mechanism to read key data such as the current system time, timing signal status, and synchronization source selection information from the configuration memory or run cache, and constructs it into a string or graphic code in a standardized display format. The processor then encodes this data byte by byte into LCD control commands and sends them to the LCD12864 control bus via the general-purpose input and output interface. This transmission process includes a series of operations such as setting the address, writing data, and waiting for the LCD response.

[0045] To ensure real-time display, the system uses a one-second refresh strategy, executing a full-screen refresh in response to a timer interrupt every second. The refresh logic includes three steps: row positioning, column jump, and data writing, ensuring that new time information and status prompts completely overwrite old information without residual flicker.

[0046] In terms of interaction, the soft-core processor runs a hierarchical menu control program, allowing users to progressively access function menus, parameter settings, and information queries via external buttons. Menu information is stored in an internal constant table or an external storage module. Key input is captured via interrupts. The processor interprets user intent based on the current menu state and key type, executing operations such as menu jumps, cursor movement, and parameter modifications. The LCD module then displays the current option, setting value, and status icon through corresponding screen redrawing operations.

[0047] To enhance the user experience, the system supports dot-matrix icon drawing. The processor can call upon predefined graphic templates, such as timing status icons, time synchronization symbols, or warning prompts, and draw corresponding graphics in designated areas of the LCD screen to intuitively reflect system status. All display and interactive control are implemented by a soft-core program, allowing flexible expansion of functions and adjustment of display content through system upgrades.

[0048] This implementation significantly enhances the interactivity and visualization of the time synchronization system by integrating an LCD12864 graphic LCD module. A menu-driven user interface controlled by a soft-core processor allows users to quickly configure the system and monitor its status, offering simple operation and intuitive feedback. The PIO interface enables precise control and refresh of the LCD, ensuring timely display updates. This design is particularly suitable for industrial and military applications requiring high real-time interface performance. This design eliminates the need for an additional LCD driver chip, simplifies the circuit structure, reduces system cost, and improves system integration and stability.

[0049] Configuration parameters include display brightness, time format, synchronization signal type selection, user authority level and serial port baud rate setting.

[0050] In this implementation, a soft-core processor is used to identify, manage, and execute configuration parameters in the time synchronization system, ensuring that the system can flexibly customize various operating characteristics according to user needs. During system startup, the soft-core processor first loads all configuration parameters from external non-volatile memory and stores them in the processor's internal registers or on-chip static random access memory (SRAM) as a reference during operation. These configuration parameters include five core categories: display brightness, time format, synchronization signal type selection, user permission level, and serial port baud rate setting. They are as follows: First, regarding display brightness control, the system achieves graded adjustment of screen brightness by controlling the power supply voltage used by the LCD backlight circuit or adjusting the duty cycle of the pulse-width modulation signal. Based on the user-set brightness parameter value, the soft-core processor generates a corresponding control code, which is output to the external backlight driver circuit via the general-purpose input / output interface. The backlight driver circuit receives this signal, adjusting the current driving the LEDs to control the overall brightness of the LCD module. The system supports five brightness levels, each with a fixed duty cycle to achieve differentiated visual effects, suitable for different environments such as daytime, nighttime, and under strong light interference.

[0051] Secondly, the time format setting function allows users to select how time information is displayed, including switching between 12-hour and 24-hour formats. Date formats support either year-month-day or day-month-year order. When generating the content for the LCD display, the soft-core processor parses the internal time data structure and reconstructs the string according to the specified format. If the user selects the 12-hour system, the processor automatically adds the AM or PM indicator and converts the hour field. The display order of the date format also depends on parameters, determining the order of the fields and the separator style. This feature enhances the localization adaptability of the time display.

[0052] When selecting synchronization signal types, users can configure the desired synchronization output mode through an interactive interface. The system supports enabling or disabling pulse output per second, per minute, and per hour. Users can also choose to enable TTL level output, RS232 serial output, and RS485 differential signal output. The processor controls the operating status and output port activation of the corresponding module based on these settings. Enabling a corresponding option opens the corresponding logic path and connects the output port. Disabling a corresponding option causes the module to enter a low-power or idle state, avoiding unnecessary resource usage and reducing interference sources.

[0053] User permission level management ensures system security. Permissions are divided into three levels: observation, configuration, and management. Observer-level users can only view the current time and synchronization status. Configuration-level users can modify parameters but cannot restart the system or clear logs. Management-level users can perform all operations. The system requires user authentication before entering the setup interface. This can be achieved through password entry, external verification modules, or jumper hardware identification. The processor dynamically generates interface content based on permission levels and restricts the response logic for inaccessible menus to prevent incorrect operations by low-privilege users.

[0054] Finally, the serial port baud rate setting parameter adjusts the RS232 serial port's communication speed, supporting six common rates, ranging from 4,800 bits per second to 115,200 bits per second. The soft-core processor automatically calculates the required frequency division ratio based on the set baud rate and writes it to the serial port control register, achieving precise synchronization of the transmit and receive frequencies. After changing the baud rate, the system immediately applies the change without restarting the serial port module, ensuring uninterrupted communication.

[0055] After all the above parameters are modified, the processor writes the new parameters into the configuration register area and stores them in the external non-volatile memory before power failure, ensuring that the system can be automatically loaded and restored to the user-set state when it is powered on next time.

[0056] By supporting the setting and storage of multiple key configuration parameters, this implementation significantly enhances the customizability and adaptability of the time synchronization system. Users can flexibly adjust display styles, signal types, and communication parameters based on different application scenarios, while a permission control mechanism ensures the security of system settings. Parameters automatically recover after a power outage, streamlining operation and maintenance, improving system stability and user experience. The visualization and interactive operation of configuration parameters further enhance the system's user-friendliness and engineering practicality.

[0057] The non-volatile external memory is a flash chip, and the soft-core processor periodically stores the configuration parameters redundantly through the SPI interface.

[0058] In this implementation, to ensure that configuration parameters are fully retained after a system power outage, reset, or abnormal restart, and automatically restored upon power-up, the time synchronization system uses an external flash chip as a non-volatile storage medium. This chip is rewritable and has long data retention, making it suitable for long-term storage of critical configuration data. This flash chip is connected to the FPGA via a serial peripheral interface, and the soft-core processor controls access to it via the SPI interface.

[0059] During system initialization, the soft-core processor first enables the SPI communication interface and performs the flash chip identification process, which includes pulling the chip select signal low, reading the chip identification code, and confirming the chip model and capacity information. Once the identification is correct, the processor reads the most recently saved configuration parameter data segment from a predefined address area. This data includes all key parameters such as display brightness, time format, synchronous output options, serial port baud rate, and permission level. The system uses a data header and checksum field to mark valid data segments. After the processor verifies the integrity and validity of the data segment through the checksum value, it loads it into the system working buffer.

[0060] During system operation, the soft-core processor continuously monitors the status of configuration parameters. When it detects any parameter change, such as when the user modifies the time format, switches the output signal type, or adjusts the screen brightness, the system activates the parameter change flag and enters a waiting state. If no other parameters change within ten seconds, the system triggers a parameter save task. Furthermore, to ensure long-term parameter security, the system automatically saves the current parameter status every five minutes, even if the parameters have not been modified.

[0061] When a save task is initiated, the soft-core processor first assembles all current parameters into a data packet, adds a data identification number, a timestamp, and a binary checksum, and selects a new free page address as the storage target. Subsequently, through the SPI interface control logic, the processor sends the write command, target address, and data content in sequence, using double buffering to ensure uninterrupted data transmission.

[0062] To prevent the lifespan of the flash chip from degrading, the system employs a cyclic redundancy mechanism. The entire storage area is divided into multiple data pages, for example, sixteen pages. Each write operation selects the next page in sequence, and when full, the first page is overwritten. Each page is timestamped. Upon power-up, the system automatically searches for the most recent, verified data page as the current valid configuration source, achieving redundant backup of configuration data.

[0063] In addition, the SPI communication module features a write status detection function. After data is written, the soft-core processor queries the flash chip's status register to confirm the write operation is complete and whether an error flag is present. If a write operation fails or a data verification error occurs, the system automatically retries the write operation. If two consecutive failures occur, the system issues an alarm and retains the last valid configuration, preventing system startup failure or operational disruptions due to storage anomalies.

[0064] The entire storage and recovery mechanism is fully controlled by the soft-core processor, eliminating the need for manual user intervention. The parameter update process does not interfere with system synchronization, ensuring stable operation of the time control, output, and display modules.

[0065] By using external flash memory chips for redundant storage, this implementation effectively improves the reliability and persistence of system configuration parameters. Even if the system experiences a power outage or reboot during operation, the last validly saved parameters can be quickly restored, ensuring stable and continuous operation of the time synchronization system. The SPI interface enables high-speed, low-occupancy communication between hardware and software, while a rotating storage strategy prevents memory cell wear caused by frequent erasing and writing to the same block, extending the life of the flash memory chips.

[0066] The data receiving unit includes a message buffer module and a redundancy check mechanism. The message buffer module is used to temporarily store the satellite data sequence to be parsed. The redundancy check mechanism uses a CRC algorithm to verify data integrity. If a data anomaly is detected, a re-request logic is triggered to prevent erroneous time information from participating in system time calculation.

[0067] In the time synchronization system of this embodiment, in order to improve the reliable reception capability of external satellite timing data, a message cache module and a redundant check mechanism are integrated into the data receiving unit. The system structure and processing flow are carefully designed to ensure the integrity and stability of data during the reception, caching, verification and forwarding processes.

[0068] Specifically, the external timing signal is typically transmitted by the satellite receiving module in a serial data format, periodically outputting a time message once per second. This time message contains key fields such as year, month, day, hour, minute, second, and millisecond, and is supplemented by a checksum at the end for integrity verification. This serial signal is first received by the serial receiving logic module within the FPGA and buffered byte by byte in the message buffer module.

[0069] The message buffer module consists of a static random access memory (SRAM) with sequential addresses, with each message occupying a fixed-length memory area. The system sets a start and end flag for each message frame and immediately marks the entire frame as "pending verification" upon receipt. This mechanism prevents incomplete or interrupted data from being mistakenly transmitted to the parsing process.

[0070] Once the cache is complete, the redundancy check mechanism is immediately activated. The system calls the CRC module to calculate the contents of the valid fields in the message and generate a checksum. This checksum is then compared bit by bit with the original checksum at the end of the message to determine whether there are any bit errors, byte loss, or illegal modification during the data reception process. The system uses a hardware-implemented CRC algorithm with high computational efficiency, completing the complete message check process in microseconds.

[0071] If the verification result is consistent, the processor sets the current message status to "valid" and forwards it to the time resolution unit for time field extraction and synchronization source update. If the verification fails, the system immediately sets the message status to "invalid" and activates the re-request logic.

[0072] The re-request logic operates in two modes: If the upstream satellite timing module supports serial port command control, the soft-core processor sends a re-acquisition command to request the latest frame. If command interaction is not supported, the system automatically waits for the next cycle of message input and records the current buffer area anomaly information in the status register for fault tracking and log generation. The system supports three consecutive reception anomalies, which are considered a communication link anomaly. This triggers the synchronization source degradation logic and switches to the backup time source to ensure system time continuity.

[0073] The entire reception and verification process is controlled by the FPGA's internal logic. Status registers are used between processing units to communicate status and interact with data pointers, ensuring deterministic processing timing and non-interference between concurrent tasks. This design not only improves the system's ability to handle high-frequency messages, but also significantly enhances its adaptability to complex electrical environments, such as data errors, crosstalk, and electromagnetic interference.

[0074] This implementation incorporates a message buffer module and a CRC-based redundancy check mechanism within the data receiving unit, enabling real-time verification and cache protection of input time data. This effectively eliminates erroneous time information caused by communication errors, ensuring that the system always executes synchronization based on correct data. Message status control and re-request logic provide the system with automatic error recovery capabilities, significantly improving overall stability and anti-interference capabilities. This makes it particularly suitable for industrial and military synchronization scenarios operating under high-noise, long-distance, or unstable communication conditions.

[0075] The soft-core processor and the FPGA logic area exchange key data through a shared memory mechanism. The shared memory uses on-chip RAM to achieve high-speed data reading and writing, and sets a mutually exclusive access flag to ensure data consistency and access security in the synchronous state.

[0076] In this implementation, a shared memory-based data communication mechanism was designed and implemented to efficiently exchange critical data between the soft-core processor and the FPGA logic area. This mechanism uses the FPGA chip's internal RAM as a carrier, partitioning a section of physical memory into a shared area that can be accessed simultaneously by both the hardware and software. This avoids access bottlenecks caused by using an external bus and improves overall data exchange efficiency.

[0077] The shared memory structure is segmented and configured by the soft-core processor during system initialization. It typically includes multiple functional areas, including the input data segment, output command segment, system status segment, time data segment, and mutual exclusion flag segment. Each area is responsible for different data exchange tasks. For example, the input data segment stores signal reception status, synchronization flags, or reference source selection results written by the FPGA logic; the output command segment is written by the soft-core processor to control synchronization signal switching, interface parameter settings, and other instructions; the time data segment stores the latest parsed local time counter value; and the system status segment is used to describe and confirm the current system operating status during interaction.

[0078] In actual operation, the soft-core processor accesses the shared memory area via the on-chip data bus, performing operations such as data reads, writes, and polling. Simultaneously, the FPGA logic area accesses the same memory space through the controller, periodically writing collected data or reading processing instructions. To prevent data conflicts or abnormal states caused by the soft-core processor and logic module reading and writing the same memory location at the same time, the system introduces a mutually exclusive access flag mechanism.

[0079] Specifically, a mutex flag is set before each shared data block. The value of this flag indicates whether the current data block is "accessible." Before reading or writing to a memory segment, the processor first checks whether the corresponding mutex flag is free (that is, the value is zero). If the flag is one, it indicates that the memory segment is being operated by the logic module, and the processor must enter a wait state or skip the current cycle. Conversely, before executing a write operation in the FPGA logic area, it is also necessary to check whether the flag is occupied by the processor. During the access process, the accessing party sets the flag to one, and then clears it to zero after the write is complete, indicating that control has been released.

[0080] This mechanism ensures that only one module can access the same shared memory at any given time, preventing data tampering or read errors during access. To improve response efficiency, the soft-core processor periodically checks the shared memory status using a polling method, while the logic module performs operations based on a fixed clock cycle. The entire process is coordinated with synchronized timing to ensure system data consistency and integrity.

[0081] The system also provides a shared memory expansion mechanism. If additional data exchange areas are required in subsequent designs, the processor can dynamically modify the memory mapping table and adjust the starting address and length of memory segments through configuration registers, enabling flexible expansion. Furthermore, the entire shared memory design is built on the FPGA's on-chip physical resources, achieving read and write speeds far exceeding those of off-chip storage solutions. Data exchange can be completed in microseconds, meeting the requirements of high-frequency, high-reliability systems.

[0082] This implementation significantly improves system data exchange speed and synchronization control capabilities by designing a shared memory mechanism to establish an efficient and stable communication channel between the soft-core processor and the FPGA logic. High-speed data paths are achieved through on-chip RAM, avoiding external storage bottlenecks. A mutually exclusive access mechanism ensures data integrity and security under concurrent access, preventing race conditions and access conflicts, improving system stability and data consistency. This makes it particularly suitable for industrial and time-based control systems with high reliability requirements.

[0083] The human-computer interaction unit also includes a key scanning module and a menu management module. The key scanning module detects user input in a periodic polling manner, and the menu management module performs content jumps, option highlights, and parameter confirmation actions according to the current page status.

[0084] This implementation integrates a key scanning module and a menu management module within the human-computer interaction unit, enabling users to control the system through physical buttons. This solution creates an embedded menu interaction system with rapid response, clear logic, and a user-friendly interface, making it particularly suitable for resource-constrained time synchronization devices with graphical LCD displays.

[0085] The key scan module connects to multiple key switch circuits via a general-purpose input / output interface. Each key pin is configured as a digital input during power-up, with a pull-up resistor maintaining a stable default voltage level. A periodic timer task based on the system clock is set up in the soft-core processor. This task executes a complete scan cycle every 10 milliseconds, reading the current voltage level of each key pin one by one.

[0086] During the scanning process, the processor detects the change between the current level and the previous scan level to determine whether a valid key trigger signal exists. To eliminate repeated triggering caused by mechanical jitter of the key, the system introduces a jitter delay counting mechanism. Only when the same level change trend is detected in three consecutive scan cycles will the key event be marked as valid input. This method effectively improves key recognition accuracy and avoids misoperation.

[0087] Once a valid key event is identified, the key scanning module immediately passes the event in code form to the menu management module. The menu management module presets a complete menu hierarchy and state jump logic. Based on the current page state, it interprets the input event type (such as up, down, confirm, or return) and performs the corresponding action based on the event content.

[0088] For up or down menu operations, the system moves the cursor within the current menu option and refreshes the LCD display, highlighting the newly selected option with a highlighted area, outline, or graphic icon. The original option returns to its normal display state. This process uses the LCD display command set to redraw the graphics, and the entire operation is completed within 50 milliseconds, ensuring zero visual feedback delay.

[0089] When the user confirms the action, the system performs a functional jump or parameter confirmation based on the currently selected menu item. For example, it jumps to the next submenu level, or writes the currently selected parameter value to the configuration register and updates the status bits in the shared memory area. If the input is a return command, the menu management module restores the previous menu page based on the status stack and refreshes the interface content to the previous state.

[0090] To enhance operational intuitiveness, the menu management module supports a partitioned page refresh mechanism, updating only the cursor row or parameter area, avoiding repeated screen clearing and improving system resource utilization. In scenarios where soft-core processor resources are sufficient, a graphical menu display can be implemented by loading an icon font library, displaying function icons next to options for enhanced user recognition.

[0091] All menu pages and transition logic are implemented using a state table. The processor uses the current menu number and input event to look up the table and locate the next state, ensuring consistent operation paths and behavior. Certain key operations, such as saving parameters or restarting the system, trigger a dedicated confirmation screen, requiring the user to reconfirm the validity of the operation, thereby improving system security and preventing incorrect operations.

[0092] By integrating key scanning and menu management functions into the human-computer interaction unit, users can complete all system parameter settings and status monitoring operations without external communication equipment, improving system independence and controllability. Polling-based key detection ensures fast and accurate input response, and state-machine-based menu control logic provides clearer operation logic and a more organized process, making it suitable for embedded device applications in complex configuration scenarios.

[0093] The time synchronization system also includes a remote access and update module. The soft-core processor realizes remote reading and updating of system firmware version, configuration parameters and operation logs through the integrated Ethernet interface.

[0094] This implementation integrates a remote access and update module within the time synchronization system to support remote access and maintenance updates of system operating status, configuration parameters, firmware versions, and log information via Ethernet. This module, leveraging a soft-core processor and an integrated Ethernet interface controller, establishes a stable and efficient remote communication and control mechanism within the embedded system.

[0095] First, the soft-core processor connects to the Ethernet physical layer chip via its embedded serial peripheral interface and initializes the network communication environment during system startup. This initialization process includes configuring information such as the local network address, subnet mask, and default gateway. This information can be obtained automatically through the Dynamic Host Configuration Protocol or manually set through the human-computer interface. After initialization is complete, the soft-core processor starts the lightweight communication protocol stack and opens a preset port to listen for remote access requests.

[0096] When a remote client sends an access request via a LAN or WAN, the soft-core processor parses the request message based on the protocol type. If the request is for a parameter read, the processor extracts the corresponding parameter values, such as the time format, synchronization output type, and serial port baud rate, from the configuration cache or non-volatile memory, packages them into a response message, and sends it to the client. If the request is for a log query, the processor accesses the log buffer or historical log file area, filters the record results based on the user-defined time range and event type, and returns them. The log content includes time synchronization status changes, communication failure records, user operation records, and abnormal alarm information, facilitating remote fault analysis and historical behavior auditing.

[0097] For firmware version read requests, the system presets a version identification field in the configuration area, and the processor returns this information directly to the client. If the client requests a firmware update, the system enters remote upgrade mode. The upgrade process is controlled by the processor, which first receives the firmware file information uploaded by the remote client, including file length, checksum, and segment identifiers. It then enters the data reception phase. The new firmware is transmitted segment by segment in data packets, each with a checksum field. The system immediately verifies the data upon receipt to ensure data integrity.

[0098] After receiving all the firmware, the processor writes the new version to a backup storage area and performs an integrity check and version identification write operation. If all checks pass, the processor initiates a system reset, automatically loads the new firmware, and enters normal operation. If there is an interruption during the transmission process, a verification failure, or an abnormal power outage, the processor will automatically restore to the old firmware at the next startup, ensuring a safe system boot and preventing system paralysis due to upgrade failure.

[0099] The entire remote access process supports multi-user authentication. Each access requires a username and password. The system supports three levels of access: user, maintenance personnel, and administrator. Different permissions correspond to different access functions. For example, user access can only read data, while administrators can modify parameters and perform firmware upgrades. User logins and operations are recorded in the security log for easy auditing and permission management.

[0100] The remote access interface supports either a command-line protocol or a web-based graphical interface. If the web interface is enabled, the processor embeds web resources and a simple server program, allowing clients to access system status and configuration pages through a browser without installing additional software, improving system usability and compatibility.

[0101] By introducing a remote access and update module, the system enables remote configuration, monitoring, debugging, and maintenance, significantly improving operational efficiency and deployment flexibility. Parameter modification and troubleshooting can be completed without on-site intervention, making it suitable for time synchronization equipment deployed in remote or complex environments. Support for breakpoint upgrades and permission control improves system stability and information security, enhancing the system's maintainability and engineering adaptability in key sectors such as industry, energy, and transportation.

[0102] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A SOPC time synchronization method based on FPGA, characterized in that: The method comprises: An integrated time synchronization system is built in a single FPGA chip. The time synchronization system includes a data receiving unit, a time analysis unit, a time control unit, and a human-computer interaction unit. Obtain external timing signals through the data receiving unit, the timing signals include time messages and synchronization pulse signals provided by the satellite timing module; The time parsing unit parses the time message, extracts time information according to preset rules, and selects a reference source based on quality parameters of multiple time sources; The time control unit generates local standard time and multiple synchronous output signals based on the selected time reference source; The human-computer interaction unit uses a configurable soft-core processor embedded in the FPGA chip to read the human-computer interaction parameters in the configuration memory, control the display interface to output the current time information, and update the configuration parameters in response to user operations; Configuration parameters are saved in non-volatile external memory in power-off state and automatically loaded after the system is powered on to ensure the continuity and stability of the time synchronization system; The human-computer interaction unit, time analysis unit and time control unit are integrated into the FPGA chip, eliminating the communication delay between chips, reducing hardware complexity and cost, and improving the integration and response speed of the time synchronization system.

2. The FPGA-based SOPC time synchronization method according to claim 1, wherein: The time parsing unit includes an IRIG-B signal parsing module, which is used to parse the input pulse width coded signal and obtain time information in B code format by identifying logical bits and time delimiters.

3. The FPGA-based SOPC time synchronization method according to claim 1, wherein: The time control unit supports the simultaneous output of multiple formats of synchronization signals, including pulses per second, pulses per minute, pulses per hour, TTL level signals, RS232 serial port signals and RS485 differential signals.

4. The FPGA-based SOPC time synchronization method according to claim 1, wherein: The display interface controlled by the human-computer interaction unit is a graphic liquid crystal display LCD12864. The soft-core processor realizes instruction transmission and refresh operation on the LCD through the PIO interface, and supports graphical output of time information and menu-based interactive operation.

5. The FPGA-based SOPC time synchronization method according to claim 1, wherein: The configuration parameters include display brightness, time format, synchronization signal type selection, user authority level and serial port baud rate setting.

6. The FPGA-based SOPC time synchronization method according to claim 1, wherein: The non-volatile external memory is a flash chip, and the soft-core processor periodically stores the configuration parameters redundantly through the SPI interface.

7. The FPGA-based SOPC time synchronization method according to claim 1, wherein: The data receiving unit includes a message buffer module and a redundancy check mechanism, wherein the message buffer module is used to temporarily store the satellite data sequence to be parsed. The redundancy check mechanism uses a CRC algorithm to verify data integrity. If a data anomaly is detected, a re-request logic is triggered to prevent erroneous time information from participating in system time calculation.

8. The FPGA-based SOPC time synchronization method according to claim 1, wherein: The soft-core processor and the FPGA logic area exchange key data through a shared memory mechanism. The shared memory uses on-chip RAM to achieve high-speed reading and writing of data, and sets a mutually exclusive access flag to ensure data consistency and access security in a synchronous state.

9. The FPGA-based SOPC time synchronization method according to claim 1, wherein: The human-computer interaction unit also includes a key scanning module and a menu management module. The key scanning module detects user input in a periodic polling manner, and the menu management module performs content jumps, option highlights, and parameter confirmation actions according to the current page status.

10. The FPGA-based SOPC time synchronization method according to claim 1, wherein: The time synchronization system also includes a remote access and update module. The soft-core processor realizes remote reading and updating of system firmware version, configuration parameters and operation logs through an integrated Ethernet interface.

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