Configuration method, device and sampling method for high-speed communication of SPI (Serial Peripheral Interface) host

Abstract

The invention belongs to the technical field of signal communication, and particularly relates to a configuration method and device for SPI host high-speed communication and a sampling method. Comprising the following steps: acquiring an on-line waveform of a communication cable between an SPI host and an SPI slave, and obtaining on-line delay time Tdelay; configuring device delay time T1 according to the on-line delay time; according to the frequency of the working clock and the frequency of the serial clock, clock delay time T2 is configured; the delay time T1 of the device and the delay time T2 of the clock meet the condition of Tdelay; t1 + T2lt; tdelay + Tsclk, wherein Tsclk represents a period of a serial clock. According to the invention, a combined scheme of device delay and clock delay is used, so that the sampling precision of the SPI host is improved, and the communication rate between SPI equipment is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal communication, and in particular relates to a configuration method, a device and a sampling method for SPI host high-speed communication. Background Art

[0002] During SPI communication, the master device provides a clock signal, a chip select signal, and a MOSI data signal to the slave device. The slave device samples the MOSI data according to the master clock and responds with a MISO data signal to the master. Due to internal chip path delays or line delays between the master and slave devices connected by a cable, sampling errors may occur when the master directly samples the MISO data signal using its own SCLK signal during high-speed communication. Furthermore, the faster the serial rate, the greater the impact of time delay on the master's sampling. This limits the communication frequency of SPI devices, necessitating delayed sampling by the master for correct communication during high-speed communication.

[0003] Existing technology uses clock delay based on the SPI host's operating clock frequency. This delay, within the allowable range of line delay, is performed by delaying N CLK clocks to ensure the SPI host sampling clock can correctly sample the MISO data signal. However, when the SPI operating clock is equal to the SCLK sent by the host, delaying N CLKs based on the SPI host's operating clock does not achieve the required accuracy and cannot meet the delayed sampling requirements. Summary of the Invention

[0004] The purpose of the present invention is to solve the problems of the prior art and to provide a configuration method, device and sampling method for SPI host high-speed communication.

[0005] In order to achieve the above object, the technical solution provided by the present invention is: A method for configuring SPI host high-speed communication, comprising: Collect the online waveform of the communication cable between the SPI master and slave, and obtain the online delay time T delay ; According to the online delay time T delay , configure the device delay time T1 so that T1 ≥ T delay ; Configure the clock delay time T2 according to the frequency of the working clock and the frequency of the serial clock. The clock delay time T2 = N*T spiclk , where T spiclk Represents the period of a working clock, N represents the number of periods of the working clock, and N is a non-negative integer; The device delay time T1 and the clock delay time T2 meet the conditions: T delay <T1+T2<Tdelay +T sclk , where T sclk Represents a serial clock cycle; The sum of the device delay time that meets the conditions and the clock delay time is used as the delayed sampling clock.

[0006] Furthermore, the clock delay time T2 is configured according to the frequency of the working clock and the frequency of the serial clock, and the clock delay time T2=N*T spiclk , including: when the frequency of the working clock is equal to the frequency of the serial clock, N=0.

[0007] Furthermore, the device delay time is formed by the accumulation of propagation delays of multiple buffer units.

[0008] Furthermore, the device delay time includes six gears, namely: 0ns, 10ns, 20ns, 30ns, 40ns and 50ns, and the device delay time is configured to be greater than or equal to the first gear of the online delay time.

[0009] Furthermore, the device delay time T1 and the clock delay time T2 satisfy the following conditions: delay +1 / 4T sclk <T1+T2<T delay +3 / 4T sclk .

[0010] A configuration device for SPI host high-speed communication includes a device delay unit and a clock delay unit, wherein: The device delay unit is used to collect the online waveform of the communication cable between the SPI host and the slave to obtain the online delay time; according to the online delay time T delay , configure the device delay time T1 so that T1 ≥ T delay ; The clock delay unit is used to obtain the device delay time T1 and configure the clock delay time T2 according to the frequency of the working clock and the frequency of the serial clock. The clock delay time T2 = N*T spiclk , where T spiclk Represents the cycle of a working clock, N represents the number of working clock cycles, N is a non-negative integer; the device delay time T1 and the clock delay time T2 meet the conditions: T delay <T1+T2<T delay +T sclk , where T sclk Represents a serial clock cycle; the sum of the device delay time that meets the conditions and the clock delay time is used as the delayed sampling clock, and the delayed sampling clock is output.

[0011] A sampling method for SPI host high-speed communication, comprising: According to the configuration method of the SPI host high-speed communication according to claims 1-5, the device delay time and the clock delay time are configured to obtain a delayed sampling clock; The SPI master performs sampling based on the delayed sampling clock.

[0012] Compared with the prior art, the present invention has the following significant advantages: the device delay time of the present invention is a fixed gear and is not affected by the SPI host operating clock frequency; when the SPI host operating clock frequency is greater than the frequency of the serial clock SCLK, a combination of device delay and clock delay can be used, thereby improving the accuracy of SPI host sampling and increasing the communication rate between SPI devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a flow chart of a sampling method for SPI host high-speed communication of the present invention; Figure 2 This is an example diagram when the frequency of the working clock of the present invention is greater than the frequency of the serial clock; Figure 3 This is an example diagram when the frequency of the working clock of the present invention is equal to the frequency of the serial clock; Figure 4 This is a schematic diagram of a configuration device for SPI host high-speed communication according to the present invention. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0015] The host of the present invention sends a serial clock signal, a chip select signal, and a MOSI data signal to the slave. The slave samples the MOSI data according to the clock provided by the host and replies with a MISO data signal to the host. The host samples the MISO data replied by the slave according to the delayed sampling clock. The present invention uses a method of combining two delay modes, device delay and clock delay, to achieve the desired delay time according to different online delay times T. delay Flexible configuration of the sampling clock delay time of the SPI master enables the SPI master to correctly sample the MISO data signal of the slave, thereby improving the communication rate between the SPI master and slave.

[0016] Example 1, as Figure 1 As shown, this embodiment provides a sampling method for SPI host high-speed communication, and the specific steps include: 1) Based on the online waveform of the communication cable between the SPI master and the slave, confirm the online delay time T between the serial clock SCLK signal line sent by the SPI master and the MISO data signal line replied by the slave. delay .

[0017] 2) Configure the SPI host to delay the sampling time. The present invention adopts the solution of device delay plus clock delay. First, according to T delay Select the device delay position, there are six positions (0ns, 10ns, 20ns, 30ns, 40ns and 50ns), the device delay time T1 is greater than or equal to T delay The device delay time is preferably configured to be greater than or equal to the first gear of the line delay time. The device delay time is formed by the cumulative propagation delay of multiple buffers (buffer units). Each buffer logic gate has an inherent propagation delay, that is, the transmission time of the signal from input to output. For example, the delay time of a buffer is T pd (Typical value is 0.1ns, depending on the process and load.) When multiple buffers are connected in series, the total delay is the accumulation of the delay of each buffer, so the total delay of M buffers is M*T pd By adjusting the number of buffers in series, the total signal path delay can be precisely controlled. By utilizing device delays, the path delay of the SPI master sampling clock can be flexibly adjusted without being affected by the SPI master operating clock.

[0018] 3) According to the frequency F of the SPI host's working clock spiclk and the serial clock frequency F sclk Select the gear of clock delay. The clock delay is an N-level D flip-flop with a working clock cycle as the clock. Configure the clock delay time T2=N*T spiclk , where T spiclk Represents the period of a working clock, N represents the number of working clock periods, and N is a non-negative integer. When the working clock frequency is equal to the serial clock frequency, N = 0. When the working clock frequency is greater than the serial clock frequency, N is a positive integer.

[0019] 4) The device delay time T1 plus the clock delay time T2 should meet the following conditions: T delay <T1+T2<T delay +T sclk ; According to the above conditions, the time of T1 and T2 can be reasonably allocated and configured until the SPI master can accurately sample the MISO data signal replied by the slave. The delayed clock sampling edge should fall as close as possible to the center of each bit of the MISO data signal, that is, T delay+1 / 4T sclk <T1+T2<T delay +3 / 4T sclk When N has multiple values ​​that meet the conditions, the best choice is the one where the delayed clock sampling edge is closest to T delay +1 / 2T sclk The value of when.

[0020] 5) The SPI master performs sampling based on the delayed sampling clock.

[0021] like Figure 2 As shown in the figure, SPICLK is the working clock of the SPI host, and SCLK is the serial clock sent by the SPI host. If SCLK is used to directly sample the MISO signal, sampling errors will occur. SCLK_Smin is the sampling clock with the minimum delay time for the SPI host to correctly sample, and SCLK_Smax is the sampling clock with the maximum delay time for the SPI host to correctly sample, that is, T delay <T1+T2<T delay +T sclk , the delayed sampling clock SCLK_S is in the range of SCLK_Smin to SCLK_Smax, and can be sampled correctly.

[0022] The present invention adopts a scheme of combining device delay and clock delay, and uses the sum of the device delay time and the clock delay time that meet the conditions as the delayed sampling clock. The serial clock SCLK sent by the SPI host is generated by dividing its working clock SPICLK, so the clock frequency F spiclk ≥F sclk .like Figure 3 As shown, when F spiclk =F sclk If the clock delay is used directly to delay N T spiclk , it will cause greater deviation, and the SPI host cannot perform sampling correctly. In this case, the present invention only adopts the device delay method. The device delay time is fixed in 6 gears and is not affected by the SPI host working clock frequency. Regardless of the relationship between the working clock frequency and the serial clock frequency, it can be adjusted according to the online delay T delay time to configure.

[0023] When the frequency of the SPI master working clock is greater than the frequency of the serial clock, a combination of device delay and clock delay can be used to improve the accuracy of SPI master sampling and increase the communication rate between SPI devices.

[0024] Example 2, as Figure 4 As shown, this embodiment provides a configuration device for SPI host high-speed communication, including a device delay unit and a clock delay unit, wherein: The device delay unit is used to collect the online waveform of the communication cable between the SPI master and the slave, receive the online delay time, and calculate the delay time according to the online delay time T. delay , configure the device delay time T1 so that T1 ≥ T delay ; The clock delay unit is used to obtain the device delay time T1 and configure the clock delay time T2 according to the frequency of the working clock and the frequency of the serial clock. The clock delay time T2 = N*T spiclk , where T spiclk Represents the cycle of a working clock, N represents the number of working clock cycles, N is a non-negative integer; the device delay time T1 and the clock delay time T2 meet the conditions: T delay <T1+T2<T delay +T sclk , where T sclk Represents the period of a serial clock. The sum of the device delay time that meets the conditions and the clock delay time is used as the delayed sampling clock, and the delayed sampling clock is finally output.

[0025] In an application, the master's clock generation module sends a serial clock signal to the slave, and the data transmission module sends a chip select signal and a MOSI data signal to the slave. The slave samples the MOSI data according to the master's clock and responds with a MISO data signal to the master. The clock delay unit outputs a delayed sampling clock that is input to the data receiving module, which samples the MISO data from the slave according to the delayed sampling clock.

[0026] For the specific definition of the configuration device for SPI host high-speed communication, please refer to the definition of the configuration method for SPI host high-speed communication above, which will not be repeated here.

[0027] Example 3. This embodiment provides a sampling method for SPI host high-speed communication, including: configuring a device delay time and a clock delay time according to a configuration method for SPI host high-speed communication to obtain a delayed sampling clock; and the SPI host performs sampling based on the delayed sampling clock.

[0028] For specific limitations on the sampling method for SPI host high-speed communication, please refer to the limitations on the configuration method for SPI host high-speed communication above, which will not be repeated here.

[0029] The present invention can effectively avoid the sampling error problem caused by the online delay of the SPI host, and the combination of device delay and clock delay adopted can flexibly configure the time of delayed sampling of the SPI host, thereby effectively improving the communication rate between SPI devices.

[0030] The above-described embodiments merely represent several implementation methods of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A configuration method for SPI host high-speed communication, characterized in that, The configuration method of the SPI host high-speed communication includes: Collect the online waveform of the communication cable between the SPI master and slave, and obtain the online delay time T delay ; According to the online delay time T delay , configure the device delay time T1 so that T1 ≥ T delay ; Configure the clock delay time T2 according to the frequency of the working clock and the frequency of the serial clock. The clock delay time T2 = N*T spiclk , where T spiclk Represents the period of a working clock, N represents the number of periods of the working clock, and N is a non-negative integer; The device delay time T1 and the clock delay time T2 meet the conditions: T delay <T1+T2<T delay +T sclk , where T sclk Represents a serial clock cycle; The sum of the device delay time that meets the conditions and the clock delay time is used as the delayed sampling clock.

2. The configuration method of SPI host high-speed communication according to claim 1, wherein The clock delay time T2 is configured according to the frequency of the working clock and the frequency of the serial clock, and the clock delay time T2=N*T spiclk , including: when the frequency of the working clock is equal to the frequency of the serial clock, N=0.

3. The configuration method of SPI host high-speed communication according to claim 1, wherein The device delay time is formed by the accumulation of propagation delays of multiple buffer units.

4. The configuration method of SPI host high-speed communication according to claim 1, wherein The device delay time includes six gears, namely: 0ns, 10ns, 20ns, 30ns, 40ns and 50ns, and the device delay time is configured to be greater than or equal to the first gear of the online delay time.

5. The configuration method of SPI host high-speed communication according to claim 1, wherein The device delay time T1 and the clock delay time T2 meet the conditions: T delay +1 / 4T sclk <T1+T2<T delay +3 / 4T sclk .

6. A configuration device for SPI host high-speed communication, characterized in that: It includes a device delay unit and a clock delay unit, wherein: The device delay unit is used to collect the online waveform of the communication cable between the SPI host and the slave to obtain the online delay time; according to the online delay time T delay , configure the device delay time T1 so that T1 ≥ T delay ; The clock delay unit is used to obtain the device delay time T1 and configure the clock delay time T2 according to the frequency of the working clock and the frequency of the serial clock. The clock delay time T2 = N*T spiclk , where T spiclk Represents the cycle of a working clock, N represents the number of working clock cycles, N is a non-negative integer; the device delay time T1 and the clock delay time T2 meet the conditions: T delay <T1+T2<T delay +T sclk , where T sclk Represents a serial clock cycle; the sum of the device delay time that meets the conditions and the clock delay time is used as the delayed sampling clock, and the delayed sampling clock is output.

7. A sampling method for SPI host high-speed communication, characterized in that: The sampling method of the SPI host high-speed communication comprises: According to the configuration method of the SPI host high-speed communication according to claims 1-5, the device delay time and the clock delay time are configured to obtain a delayed sampling clock; The SPI master performs sampling based on the delayed sampling clock.

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