Obstacle modeling and avoiding method and device applied to superconducting quantum chip wiring environment

Abstract

The embodiment of the invention discloses an obstacle modeling and avoiding method and device applied to a superconducting quantum chip wiring environment. A specific embodiment of the method comprises the following steps: for each path segment, executing the following collision detection steps: determining a minimum distance between the path segment and a corresponding original obstacle polygon; determining a first path point corresponding to the path segment as a candidate node in response to determining that the minimum distance is smaller than the safe buffer distance; constructing a path search graph corresponding to the superconducting quantum chip; adding each candidate node into the path search graph, and planning an obstacle avoidance path from the starting path point to the ending path point through an intelligent obstacle avoidance path planning algorithm; and performing optimization modeling on each physical device and the obstacle avoidance path on the superconducting quantum chip to generate a superconducting quantum chip wiring modeling graph. According to the embodiment, the collision detection efficiency can be remarkably improved, rapid detection is realized by adopting an optimization algorithm based on computational geometry, and the method is particularly suitable for large-scale quantum chip layout.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of chip obstacle modeling and avoidance, and more specifically, to a method and apparatus for obstacle modeling and avoidance applied to a superconducting quantum chip wiring environment. Background Art

[0002] With the rapid development of superconducting quantum computing technology, the integration and complexity of quantum chips have continued to increase. The number of qubits integrated on a chip has grown from a few in the early days to hundreds or even thousands today. Consequently, the wiring structures for the interconnection networks, control circuits, and readout circuits between qubits have become extremely complex and dense. In this high-density quantum chip layout, traditional manual wiring methods are no longer able to meet the design efficiency and accuracy requirements. Existing electronic design automation (EDA) tools, primarily designed for conventional semiconductor chip design, lack specific considerations for the unique geometries, stringent coherence requirements, and physical constraints of ultra-low-temperature operating environments of quantum devices. In particular, during the wiring of quantum chips, due to the fragility of quantum states and the limitations of quantum coherence time, wiring paths must strictly avoid various obstacles (such as other qubits, couplers, control electrodes, etc.) and maintain sufficient safety distances to prevent crosstalk and decoherence. This places extremely high demands on the accuracy of obstacle modeling and the reliability of obstacle avoidance algorithms. However, the current lack of high-precision obstacle modeling technology and intelligent obstacle avoidance systems specifically tailored to the wiring environment of superconducting quantum chips has led to long quantum chip design cycles and low success rates, severely hindering the development of quantum computing hardware. Summary of the Invention

[0003] The content of this disclosure is used to briefly introduce concepts that will be described in detail in the detailed description section below. The content of this disclosure is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0004] Some embodiments of the present disclosure provide methods, devices, electronic devices, and computer-readable media for obstacle modeling and avoidance in a superconducting quantum chip wiring environment to address the technical issues mentioned in the background technology section above.

[0005] In a first aspect, some embodiments of the present disclosure provide an obstacle modeling and avoidance method for a superconducting quantum chip wiring environment. The method comprises: geometrically modeling and initializing each physical device on the superconducting quantum chip; performing a buffer expansion on an original obstacle polygon corresponding to each physical device to generate an extended obstacle polygon; determining an initial wiring path on the superconducting quantum chip, wherein the initial wiring path comprises a sequence of path points, where two adjacent path points form a path segment; performing the following collision detection steps for each path segment: determining a minimum distance between the path segment and the corresponding original obstacle polygon; in response to determining that the minimum distance is less than a safety buffer distance, determining the first path point corresponding to the path segment as a candidate node; constructing a path search graph corresponding to the superconducting quantum chip, wherein the spacing between nodes in the path search graph is a preset spacing; adding each candidate node to the path search graph, and planning an obstacle avoidance path from a starting path point to an ending path point using an intelligent obstacle avoidance path planning algorithm; and optimizing and modeling each physical device and obstacle avoidance path on the superconducting quantum chip to generate a superconducting quantum chip wiring modeling graph.

[0006] In a second aspect, some embodiments of the present disclosure provide an obstacle modeling and obstacle avoidance device for use in a superconducting quantum chip wiring environment, the device comprising: an initialization unit configured to perform geometric modeling and initialization processing on each physical device on the superconducting quantum chip; an expansion unit configured to perform buffer expansion on the original obstacle polygon corresponding to each physical device to generate an expanded obstacle polygon; a determination unit configured to determine an initial wiring path on the superconducting quantum chip, wherein the initial wiring path comprises: a sequence of path points, wherein two adjacent path points form a path segment; and a distance determination unit configured to perform the following collision detection steps for each path segment: The method comprises the following steps: determining a minimum distance between the path segment and the corresponding original obstacle polygon; in response to determining that the minimum distance is less than the safety buffer distance, determining the first path point corresponding to the path segment as a candidate node; a construction unit configured to construct a path search graph corresponding to the superconducting quantum chip, wherein the spacing between each node in the path search graph is a preset spacing; a planning unit configured to add each candidate node to the path search graph, and plan an obstacle avoidance path from the starting path point to the ending path point through an intelligent obstacle avoidance path planning algorithm; and a modeling unit configured to optimize and model each physical device and obstacle avoidance path on the superconducting quantum chip to generate a superconducting quantum chip wiring modeling diagram.

[0007] In a third aspect, some embodiments of the present disclosure provide an electronic device comprising: one or more processors; a storage device on which one or more programs are stored, and when the one or more programs are executed by one or more processors, the one or more processors implement the method described in any implementation of the first aspect above.

[0008] In a fourth aspect, some embodiments of the present disclosure provide a computer-readable medium having a computer program stored thereon, wherein when the program is executed by a processor, the method described in any implementation of the first aspect is implemented.

[0009] The above-mentioned various embodiments of the present disclosure have the following beneficial effects: through the obstacle modeling and obstacle avoidance methods applied to the superconducting quantum chip wiring environment of some embodiments of the present disclosure, micron-level precision geometric modeling of various devices in the superconducting quantum chip can be achieved, supporting accurate mathematical representation of complex structures such as quantum bits, couplers and control circuits, and providing accurate obstacle environment description for subsequent path planning; it is conducive to establishing a configurable safety buffer zone through the Minkowski sum algorithm, and can dynamically adjust the buffer distance according to process requirements to effectively prevent electromagnetic interference and physical conflicts between wiring paths and devices; it can significantly improve the efficiency of collision detection and achieve rapid detection using an optimization algorithm based on computational geometry, which is particularly suitable for large-scale quantum chip layout; it is conducive to reducing the difficulty of quantum chip wiring, automating wiring through an automated obstacle avoidance system, and at the same time ensuring that the wiring quality meets the process requirements of superconducting quantum circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that components and elements are not necessarily drawn to scale.

[0011] Figure 1 is a flow chart of some embodiments of the obstacle modeling and obstacle avoidance method applied to the superconducting quantum chip wiring environment according to the present disclosure; Figure 2 This is a schematic diagram of geometric modeling in the obstacle modeling and obstacle avoidance method applied to the superconducting quantum chip wiring environment in some embodiments of the present disclosure; Figure 3 is a comparative schematic diagram of buffer zone expansion in obstacle modeling and obstacle avoidance methods applied to superconducting quantum chip wiring environments according to some embodiments of the present disclosure; Figure 4 This is a planning diagram of an intelligent obstacle avoidance path planning algorithm in an obstacle modeling and obstacle avoidance method applied to a superconducting quantum chip wiring environment in some embodiments of the present disclosure; Figure 5 This is a schematic diagram of a superconducting quantum chip wiring modeling diagram in an obstacle modeling and obstacle avoidance method applied to a superconducting quantum chip wiring environment in some embodiments of the present disclosure; Figure 6 1 is a schematic structural diagram of some embodiments of an obstacle modeling and obstacle avoidance device applied to a superconducting quantum chip wiring environment according to the present disclosure; Figure 7 It is a structural diagram of an electronic device suitable for implementing some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0013] It should also be noted that, for ease of description, only the parts related to the invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0014] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0015] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0016] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0017] The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0018] Figure 1 This is a process 100 of some embodiments of the obstacle modeling and obstacle avoidance method applied to a superconducting quantum chip wiring environment in some embodiments of the present disclosure. The obstacle modeling and obstacle avoidance method applied to a superconducting quantum chip wiring environment includes the following steps: Step 101: Perform geometric modeling and initialization processing on each physical device on the superconducting quantum chip.

[0019] In some embodiments, an entity (e.g., a computing device) executing an obstacle modeling and avoidance method for a superconducting quantum chip wiring environment may perform geometric modeling and initialization on each physical device on the superconducting quantum chip. Each physical device includes each qubit, each coupler, and each control circuit.

[0020] It should be noted that: Data structure 1: obstacle geometry representation structure The obstacle geometry is represented using a polygonal structure represented by an ordered sequence of vertices. Each obstacle consists of a series of two-dimensional coordinate points, forming a closed polygonal boundary. Vertex coordinate accuracy reaches micrometer levels, enabling precise description of the geometry of various devices on the quantum chip. This data structure supports polygonal representations of arbitrary complexity, including both convex and concave polygons.

[0021] Data Structure 2: Quantum Device Component Structure The quantum device component structure is used to store complete information about quantum devices, including geometric boundary polygons, geometric center position coordinates, device type identification, and device size parameters. This structure can distinguish different types of quantum devices, such as qubits and couplers, and assign corresponding geometric parameters and physical properties to each device type.

[0022] Data Structure 3: Extended Obstacle Buffer Structure The extended obstacle buffer structure stores a collection of obstacle boundary polygons after they have been expanded by a safety distance. This structure maintains the mapping between the original obstacle and its corresponding extended boundary, supports dynamic buffer resizing, and ensures that the expanded polygons remain geometrically valid and topologically correct.

[0023] In practice, the above-mentioned execution entity can perform geometric modeling and initialization processing on each physical device on the superconducting quantum chip through the following steps: In the first step, for each qubit, the following processing steps are performed: 1. Use a square with a preset side length to represent the quantum bit.

[0024] 2. Determine the central coordinates of the geometric center of the quantum bit.

[0025] 3. Based on the above center coordinates, determine the coordinates of the four vertices corresponding to the quantum bit.

[0026] As an example, for a quantum bit device, the side length is set to the preset side length s qubit The square is represented by a square with a geometric center at coordinate (x c ,y c ), then the coordinates of its four vertices are: .

[0027] Among them, P1, P2, P3, and P4 represent the coordinates of four vertices.

[0028] In the second step, for each control line, the control line is modeled as a rectangular strip. The control line is modeled as a rectangular strip, and its width is determined by the process requirements.

[0029] In the third step, for each coupler, the coupler is modeled as a coupler square, where the side length of the coupler square is less than the preset side length. For other devices such as couplers, similar geometric modeling methods are used, but the size parameter s coupler Typically smaller than the qubit size.

[0030] The example effect of the implementation of step 101 is as follows Figure 2 As shown, the complete quantum chip obstacle environment layout is displayed, including the accurate geometric modeling results of 16 quantum bits (blue squares), 9 couplers (green squares) and multiple control lines (red rectangles).

[0031] Step 102 : For each original obstacle polygon corresponding to a physical device, perform buffer expansion on the original obstacle polygon to generate an expanded obstacle polygon.

[0032] In some embodiments, the execution entity may perform a buffer zone expansion on the original obstacle polygon corresponding to each physical device to generate an expanded obstacle polygon.

[0033] In practice, the above execution entity can determine the extended obstacle polygon by the following formula based on the preset safety buffer distance: P expanded =P⊕B(d buffer ), Among them, B(d buffer ) represents the radius d buffer The disk is ⊕, which represents the Minkowski sum operation. The Minkowski sum operation refers to the Minkowski Sum operation.

[0034] As an example, given the original obstacle polygon P = {p1, p2, ..., p n} and safety buffer distance d buffer , expand the obstacle polygon P expanded Obtained through the following mathematical transformation: P expanded =P⊕B(d buffer ), In a specific implementation, the aforementioned execution entity can employ a polygonal buffer expansion algorithm based on computational geometry theory. This algorithm controls the accuracy and quality of the expansion process by setting specific geometric parameters. These specific geometric parameters include: a buffer distance parameter (buffer_distance) that defines the radius of the safety buffer around obstacles; an endpoint processing mode parameter (cap_style), where we use the CAP_ROUND circular endpoint processing mode to ensure a smooth buffer boundary and avoid sharp corners; and a join mode parameter (join_style), where we use the JOIN_ROUND circular join mode to avoid sharp outer corners and provide a smoother buffer boundary.

[0035] When performing a buffering operation, a circular endpoint processing mode is used, which means that when the boundary segment of a polygon is extended, its endpoints will be extended in a semicircular manner instead of a square or straight truncation. This circular endpoint processing ensures that the extended boundary maintains a smooth curve transition at the endpoints of the segment, avoiding geometric discontinuities that may be caused by sharp corners. At the same time, the system sets a circular connection mode to handle the connection area between adjacent polygon edges. When two adjacent polygon edges are buffered and extended, their connection will form an arc transition instead of a sharp corner or bevel. This circular connection method is based on an arc with the connection point as the center and the buffer distance as the radius to fill the gap area between the two extended edges. The mathematical expression of the circular connection mode is: for the angle θ between two adjacent edges, the arc angle range of the connection area is π-θ, ​​and the arc radius is equal to the set safety buffer distance d buffer This double circular processing strategy ensures the geometric continuity of the expansion result, making the expanded polygon boundary differentiable everywhere, without geometric singularities or discontinuous derivatives. Geometric continuity is crucial for subsequent collision detection algorithms, as smooth boundaries can provide more stable and accurate distance calculation results. At the same time, circular processing also ensures the topological consistency of the expansion operation, that is, the expanded polygon maintains the same topological structure as the original polygon, and does not have abnormal geometric phenomena such as self-intersections or holes.

[0036] In addition, adaptive resolution control is used in buffering operations to dynamically adjust the discretization accuracy of the arc according to the size of the buffer distance. The system adopts a segmented resolution control strategy based on the buffer distance threshold. When the buffer distance is less than 1.0 micron, the system increases the angular resolution of the arc to 32-64 sampling points, ensuring that each angular step does not exceed 5.625°-11.25°, thereby maintaining sub-micron geometric accuracy within the tiny buffer area. When the buffer distance is in the medium range of 1.0-3.0 microns, the system uses a standard 16 sampling points for arc discretization with an angular step of 22.5°, balancing geometric quality and computational efficiency. When the buffer distance exceeds 3.0 microns, the system intelligently reduces the resolution to 8 sampling points and expands the angular step to 45°. Although some geometric precision is sacrificed, the processing speed of large-scale buffer calculations is significantly improved. This dynamic adjustment mechanism automatically selects the optimal combination of discretization parameters by monitoring the ratio of buffer distance to polygon complexity in real time, ensuring high-precision modeling in dense areas of quantum devices (such as quantum bit arrays) and improving computing efficiency in sparse control line areas. Ultimately, it achieves an intelligent balance between geometric quality and algorithm performance. It is particularly suitable for complex wiring environments in superconducting quantum chips where different functional areas have different precision requirements.

[0037] The expansion effect of step 102 is as follows Figure 3 As an example, Figure 3 The left side shows the precise geometric modeling of the original obstacle polygons. Figure 3 The right side shows the obstacle boundary (orange dashed area) after the 0.5μm safety buffer distance is extended, clearly comparing the geometric differences before and after the extension.

[0038] Step 103: Determine an initial wiring path on the superconducting quantum chip.

[0039] In some embodiments, the execution entity may determine an initial wiring path on the superconducting quantum chip, wherein the initial wiring path includes a sequence of path points, where two adjacent path points form a path segment.

[0040] For example, given the initial routing path: Path={waypoint1,waypoint2,...,waypoint m}.

[0041] Step 104: For each path segment, perform the following collision detection steps: Step 1041 : Determine the minimum distance between the path segment and the corresponding original obstacle polygon.

[0042] In some embodiments, the execution entity may determine a minimum distance between the path segment and the corresponding original obstacle polygon.

[0043] In practice, the execution entity may determine the minimum distance between the path segment and the corresponding original obstacle polygon by the following steps: The first step is to perform collision detection between the above path segment and the corresponding original obstacle polygon using the following formula: , Among them, L i Represents a path segment, P j Represents the corresponding original obstacle polygon, and collision represents the collision detection result; In the second step, in response to determining that the collision detection result indicates no collision, the minimum distance between the above path segment and the corresponding original obstacle polygon is determined by the following formula: .

[0044] As an example, the path segment L i = waypoint i →waypoint (i+1) .

[0045] The corresponding original obstacle polygon may refer to an obstacle polygon closest to the path segment.

[0046] Step 1042: In response to determining that the minimum distance is less than the safety buffer distance, the first path point corresponding to the path segment is determined as a candidate node.

[0047] In some embodiments, the execution entity may determine the first path point corresponding to the path segment as a candidate node in response to determining that the minimum distance is less than the safety buffer distance.

[0048] When d min <d buffe When , the buffer zone corresponding to the original obstacle polygon is determined to be in violation. The above execution entity can use efficient geometric calculation methods to implement intersection determination and distance calculation. For a detection task containing n obstacles and m path segments, the algorithm time complexity is O(nm).

[0049] As an example, the path segment L i The corresponding first path point is waypoint i .

[0050] Step 105: construct a path search graph corresponding to the superconducting quantum chip.

[0051] In some embodiments, the execution entity may construct a path search graph corresponding to the superconducting quantum chip, wherein the distance between each node in the path search graph is a preset distance.

[0052] As an example, based on the A* search algorithm, a path search graph is constructed in the two-dimensional chip space of the superconducting quantum chip, and the node spacing is set to step size =2.0μm, ensuring the accuracy requirement of path planning.

[0053] Step 106 , adding each candidate node to the above path search graph, and planning an obstacle avoidance path from the starting path point to the ending path point through an intelligent obstacle avoidance path planning algorithm.

[0054] In some embodiments, the execution entity may add each candidate node to the path search graph, and plan an obstacle avoidance path from the starting path point to the ending path point through an intelligent obstacle avoidance path planning algorithm.

[0055] As an example, the core evaluation function of the A* search algorithm is: f(n)=g(n)+h(n).

[0056] Among them, g(n) represents the actual cost from the starting point (starting path point) to node n, and h(n) represents the heuristic estimated cost from node n to the end point (ending path point).

[0057] Next, the Euclidean distance is used as the heuristic function: .

[0058] Among them, the ones with the goal subscript are the horizontal coordinate x and the vertical coordinate y of the end point.

[0059] During the node expansion process, the algorithm considers neighbor nodes in 8 directions, and the movement vectors are: {(-1,-1),(-1,0),(-1,1),(0,-1),(0,1),(1,-1),(1,0),(1,1)}.

[0060] For each candidate node, the execution body calls the collision detection algorithm to verify the feasibility of the path segment. Only nodes that pass the collision detection will be added to the search queue. The implementation effect of step 106 is as follows: Figure 4 As shown in the figure, the left side shows the search process of the A* search algorithm, including: explored nodes (light blue dots) and boundary nodes (yellow dots), and the right side shows the final obstacle avoidance path (green line), which successfully bypasses all obstacles and meets the safety buffer requirements.

[0061] Step 107 : Optimize and model each physical device and obstacle avoidance path on the superconducting quantum chip to generate a superconducting quantum chip wiring modeling diagram.

[0062] In some embodiments, the execution entity may optimize and model each physical device and obstacle avoidance path on the superconducting quantum chip to generate a superconducting quantum chip wiring modeling diagram. For example, the execution entity may integrate obstacle modeling, buffer generation, collision detection, and path planning modules, using spatial indexing technology to optimize computing performance and achieve path smoothing, thereby forming a complete quantum chip wiring obstacle avoidance solution.

[0063] The aforementioned execution entities can integrate the aforementioned physical devices and obstacle avoidance paths to form a complete obstacle modeling and avoidance solution (superconducting quantum chip wiring modeling diagram). In practical applications, the system supports dynamic adjustment of safety buffer distance parameters to adapt to the requirements of different process nodes and design rules. For complex quantum chip layouts, the system uses spatial indexing technology to optimize collision detection performance, partitioning obstacles by spatial location and reducing unnecessary geometric calculations.

[0064] The complete superconducting quantum chip wiring modeling diagram is as follows Figure 5 As shown, the comprehensive application effect of obstacle modeling and obstacle avoidance system in complex quantum chip environment is demonstrated, including the complete technical chain of precise geometric modeling, safety buffer zone generation and intelligent obstacle avoidance path planning.

[0065] Further references Figure 6 As an implementation of the methods shown in the above figures, the present disclosure provides some embodiments of an obstacle modeling and obstacle avoidance device applied to a superconducting quantum chip wiring environment. These device embodiments are similar to Figure 1 Corresponding to the method embodiments shown, the obstacle modeling and obstacle avoidance device applied to the superconducting quantum chip wiring environment can be specifically applied to various electronic devices.

[0066] like Figure 6As shown, in some embodiments, an obstacle modeling and obstacle avoidance device 600 for a superconducting quantum chip wiring environment includes: an initialization unit 601, an expansion unit 602, a determination unit 603, a distance determination unit 604, a construction unit 605, a planning unit 606, and a modeling unit 607. The initialization unit 601 is configured to perform geometric modeling and initialization processing on each physical device on the superconducting quantum chip; the expansion unit 602 is configured to perform a buffer zone expansion on the original obstacle polygon corresponding to each physical device to generate an expanded obstacle polygon; the determination unit 603 is configured to determine an initial wiring path on the superconducting quantum chip, wherein the initial wiring path includes: a sequence of path points, where two adjacent path points form a path segment; and the distance determination unit 604 is configured to perform the following collision detection steps for each path segment: determining the collision between the path segment and the corresponding original obstacle polygon. In response to determining that the minimum distance is less than the safety buffer distance, the first path point corresponding to the path segment is determined as a candidate node; the construction unit 605 is configured to construct a path search graph corresponding to the superconducting quantum chip, wherein the spacing between each node in the path search graph is a preset spacing; the planning unit 606 is configured to add each candidate node to the path search graph, and plan an obstacle avoidance path from the starting path point to the ending path point through an intelligent obstacle avoidance path planning algorithm; the modeling unit 607 is configured to optimize and model each physical device and obstacle avoidance path on the superconducting quantum chip to generate a superconducting quantum chip wiring modeling diagram.

[0067] It is understandable that the various units and references recorded in the obstacle modeling and obstacle avoidance device 600 for superconducting quantum chip wiring environment are Figure 1 Therefore, the operations, features, and beneficial effects described above for the method are also applicable to the obstacle modeling and obstacle avoidance device 600 applied to the superconducting quantum chip wiring environment and the units included therein, and will not be repeated here.

[0068] Reference below Figure 7 , which shows a schematic structural diagram of an electronic device (such as a computing device) suitable for implementing some embodiments of the present disclosure. Figure 7 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure. Figure 7As shown, the computer device includes a processor, a memory and a network interface connected via a system bus, wherein the memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium can store an operating system and a computer program. The computer program includes program instructions, which, when executed, can enable the processor to execute any obstacle modeling and obstacle avoidance method applied to the superconducting quantum chip wiring environment. The processor is used to provide computing and control capabilities to support the operation of the entire computer device. The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium, which, when executed by the processor, can enable the processor to execute any obstacle modeling and obstacle avoidance method applied to the superconducting quantum chip wiring environment. The network interface is used for network communication, such as sending assigned tasks, etc. Those skilled in the art will understand that Figure 7 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present disclosure, and does not constitute a limitation on the computer device to which the solution of the present disclosure is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0069] It should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0070] In one embodiment, the processor is configured to execute a computer program stored in a memory to implement the following steps: geometrically modeling and initializing each physical device on the superconducting quantum chip; performing a buffer expansion on an original obstacle polygon corresponding to each physical device to generate an extended obstacle polygon; determining an initial wiring path on the superconducting quantum chip, wherein the initial wiring path includes a sequence of path points, where two adjacent path points form a path segment; performing the following collision detection steps for each path segment: determining a minimum distance between the path segment and the corresponding original obstacle polygon; in response to determining that the minimum distance is less than a safety buffer distance, determining the first path point corresponding to the path segment as a candidate node; constructing a path search graph corresponding to the superconducting quantum chip, wherein the spacing between nodes in the path search graph is a preset spacing; adding each candidate node to the path search graph, and planning an obstacle avoidance path from a starting path point to an ending path point using an intelligent obstacle avoidance path planning algorithm; and optimizing and modeling each physical device and obstacle avoidance path on the superconducting quantum chip to generate a superconducting quantum chip wiring modeling graph.

[0071] An embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. The computer program includes program instructions. The method implemented when the program instructions are executed can refer to the various embodiments of the obstacle modeling and obstacle avoidance method applied to the superconducting quantum chip wiring environment of the present disclosure.

[0072] The computer-readable storage medium may be an internal storage unit of the computer device described in the aforementioned embodiment, such as a hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a SmartMedia Card (SMC), a Secure Digital (SD) card, a flash memory card, etc., provided on the computer device.

[0073] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0074] The above descriptions are merely some preferred embodiments of the present disclosure and illustrate the underlying technical principles. Those skilled in the art should understand that the scope of the invention encompassed by the embodiments of the present disclosure is not limited to technical solutions formed by specific combinations of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the aforementioned inventive concept. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.

Claims

1. An obstacle modeling and avoidance method applied to a superconducting quantum chip wiring environment, characterized in that: include: Perform geometric modeling and initialization on each physical device on the superconducting quantum chip; For an original obstacle polygon corresponding to each physical device, performing buffer expansion on the original obstacle polygon to generate an expanded obstacle polygon; Determining an initial wiring path on the superconducting quantum chip, wherein the initial wiring path includes: a path point sequence, where two adjacent path points form a path segment; For each path segment, the following collision detection steps are performed: determining a minimum distance between the path segment and the corresponding original obstacle polygon; In response to determining that the minimum distance is less than the safety buffer distance, determining a first path point corresponding to the path segment as a candidate node; Constructing a path search graph corresponding to the superconducting quantum chip, wherein the spacing between nodes in the path search graph is a preset spacing; Add each candidate node to the path search graph, and plan an obstacle avoidance path from the starting path point to the ending path point using an intelligent obstacle avoidance path planning algorithm; Optimize and model each physical device and obstacle avoidance path on the superconducting quantum chip to generate a superconducting quantum chip wiring modeling diagram.

2. The method according to claim 1, characterized in that Each physical device includes: each quantum bit, each coupler, and each control circuit; and the geometric modeling and initialization processing of each physical device on the superconducting quantum chip includes: For each qubit, the following processing steps are performed: The quantum bit is represented by a square with a preset side length; Determining the central coordinates of the geometric center of the quantum bit; Determine the coordinates of the four vertices corresponding to the quantum bit according to the center coordinates; For each control line, the control line is modeled as a rectangular strip; For each coupler, the coupler is modeled as a coupler square, wherein a side length of the coupler square is less than a preset side length.

3. The method according to claim 2, characterized in that The buffer expansion of the original obstacle polygon to generate an extended obstacle polygon includes: The extended obstacle polygon is determined by the following formula using the preset safety buffer distance: P expanded =P⊕B(d buffer ), Among them, B(d buffer ) represents the radius d buffer The disk of , ⊕ represents the Minkowski sum operation.

4. The method according to claim 3, characterized in that Determining the minimum distance between the path segment and the corresponding original obstacle polygon includes: The collision detection between the path segment and the corresponding original obstacle polygon is performed using the following formula: ， Among them, L i Represents a path segment, P j Represents the corresponding original obstacle polygon, and collision represents the collision detection result; In response to determining that the collision detection result indicates no collision, a minimum distance between the path segment and the corresponding original obstacle polygon is determined by the following formula: 。 5. An obstacle modeling and avoidance device applied to a superconducting quantum chip wiring environment, characterized in that: include: an initialization unit, configured to perform geometric modeling and initialization processing on each physical device on the superconducting quantum chip; an expansion unit configured to perform buffer expansion on an original obstacle polygon corresponding to each physical device to generate an expanded obstacle polygon; a determining unit configured to determine an initial wiring path on the superconducting quantum chip, wherein the initial wiring path includes: a sequence of path points, where two adjacent path points form a path segment; a distance determination unit configured to perform the following collision detection steps for each path segment: determining a minimum distance between the path segment and a corresponding original obstacle polygon; and in response to determining that the minimum distance is less than a safety buffer distance, determining a first path point corresponding to the path segment as a candidate node; a construction unit configured to construct a path search graph corresponding to the superconducting quantum chip, wherein the distance between each node in the path search graph is a preset distance; a planning unit configured to add each candidate node to the path search graph and plan an obstacle avoidance path from a starting path point to an ending path point using an intelligent obstacle avoidance path planning algorithm; The modeling unit is configured to optimize and model each physical device and obstacle avoidance path on the superconducting quantum chip to generate a superconducting quantum chip wiring modeling diagram.

6. An electronic device, characterized in that: include: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 4.

7. A computer-readable medium, characterized in that A computer program is stored thereon, wherein when the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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