PCB signal processing method, electronic device and computer program product

Abstract

The invention provides a PCB signal processing method, electronic equipment and a computer program product, and relates to the technical field of computers. The PCB signal processing method comprises the steps that based on signal information of a PCB signal, a first worksheet containing the signal information is determined, and the signal information comprises a signal identifier and a signal length; and classifying the signal identifiers of the target signals based on the signal types, and determining a second worksheet containing the signal identifiers of different signal types. And based on the signal identifier of the first worksheet and the signal identifier of the second worksheet, matching the signal of the first worksheet with the target signal of the second worksheet, and determining the signal information of the target signal of the second worksheet. And performing difference value calculation on the signal lengths between the target signals of the second worksheet based on the signal types, and determining a length difference value between the target signals of the same signal type. And adjusting the signal length of the target signal of which the length difference value does not meet the constraint condition until the constraint condition is met.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a PCB signal processing method, electronic equipment, and computer program product. Background Art

[0002] With the advancement of communication technology and the demand for 4G and 5G communication products, PCB designs are experiencing increasing signal frequencies and densities, leading to increasingly stringent requirements for signal integrity. For PCB designers, ensuring the length consistency of a set of screen signals and meeting specific regulations has become particularly complex and time-consuming. Traditional methods make it difficult to intuitively and quickly check and adjust these signal parameters. Summary of the Invention

[0003] The present disclosure provides a PCB signal processing method, electronic equipment, and computer program product.

[0004] According to one aspect of the present disclosure, a method for processing a PCB signal is provided, comprising: determining a first working table containing the signal information based on signal information of the PCB signal, wherein the signal information includes a signal identifier and a signal length; classifying the signal identifier of a target signal based on the signal type, and determining a second working table containing signal identifiers of different signal types; matching the signal of the first working table with the target signal of the second working table based on the signal identifier of the first working table and the signal identifier of the second working table, and determining the signal information of the target signal of the second working table; calculating the difference in signal lengths between the target signals of the second working table based on the signal type, and determining the length difference between target signals of the same signal type; and adjusting the signal length of the target signal whose length difference does not meet the constraint condition until the constraint condition is met.

[0005] According to one aspect of a PCB signal processing method, a first worksheet is constructed based on the signal identifier and signal length of the PCB signal to form a complete original data source. Target signals are classified according to signal type, and a structured second worksheet is generated to achieve orderly signal management. By matching the signal identifiers in the two worksheets, the detailed signal information in the first worksheet is accurately mapped to the target signal in the second worksheet, ensuring that the classified signal has complete attribute data. For target signals within the same signal type, the difference between the maximum and minimum lengths is calculated to obtain the length difference of the target signal of this type, which is used to determine whether the constraint conditions are met. Signals that do not meet the constraint conditions are closed-loop corrected and re-verified until all target signals meet the constraint conditions of the design specification. This achieves full process automation and standardization from data extraction, classification analysis, matching association, difference calculation to signal parameter adjustment, significantly improving the accuracy and efficiency of signal equal length matching in high-speed and high-density PCB design, effectively ensuring signal integrity, reducing the risk of errors caused by manual intervention, and enhancing the reusability of design results and the collaborative efficiency between projects.

[0006] According to at least one embodiment of the present disclosure, a PCB signal processing method, performing a signal length difference calculation between target signals in the second worktable based on signal type to determine the length difference between target signals of the same signal type, includes: determining two target signals in each differential pair of target signals of the same signal type; performing a signal length difference calculation on the two target signals to determine the length difference between each differential pair of target signals of the same signal type.

[0007] According to the technical solution of this embodiment, the actual routing matching degree of each pair of differential signals can be accurately quantified, thereby achieving refined control of equal-length wiring of differential signals.

[0008] According to at least one embodiment of the present disclosure, a PCB signal processing method is provided, wherein signal length differences between target signals in the second worktable are calculated based on signal type to determine length differences between target signals of the same signal type. The method includes determining a maximum length and a minimum length of the target signals of the same signal type based on the signal lengths of the target signals of the same signal type, and using the difference between the maximum length and the minimum length as the length difference of the target signals of the same signal type.

[0009] According to the technical solution of this embodiment, the overall length discreteness and matching consistency of signals of the same signal type during the wiring process can be accurately reflected, and a quantitative evaluation of the equal-length status of all networks in the signal group can be achieved, while effectively identifying abnormal signal paths with significant deviations.

[0010] According to the PCB signal processing method of at least one embodiment of the present disclosure, when a target signal passes through a resistor element, the signal lengths of the signals at the left and right ends of the resistor element are added, and the result of the addition is used as the signal length of the target signal.

[0011] According to the technical solution of this embodiment, the actual physical path length of the target signal in the entire network can be accurately restored, effectively solving the problem of length measurement breakpoints caused by discrete components such as resistors dividing the routing into multiple segments, avoiding misjudgment caused by only taking the length of a certain segment, and ensuring the accuracy of length matching analysis.

[0012] According to at least one embodiment of the present disclosure, the PCB signal processing method further includes: determining a corresponding signal delay length based on the electrical delay of the target signal passing through a via; multiplying the number of vias of the target signal by the signal delay length to determine a first signal length; and adding the first signal length to the original signal length of the target signal, with the result of the addition serving as the final signal length of the target signal.

[0013] According to the technical solution of this embodiment, it can effectively compensate for the timing deviation misjudgment problem caused by traditional reliance on physical length analysis, improve the accuracy of equal-length matching, accurately identify the offset or skew risk caused by the cumulative delay of vias, and provide a scientific basis for subsequent length adjustment, thereby ensuring signal synchronization and enhancing signal integrity.

[0014] According to at least one embodiment of the present disclosure, a method for processing a PCB signal includes: when the number of vias of the target signal is greater than or equal to a target number, adjusting the number of vias of the target signal.

[0015] According to the technical solution of this embodiment, the structural discontinuity in the high-speed signal path can be effectively controlled, reducing the risks of impedance mutation, signal reflection, high-frequency attenuation and electromagnetic interference caused by too many vias, reducing the hidden dangers of electrical mismatch, and improving transmission quality.

[0016] According to at least one embodiment of the PCB signal processing method of the present disclosure, before determining the first worksheet containing the signal information based on the signal information of the PCB signal, the method further includes: performing macro processing on the PCB signal based on electronic design software to determine the signal information of the PCB signal.

[0017] The technical solution of this embodiment enables efficient conversion from a PCB design database to structured analysis data, significantly improving the speed and accuracy of data acquisition and avoiding human reading errors. Furthermore, macro processing scripts can be standardized and reused, making them suitable for rapid verification on the same platform or across multiple projects, significantly shortening the design cycle and enhancing the intelligent and standardized level of PCB design.

[0018] According to another aspect of the present disclosure, an electronic device is provided, comprising: a memory storing execution instructions; and a processor executing the execution instructions stored in the memory, so that the processor executes the PCB signal processing method of any embodiment of the present disclosure.

[0019] According to another aspect of the present disclosure, a readable storage medium is provided, in which execution instructions are stored. When the execution instructions are executed by a processor, they are used to implement the PCB signal processing method of any embodiment of the present disclosure.

[0020] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, wherein when the computer program is executed by a processor, the method for processing a PCB signal according to any embodiment of the present disclosure is implemented.

[0021] The beneficial effects of the technical solution of the present application are at least as follows: by constructing a first worksheet based on the signal identifier and signal length of the PCB signal, a complete original data source is formed. The target signal is classified according to the signal type, and a structured second worksheet is generated to achieve orderly management of the signal. By matching the signal identifiers in the two worksheets, the detailed signal information in the first worksheet is accurately mapped to the target signal in the second worksheet, ensuring that the classified signal has complete attribute data. For the target signals within the same signal type, the difference between the maximum and minimum lengths is calculated to obtain the length difference of the target signal of this type, which is used to determine whether the constraint conditions are met. For signals that do not meet the constraint conditions, closed-loop correction is performed and re-verified until all target signals meet the constraint conditions of the design specifications, realizing the automation and standardization of the entire process from data extraction, classification analysis, matching association, difference calculation to signal parameter adjustment, significantly improving the accuracy and efficiency of equal length matching of signals in high-speed and high-density PCB design, effectively ensuring signal integrity, reducing the error risk caused by manual intervention, and enhancing the reusability of design results and the collaborative efficiency between projects. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0023] Figure 1 It is a schematic diagram of the overall flow of a method for processing PCB signals according to one embodiment of the present disclosure.

[0024] Figure 2 This is a schematic block diagram of a main control chip communicating with a connector via differential signal lines in a PCB signal processing method according to an embodiment of the present disclosure.

[0025] Figure 3 It is a flowchart of determining the length difference of target signals of the same signal type in a PCB signal processing method according to an embodiment of the present disclosure.

[0026] Figure 4 It is a flowchart of determining the length difference of target signals of the same signal type in a PCB signal processing method according to another embodiment of the present disclosure.

[0027] Figure 5 It is a flow chart of determining the signal length based on the number of vias in a PCB signal processing method according to one embodiment of the present disclosure.

[0028] Figure 6 It is a schematic diagram of the overall flow of a method for processing PCB signals according to another embodiment of the present disclosure.

[0029] Figure 7 It is a schematic block diagram of the structure of a PCB signal processing device according to an embodiment of the present disclosure.

[0030] Figure 8 is a schematic structural block diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] The present disclosure is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are intended only to illustrate the relevant content and are not intended to limit the present disclosure. It should also be noted that, for ease of description, only the portions relevant to the present disclosure are shown in the accompanying drawings.

[0032] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure can be combined with each other. The technical solution of the present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0033] The design of camera or display interfaces for mobile terminals requires simultaneous processing of multiple MIPI differential signals (such as four camera signals or eight LCD signals). Each signal group must meet stringent requirements for equal differential line length, inter-group spacing, and impedance control. Traditional manual routing measurement methods, when dealing with multiple signal groups, require individual length adjustments, via counts, and repeated verification. This is inefficient and prone to signal distortion or crosstalk due to human error. For example, if the length difference of a MIPI signal group exceeds the equal differential line length requirement due to layout constraints, manual corrections may require rerouting and affect the layout of adjacent signals.

[0034] To this end, the present disclosure proposes a method for processing PCB signals, wherein, in this method, a first worksheet is determined based on the identification and length information of the PCB signal, and the target signal is classified and sorted according to the signal type to form a second worksheet. The signal identifications in the two worksheets are used for matching, and the detailed information of each target signal in the second worksheet is accurately extracted from the signal information in the first worksheet. The length difference of signals of the same type is calculated, and the target signals that do not meet the constraints are identified. The line length layout of these signals is adjusted until the constraints are met. Automation realizes the full process management from data collection, classification and sorting to precise adjustment, greatly improving the processing speed and accuracy, effectively solving the problem of time-consuming and error-prone manual operation in complex PCB design, and ensuring the quality and stability of high-speed signal transmission.

[0035] For the convenience of description and to make the technical solution of the present disclosure easier to understand, the terms of the present disclosure are first explained before describing the technical solution of the present disclosure.

[0036] PCB signals are the paths used to transmit electrical signals or data on a printed circuit board (PCB). They are responsible for accurately and consistently delivering information from nodes such as chips, connectors, and power supplies from one end to the other in a timely manner. They can range from simple wire connections to complex networks comprised of multiple wires, vias, and copper foil to enable communication and power transmission between electronic components. For high-speed systems, PCB signals must also meet constraints such as impedance, length, delay, and the number of vias to ensure data integrity and timing synchronization.

[0037] A differential pair (DP) is a pair of mutually coupled, oppositely polarized signal lines used to transmit differential signals in high-speed circuit design. These lines, typically labeled P (positive, +) and N (negative, -), adhere to design specifications such as impedance matching, equal trace lengths, routing on the same layer, consistent spacing, and avoiding crossovers to ensure signal integrity. These pairs are widely used in high-speed interfaces such as MIPI, PCIe, USB, HDMI, and DDR, supporting high data rates, minimizing electromagnetic radiation, and improving timing accuracy.

[0038] Figure 1 FIG. 1 shows a schematic diagram of the overall process of a method for processing PCB signals according to an embodiment of the present disclosure. Figure 1 The method M100 shown includes steps S110 to S150. The method M100 can be executed by an electronic device such as a mobile phone or a tablet computer.

[0039] In step S110 , based on the signal information of the PCB signal, a first working table containing the signal information is determined, where the signal information includes a signal identifier and a signal length.

[0040] During the post-analysis phase of PCB (printed circuit board) design, electronic design automation tools are first used to perform data extraction on the routed board to obtain signal information for each net. The signal identifiers and lengths for all signals are collated and imported into a spreadsheet, creating the first worksheet. This first worksheet is a structured, computable data source, listing each signal name and length by row, and may also include extended information such as the number of vias.

[0041] Optionally, the signal information includes the number of vias.

[0042] In step S120 , the signal identifiers of the target signal are classified based on the signal type, and a second working table containing signal identifiers of different signal types is determined.

[0043] Based on the signal identifier of each target signal, its signal type is identified, and target signals of the same signal type are grouped together. These signal identifiers, classified by signal type, and their associated information (such as subsequent associated signal lengths and number of vias) are aggregated into a structured data table, the second worksheet. This second worksheet logically groups and visualizes the raw data, facilitating subsequent independent length analysis, difference calculation, rule checking, and problem location for target signals of different signal types, improving the organization and efficiency of the analysis.

[0044] Optionally, the signal identification of the target signal may be classified based on the signal type, or may be classified based on the signal function, protocol type, or device to which the signal is connected.

[0045] The above signal types include high-speed signals, differential signals and / or clock signals, etc.

[0046] In step S130 , based on the signal identifiers of the first working table and the signal identifiers of the second working table, the signal of the first working table is matched with the target signal of the second working table to determine the signal information of the target signal of the second working table.

[0047] Using the signal identifiers in the two worksheets as a bridge, the signal information of each signal in the first worksheet is accurately associated with the corresponding target signal in the second worksheet. This provides complete and accurate data support for subsequent analysis, such as calculating length differences and checking whether impedance control requirements are met.

[0048] In step S140 , a signal length difference calculation is performed between target signals in the second working table based on the signal type to determine the length difference between target signals of the same signal type.

[0049] For all target signals within the same signal type, the trace lengths of each signal are extracted, and the overall length difference (length difference) of all target signals within that signal type is determined. This length difference is used to assess the consistency of length matching during the routing process for this group of signals. This enables systematic analysis of multiple signal channels and can quickly identify abnormal signals with excessive length deviations.

[0050] Preferably, when a target signal passes through a resistor element, the signal lengths of the signals on the left and right ends of the resistor element are added together, and the result of the addition is used as the signal length of the target signal, accurately reflecting the actual physical path length of the target signal in the entire PCB signal network, avoiding length measurement breakpoints or errors caused by component insertion, thereby ensuring the accuracy of the length matching calculation. Figure 2 As shown, the main control chip communicates with the connector via differential signal lines. Differential clock signals (TX_CLKN and TX_CLKP) are output from the main control chip, pass through resistor R1, and reach the connector. Differential data signals (TX_D0N and TX_D0P) are output from the main control chip, pass through resistor R2, and reach the connector. The signal length of the differential clock signal TX_CLKN is TX_CLKN + TX_CLK-, and the signal length of the differential clock signal TX_CLKP is TX_CLKN + TX_CLK+. The signal length of the differential data signal TX_D0N is TX_D0N + TX_D0-, and the signal length of the differential data signal TX_D0P is TX_D0P + TX_D0+.

[0051] In step S150 , the signal length of the target signal whose length difference does not satisfy the constraint condition is adjusted until the constraint condition is satisfied.

[0052] After signal classification, information matching, and length difference calculation, if the length differences of some target signals exceed the allowable range of the constraints, routing adjustments must be made to these target signals that do not meet the constraints. Adjustments can include adding serpentine routing, optimizing routing paths, or modifying via locations until the length differences are within the design constraints.

[0053] The above constraints include that the signal length between each differential pair is less than or equal to 24MIL, the difference in signal length between different differential pairs of the same signal type is less than or equal to 42MIL, the signal lengths of the left and right ends of the resistor element in the differential pair are equal, and / or the number of vias of the target signal is less than the target number.

[0054] Preferably, when the number of vias for a target signal is greater than or equal to the target number, the number of vias for that target signal is adjusted. This effectively controls the via density in the signal path, avoiding issues such as impedance discontinuity, signal reflection, high-frequency attenuation, and electromagnetic interference caused by excessive vias. Vias are key structures for electrical connections between different layers in a PCB. Actively optimizing the via count by setting a target number (e.g., merging redundant vias and optimizing routing paths to reduce inter-layer switching) can improve signal transmission quality, reduce loss and noise, enhance manufacturing reliability, and reduce the risk of drilling defects.

[0055] Preferably, the signal lengths of target signals whose length differences exceed the target value are adjusted. This achieves equal length matching requirements in high-speed signal networks, ensuring that the electrical path lengths (i.e., signal length differences) within the same signal group or between differential pairs are within the design tolerance. This adjustment process compensates for shorter signals by adding serpentine traces or optimizes routing paths to reduce redundancy in overly long signals, thereby eliminating issues such as timing offset, signal phase mismatch, and receiver sampling errors caused by length mismatch.

[0056] Optionally, by marking target signals that meet the constraints with colors, it is more intuitive to find target signals that do not meet the constraints and make adjustments.

[0057] In summary, the method disclosed in the present invention extracts complete signal information including signal identification and signal length from PCB design, and constructs a first worksheet as the data basis. The target signal is classified according to the signal type, and a second worksheet is generated to realize structured management of the signal. By matching the signal identifications in the two worksheets, the signal information in the first worksheet is accurately mapped to the target signal in the second worksheet, ensuring that the classified signal has complete attribute data. On this basis, the length difference of the target signals within the same signal type is calculated to identify abnormal signals that do not meet the design constraints. These substandard target signals are adjusted in a targeted manner until their length difference meets the design specification requirements of the constraints. The full process automated management from data extraction, classification analysis to problem location and closed-loop optimization is realized, which significantly improves the efficiency and accuracy of equal-length matching of signals in high-speed and high-density PCB design, effectively ensures signal integrity, shortens the design iteration cycle, and enhances the stability and reusability of the product in complex application scenarios.

[0058] Regarding step S140, in some embodiments of the present disclosure, it may include the following: Figure 3 Steps S310 to S320 are shown.

[0059] In step S310 , two target signals of each differential pair among target signals of the same signal type are determined.

[0060] Further, differential signals that exist in pairs are identified in each type of target signal. Differential transmission relies on the symmetry between the two traces (P / N ends). Therefore, the two target signals in each differential pair must be accurately located to perform subsequent length difference calculation and matching optimization to ensure that they meet the design requirements of differential impedance and timing alignment.

[0061] In step S320 , a difference calculation is performed on the signal lengths of the two target signals to determine the length difference of each differential pair in the target signals of the same signal type.

[0062] After identifying the two target signals for each differential pair of the same signal type, a difference calculation is performed based on the length data of the two target signals to determine the actual length difference of each pair of target signals. This length difference directly reflects the degree of routing matching, is used to determine whether design constraints are exceeded, and provides a quantitative basis for whether subsequent adjustments are necessary.

[0063] By identifying the two target signals of each differential pair of the same signal type and calculating the difference based on their signal lengths, the precise quantification of the degree of routing matching for each pair of differential signals is achieved. This system can automatically and efficiently determine the actual length difference between each differential pair and, based on the set constraints, quickly identify abnormal signal pairs that do not meet the requirements. This significantly improves the accuracy and efficiency of high-speed signal equal length matching analysis, avoids omissions and errors in manual comparisons, and provides a clear basis for subsequent targeted adjustments, effectively ensuring the timing consistency and transmission integrity of differential signals, and improving the quality and reliability of PCB designs.

[0064] Regarding step S140, in some other embodiments of the present disclosure, it may include the following: Figure 4 Steps S410 to S420 are shown.

[0065] In step S410 , based on the signal lengths of the target signals of the same signal type, the maximum length and the minimum length of the target signals of the same signal type are determined.

[0066] In PCB design, for all target signals of the same signal type (such as MIPI, DDR, USB, etc.), the first step is to obtain the trace length data (i.e., signal length) for each target signal. By comparing and analyzing these length values ​​across all target signals of that signal type, the maximum length corresponding to the longest signal path and the minimum length corresponding to the shortest signal path are determined. This approach aims to quantify the overall length distribution of this type of signal during the routing process, providing basic data for subsequent length difference calculations. This allows us to determine whether the group of signals meets the equal length design rule, ensuring timing consistency and electrical matching between high-speed signals.

[0067] In step S420 , the difference between the maximum length and the minimum length is used as the length difference of the target signal of the same signal type.

[0068] After obtaining the maximum and minimum lengths of each target signal of the same signal type, the difference is used as the length difference of the target signals of the group, i.e., the signal type, to reflect the overall matching quality of the target signals of this type during the wiring process.

[0069] By determining the maximum and minimum lengths of target signals of the same signal type and using the difference as the length difference for that signal type, a quantitative assessment of the routing consistency of the entire group of target signals is achieved. This method can quickly reflect the degree of length dispersion of all networks within that target signal type, accurately identifying any out-of-tolerance situations and effectively supporting automated verification of equal-length design rules within the group. In combination with tools like Excel, batch calculations and conditional formatting can be implemented, significantly improving analysis efficiency and enhancing the standardization and repeatability of PCB designs.

[0070] In some embodiments of the present disclosure, the following may also be included: Figure 5 Steps S510 to S530 are shown.

[0071] In step S510 , a corresponding signal delay length is determined based on the electrical delay of the target signal passing through the hole.

[0072] In high-speed signal transmission, vias not only introduce physical path discontinuities but also introduce additional parasitic inductance and capacitance, slowing signal propagation and generating non-negligible electrical delay. By analyzing the electrical characteristics of vias (such as transmission delay time), we equate them to a virtual trace length—the signal delay length—and incorporate this signal delay length into the total signal length calculation. This allows length matching to no longer rely solely on physical geometric length, but instead comprehensively considers the actual equivalent length of electrical behavior, improving matching accuracy.

[0073] In step S520 , the number of vias of the target signal is multiplied by the signal delay length to determine a first signal length.

[0074] In high-speed PCB design, each via introduces a certain amount of electrical delay, manifesting as a slower signal propagation speed or a longer equivalent path length. Assuming each via contributes approximately the same amount to the delay, the total equivalent length increment caused by all vias, or the first signal length, can be calculated by multiplying the total number of vias in the signal path by the equivalent signal delay length of a single via.

[0075] In step S530 , the first signal length is added to the original signal length of the target signal, and the addition result is used as the final signal length of the target signal.

[0076] After calculating the number of vias and their equivalent signal delay lengths, the resulting first signal length must be added to the signal's original physical trace length to arrive at the target signal's final signal length. This final signal length not only reflects the geometric distance of the signal path but also incorporates the propagation delays caused by vias, enabling a more accurate assessment of the signal's equivalent electrical length under actual operating conditions.

[0077] The equivalent delay length is determined based on the electrical delay caused by the target signal passing through the vias. The first signal length is then multiplied by the number of vias. This delay length is then added to the original physical trace length of the target signal to form an equivalent total length that takes electrical effects into account. This method breaks through the limitations of traditional equal-length matching that relies solely on geometric length and quantifies the parasitic parameters and propagation delay introduced by vias into a calculable length compensation value, significantly improving the accuracy of high-speed signal path analysis.

[0078] In a specific embodiment, the PCB signal processing method may include: Figure 6 Steps S610 to S660 are shown.

[0079] In step S610, macro processing is performed on the PCB signal based on electronic design software to determine signal information of the PCB signal.

[0080] After completing PCB routing, detailed parameters for each signal are required for subsequent analysis. By running a macro program in electronic design software, signal information for all nets can be exported in batches, including key attributes such as signal name, signal length, number of vias, and layer location. This method achieves efficient conversion from PCB design data to structured analysis data, significantly improving the speed and accuracy of data acquisition compared to traditional manual measurement methods.

[0081] The above-mentioned electronic design software includes Mentor PADS software, Cadence Allegro software or AltiumDesigner software, etc.

[0082] In step S620, based on the signal information of the PCB signal, a first working table containing the signal information is determined, where the signal information includes a signal identifier and a signal length.

[0083] In step S630, the signal identifier of the target signal is classified based on the signal type, and a second working table containing signal identifiers of different signal types is determined.

[0084] In step S640, based on the signal identifiers of the first working table and the signal identifiers of the second working table, the signal of the first working table is matched with the target signal of the second working table to determine the signal information of the target signal of the second working table.

[0085] In step S650 , a signal length difference calculation is performed between target signals in the second working table based on the signal type to determine the length difference between target signals of the same signal type.

[0086] In step S660 , the signal length of the target signal whose length difference does not satisfy the constraint condition is adjusted until the constraint condition is satisfied.

[0087] The above steps S620 to S660 correspond one-to-one to steps S110 to S150 in method M100 and are not described again here.

[0088] In a specific embodiment, macro processing is performed on the PCB board diagram after wiring is completed based on electronic design automation software, and a script is run to batch export signal information of all networks, including signal identification, signal length and number of vias, and these data are organized to generate a structured first worksheet, namely sheet 1 of the Excel file.

[0089] The target signals are classified according to the signal types, and the signal groups that need to be focused on are screened out to form the second worksheet, i.e., sheet 2 of the Excel file.

[0090] By matching the signal identifiers in the first worksheet with the second worksheet, the detailed signal information (such as length and number of vias) in the first worksheet is mapped to the corresponding target signal in the second worksheet, ensuring that the classified target signal has complete attribute data.

[0091] For target signals that include differential pairs, further identify the positive and negative signals (e.g., P / N terminals) within each differential pair and calculate their length differences to determine whether they meet the equal length requirement within the differential pair, such as within 24 mils. Furthermore, for all target signals of the same signal type, calculate the maximum and minimum signal lengths. The difference between the two is used as the overall length difference for the group of signals to verify the equal length constraint between groups, such as 42 mils between groups. For example, use Excel's SUMIF conditional formatting to perform matching calculations on the first and second worksheets.

[0092] On this basis, the impact of vias on signal delay is considered. Based on the electrical delay characteristics of a single via, its equivalent delay length is determined. This delay length is multiplied by the actual number of vias for the target signal to obtain the first signal length introduced by the via. This first signal length is added to the original signal length to obtain the final signal length that reflects the actual electrical behavior, which is used for more accurate equal-length analysis. For signals whose length difference exceeds the target value, adjustments are returned to the PCB design software, such as using serpentine routing to compensate for shorter lines or optimizing paths to reduce excessively long lines, until all target signals meet the design constraints. This completes the complete technical process from data extraction, classification analysis, problem identification, to closed-loop optimization.

[0093] Furthermore, if multiple projects use the same signal type (for example, the MIPI CSI-2 camera interface or the MIPI DSI display interface), or are based on the same hardware platform (such as a family of products using the same main control chip), their signal naming rules, classification methods, and equal length requirements (such as 24MIL / 42MIL) are consistent. Therefore, an Excel analysis template (including formulas, functions, conditional formatting, macros, etc.) developed for one project can be directly reused in other similar projects, eliminating the need to rewrite formulas or manually set rules each time. This improves work efficiency and analysis consistency, while also reducing the risk of human error.

[0094] Based on any of the above embodiments, the present disclosure further provides a PCB signal processing device 700 . Figure 7 FIG. 1 is a schematic block diagram of a PCB signal processing device according to an embodiment of the present disclosure. Figure 7 As shown, the PCB signal processing device 700 includes: A signal extraction module 710 is configured to determine a first working table based on signal information of the PCB signal; The signal classification module 720 is configured to classify the signal identifier of the target signal according to the signal type, and determine a second working table containing signal identifiers of different signal types.

[0095] The signal matching module 730 is configured to match the signal of the first working table with the target signal of the second working table according to the signal identifier of the first working table and the signal identifier of the second working table, and determine the signal information of the target signal of the second working table.

[0096] The difference calculation module 740 is configured to perform signal length difference calculation on the target signals in the second working table according to the signal type, and determine the length difference between the target signals of the same signal type.

[0097] The signal adjustment module 750 adjusts the signal length of the target signal whose length difference does not meet the constraint condition until the constraint condition is met.

[0098] The above-mentioned PCB signal processing device can be in the form of computer software, and each module of the above-mentioned PCB signal processing device can be implemented by a computer software module.

[0099] The implementation process of the functions and effects of each module in the above-mentioned PCB signal processing device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, and will not be repeated here.

[0100] The present disclosure also provides an electronic device 1000 . Figure 8A schematic diagram showing a hardware implementation using a processing system is shown.

[0101] The hardware structure of electronic device 1000 can be implemented using a bus architecture. The bus architecture can include any number of interconnecting buses and bridges, depending on the specific application and overall design constraints of the hardware. Bus 1100 connects various circuits including one or more processors 1200, memory 1300, and / or hardware modules. Bus 1100 can also connect various other circuits 1400, such as peripheral devices, voltage regulators, power management circuits, external antennas, etc. Bus 1100 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Component Architecture (EISA) bus. Buses can be divided into address buses, data buses, control buses, etc. For ease of illustration, the figure shows only one connecting line, but this does not mean that there is only one bus or only one type of bus.

[0102] For ease of explanation, some steps of the above method are described as corresponding to modules. It should be understood that the corresponding modules for performing one or more steps of the above method can be one or more hardware modules specifically configured to perform the corresponding steps, or implemented by a processor configured to perform the corresponding steps, or stored in a computer-readable medium for implementation by a processor, or implemented by some combination thereof.

[0103] The present disclosure also provides a readable storage medium having a computer program stored therein, which is used to implement the above-mentioned method when the computer program is executed by a processor. "Readable storage medium" can be any device that can contain, store, communicate, propagate or transmit a program for use in an instruction execution system, device or equipment or in combination with these instruction execution systems, devices or equipment. More specific examples of readable storage media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and editable read-only memory (EPROM or flash memory), an optical fiber device, and a portable read-only memory (CDROM), etc.

[0104] The present disclosure also provides a computer program product. The method of the present disclosure can be implemented in whole or in part using software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed, the process or function of the present disclosure is performed in whole or in part.

[0105] A computer program or instruction can be stored in a readable storage medium or transferred from one readable storage medium to another. For example, the computer program or instruction can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The readable storage medium can be any accessible medium or a data storage device such as a server or data center that integrates one or more accessible media. The accessible medium can be a magnetic medium such as a floppy disk, hard disk, or magnetic tape; an optical medium such as a digital video disk; or a semiconductor medium such as a solid-state drive. The computer-readable storage medium can be a volatile or non-volatile storage medium, or can include both volatile and non-volatile types of storage media.

[0106] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0107] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, electronic devices, and computer program products according to the present disclosure. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as the combination of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0108] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0109] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0110] In the description of this specification, the description with reference to the terms "one embodiment / method", "some embodiments / methods", "example", "specific example", or "some examples" means that the specific features, structures, or characteristics described in conjunction with the embodiment / method or example are included in at least one embodiment / method or example of the present disclosure. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment / method or example. Moreover, the specific features, structures, or characteristics described may be combined in a suitable manner in any one or more embodiments / methods or examples. In addition, those skilled in the art may combine and combine different embodiments / methods or examples described in this specification and the features of different embodiments / methods or examples, unless they are contradictory.

[0111] Those skilled in the art will appreciate that the above embodiments are merely intended to clearly illustrate the present disclosure and are not intended to limit the scope of the present disclosure. Other changes or modifications may be made based on the above disclosure, and such changes or modifications are still within the scope of the present disclosure.

Claims

1. A method for processing PCB signals, characterized in that: include: Determining a first work table containing the signal information based on signal information of the PCB signal, wherein the signal information includes a signal identifier and a signal length; classifying the signal identifier of the target signal based on the signal type, and determining a second working table containing signal identifiers of different signal types; matching the signal of the first working table with the target signal of the second working table based on the signal identifier of the first working table and the signal identifier of the second working table to determine signal information of the target signal of the second working table; performing a difference calculation on the signal lengths between the target signals in the second working table based on the signal type to determine the length difference between the target signals of the same signal type; as well as The signal length of the target signal whose length difference does not satisfy the constraint condition is adjusted until the constraint condition is satisfied.

2. The PCB signal processing method according to claim 1, wherein: Calculating the difference in signal lengths between target signals in the second working table based on the signal type to determine the length difference between target signals of the same signal type includes: determining two target signals of each differential pair among target signals of the same signal type; A difference calculation is performed on the signal lengths of the two target signals to determine a length difference of each differential pair in the target signals of the same signal type.

3. The PCB signal processing method according to claim 1, wherein: Calculating the difference in signal lengths between target signals in the second working table based on the signal type to determine the length difference between target signals of the same signal type includes: Determining a maximum length and a minimum length of target signals of the same signal type based on signal lengths of target signals of the same signal type; The difference between the maximum length and the minimum length is used as the length difference of the target signal of the same signal type.

4. The PCB signal processing method according to claim 1, wherein: When a target signal passes through a resistor element, the signal lengths of the signals at the left and right ends of the resistor element are added, and the result of the addition is used as the signal length of the target signal.

5. The PCB signal processing method according to claim 1, wherein: Also includes: determining a corresponding signal delay length based on an electrical delay of the target signal passing through the hole; Multiplying the number of vias of the target signal by the signal delay length to determine a first signal length; The first signal length is added to the original signal length of the target signal, and the addition result is used as the final signal length of the target signal.

6. The method for processing PCB signals according to claim 1, wherein: Also includes: When the number of vias of the target signal is greater than or equal to the target number, the number of vias of the target signal is adjusted.

7. The method for processing PCB signals according to claim 1, wherein: Before determining the first worksheet containing the signal information based on the signal information of the PCB signal, the method further includes: performing macro processing on the PCB signal based on electronic design software to determine the signal information of the PCB signal.

8. An electronic device, characterized in that: include: a memory storing execution instructions; as well as A processor, wherein the processor executes the execution instruction stored in the memory, so that the processor executes the PCB signal processing method according to any one of claims 1 to 7.

9. A readable storage medium, characterized in that: The readable storage medium stores execution instructions, which are used to implement the PCB signal processing method according to any one of claims 1 to 7 when executed by the processor.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method for processing a PCB signal according to any one of claims 1 to 7 is implemented.

Images