A neuromorphic processor that supports asynchronous event-driven processing

Abstract

The application discloses a neuromorphic processor supporting asynchronous event driving, comprising: an event dispatcher, configured to receive events and send the events to a neuromorphic processing core or an event queue according to a current time step state; the event dispatcher is configured to ensure the correctness of the event processing sequence through time step conflict detection and a timestamp-based scheduling strategy; the event queue is configured to cache non-current time step events or events that cannot be processed immediately; the neuromorphic processing core is configured to execute an event processing program based on a neuromorphic instruction set architecture; the neuromorphic instruction set comprises a BRE instruction, configured to dynamically jump to a corresponding processing program according to an event type, and realize low-power mode switching in cooperation with a clock gating module; the processor executes the BRE instruction after the event processing is completed, enters a sleep state, and suspends a clock signal through the clock gating until a new event arrives. The application has the advantages of good compatibility, good adaptability, low power consumption and the like.

Description

Technical Field

[0001] This invention relates primarily to the field of processor technology, and more specifically to a neuromorphic processor that supports asynchronous event-driven processing. Background Technology

[0002] Neuromorphic computing is a rapidly developing new computing paradigm that achieves more efficient perception, learning, and reasoning capabilities by simulating the computational methods of the human brain. This computing approach is widely used in the field of artificial intelligence, especially in deep learning, pattern recognition, and signal processing. However, compared to traditional architectures, neuromorphic computing emphasizes sparse computation and event-driven characteristics, offering higher power efficiency and computational potential.

[0003] By analyzing the computational bottlenecks and requirements of Spike Neural Networks (SNNs), a neuromorphic instruction set is defined to integrate neuromorphic computing with the instruction set architecture. This approach leverages the efficiency of neuromorphic computing in handling sparse events, while the scalability of the instruction set architecture provides developers with significant freedom, allowing them to define and extend the instruction set according to specific application needs, thus efficiently implementing various neuron models. This is particularly important for neuromorphic computing because it allows designers to leverage its characteristics and extend instructions and event-driven mechanisms to create neuron model processing architectures that are both flexible and efficient.

[0004] Spiking neural networks (SNNs) are one of the most representative models in neuromorphic computing. Unlike traditional neural networks, SNNs use discrete pulse signals to transmit information, giving them a more realistic biological background, but also making them more difficult to implement efficiently on traditional hardware. In recent years, hardware design has gradually shifted towards supporting the computational needs of SNNs, and researchers have developed various neuromorphic processors, such as IBM's TrueNorth and Intel's Loihi chips. These hardware devices typically employ specific designs to optimize the performance of SNNs, thus exhibiting a lack of flexibility.

[0005] Currently, IBM TrueNorth is one of the earliest hardware solutions for neuromorphic computing, structurally mimicking biological neural networks and heavily employing low-power design. It achieves 1 million neurons and 256 million synapses, processing 4.6 billion spiking events per second. However, TrueNorth's architecture is relatively fixed, primarily supporting specific spiking neural network models, resulting in insufficient flexibility. Furthermore, its design is heavily weighted towards inference tasks, offering limited support for neural network training and traditional general-purpose computing. Intel Loihi is another neuromorphic hardware solution that supports online learning and dynamic weight adjustment. It integrates multiple neuron cores, enabling efficient handling of sparse computations in spiking neural networks. Similar to TrueNorth, it primarily uses a dedicated architecture, supporting a limited range of computational modes, and requires additional hardware adaptation when dealing with rapidly changing network models. Moreover, while its power optimization employs event-driven principles, there is still room for improvement in energy consumption during periods without events.

[0006] Existing neuromorphic computing hardware often employs highly specialized architectures, typically tightly coupled with specific algorithms. While this design can deliver high performance in specific applications, such as convolutional neural networks (CNNs) or spiking neural networks, it also exposes significant limitations. Due to the deep coupling between the hardware architecture and the algorithm, these hardware components struggle to flexibly adapt to the demands of rapidly evolving neural network models. If developers need to support new network models or functionalities, they often have to redesign the hardware architecture. This process is not only resource-intensive but also time-consuming, significantly limiting the hardware's flexibility and adaptability.

[0007] In terms of power consumption optimization, existing neuromorphic hardware does not incorporate event-driven mechanisms to reduce energy consumption. For example, during non-event-triggered periods, i.e., when neurons are in a silent state, many hardware modules remain active and fail to fully enter low-power mode. Such a design cannot fully utilize the sparse event characteristics of spiking neural networks, resulting in higher energy consumption and limited power efficiency under low load or idle conditions.

[0008] Furthermore, many neuromorphic hardware devices are designed with a focus on handling inference or training tasks in neural networks, but lack the ability to support general-purpose computing. This single-task-oriented design performs poorly in multi-task scenarios. For example, these devices are typically inefficient when attempting to run traditional programs or general-purpose computing tasks, which severely limits their use in diverse application scenarios. Summary of the Invention

[0009] To address the technical problems existing in the prior art, this invention provides a neuromorphic processor that effectively solves the timestep conflict problem, avoids incorrect processing order of events at different timesteps, and has low power consumption, supporting asynchronous event-driven processing.

[0010] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows:

[0011] A neuromorphic processor supporting asynchronous event-driven processing includes:

[0012] An event scheduler is used to receive events and send them to the neuromorphic processing kernel or event queue according to the current time step state. The event scheduler is configured to ensure the correctness of the event processing order through time step conflict detection and a timestamp-based scheduling strategy.

[0013] An event queue, coupled to the event scheduler, is used to cache events that are not in the current time step or events that cannot be processed immediately.

[0014] The neuromorphic processing core is used to execute event handling programs based on a neuromorphic instruction set architecture. The neuromorphic instruction set is an event-oriented instruction set that includes BRE instructions, which are used to dynamically jump to the corresponding processing program according to the event type and work with the clock gating module to achieve low-power mode switching. After the processor completes event processing, it executes the BRE instructions, enters a sleep state, and pauses the clock signal through clock gating until a new event arrives.

[0015] Preferably, the neuromorphic instruction set architecture is configured with:

[0016] Multiple configurable registers are included, some of which are general-purpose registers and others are special-function registers, used to store synaptic weights, source neuron and target neuron numbers, neuron states and time delay parameters;

[0017] The neuron instruction memory and neuron data memory are tightly coupled with the neuromorphic processing kernel, supporting in-memory computing operations;

[0018] The neuromorphic instruction set reserves encoding space, allowing users to extend instruction functionality through custom instruction encoding.

[0019] Preferably, the special function register includes:

[0020] Neuron state register, used to store the membrane potential of the neuron in the current event;

[0021] Synaptic weight registers are used to dynamically store the connection weights between source neurons and target neurons;

[0022] The membrane potential threshold register is configured to trigger a neuron reset operation in a Timestep-only event.

[0023] Preferably, the neuromorphic instruction set architecture uses the bfloat16 data format.

[0024] Preferably, the neuromorphic instruction set architecture employs a four-stage pipeline structure, including four stages: instruction fetch, decoding, operand fetch, and execution. The instruction fetch stage is used to read instructions from the neuron instruction memory; the decoding stage is used to resolve the instruction type and operand address; the operand fetch stage is used to load data from registers or neuron data memory; and the execution stage is used to complete calculations through arithmetic logic units and write the results back to registers or memory.

[0025] This invention also discloses an asynchronous event scheduling method based on a neuromorphic processor supporting asynchronous event-driven operation as described above, comprising the following steps:

[0026] Receive input events and extract their time step identifiers;

[0027] If the event time step matches the current time step and the neuromorphic processing kernel is in a ready state, the event is directly transmitted to the neuromorphic processing kernel; otherwise, the event is written to the event queue in time step order.

[0028] After the neuromorphic processing kernel finishes processing the current event, it selects the earliest event that entered the queue from the event queue for processing.

[0029] When the queue is empty and no new events arrive, the BRE instruction is triggered to put the processor into a low-power sleep state.

[0030] Preferably, the execution logic of the BRE instruction includes:

[0031] When a Spike-only event is detected, the weight accumulation and state update operations of the target neuron are triggered.

[0032] When a Timestep-only event is detected, a global neuron membrane potential threshold determination is performed, and neurons exceeding the threshold are pulsed and their membrane potentials are reset.

[0033] When a Spike-with-Timestep event is detected, the postsynaptic neuron state is updated synchronously and a new spike event is generated.

[0034] Preferably, the specific process of synchronously updating the postsynaptic neuron state and generating new impulse events is as follows:

[0035] At each time step, the processor calculates the membrane potential change of the postsynaptic neuron based on the pulse signal generated by the presynaptic neuron. First, it detects whether the presynaptic neuron generates a pulse in the current time step. If a pulse is detected, it calculates the effect of the pulse on the target neuron. Based on the synaptic weights, it completes the state update. When the membrane potential exceeds the threshold, the neuron generates a new pulse and propagates it to subsequent neurons. Otherwise, the membrane potential will continue to accumulate in the current time step until the firing condition is met.

[0036] Preferably, the specific process by which the processor enters a low-power sleep state is as follows:

[0037] After the BRE instruction is executed, the clock signals of the neuromorphic processing kernel and the event scheduler are turned off;

[0038] When a new event arrives, the clock is reactivated via an interrupt signal, and the process jumps to the corresponding handler entry address based on the event type.

[0039] The clock gating module is configured to reduce the processor's power consumption to a static power level during periods of no events.

[0040] Preferably, after processing each event, the processor automatically executes a BRE instruction to put the processor into an event waiting state; if there are no events to process, it enters a low-power state; otherwise, it dynamically jumps to the corresponding event handler according to the type of event that arrives.

[0041] Compared with the prior art, the advantages of the present invention are as follows:

[0042] This invention innovatively integrates neuromorphic computing and an asynchronous event instruction set architecture, cleverly combining the flexibility of traditional general-purpose processors with the efficiency of neuromorphic hardware, thus solving the balance problem between hardware architecture flexibility and specialized performance. This architecture not only efficiently handles the computational tasks of spiking neural networks but also retains support for traditional computing needs, demonstrating excellent compatibility and adaptability. Particularly in event-driven mode, this invention can efficiently handle the computational demands of complex neural networks, providing a highly efficient solution for the system.

[0043] Furthermore, the invention introduces an event-driven clock gating technique that fully leverages the event sparsity of spiking neural networks to significantly reduce ineffective power consumption during idle periods. This design not only greatly improves energy efficiency, making it particularly suitable for low-power applications, but also simplifies hardware implementation and provides flexible and efficient scalability through register sets and pipeline architectures optimized for spiking neural network tasks.

[0044] Building upon this, the introduction of the event scheduler and time step concepts further optimizes the timing management of the computation process. The event scheduler, by effectively managing time steps, ensures that events are triggered sequentially within the correct time steps, avoiding conflicts between time steps. This not only improves the accuracy and efficiency of the computation but also enables the system to handle asynchronous pulse events more accurately and efficiently.

[0045] Overall, this invention significantly outperforms existing technologies in terms of performance, energy efficiency, flexibility, and timing management, providing an innovative design approach for low-power, high-efficiency neuromorphic computing hardware. Attached Figure Description

[0046] Figure 1 This is an architectural diagram of the neuromorphic processor of the present invention in an embodiment.

[0047] Figure 2 This is a structural diagram of the neuromorphic processor of the present invention in an embodiment.

[0048] Figure 3 This is a structural diagram of the neuromorphic instruction set in this invention.

[0049] Figure 4 This is a schematic diagram of the sparse event flow of the spiking neural network in this invention.

[0050] Figure 5 This is a flowchart of the Spike-only event in this invention.

[0051] Figure 6 This is a flowchart of the Timestep-only event in this invention.

[0052] Figure 7 This is a flowchart of the Spike-with-Timestep event in this invention.

[0053] Figure 8 This is a schematic diagram illustrating the execution of the BRE instruction in this invention. Detailed Implementation

[0054] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0055] like Figure 1 As shown, the asynchronous event-driven neuromorphic processor provided in this embodiment of the invention includes an event scheduler, an event queue, and a neuromorphic processing kernel.

[0056] The event scheduler receives events and sends them to the neuromorphic processing kernel or event queue according to the current time step state. The event scheduler is configured to ensure the correctness of the event processing order through time step conflict detection and a timestamp-based scheduling strategy (first-in, first-out).

[0057] An event queue, coupled with the event scheduler, is used to cache events that are not in the current time step or that cannot be processed immediately.

[0058] The neuromorphic processing core is used to execute event handling programs based on the neuromorphic instruction set architecture. The neuromorphic instruction set is an event-oriented instruction set that includes BRE instructions, which are used to dynamically jump to the corresponding processing program according to the event type and work with the clock gating module to achieve low-power mode switching. After the processor completes the event processing, it executes the BRE instructions, enters a sleep state, and pauses the clock signal through clock gating until a new event arrives.

[0059] The processor architecture described above employs the asynchronous event processing mechanism of spiking neural networks and introduces the concept of time steps. Specifically, events input to the Network On-Chip (NOC) first pass through an event scheduler responsible for handling the time step issue of pulse events, ensuring that events at different time steps are processed correctly. Since spiking neural networks are event-driven models, the pulse events emitted by each neuron are typically asynchronous; therefore, processing these events can lead to time step conflicts. To address this issue, before the pulse events enter the neuromorphic processing kernel, the events are preprocessed by the event scheduler, specifically as follows:

[0060] The event scheduler first determines whether the current pulse event belongs to the current time step. Since event processing at different time steps is independent, ensuring that each event is processed within the correct time step is one of the core tasks of the system.

[0061] The event scheduler further determines whether the event should be sent directly to the neuromorphic processing kernel for processing, or whether it should first be written to the event queue. The purpose of the event queue is to buffer events that cannot be processed immediately, ensuring that events are processed in the correct order and timing.

[0062] Before the neuromorphic processing kernel processes the events, the event scheduler ensures that the event time steps do not conflict. If there are unprocessed events in the event queue, the scheduler will pass the events to the neuromorphic processing kernel according to the timestamp order rules to ensure that each event is processed fairly and to avoid data loss or misprocessing due to time step conflicts.

[0063] This mechanism effectively resolves time step conflicts, prevents event time step misalignment, ensures that each pulse event enters the processing unit in the predetermined time step order, and guarantees the correctness and stability of the spiking neural network model.

[0064] like Figure 2As shown, to achieve efficient computation and data processing, the innovative neuromorphic instruction set architecture (ISA) based on an event-driven mechanism is configured with 32 registers, which have been extended with specific functions, such as storing synaptic weights, source and target neuron numbers, neuron states (e.g., membrane potential thresholds), and time delays. In addition, a 2048-byte instruction closely coupled memory (ICCM) and a 1024-byte data closely coupled memory (DCCM) are defined to support the development of various neuron models and feature in-memory computation. Specifically, the instruction set defines a flexible register numbering and allocation strategy, where registers 0 to 15 of the floating-point and integer registers are designed as general-purpose registers, supporting various operations such as data transfer, arithmetic operations, and logical operations. This design makes the registers highly flexible and reusable in different tasks. Furthermore, some special-function registers are defined specifically to support the management of specific parameters during spiking neural network operations. For example, they can store key data related to spiking neural networks, including time delays, synaptic weights, and membrane potential thresholds. These parameters are crucial for simulating neuronal behavior, performing time-step updates, and triggering spiking events.

[0065] Specifically, these special registers play a crucial role in instruction execution. For example, in the pulse event processing of spiking neural networks, the time delay register can be used to simulate the delay process of neural signals propagating between neurons, while the synaptic weight register is used to store the weight values ​​of neuronal connections, thus affecting the strength of signal transmission. Through the efficient management of these registers, the processor can complete complex neural network computation tasks with lower energy consumption while maintaining high computational accuracy.

[0066] The processor implementation employs a four-stage pipeline design, comprising instruction fetch, decode, operand fetch, and execution. This architecture fully utilizes hardware resources, achieving parallel processing of instructions in stages, thereby improving instruction throughput and overall performance. This architecture significantly optimizes the execution efficiency of complex operations in spiking neural network tasks.

[0067] During the parameter initialization phase, the processor loads the neuron model, the number of neurons, and the time window parameters for event processing, while also storing information such as synaptic weights and neuron connection topology. This phase ensures that the processor can correctly identify the mapping relationship between source neurons and target neurons.

[0068] The instruction set architecture of this invention adopts the bfloat16 (BF16) data format, a data representation method widely used in the field of deep learning. While maintaining the same numerical range as single-precision floating-point numbers (FP32), bfloat16 reduces the bit width, compressing the representation of floating-point numbers from 32 bits to 16 bits, thereby reducing storage requirements and improving computational efficiency. Furthermore, its computational precision is higher than the 8-bit integer operations commonly used in neural networks. This characteristic significantly improves performance and energy efficiency while reducing memory bandwidth requirements and power consumption, making it particularly suitable for large-scale neural network training and inference scenarios.

[0069] To adapt to different neural network applications, the processor instruction set of this invention is flexible and comprehensive, supporting various neuron computation models. For example, in the LIF (Leaky Integrate-and-Fire) model, the processor can perform leakage current calculations, threshold determination, and accumulation of neuron membrane potentials, simulating the impulse firing characteristics of neurons. The processor instruction set also supports more complex nonlinear dynamics calculations, accurately simulating the diverse behaviors of neurons, such as the more complex Izhikevich model. Through flexible combination of instructions, the processor can flexibly adapt to different neural network structures and algorithm requirements, exhibiting significant versatility.

[0070] The instruction set of this invention also includes a neuromorphic instruction set, which users can flexibly extend according to a custom instruction encoding format, such as... Figure 3 As shown, the core of the neuromorphic instruction set includes optimizing event response and sparse computation efficiency. In traditional instruction set architectures, processors typically employ a synchronous mode, executing instructions at a fixed rhythm each cycle. This approach is inefficient when handling discontinuous or sparse tasks. Event-driven architectures, on the other hand, are event-triggered; computation modules are activated only when an event occurs, and the processor enters a low-power mode when no events occur, thus significantly reducing energy consumption. This design is particularly crucial in spiking neural networks because they possess sparse excitation and time-step synchronization characteristics (such as...). Figure 4 As shown in the figure, traditional hardware is difficult to process efficiently.

[0071] The processor of this invention, through a general-purpose computing extension approach, not only supports spiking neural network computation but also provides flexible hardware and instruction set configuration capabilities. Users can extend the instruction set according to specific needs, thereby adapting to various new neural network models. This flexible design effectively reduces hardware development costs and time, and significantly improves system adaptability.

[0072] Meanwhile, this invention introduces an optimized event-driven mechanism and combines it with clock gating technology to optimize power consumption. In the absence of events, the processor can fully enter a sleep state, significantly reducing unnecessary power consumption. This mechanism fully utilizes the sparse computing characteristics of spiking neural networks, enabling the hardware to not only perform excellently under high-load tasks but also significantly reduce power consumption under low-load or idle states.

[0073] Through the above innovations, this invention not only breaks through the limitations of traditional neuromorphic hardware in terms of flexibility and energy consumption optimization and improves scalability, but also takes into account general computing capabilities, providing broader possibilities for the application of hardware in multi-tasking scenarios.

[0074] This invention also provides an asynchronous event scheduling method based on a neuromorphic processor supporting asynchronous event-driven operation as described above, comprising the following steps:

[0075] Receive input events and extract their time step identifiers;

[0076] If the event time step matches the current time step and the neuromorphic processing kernel is in a ready state, the event is directly transmitted to the neuromorphic processing kernel; otherwise, the event is written to the event queue in time step order.

[0077] After the neuromorphic processing kernel finishes processing the current event, it selects the earliest event that entered the queue from the event queue for processing.

[0078] When the queue is empty and no new events arrive, the BRE instruction is triggered to put the processor into a low-power sleep state.

[0079] Specifically, the instruction set introduces BRE (BRanch on Event) instructions for efficiently handling various types of critical events, such as Spike-only, Timestep-only, and Spike-with-Timestep. The introduction of BRE instructions greatly simplifies the switching time between different events and improves the processor's response efficiency in multi-event processing scenarios.

[0080] Spike-only events simulate the updating of neuronal membrane potentials within a time step, serving both as signal transmission in the input layer and representing the accumulation of neuronal membrane potentials within that time step. This process constitutes the core mechanism of spiking neural networks. In this invention, the processing of spike-only events is efficiently accomplished by an optimized instruction set, whose main functions include event reception and neuron state calculation.

[0081] like Figure 5As shown, when the processor detects a spike-only event (i.e., a neuron generates a spike signal), the corresponding computational logic is rapidly triggered. The processor retrieves synaptic information based on the event information (e.g., source neuron ID and target neuron ID) and updates the membrane potential and the state of the target neuron, including key calculations such as weight accumulation. This process relies on an event-driven mechanism to achieve efficient processing, enabling neuronal computation to quickly respond to input spikes and complete state updates. Figure 5 The dashed box visually illustrates the process.

[0082] Timestep-only events are specifically designed for global control of the input layer, giving timesteps a more explicit computational semantic. They can be used for time synchronization in non-spiking neural network computations, or as an auxiliary mechanism for spiking events. For example, this event can uniformly evaluate the membrane potentials of all neurons at each timestep and determine whether to fire a spiking signal based on the calculation results, thereby defining a new output event.

[0083] like Figure 6 As shown, whenever a Timestep-only event is triggered, the processor performs a series of processing operations on the neuron's membrane potential. First, it checks whether the neuron's current membrane potential exceeds a set threshold voltage. For neurons exceeding the threshold, the processor triggers a corresponding event, causing its membrane potential to quickly return to the resting state and firing a pulse signal at the synapse. This process simulates the periodic membrane potential updates of biological neurons, allowing spiking neural networks to naturally embody the concept of time steps. For example, in some neuromorphic computing tasks, Timestep-only events can prevent the membrane potential from accumulating indefinitely and perform normalization at appropriate time steps to maintain computational stability. Figure 6 The dashed box in the image visually illustrates the triggering process of this event and its role in the updating of neuronal membrane potential.

[0084] like Figure 7 As shown, the Spike-with-Timestep event is a mechanism for global control after the input layer. It assigns explicit temporal semantics to neuron computations at time steps, supporting both non-spiking neural network computations and serving as an auxiliary mechanism for spike events to ensure that spike transmission and state updates between neurons remain synchronized. When a time step arrives, if a neuron after the input layer generates a spike, the Spike-with-Timestep event must be triggered to ensure that the spike signal propagates correctly according to the neural network computation rules.

[0085] At each time step, the processor calculates the membrane potential change of the postsynaptic neuron based on the pulse signal generated by the presynaptic neuron. First, it checks whether the presynaptic neuron has generated a pulse in the current time step. If a pulse is detected, its effect on the target neuron is calculated. Based on the synaptic weights, a state update is performed. When the membrane potential exceeds a threshold, the postsynaptic neuron generates a new pulse and propagates it to subsequent neurons. Otherwise, the membrane potential continues to accumulate in subsequent time steps until the firing condition is met. Furthermore, the triggering of the Spike-with-Timestep event ensures that all neurons compute synchronously at each time step. In non-spiking neural network computation tasks, this event can also serve as a time synchronization signal, coordinating the collaborative work of different computational units and improving computational consistency.

[0086] The introduction of Spike-with-Timestep events allows the processor to precisely control the state evolution of neurons, ensuring that the membrane potential updates of postsynaptic neurons conform to the computational laws of biological neural networks. Simultaneously, this mechanism enhances computational flexibility, enabling efficient integration of spiking neural network computation with non-spiking neural network tasks, improving overall computational efficiency while maintaining accuracy. Based on an event-driven processing approach, this mechanism reduces unnecessary computational overhead, optimizing the system for both efficiency and real-time performance.

[0087] After processing each event, the processor of this invention automatically executes a BRE instruction, causing the processor to enter an event waiting state. If there are no events to process, it enters a low-power state; otherwise, it dynamically jumps to the corresponding event handler based on the type of the upcoming event. This design fully leverages the high efficiency of the event-driven mechanism and plays a crucial role in this architecture.

[0088] Specifically, the BRE instruction, combined with clock gating technology, can effectively control the processor's power consumption. When the BRE instruction is executed to enter a low-power state upon event completion, the processor will actively pause the clock signal (e.g., ...). Figure 8 As shown in the diagram, this allows the processor to enter a low-power standby state until the next event occurs. In this state, the processor not only reduces unnecessary energy consumption but also effectively utilizes the sparsity of the spiking neural network, avoiding meaningless computations during periods without events. When a new event is triggered, the clock signal is reactivated, and the processor immediately resumes from standby, jumping to the corresponding program segment based on the event type. This design ensures that the processor can respond quickly to complex asynchronous events while avoiding power waste caused by continuous operation.

[0089] This invention innovatively integrates neuromorphic computing and an asynchronous event instruction set architecture, cleverly combining the flexibility of traditional general-purpose processors with the efficiency of neuromorphic hardware, thus solving the balance problem between hardware architecture flexibility and specialized performance. This architecture not only efficiently handles the computational tasks of spiking neural networks but also retains support for traditional computing needs, demonstrating excellent compatibility and adaptability. Particularly in event-driven mode, this invention can efficiently handle the computational demands of complex neural networks, providing a highly efficient solution for the system.

[0090] Furthermore, the invention introduces an event-driven clock gating technique that fully leverages the sparsity of spiking neural networks to significantly reduce the ineffective energy consumption of neurons. This design not only greatly improves energy efficiency, making it particularly suitable for low-power applications, but also simplifies hardware implementation and provides flexible and efficient scalability through register sets and pipeline architectures optimized for spiking neural network tasks.

[0091] Building upon this, the introduction of the event scheduler and time step concepts further optimizes the timing management of the computation process. The event scheduler, by effectively managing time steps, ensures that events are triggered sequentially within the correct time steps, avoiding conflicts between time steps. This not only improves the accuracy and efficiency of the computation but also enables the system to handle asynchronous pulse events more accurately and efficiently.

[0092] Overall, this invention significantly outperforms existing technologies in terms of performance, energy efficiency, flexibility, and timing management, providing innovative design ideas for next-generation low-power, high-efficiency neuromorphic computing hardware.

[0093] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A neuromorphic processor supporting asynchronous event-driven, characterized in that, The application comprises: an event scheduler for receiving events and sending the events to a neuromorphic processing core or an event queue according to a current time step state; the event scheduler is configured to ensure the correctness of the event processing sequence through time step conflict detection and a timestamp-based scheduling strategy; an event queue coupled to the event scheduler for buffering non-current time step events or events that cannot be processed immediately; a neuromorphic processing core for executing an event processing program based on a neuromorphic instruction set architecture; the neuromorphic instruction set is an event processing-oriented instruction set, which comprises a BRE instruction for dynamically jumping to a corresponding processing program according to an event type and realizing low-power mode switching in cooperation with a clock gating module; wherein the processor enters a sleep state after the event processing is completed and suspends a clock signal through clock gating until a new event arrives; the neuromorphic instruction set architecture adopts a four-stage pipeline structure, including a fetch stage, a decode stage, an operand fetch stage and an execution stage; in the fetch stage, instructions are read from a neuron instruction memory; in the decode stage, instruction types and operand addresses are parsed; in the operand fetch stage, data is loaded from a register or a neuron data memory; in the execution stage, calculation is completed through an arithmetic logic unit and the results are written back to a register or a memory.

2. The neuromorphic processor supporting asynchronous event-driven of claim 1, wherein, The neuromorphic instruction set architecture is configured with: a plurality of functionally configurable registers, part of which are general-purpose registers and part of which are special function registers, for storing synaptic weights, source neuron and target neuron numbers, neuron states and time delay parameters; a neuron instruction memory and a neuron data memory are tightly coupled to the neuromorphic processing core, supporting integrated computing and storage operations; the neuromorphic instruction set reserves coding space, supporting users to extend instruction functions through custom instruction coding.

3. The neuromorphic processor supporting asynchronous event-driven of claim 2, wherein, The special function registers comprise: a neuron state register for storing the membrane potential of the current event neuron; a synaptic weight register for dynamically storing the connection weight between the source neuron and the target neuron; a membrane potential threshold register configured to trigger a neuron reset operation in a Timestep-only event.

4. The neuromorphic processor supporting asynchronous event-driven of claim 1 or 2 or 3, wherein, The neuromorphic instruction set architecture adopts a bfloat16 data format.

5. An asynchronous event scheduling method for a neuromorphic processor supporting asynchronous event-driven based on any one of claims 1-4, characterized in that, The application comprises the following steps: receiving an input event and extracting its time step identifier; if the event time step matches the current time step and the neuromorphic processing core is in a ready state, the event is directly transmitted to the neuromorphic processing core; otherwise, the event is written into the event queue in time step sequence; after the neuromorphic processing core processes the current event, the event that has been in the queue for the longest time is selected from the event queue for processing; when the queue is empty and no new event arrives, a BRE instruction is triggered to make the processor enter a low-power sleep state.

6. The asynchronous event scheduling method of claim 5, wherein, The execution logic of the BRE instruction comprises: when a Spike-only event is detected, the weight accumulation and state update operation of the target neuron are triggered; when a Timestep-only event is detected, global neuron membrane potential threshold determination is performed, and the pulse emission and membrane potential reset of the neuron that exceeds the threshold are performed. When a Spike-with-Timestep event is detected, the postsynaptic neuron state is updated synchronously and a new spike event is generated.

7. The asynchronous event scheduling method of claim 6, wherein, The specific process of updating the postsynaptic neuron state synchronously and generating a new spike event is as follows: At each time step, the processor calculates the membrane potential change of the postsynaptic neuron according to the spike signal generated by the presynaptic neuron; first, it detects whether the presynaptic neuron generates a spike at the current time step; if a spike is detected, the effect of the spike on the target neuron is calculated; the state is updated according to the synaptic weight; when the membrane potential exceeds the threshold, the neuron generates a new spike and propagates it to the subsequent neuron; otherwise, the membrane potential will continue to accumulate at the current time step until the discharge condition is met.

8. The asynchronous event scheduling method according to claim 5 or 6 or 7, characterized in that, The specific process of the processor entering a low-power sleep state is as follows: After the execution of the BRE instruction, the clock signals of the neuromorphic processing core and the event scheduler are turned off; When a new event arrives, the clock is reactivated through an interrupt signal, and the program entry address corresponding to the event type is jumped to according to the event type; The clock gating module is configured to reduce the power consumption of the processor to a static power level during no event.

9. The asynchronous event scheduling method according to claim 5 or 6 or 7, characterized in that, After processing each event, the processor automatically executes a BRE instruction to make the processor enter an event waiting state; if there is no event to be processed, the processor enters a low-power state, otherwise, it dynamically jumps to the corresponding event processing program according to the type of the arrived event.

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