Secondary circuit visualization method and device, electronic equipment and storage medium

Abstract

The invention relates to the technical field of power systems, and provides a secondary circuit visualization method and device, electronic equipment and a storage medium, and the secondary circuit visualization method comprises the steps: obtaining at least one to-be-recognized image which carries the structure information of a secondary circuit; at least one to-be-recognized image is recognized, a node topological structure is obtained, and the node topological structure comprises the hierarchical relation corresponding to the multiple node elements and the connection relation among the multiple node elements. And determining a graphic data model and an index map according to the hierarchical relationship and the connection relationship. And determining a visual image corresponding to the secondary loop according to the graphic data model and the index map. According to the method and the device, the intuition of the visual image can be improved, so that the user experience of the visual image is improved.

Description

Technical Field

[0001] The present application relates to the technical field of power systems, and in particular to a secondary circuit visualization method, device, electronic device, and storage medium. Background Art

[0002] In the power system, the secondary circuit is a measurement circuit, control circuit, protection circuit, signal circuit and power supply circuit composed of modules such as voltage / current transformers, control switches, relays, fault recorders, indicator lights, alarms, DC panels, and battery packs. The secondary circuit is a low-voltage electrical circuit used to monitor, control and protect primary equipment, and works in conjunction with the high-voltage primary circuit to ensure the safe and stable operation of the power system.

[0003] Since the wiring of the secondary circuits in the power system is complex and has many points and a wide range, the debugging and operation and maintenance of the secondary circuits are relatively difficult.

[0004] Traditional technical solutions use technologies like CAD (Computer Aided Design) to visualize secondary circuits, facilitating commissioning and maintenance. However, CAD visualizations lack intuitiveness, requiring operators to adjust their viewing angles to fully appreciate the model. This results in a low level of intelligence and a poor user experience. Summary of the Invention

[0005] The embodiments of the present application provide a secondary circuit visualization method, device, chip, electronic device, and computer-readable storage medium, which can improve the intuitiveness of the visualized image and enhance the user experience of the visualized image.

[0006] In a first aspect, the present application provides a secondary circuit visualization method, comprising: obtaining at least one image to be identified, the image to be identified carrying structural information of the secondary circuit; identifying the at least one image to be identified to obtain a node topology structure, the node topology structure including hierarchical relationships corresponding to multiple node elements and connection relationships between the multiple node elements; determining a graph data model and an index graph based on the hierarchical relationships and connection relationships; and determining a visualization image corresponding to the secondary circuit based on the graph data model and the index graph.

[0007] In some embodiments, identifying at least one image to be identified and obtaining a node topology structure includes: matching the at least one image to be identified based on a preset component library to obtain a plurality of node elements, wherein the image similarity between a first image region corresponding to a first node element in the first image to be identified and a first component image is greater than or equal to a preset similarity threshold, the first node element is any one of the plurality of node elements, the first image to be identified is an image in the at least one image to be identified where the first node element is located, and the first component image is an image in the preset component library that matches the first image region. Based on the plurality of node elements, identifying the at least one image to be identified to obtain connection relationships between the plurality of node elements, hierarchical relationships corresponding to the plurality of node elements, and multiple sets of description information corresponding to the plurality of node elements. Determining a hierarchical description model based on the connection relationships between the plurality of node elements, the hierarchical relationships corresponding to the plurality of node elements, and the multiple sets of description information corresponding to the plurality of node elements. Determining a node topology structure based on the hierarchical description model and the connection relationships between the plurality of node elements and the hierarchical relationships corresponding to the plurality of node elements.

[0008] In some embodiments, a hierarchical relationship includes at least a first level, at least one second level, and multiple third levels, wherein the at least one second level is a sublevel of the first level, and the multiple third levels are sublevels of the at least one second level corresponding to the second level. Determining a graph data model and an index graph based on the hierarchical relationship and the connection relationship includes: determining the graph data model based on the hierarchical relationship and the connection relationship based on a layered description model. Determining multiple index identifiers based on the hierarchical relationship, wherein the index identifiers include at least a first index identifier, at least one second index identifier, and multiple third index identifiers, wherein the first index identifier is an index identifier corresponding to the first level, the at least one second index identifier corresponds to the at least one second level, and the multiple third index identifiers correspond one-to-one with the multiple third levels. Determining an index graph based on the multiple index identifiers and the graph data model, wherein the index graph includes at least a first index graph, at least one second index graph, and multiple third index graphs, wherein the first index graph is an index graph corresponding to the first index identifier, the at least one second index graph corresponds to the at least one second index identifier, and the multiple third index graphs correspond one-to-one with the multiple third index identifiers.

[0009] In some embodiments, after determining the graph data model and the index graph based on the hierarchical relationship and the connection relationship, the method further includes: storing the graph data model and the index graph in a relational database.

[0010] In some embodiments, determining a visualization image corresponding to a secondary loop based on a graph data model and an index graph includes: determining visualization images corresponding to a first index graph, at least one second index graph, and multiple third index graphs based on a preset graph database, thereby obtaining a first visualization image, at least one second visualization image, and multiple third visualization images; and determining a visualization image corresponding to the secondary loop based on a force-directed layout algorithm, the first visualization image, the at least one second visualization image, and the multiple third visualization images.

[0011] In some embodiments, determining, based on a preset graph database, visual images corresponding to a first index graph, at least one second index graph, and multiple third index graphs includes: if a visual image corresponding to a target index graph exists in the preset graph database, obtaining the visual image corresponding to the target index graph to obtain the target visual image, thereby obtaining the first visual image, at least one second visual image, and multiple third visual images, where the target index graph is any one of the first index graph, at least one second index graph, and the multiple third index graphs. If a visual image corresponding to the target index graph does not exist in the preset graph database, generating the target visual image based on a graph data model to obtain the first visual image, at least one second visual image, and multiple third visual images.

[0012] In some embodiments, after determining the visual image corresponding to the secondary circuit based on the graph data model and the index graph, the method further includes: in response to the received error message, determining a primitive node corresponding to the error message in the visual image corresponding to the secondary circuit, and displaying an error icon on the primitive node in the visual image corresponding to the secondary circuit.

[0013] In a second aspect, the present application provides a secondary circuit visualization device, including an acquisition module and a processing module.

[0014] The acquisition module is used to acquire at least one image to be identified, where the image to be identified carries structural information of the secondary circuit.

[0015] The processing module is used to identify at least one image to be identified and obtain a node topology structure, where the node topology structure includes a hierarchical relationship corresponding to a plurality of node elements and a connection relationship between the plurality of node elements.

[0016] The processing module is further used to determine the graph data model and index graph based on the hierarchical relationship and the connection relationship.

[0017] The processing module is further used to determine a visualization image corresponding to the secondary circuit according to the graphic data model and the index map.

[0018] In a third aspect, the present application provides a chip, which is used to execute any method in the first aspect above.

[0019] In a fourth aspect, the present application provides an electronic device, comprising a processor and a memory, wherein the processor is configured to execute a computer program stored in the memory to implement the method as described in any one of the first aspects above. Alternatively,

[0020] The electronic device includes the chip according to the third aspect.

[0021] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the method as described in any one of the above-mentioned first aspects.

[0022] In the technical solution provided by this application, after acquiring at least one image to be identified, the visualization device can identify the at least one image to be identified and obtain a node topology structure. The image to be identified carries structural information about the secondary circuit. The node topology structure includes the hierarchical relationship corresponding to multiple node elements and the connection relationship between the multiple node elements. Based on the hierarchical relationship and connection relationship, a graph data model and an index map are determined. Finally, based on the graph data model and the index map, a visualization image corresponding to the secondary circuit is determined. The technical solution provided by this application can improve the intuitiveness of the visualization image, thereby enhancing the user experience of the visualization image. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 This is a flow chart of a secondary circuit visualization method provided in an embodiment of the present application;

[0025] Figure 2 This is a flow chart of a method for obtaining a node topology structure in a secondary circuit visualization method provided in an embodiment of the present application;

[0026] Figure 3 This is a schematic diagram of a hierarchical description model of a secondary circuit visualization method provided in an embodiment of the present application;

[0027] Figure 4 This is a schematic diagram of a node topology structure of a secondary circuit visualization method provided by an embodiment of the present application;

[0028] Figure 5 This is a schematic diagram of a graphical data model of a secondary circuit visualization method provided in an embodiment of the present application;

[0029] Figure 6 This is a schematic diagram of an index diagram of a secondary circuit visualization method provided by an embodiment of the present application;

[0030] Figure 7 This is a schematic diagram of a fault location process of a secondary circuit visualization method provided in an embodiment of the present application;

[0031] Figure 8 This is a data configuration flow diagram of a secondary circuit visualization method provided by an embodiment of the present application;

[0032] Figure 9 This is a schematic structural diagram of a secondary circuit visualization device provided in an embodiment of the present application;

[0033] Figure 10 This is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] In the following description, specific details such as specific system structures and technologies are provided for illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obstructing the description of the present application with unnecessary details.

[0035] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0036] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0037] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0038] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0039] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0040] In a power system, the primary circuit is a high-voltage circuit (such as busbars, transformers, and circuit breakers) that directly transmits electrical energy, typically ranging from 10kV to 1000kV. The secondary circuit is a low-voltage electrical circuit used to monitor, control, and protect primary equipment in the power system. It works in conjunction with the high-voltage primary circuit (main circuit) to ensure safe and stable operation of the power system.

[0041] However, due to the complex wiring and widespread nature of secondary circuits, commissioning and maintenance are challenging. For example, improper wiring or improper operation during commissioning or maintenance can cause power system anomalies or even failures.

[0042] In traditional technical solutions, operation and maintenance personnel can visualize the secondary circuit through CAD or paper drawings. However, since the technical solutions of visualizing secondary circuits with CAD technology and paper drawings cannot update the visualized secondary circuits in real time, the real-time performance and intelligence level are low.

[0043] In addition, operators can use SCD (Substation Configuration Description) technology to build a 3D data twin model to visualize the secondary circuit. However, this solution is not only bloated with information, but also requires operators to adjust their viewing angle to observe the entire model, which lacks intuitiveness and reduces the user experience.

[0044] Moreover, the network topology diagram constructed based on SCD technology can display the logical connection relationship between multiple devices. Part of the topology diagram is a virtual connection and cannot reflect the operating conditions of the secondary circuit.

[0045] In view of this, an embodiment of the present application provides a secondary circuit visualization method, which can improve the intuitiveness of the visualized image to enhance the user experience of the visualized image.

[0046] The technical solutions provided in the embodiments of this application can be applied to devices or electronic devices with computing functions such as computers, personal computers (PCs), and this application does not limit this. This application uses a visualization device as an example to illustrate the technical solutions provided in this application.

[0047] Figure 1 A flow chart of a secondary circuit visualization method provided in an embodiment of the present application. Figure 1 As shown, the following steps are included:

[0048] Step S101: obtaining at least one image to be identified, where the image to be identified carries structural information of a secondary circuit.

[0049] In an embodiment of the present application, the visualization device can determine an image to be recognized based on a scanned image of a secondary circuit wiring schematic diagram. Specifically, a user can upload a scanned image of the secondary circuit wiring schematic diagram to the visualization device. The scanned image of the secondary circuit wiring schematic diagram carries structural information of the secondary circuit. In response to receiving the scanned image of the secondary circuit wiring schematic diagram, the visualization device determines the scanned image of the secondary circuit wiring schematic diagram as the image to be recognized.

[0050] Step S102: Identify at least one image to be identified to obtain a node topology structure, where the node topology structure includes a hierarchical relationship corresponding to a plurality of node elements and a connection relationship between the plurality of node elements.

[0051] Figure 2 A flowchart of a method for obtaining a node topology structure of a secondary circuit visualization method provided in an embodiment of the present application. In an embodiment of the present application, a visualization device recognizes at least one image to be recognized, and a method for obtaining a node topology structure may include:

[0052] Step A1: Based on a preset component library, at least one image to be identified is matched respectively to obtain multiple node elements, the image similarity between the first image area corresponding to the first node element in the first image to be identified and the first component image is greater than or equal to a preset similarity threshold, the first node element is any one of the multiple node elements, the first image to be identified is an image where the first node element is located in at least one image to be identified, and the first component image is an image in the preset component library that matches the first image area.

[0053] Node elements can be secondary elements.

[0054] The visualization device can use a CAD tool to identify the stamp of at least one image to be identified to obtain basic information of the at least one image to be identified. The visualization device can also adjust the identification area of ​​the image to be identified and match the image to be identified using a preset component library to obtain multiple node elements.

[0055] Exemplarily, the first image to be identified is any one of at least one image to be identified, and the visualization device can adjust the identification area of ​​the first image to be identified to obtain a sub-image of the first image to be identified (the first sub-image to be identified). Traverse the preset component library, and determine the node elements corresponding to the component images in the preset component library whose image similarity with the first sub-image to be identified is greater than or equal to the preset similarity threshold as the node elements corresponding to the first sub-image to be identified. It should be understood that if there are multiple component images in the preset component library whose image similarity with the first sub-image to be identified is greater than or equal to the preset similarity threshold, the visualization device can determine the node element corresponding to the component image with the greatest image similarity as the node element corresponding to the first sub-image to be identified.

[0056] Node elements may include substation elements (Substation), cabinet elements (Cubicle) and device elements (Device).

[0057] Among them, the substation elements may include multiple regional elements (Region), multiple panel cabinet connection cable elements (Cable) and full station bay elements (Bay).

[0058] The bay element (Bay) of the entire station can include a device reference (DeviceRef) attribute. The device reference (DeviceRef) attribute is used to classify by bay to facilitate browsing the visualization interface of the secondary device loop under the bay.

[0059] The cable element (Cable) connecting the cabinet can include multiple cable cores (Core), cabinet A (CubicleA), cabinet B (CubicleB) ... cabinet N (CubicleN) and other cabinets, and cable types (type) and other elements.

[0060] Cable elements (Cable) can be divided into many types according to their functions, such as control cable (ControlCable), power cable (PowerCable), optical cable (FiberCable), Ethernet (NetworkCable), pigtail cable (PigtailCable), coaxial cable (CoaxialCable), etc.

[0061] Cable elements (Cable) can be used to connect screen cabinets, such as connecting screen cabinet A and screen cabinet B, and cable cores (Core) can be used to connect devices in the screen cabinets.

[0062] The region element (Region) can only contain the attributes of the cabinet element (Cubicle).

[0063] The cabinet element (Cubicle) can include cable core elements (Core), device elements (Device), cable elements (Cable), etc.

[0064] A cable core element (Core) can include attributes such as Board A (BoardA), Board B (BoardB), Class (Class), Device A (DeviceA), Device B (DeviceB), Port A (PortA), and Port B (PortB). The Class (Class) describes the function of the cable core. It can include types such as conductors and short connectors. For example, if devices A and B are in the same cabinet and device, the Class (Class) is short connector. Otherwise, the Classes are separated by AB and connected to the corresponding ports on the device boards.

[0065] Cable elements (Cable): The cables inside a cabinet have cabinet AB attribute values ​​that represent the same cabinet. They describe how the cable cores inside the cabinet connect different devices, such as switch cascades or switches connected to other communication devices.

[0066] Device elements (Device) can include attributes such as type (Class), template (model), supplier, etc. Devices can include intelligent devices (IED), terminal blocks (TD), switches (KK), handles (BS), lightning arresters (FLQ), thermostats (WKQ), printers (DYJ), etc.

[0067] Device elements (Device) can also include board elements (Board), port elements (Port), etc.

[0068] When a device element (Device) represents a terminal strip with the same name, the board element (Board) it contains can be used to represent a terminal in the terminal strip, and the name (name) attribute of the board element (Board) is the terminal name of a terminal strip; the port element (Port) contained in the board element (Board) can be used to represent a connection point of a terminal in the terminal strip, and the name (name) attribute of the port element (Port) is the name of the connection point of a terminal in the terminal strip.

[0069] In the embodiment of the present application, the attributes of the node elements may be stored in the relational database, and the visualization device may obtain the attributes of multiple node elements in the relational database.

[0070] Step A2: Based on multiple node elements, identify at least one image to be identified respectively to obtain connection relationships between multiple node elements, hierarchical relationships corresponding to multiple node elements, and multiple groups of description information corresponding to multiple node elements.

[0071] In an embodiment of the present application, the visualization device can identify the connection relationship between multiple node elements based on a preset recognition model, and determine the hierarchical relationship corresponding to the multiple node elements and multiple groups of descriptive information corresponding to the multiple node elements based on the connection relationship between the multiple node elements and the relationship database.

[0072] Step A3: Determine a hierarchical description model according to the connection relationship between the multiple node elements, the hierarchical relationship corresponding to the multiple node elements, and the multiple groups of description information corresponding to the multiple node elements.

[0073] For example, Figure 3 A schematic diagram of a hierarchical description model of a secondary circuit visualization method provided in an embodiment of the present application. Figure 3 As shown in Figure 1, multiple node elements may include substation elements (Substation), region elements (Region), cabinet elements (Cubicle), device elements (Device), board elements (Board), port elements (Port), core (Core), cable elements (Cable), bay elements (Bay) and device references (Device Ref). The hierarchical description model corresponding to multiple node elements is as follows: Figure 3 shown.

[0074] Step A4: Based on the hierarchical description model, the node topology structure is determined according to the connection relationship between the multiple node elements and the hierarchical relationship corresponding to the multiple node elements.

[0075] The hierarchical relationship may include at least a first level, at least one second level, and multiple third levels, wherein at least one second level is a sub-level of the first level, and multiple third levels are sub-levels corresponding to the second level in at least one second level. For example, the first level may be a station node (a node corresponding to a substation element (Substation)), and the first level may be one or more, which is not limited in this application. At least one second level may be a regional node (a node corresponding to at least one regional element (Region)), and multiple third levels may be cabinet nodes (nodes corresponding to a cabinet element (Cubicle)).

[0076] In some embodiments, the hierarchical relationship may also include four levels, five levels...N levels, which is not limited in this application.

[0077] Figure 4A schematic diagram of a node topology structure of a secondary circuit visualization method provided in an embodiment of the present application. Figure 4 As shown, the first level may include: station node 1 and station node 2. The second level may include: area node 1, area node 2, cable node 1 (node ​​corresponding to the cable element (Cable)), cable node 2, bay node 1 (node ​​corresponding to the bay element (Bay) of the entire station), and bay node 2. The third level may include: panel node 1, panel node 2, cable core node 1 (node ​​corresponding to the cable core (Core)), and cable core node 2. The fourth level may include: device node 1 (node ​​corresponding to the device element (Device)), device node 2, cable node 3, cable node 4, cable core node 3, and cable core node 4. The fifth level may include: board node 1 (node ​​corresponding to the board element (Board)), board node 2, terminal node 1 (node ​​corresponding to the port element (Port)), terminal node 2, cable core node 5, and cable core node 6. The sixth level may include: terminal node 3 and terminal node 4.

[0078] In the embodiment of the present application, the visualization device may store the node topology structure as an SDD file (System Description Document).

[0079] Step S103: Determine the graph data model and index graph according to the hierarchical relationship and the connection relationship.

[0080] In the embodiment of the present application, the visualization device can determine the graphic data model according to the hierarchical relationship and the connection relationship. Specifically, the visualization device can determine the graphic data model according to the hierarchical relationship and the connection relationship based on the layered description model.

[0081] Figure 5 This is a diagram of a graphical data model of a secondary circuit visualization method provided in an embodiment of the present application. Figure 5 As shown, the substation includes area A and area B. Area A includes panel cabinet A and panel cabinet B. Panel cabinet A includes equipment A and equipment B. Equipment A includes board A, which includes port A. Equipment B includes board B, which includes port B.

[0082] Cabinet B includes devices C and D. Device C includes board C, which includes port C. Ports A and C are connected via the core of cable A. Device D includes board D, which includes port D. Ports B and D are connected via the core of cable A.

[0083] Area B includes cabinets C and D. Cabinet C includes devices E and F. Devices E and B are connected via the core of cable C. Device E includes board E, which includes port E. Device F includes board F, which includes port F.

[0084] Cabinet D includes devices G and H. Device G includes board G, which includes port G. Port E is connected to port G via the core of cable B. Device H includes board H, which includes port H. Port F is connected to port H via the core of cable B.

[0085] In an embodiment of the present application, the visualization device can determine multiple index identifiers based on a hierarchical relationship, where the index identifiers include at least a first index identifier, at least one second index identifier, and multiple third index identifiers, where the first index identifier is the index identifier corresponding to the first level, at least one second index identifier corresponds to at least one second level, and multiple third index identifiers correspond one-to-one with multiple third levels. Furthermore, based on the multiple index identifiers and the graphic data model, an index graph is determined, where the index graph includes at least a first index graph, at least one second index graph, and multiple third index graphs, where the first index graph is the index graph corresponding to the first index identifier, at least one second index graph corresponds to at least one second index identifier, and multiple third index graphs correspond one-to-one with multiple third index identifiers.

[0086] For example, the first index identifier may be an index identifier corresponding to a substation, the second index identifier may be an index identifier corresponding to a region, and the third index identifier may be an index identifier corresponding to a panel cabinet. The first index map may be an index map corresponding to a substation, the second index map may be an index map corresponding to a region, and the third index map may be an index map corresponding to a panel cabinet.

[0087] It should be understood that at least one second index identifier may be displayed in the first index map, so that the operation and maintenance personnel can click the second index identifier to open the second index map corresponding to the second index identifier. Any second index map in the at least one second index map may also display a third index identifier, so that the operation and maintenance personnel can click the third index identifier to open the third index map corresponding to the third index identifier.

[0088] For example, Figure 6 This is a schematic diagram of an index diagram of a secondary circuit visualization method provided in an embodiment of the present application. Figure 6 As shown, Figure 6 (a) is the first index map, which is the index map corresponding to substation 1. The first index map shows four second index marks, namely area 1, area 2, area 3 and area 4. If the operation and maintenance personnel click on area 1, the visualization device can display Figure 6 (b) in the figure is the second index map, which shows N cabinets, namely cabinet 1, cabinet 2, cabinet 3, and cabinet N. If the operator clicks on the visualization device of cabinet 1, the Figure 6(c) in the figure is the third index diagram. The third index diagram may include multiple sub-panel cabinets connected by multiple cables, namely, panel cabinet n1, panel cabinet n2, panel cabinet n3, panel cabinet n4, panel cabinet n5...panel cabinet nN, and the multiple cables are respectively, namely, cable n1, cable n2, cable n3, cable n4, cable n5...cable nN.

[0089] Step S104: Determine a visualization image corresponding to the secondary loop according to the graphic data model and the index graph.

[0090] In an embodiment of the present application, a method for a visualization device to determine a visualization image corresponding to a secondary circuit based on a graphic data model and an index map may include:

[0091] First, the visualization device can determine the visualization images corresponding to the first index map, at least one second index map and multiple third index maps based on a preset graphic database to obtain the first visualization image, at least one second visualization image and multiple third visualization images.

[0092] In an embodiment of the present application, if there is a visualization image corresponding to the target index map in the preset graphic database, the visualization device obtains the visualization image corresponding to the target index map to obtain the target visualization image, thereby obtaining a first visualization image, at least one second visualization image and multiple third visualization images, and the target index map is any one of the first index map, at least one second index map and multiple third index maps.

[0093] If the visualization image corresponding to the target index image does not exist in the preset graphic database, the target visualization image is generated based on the graphic data model, thereby obtaining a first visualization image, at least one second visualization image, and a plurality of third visualization images. The target visualization image is then stored in the preset graphic database.

[0094] In the technical solution provided in the embodiment of the present application, multiple visualization images can be stored in the preset graphic database. If the target visualization image exists in the preset graphic database, the visualization device does not need to generate the target visualization image, which can save the generation time of the visualization image and the computing power of the visualization device, thereby reducing the secondary circuit visualization cost.

[0095] Then, the visualization device may determine a visualization image corresponding to the secondary loop based on the force-directed layout algorithm, the first visualization image, the at least one second visualization image, and the plurality of third visualization images.

[0096] Specifically, the visualization device can optimize the layout of the secondary circuit visualization graph through a layout optimization algorithm, so as to improve the response time and operation and maintenance efficiency of the visualization device when the user checks the circuit operation status. The visualization device can combine the connection relationship characteristics of the device elements (Device), simulate the device elements (Device) with connection points as nodes, and use a force-directed layout algorithm to optimize the layout of the secondary circuit visualization graph. The visualization device can also use other layout optimization algorithms to optimize the layout of the secondary circuit visualization graph, which is not limited in this application.

[0097] In the technical solution provided in the embodiment of the present application, operation and maintenance personnel can enter the secondary circuit visualization of the cable through the cable loop in the panel cabinet loop visualization interface. The visualization device can display a visualization graphic of all connection relationships with each cable core in the cable, so that operation and maintenance personnel can monitor the visualization process of the secondary circuit.

[0098] It should be understood that the force-directed layout algorithm adjusts node positions by simulating the interactions of forces in a physical system, calculating the push and pull between graphical nodes in the interface. The root node can be the source device graphical node, and all device element (Device) entity objects connected to it are connected nodes.

[0099] Node: Each device element (Device) entity object in the interface is a node.

[0100] Edge: The cable core connecting two device physical nodes is an edge.

[0101] Force: Pulling force describes the movement of two nodes closer to each other; pushing force describes the repulsion between all nodes. Pushing force can prevent graph overlap.

[0102] The formula for calculating the pulling force can be: F(i,j)=k*(|Pi-Pj|-l);

[0103] Among them, F is used to represent tension, i and j are used to represent nodes, P is used to represent position, l is used to represent natural length, and k is used to represent force coefficient.

[0104] The thrust calculation formula can be:

[0105] Among them, F is used to represent thrust, i and j are used to represent nodes, P is used to represent position, and k is used to represent force coefficient.

[0106] The method for optimizing the layout of the secondary loop visualization graph using the force-directed layout algorithm by the visualization device may include:

[0107] Step B1: The source device node is used as the initial position of all nodes, and the source device node position is fixed at the center of the interface.

[0108] The visualization device may use the source device node as the initial position of all nodes and fix the source device node position at the center of the interface.

[0109] Step B2: Traverse each pair of nodes and calculate the push and pull based on the direct connection, indirect connection and no connection relationship between the nodes.

[0110] The visualization device can clear the pull and push forces on the nodes and traverse each pair of nodes, that is, traverse each pair of nodes (i, j), and calculate the push and pull forces based on the direct connection, indirect connection and no connection relationship between the nodes.

[0111] The visualization device can determine the node pull and the node push according to whether the nodes are directly connected. Specifically, if the nodes are directly connected, the node pull is determined, and if not, the node push is determined.

[0112] Step B3: Update the position of each node according to the calculated resultant force direction and magnitude.

[0113] Step B4: If the current iteration value is greater than or equal to the maximum iteration number, the layout optimization is terminated.

[0114] The visualization device can set a maximum number of iterations and determine whether the current iteration value is greater than or equal to the set maximum number of iterations. If so, the layout optimization ends and the current image is determined to be the visualization image corresponding to the secondary circuit. If the current iteration value is less than the maximum number of iterations, steps B1 to B3 are repeated until the current iteration value is greater than or equal to the set maximum number of iterations.

[0115] In the embodiment of the present application, after the visualization device determines the visualization image corresponding to the secondary circuit according to the graphic data model and the index map, the technical solution provided by the embodiment of the present application further includes:

[0116] The visualization device may respond to the received error information and determine the primitive node corresponding to the error information in the visualization image corresponding to the secondary circuit, and then display an error icon on the primitive node in the visualization image corresponding to the secondary circuit.

[0117] In the embodiment of the present application, the visualization device can transmit the fault point information to the upper layer by displaying the corresponding primitive node of the error icon in the visualization image, and the operation and maintenance personnel can locate the fault to the lower layer according to the index.

[0118] Continue to see Figure 6 , if the fault point corresponding to the error information is Figure 6 The visualization device can display the error icon in the visualization image corresponding to the cabinet n3 in the image (c) and pass the fault point to the upper layer. Figure 6 (b) Image screen cabinet 1 visualization image, finally passed to Figure 6 In the visualization image corresponding to the image area 1 in (a), if the display module of the visualization device stays at Figure 6 In the visualization interface corresponding to image (a), the operation and maintenance personnel observed Figure 6 After the error icon is displayed in the visualization "area 1" corresponding to the image (a), you can Figure 6 Click on "Area 1" on the visualization interface corresponding to the image (a) in the figure, and the instruction to open the visualization image corresponding to "Area 1" is sent to the visualization device, and the visualization device displays Figure 6 The visualization image corresponding to image (b) in the figure, the operation and maintenance personnel observed Figure 6 After the error icon is displayed on the "Screen Cabinet 1" of the visualization image corresponding to the image (b) in the figure, you can Figure 6 Click on the “Screen Cabinet 1” in the visualization interface corresponding to the image (b) in the figure, and the visualization device will send the instruction of the visualization image corresponding to “Screen Cabinet 1” to the visualization device, and the visualization device will display Figure 6 The visualization image corresponding to image (c) in the figure, the operation and maintenance personnel observed Figure 6 After the error icon is displayed for "screen cabinet n3" in the visualization image corresponding to image (c) in FIG. 1 , it can be determined that there is a fault in screen cabinet n3.

[0119] In some embodiments, if the error message corresponds to a primitive node in the visualization image corresponding to the secondary loop accurately corresponding to the device loop, the visualization device displays an error icon at the primitive node in the visualization image corresponding to the device loop.

[0120] For example, Figure 7 A schematic diagram of the fault location process of a secondary circuit visualization method provided in an embodiment of the present application. The visualization device can display an error icon in the device loop visualization image, and pass it upward in sequence to the cable loop visualization image → the panel cabinet loop visualization image → the regional visualization image → the substation overview visualization image. If the fault point is device N corresponding to area 1, the operation and maintenance personnel can observe that "area 1" in the substation overview visualization image displays an error icon. After the operation and maintenance personnel clicks the index icon corresponding to "area 1", the operation and maintenance personnel can observe that "panel cabinet 1" in the regional visualization image displays an error icon. After the operation and maintenance personnel clicks the index icon corresponding to "panel cabinet 1", the operation and maintenance personnel can observe that "cable 1" in the panel cabinet loop visualization image displays an error icon. After the operation and maintenance personnel clicks the index icon corresponding to "cable 1", the operation and maintenance personnel can observe that "device N" in the cable loop visualization image displays an error icon. After the operation and maintenance personnel clicks the index icon corresponding to "device N", the operation and maintenance personnel can observe the fault point in the device loop visualization image corresponding to "device N".

[0121] In some embodiments, the visualization device may play an error prompt tone while displaying an error icon on a primitive node in a visualization image to ensure that operation and maintenance personnel can obtain error information.

[0122] In some embodiments, after determining the graphic data model and the index graph according to the hierarchical relationship and the connection relationship, the visualization device may further store the graphic data model and the index graph in a relational database.

[0123] For example, Figure 8 This is a data configuration flow diagram of a secondary circuit visualization method provided in an embodiment of the present application. Figure 8 As shown, after determining the node topology, the visualization device can store the node topology as an SDD file, import the SDD file into the graphic model configuration tool, and then automatically parse the SDD file to construct the logical relationship (graphic data model) of the entire station (substation) circuit, thereby creating a visualization sub-graph (index graph) of each panel cabinet circuit, and storing each visualization sub-graph of the panel cabinet circuit in a relational database. The visualization device can also create a regional index (second index identifier) ​​based on the visualization sub-graph of each panel cabinet circuit, and create an overall index of the entire station (first index identifier).

[0124] Continue to see Figure 8 In the process of determining the visualization image corresponding to the secondary circuit according to the graphic data model and the index map, the visualization device can determine the visualization image corresponding to the secondary circuit according to the graphic database as follows: Figure 8 shown.

[0125] After creating an image data class, the visualization device checks the relational database to see if a corresponding graphic exists. If so, it retrieves the graphic from the relational database and creates a graphic item through image-to-model mapping. This graphic item is used to visualize the cable loop and then digitally transferred to the real-time database. The visualized cable loop image is stored in the graphic database. This allows for secondary device visualization through feature comparison and extraction. Finally, in response to human-computer interaction, the visualized image is displayed.

[0126] The visual image generated by the secondary circuit visualization provided in the embodiment of the present application can intuitively display the error icon. The operation and maintenance personnel do not need to find the fault point through the visual image. The fault location process is simple, and there is no need to train the operation and maintenance personnel, so the operation and maintenance training cost is low.

[0127] In the technical solution provided by the embodiment of the present application, after obtaining at least one image to be identified, the visualization device can identify at least one image to be identified and obtain a node topology structure. The image to be identified carries the structural information of the secondary circuit, and the node topology structure includes the hierarchical relationship corresponding to multiple node elements and the connection relationship between multiple node elements. And according to the hierarchical relationship and the connection relationship, the graphic data model and the index map are determined. Finally, according to the graphic data model and the index map, the visualization image corresponding to the secondary circuit is determined. The technical solution provided by the present application can update the visualization image of the secondary circuit in real time, improve the timeliness of the secondary circuit visualization solution, display the error icon corresponding to the fault point in the visualization image, and jump and display the visualization image corresponding to the fault point of the visualization image in response to human-computer interaction, which can improve the intelligence and intuitiveness of the visualization image of the secondary circuit, so as to improve the user experience of the visualization image.

[0128] It should be understood that, provided there is no logical conflict, the above-mentioned embodiments can be combined with each other to meet actual application requirements. The specific embodiments or implementation plans obtained by these combinations still fall within the scope of protection of this application.

[0129] Corresponding to the secondary circuit visualization method in the above embodiment, an embodiment of the present application provides a secondary circuit visualization device, which can be implemented by software, hardware, or a combination of both as part or all of a computer device, and is used to execute the steps in the secondary circuit visualization method in the above embodiment.

[0130] Figure 9 A structural schematic diagram of a secondary circuit visualization device 90 provided in an embodiment of the present application is shown. For ease of explanation, only the parts related to the embodiment of the present application are shown.

[0131] Reference Figure 9 The device 90 includes an acquisition module 910 and a processing module 920.

[0132] The acquisition module 910 is configured to acquire at least one image to be identified, where the image to be identified carries structural information of the secondary circuit.

[0133] The processing module 920 is configured to identify at least one image to be identified and obtain a node topology structure. The node topology structure includes a hierarchical relationship corresponding to a plurality of node elements and a connection relationship between the plurality of node elements.

[0134] The processing module 920 is further configured to determine a graph data model and an index graph according to the hierarchical relationship and the connection relationship.

[0135] The processing module 920 is further configured to determine a visualization image corresponding to the secondary loop according to the graphic data model and the index graph.

[0136] In some embodiments, the processing module 920 is specifically used to: match at least one image to be identified based on a preset component library to obtain multiple node elements, wherein the image similarity between the first image area corresponding to the first node element in the first image to be identified and the first component image is greater than or equal to a preset similarity threshold, the first node element is any one of the multiple node elements, the first image to be identified is the image where the first node element is located in at least one image to be identified, and the first component image is an image in the preset component library that matches the first image area. Based on the multiple node elements, identify at least one image to be identified to obtain the connection relationship between the multiple node elements, the hierarchical relationship corresponding to the multiple node elements, and the multiple groups of description information corresponding to the multiple node elements. Determine a hierarchical description model based on the connection relationship between the multiple node elements, the hierarchical relationship corresponding to the multiple node elements, and the multiple groups of description information corresponding to the multiple node elements. Based on the hierarchical description model, determine the node topology structure based on the connection relationship between the multiple node elements and the hierarchical relationship corresponding to the multiple node elements.

[0137] In some embodiments, the hierarchical relationship includes at least a first level, at least one second level, and multiple third levels, at least one second level is a sub-level of the first level, and the multiple third levels are sub-levels of the at least one second level corresponding to the second level. The processing module 920 is specifically configured to: determine a graph data model based on the hierarchical description model and the hierarchical relationship and the connection relationship. According to the hierarchical relationship, determine multiple index identifiers, the index identifiers include at least a first index identifier, at least one second index identifier, and multiple third index identifiers, the first index identifier is the index identifier corresponding to the first level, the at least one second index identifier corresponds to the at least one second level, and the multiple third index identifiers correspond one-to-one with the multiple third levels. According to the multiple index identifiers and the graph data model, determine an index graph, the index graph includes at least a first index graph, at least one second index graph, and multiple third index graphs, the first index graph is the index graph corresponding to the first index identifier, the at least one second index graph corresponds to the at least one second index identifier, and the multiple third index graphs correspond one-to-one with the multiple third index identifiers.

[0138] In some embodiments, the processing module 920 is further configured to store the graph data model and the index graph in a relational database.

[0139] In some embodiments, the processing module 920 is specifically configured to: determine, based on a preset graph database, visualization images corresponding to the first index graph, at least one second index graph, and multiple third index graphs, to obtain the first visualization image, at least one second visualization image, and multiple third visualization images; and determine, based on the force-directed layout algorithm, the first visualization image, the at least one second visualization image, and the multiple third visualization images, a visualization image corresponding to the secondary loop.

[0140] In some embodiments, processing module 920 is specifically configured to: if a visualization image corresponding to the target index map exists in a preset graph database, obtain the visualization image corresponding to the target index map to obtain the target visualization image, thereby obtaining a first visualization image, at least one second visualization image, and multiple third visualization images, where the target index map is any one of the first index map, the at least one second index map, and the multiple third index maps. If a visualization image corresponding to the target index map does not exist in the preset graph database, generate the target visualization image based on the graph data model, thereby obtaining the first visualization image, at least one second visualization image, and multiple third visualization images.

[0141] In some embodiments, the processing module 920 is further configured to: in response to the received error information, determine the primitive node corresponding to the error information in the visual image corresponding to the secondary circuit, and display an error icon on the primitive node in the visual image corresponding to the secondary circuit.

[0142] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of this application. Their specific functions and technical effects can be found in the method embodiment section and will not be repeated here.

[0143] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0144] Based on the same inventive concept, an embodiment of the present application also provides an electronic device.

[0145] Figure 10 Schematic diagram of the structure of an electronic device provided by an embodiment of the present application. Figure 10 As shown, the electronic device 10 of this embodiment includes: at least one processor 1010 ( Figure 10 Only one is shown), memory 1020, and communication module 1040, memory 1020 stores computer program 1030 that may be run on processor 1010. When processor 1010 executes computer program 1030, steps in the above-mentioned secondary circuit visualization method embodiment are implemented, such as Figure 1 Alternatively, when the processor 1010 executes the computer program 1030, the functions of the modules / units in the above-mentioned device embodiments are realized, for example Figure 9 The functions of modules 910 to 920 are shown, and the communication module 1040 can be a separate communication unit for communicating with an external server or terminal device.

[0146] The electronic device 10 may include, but is not limited to: a processor 1010 and a memory 1020. Those skilled in the art will appreciate that Figure 10 It is only an example of the electronic device 10 and does not constitute a limitation of the electronic device 10. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the electronic device 10 may also include an input sending device, a network access device, a bus, etc.

[0147] The processor 1010 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0148] In some embodiments, the memory 1020 may be an internal storage unit of the electronic device 10, such as a hard disk or memory of the electronic device 10. The memory 1020 may also be an external storage device of the electronic device 10, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 10. The memory 1020 may also include both an internal storage unit of the electronic device 10 and an external storage device. The memory 1020 is used to store an operating system, application programs, a boot loader, data, and other programs, such as the program code of the computer program 1030. The memory 1020 may also be used to temporarily store data that has been sent or is about to be sent.

[0149] In addition, those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units in the various embodiments of the present application can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0150] An embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on an electronic device, the electronic device executes the steps in the above-mentioned method embodiments.

[0151] An embodiment of the present application provides a chip, which includes a processor and a memory. The memory stores a computer program, and when the computer program is executed by the processor, the steps in the above-mentioned method embodiments are implemented.

[0152] An embodiment of the present application provides a computer program product. When the computer program product is run on an electronic device, the electronic device executes the steps in the above-mentioned various method embodiments.

[0153] It should be understood that the processor mentioned in the embodiments of the present application may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0154] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct RAM bus random access memory (DR RAM).

[0155] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0156] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0157] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0158] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the system embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0159] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0160] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0161] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program, when executed by the processor, can implement the steps of the above-mentioned various method embodiments. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include at least: any entity or device capable of carrying the computer program code to a large-screen device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electric carrier signal, a telecommunication signal and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0162] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A secondary circuit visualization method, characterized in that: The method comprises: Acquire at least one image to be identified, where the image to be identified carries structural information of a secondary circuit; Identify the at least one image to be identified to obtain a node topology structure, where the node topology structure includes a hierarchical relationship corresponding to a plurality of node elements and a connection relationship between the plurality of node elements; Determining a graph data model and an index graph according to the hierarchical relationship and the connection relationship; A visualization image corresponding to the secondary loop is determined according to the graphic data model and the index map.

2. The secondary circuit visualization method according to claim 1, characterized in that: The step of identifying the at least one image to be identified to obtain a node topology structure includes: Based on a preset component library, matching is performed on the at least one image to be identified to obtain the multiple node elements, wherein an image similarity between a first image region corresponding to a first node element in the first image to be identified and a first component image is greater than or equal to a preset similarity threshold, the first node element is any one of the multiple node elements, the first image to be identified is an image in the at least one image to be identified where the first node element is located, and the first component image is an image in the preset component library that matches the first image region; Based on the multiple node elements, the at least one to-be-identified image is identified respectively to obtain connection relationships between the multiple node elements, hierarchical relationships corresponding to the multiple node elements, and multiple groups of description information corresponding to the multiple node elements; Determining a hierarchical description model according to the connection relationship between the multiple node elements, the hierarchical relationship corresponding to the multiple node elements, and the multiple groups of description information corresponding to the multiple node elements; Based on the hierarchical description model, the node topology structure is determined according to the connection relationship between the multiple node elements and the hierarchical relationship corresponding to the multiple node elements.

3. The secondary circuit visualization method according to claim 2, characterized in that: The hierarchical relationship includes at least a first level, at least one second level, and multiple third levels, the at least one second level is a sublevel of the first level, and the multiple third levels are sublevels corresponding to the second level in the at least one second level. Determining a graph data model and an index graph based on the hierarchical relationship and the connection relationship includes: Determining a graphic data model based on the hierarchical description model and the hierarchical relationship and the connection relationship; Determining, based on the hierarchical relationship, a plurality of index identifiers, the index identifiers including at least a first index identifier, at least one second index identifier, and a plurality of third index identifiers, wherein the first index identifier is an index identifier corresponding to the first level, the at least one second index identifier corresponds to the at least one second level, respectively, and the plurality of third index identifiers correspond one-to-one to the plurality of third levels; According to the multiple index identifiers and the graphic data model, the index map is determined, and the index map includes at least a first index map, at least one second index map and multiple third index maps, the first index map is the index map corresponding to the first index identifier, the at least one second index map corresponds to the at least one second index identifier respectively, and the multiple third index maps correspond one-to-one to the multiple third index identifiers.

4. The secondary circuit visualization method according to claim 3, characterized in that: After determining the graph data model and the index graph according to the hierarchical relationship and the connection relationship, the method further includes: The graph data model and the index graph are stored in a relational database.

5. The secondary circuit visualization method according to claim 3, characterized in that: Determining the visualization image corresponding to the secondary loop according to the graphic data model and the index map includes: Determining, based on a preset graph database, visualization images corresponding to the first index map, the at least one second index map, and the plurality of third index maps, to obtain a first visualization image, at least one second visualization image, and a plurality of third visualization images; A visualization image corresponding to the secondary loop is determined based on a force-directed layout algorithm, the first visualization image, the at least one second visualization image, and the plurality of third visualization images.

6. The secondary circuit visualization method according to claim 5, characterized in that: The determining, based on a preset graphic database, visual images corresponding to the first index map, the at least one second index map, and the plurality of third index maps includes: If a visualization image corresponding to the target index map exists in the preset graphic database, obtaining the visualization image corresponding to the target index map to obtain the target visualization image, thereby obtaining a first visualization image, at least one second visualization image, and a plurality of third visualization images, wherein the target index map is any one of the first index map, the at least one second index map, and the plurality of third index maps; If the visualization image corresponding to the target index graph does not exist in the preset graphic database, the target visualization image is generated based on the graphic data model, thereby obtaining a first visualization image, at least one second visualization image, and multiple third visualization images.

7. The secondary circuit visualization method according to any one of claims 1 to 6, characterized in that: After the step of determining the visualization image corresponding to the secondary loop according to the graphic data model and the index map, the method further includes: In response to the received error information, determining a primitive node corresponding to the error information in the visualization image corresponding to the secondary loop; The primitive node displays an error icon in the visualization image corresponding to the secondary loop.

8. A secondary circuit visualization device, characterized in that: The device comprises: An acquisition module, configured to acquire at least one image to be identified, wherein the image to be identified carries structural information of the secondary circuit; a processing module, configured to identify the at least one image to be identified and obtain a node topology structure, wherein the node topology structure includes a hierarchical relationship corresponding to a plurality of node elements and a connection relationship between the plurality of node elements; The processing module is further configured to determine a graph data model and an index graph according to the hierarchical relationship and the connection relationship; The processing module is further configured to determine a visualization image corresponding to the secondary loop based on the graphic data model and the index graph.

9. An electronic device, characterized in that: The system comprises a processor and a memory, wherein the processor is configured to execute a computer program stored in the memory to implement the secondary circuit visualization method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the secondary circuit visualization method as described in any one of claims 1 to 7 is implemented.

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