Driving method of display panel and display device

Abstract

The invention provides a driving method of a display panel and a display device. The display panel comprises a plurality of sub-pixels, a plurality of scanning signal lines and a plurality of light-emitting signal lines. One row of sub-pixels is electrically connected with one scanning signal line, and one row of sub-pixels is electrically connected with one light-emitting signal line; the driving method comprises the steps that in a display frame, effective level signals are loaded to scanning signal lines electrically connected with at least part of row sub-pixels in multiple rows of sub-pixels, and then effective level signals are loaded to light-emitting signal lines electrically connected with the at least part of row sub-pixels; a first time interval is formed between the end moment of the effective level signals loaded on the scanning signal lines electrically connected with the sub-pixels in the same row and the start moment of the effective level signals loaded on the light-emitting signal lines electrically connected with the sub-pixels in the row.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving method for a display panel and a display device. Background Art

[0002] Display panels, such as organic light-emitting diode (OLED) and quantum dot light-emitting diode (QLED) panels, typically include multiple pixel units. Each pixel unit can include multiple sub-pixels of different colors. By controlling the brightness of these sub-pixels, the desired color can be mixed to display a color image. Summary of the Invention

[0003] The embodiment of the present disclosure provides a method for driving a display panel, wherein the display panel includes: a plurality of sub-pixels, a plurality of scanning signal lines, and a plurality of light-emitting signal lines; a row of sub-pixels is electrically connected to one of the scanning signal lines, and a row of sub-pixels is electrically connected to one of the light-emitting signal lines;

[0004] The driving method includes:

[0005] In a display frame, firstly, an effective level signal is applied to the scanning signal lines electrically connected to at least some rows of sub-pixels in a plurality of rows of sub-pixels, and then an effective level signal is applied to the light emitting signal lines electrically connected to the at least some rows of sub-pixels;

[0006] There is a first time interval between the end time of loading the valid level signal on the scanning signal line electrically connected to the sub-pixels in the same row and the start time of loading the valid level signal on the luminescence signal line electrically connected to the sub-pixels in the same row.

[0007] In some possible implementations, after loading the valid level signal to the scanning signal line electrically connected to each row of sub-pixels in the multiple rows of sub-pixels in sequence, the valid level signal is then loaded to the light emitting signal line electrically connected to each row of sub-pixels in the multiple rows of sub-pixels in sequence.

[0008] In some possible implementations, the end time of loading the valid level signal on the scanning signal line electrically connected to the last row of sub-pixels is the same as the start time of loading the valid level signal on the luminescence signal line electrically connected to the first row of sub-pixels.

[0009] In some possible implementations, there is a second time interval between the end time when the effective level signal is loaded on the scanning signal line electrically connected to the last row of sub-pixels and the start time when the effective level signal is loaded on the luminous signal line electrically connected to the first row of sub-pixels.

[0010] In some possible implementations, after loading valid level signals to the scanning signal lines electrically connected to some rows of sub-pixels in multiple rows of sub-pixels in sequence, valid level signals are then loaded to the light emitting signal lines electrically connected to each row of sub-pixels in the multiple rows of sub-pixels in sequence.

[0011] In some possible implementations, the time when the effective level signal is loaded on the scanning signal line electrically connected to the last row of sub-pixels is later than the time when the effective level signal is loaded on the light emitting signal line electrically connected to the first row of sub-pixels.

[0012] In some possible implementations, there is at least one holding frame between two adjacent display frames, and in the holding frame, an effective level signal is loaded to the light emitting signal line electrically connected to each row of sub-pixels.

[0013] The display device provided by the embodiment of the present disclosure includes: a display panel and a gate driving circuit;

[0014] The display panel includes: multiple rows of sub-pixels, multiple scanning signal lines, and multiple light-emitting signal lines; a row of sub-pixels is electrically connected to one of the scanning signal lines, and a row of sub-pixels is electrically connected to one of the light-emitting signal lines;

[0015] The gate driving circuit is electrically connected to the multiple rows of sub-pixels and is configured to, in a display frame, first apply an effective level signal to the scanning signal lines electrically connected to at least some of the multiple rows of sub-pixels, and then apply an effective level signal to the light emitting signal lines electrically connected to the at least some of the rows of sub-pixels;

[0016] There is a first time interval between the end time of loading the valid level signal on the scanning signal line electrically connected to the sub-pixels in the same row and the start time of loading the valid level signal on the luminescence signal line electrically connected to the sub-pixels in the same row.

[0017] In some possible implementations, the gate driving circuit includes a plurality of shift register units;

[0018] The shift register unit is arranged corresponding to at least two adjacent rows of sub-pixels.

[0019] In some possible implementations, the gate driving circuit includes a first gate driving circuit and a second gate driving circuit;

[0020] The first gate driving circuit is disposed corresponding to the odd-numbered rows of sub-pixels, and the second gate driving circuit is disposed corresponding to the even-numbered rows of sub-pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Some structural schematic diagrams of display devices provided by embodiments of the present disclosure;

[0022] Figure 2 A flowchart of a driving method provided in an embodiment of the present disclosure;

[0023] Figure 3 Some signal diagrams provided for embodiments of the present disclosure;

[0024] Figure 4 Some other signal diagrams provided for embodiments of the present disclosure;

[0025] Figure 5 Some further signal diagrams provided for embodiments of the present disclosure;

[0026] Figure 6 Some signal timing diagrams provided for embodiments of the present disclosure;

[0027] Figure 7 Some further signal diagrams provided for embodiments of the present disclosure;

[0028] Figure 8 Other signal timing diagrams provided for embodiments of the present disclosure;

[0029] Figure 9 Some further signal timing diagrams provided for embodiments of the present disclosure;

[0030] Figure 10 Some further signal diagrams provided for embodiments of the present disclosure;

[0031] Figure 11 Some further signal timing diagrams provided for embodiments of the present disclosure;

[0032] Figure 12 Some further signal timing diagrams provided for embodiments of the present disclosure;

[0033] Figure 13 Some further signal diagrams provided for embodiments of the present disclosure;

[0034] Figure 14 Some further signal timing diagrams provided for embodiments of the present disclosure;

[0035] Figure 15 Some other structural schematic diagrams of display devices provided by embodiments of the present disclosure;

[0036] Figure 16 Some further structural schematic diagrams of display devices provided by embodiments of the present disclosure;

[0037] Figure 17 Some further structural schematic diagrams of display devices provided by embodiments of the present disclosure;

[0038] Figure 18 Some further structural schematic diagrams of the display device provided in the embodiments of the present disclosure. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0040] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0041] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0042] The display device provided by the embodiment of the present disclosure is as follows: Figure 1 As shown, it includes: a display panel 100 and a gate driving circuit 10;

[0043] The display panel 100 includes a base substrate and a plurality of sub-pixels spx (eg Figure 1 There are n*m ​​sub-pixels in the image, where n is the number of rows and m is the number of columns); illustratively, the multiple sub-pixels may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve color display. Alternatively, the multiple sub-pixels may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve color display. Of course, in actual applications, the luminous colors of the multiple sub-pixels can be designed and determined based on the actual application environment and are not limited here.

[0044] Different display application scenarios require different display effects. For example, in static images, it is necessary to reduce power consumption rather than pursue a higher refresh rate. In game mode, a higher refresh rate is pursued for a smoother display. The display panel provided in the embodiment of the present disclosure can be applied to a variety of different refresh rates. In some embodiments of the present disclosure, such as Figure 1 As shown, the display panel 100 includes: a plurality of scanning signal lines (eg Figure 1 SC1, SC2, SC3, SC4, SC5, SCn) and multiple light-emitting signal lines (such as Figure 1 EM1, EM2, EM3, EM4, EM5, EMn); wherein a row of sub-pixels spx is associated with a scanning signal line (eg Figure 1 SC1, SC2, SC3, SC4, SC5, SCn) are electrically connected, and a row of sub-pixels spx is connected to a light-emitting signal line (for example Figure 1 EM1, EM2, EM3, EM4, EM5, EMn) are electrically connected;

[0045] For example, Figure 1 As shown, the first row of sub-pixels spx is electrically connected to the scanning signal line SC1 and the light-emitting signal line EM1; the second row of sub-pixels spx is electrically connected to the scanning signal line SC2 and the light-emitting signal line EM2; the third row of sub-pixels spx is electrically connected to the scanning signal line SC3 and the light-emitting signal line EM3; the fourth row of sub-pixels spx is electrically connected to the scanning signal line SC4 and the light-emitting signal line EM4; the fifth row of sub-pixels spx is electrically connected to the scanning signal line SC5 and the light-emitting signal line EM5; the nth row of sub-pixels spx is electrically connected to the scanning signal line SCn and the light-emitting signal line EMn.

[0046] For example, Figure 1 As shown, the display device may further include: a plurality of data lines (eg Figure 1 DA1, DA2, DA3, DA4, DA5, DAm), gate drive circuit 10 and source drive circuit 20.

[0047] The gate drive circuit 10 is connected to the scanning signal line (eg Figure 1 SC1, SC2, SC3, SC4, SC5, SCn) and luminous signal lines (e.g. Figure 1 EM1, EM2, EM3, EM4, EM5, EMn) are electrically connected to multiple rows of sub-pixels spx, and are configured to first electrically connect the scan signal lines (e.g., Figure 1After the effective level signal is loaded to the SC1, SC2, SC3, SC4, SC5, SCn) in the row, the light emitting signal line (for example, Figure 1 EM1, EM2, EM3, EM4, EM5, EMn) in the EM1, EM2, EM3, EM4, EM5, EMn) are loaded with a valid level signal;

[0048] The source driving circuit 20 and the data line (eg Figure 1 DA1, DA2, DA3, DA4, DA5, DAm) are electrically connected. Wherein, a column of sub-pixels spx is connected to a data line (for example Figure 1 DA1, DA2, DA3, DA4, DA5, DAm) are electrically connected.

[0049] When the display panel 100 is working, a control signal is input to the gate drive circuit 10, so that the gate drive circuit sends a signal to the electrically connected scanning signal lines (eg Figure 1 SC1, SC2, SC3, SC4, SC5, SCn) and luminous signal lines (e.g. Figure 1 The EM1, EM2, EM3, EM4, EM5, EMn in the figure) output valid level signals, thereby driving the scanning signal lines (such as SC1, SC2, SC3, SC4, SC5, SCn in the figure) and the light-emitting signal lines (such as EM1, EM2, EM3, EM4, EM5, EMn in the figure).

[0050] Exemplarily, the effective level signal may be a low level signal. Of course, the effective level signal may also be a high level signal. It can be set according to requirements and is not limited here.

[0051] The source driving circuit 20 inputs a data voltage to the data line according to the display data, thereby charging the sub-pixel spx, so that the sub-pixel spx inputs the corresponding data voltage to realize the picture display function.

[0052] Exemplarily, the first column of sub-pixels spx is electrically connected to the data line DA1, the second column of sub-pixels spx is electrically connected to the data line DA2, the third column of sub-pixels spx is electrically connected to the data line DA3, the fourth column of sub-pixels spx is electrically connected to the data line DA4, the fifth column of sub-pixels spx is electrically connected to the data line DA5, and the mth column of sub-pixels spx is electrically connected to the data line DAm.

[0053] Exemplarily, each sub-pixel spx has a pixel circuit, and each pixel circuit includes a light-emitting device, a driving transistor, a data writing transistor, a light-emitting transistor and a pixel electrode; wherein the driving transistor is used to generate a driving current for driving the light-emitting device to emit light according to the data voltage; the gate of the data writing transistor is electrically connected to the corresponding scanning signal line, the first electrode of the data writing transistor is electrically connected to the corresponding data line, and the second electrode of the data writing transistor is electrically connected to the pixel electrode; the gate of the light-emitting transistor is electrically connected to the corresponding light-emitting signal line, the first electrode of the light-emitting transistor is electrically connected to the driving transistor, and the second electrode of the light-emitting transistor is electrically connected to the light-emitting device.

[0054] For example, the gate drive circuit sends signals to the electrically connected scanning signal lines (eg Figure 1 SC1, SC2, SC3, SC4, SC5, SCn) in the data writing circuit loads an effective level signal, thereby controlling the data writing transistor to be turned on. The turned-on data writing transistor will turn on the corresponding electrically connected data line (for example Figure 1 The data voltage on DA1, DA2, DA3, DA4, DA5, DAm) in the sub-pixel is provided to the pixel electrode, thereby charging the pixel electrode in the sub-pixel. The gate drive circuit provides a signal to the electrically connected light emitting signal line (e.g. Figure 1 EM1, EM2, EM3, EM4, EM5, and EMn) in the circuit are loaded with an effective level signal, thereby controlling the light-emitting transistor to be turned on. The turned-on light-emitting transistor provides the driving current generated by the driving transistor to the light-emitting device, so that the light-emitting device emits light after receiving the driving current, thereby realizing the picture display function.

[0055] For example, Figure 1 As shown, the source driver circuit 10 can be set as one; of course, the source driver circuit can be set as two, that is, one source driver circuit 10 is connected to half the number of data lines, and the other source driver circuit 10 is connected to the other half of the number of data lines. The source driver circuit 10 can also be set to three, four, or more, which can be designed and determined according to the needs of actual application and is not specifically limited here.

[0056] It should be noted that the pixel array structure in the display panel of the embodiment of the present disclosure can also be a dual-gate structure, that is, two gate lines are set between two adjacent rows of sub-pixels. This arrangement can reduce half of the data lines, that is, some adjacent columns of sub-pixels contain data lines, and some adjacent columns of sub-pixels do not include data lines. The specific sub-pixel arrangement structure and data lines, and the arrangement of the scan lines are not limited.

[0057] Currently, video games, live sports, and high-speed action videos contain a large number of fast-moving scenes, which places increasingly stringent performance demands on displays. Traditional film footage is typically shot at 24 frames per second (fps), while HFR technology can use 48fps, 60fps, 120fps, or even higher. This requires a display panel that supports high frame rates to play HFR content. To reduce the blurring of fast-moving images on the screen, the display panel also requires a high refresh rate. A higher refresh rate means more images can be displayed in the same amount of time. Typically, a display panel refresh rate of at least 120Hz is required to support low-motion blur mode. Furthermore, when the display panel refresh rate does not match the frame rate of the video content, display tearing and lag can occur.

[0058] To address the above issues, the current main optimization direction is to simply increase the refresh rate of the display panel. However, this method sometimes fails to achieve the desired effect and has certain limitations.

[0059] Therefore, the embodiment of the present disclosure provides a method for driving a display panel, such as Figure 2 As shown, specifically including:

[0060] S10, in a display frame, first applying an effective level signal to the scanning signal lines electrically connected to at least some of the rows of sub-pixels in the plurality of rows of sub-pixels, and then applying an effective level signal to the light emitting signal lines electrically connected to the at least some of the rows of sub-pixels;

[0061] S20 , there is a first time interval between the end time of the valid level signal loaded on the scanning signal line electrically connected to the sub-pixels in the same row and the start time of the valid level signal loaded on the light emitting signal line electrically connected to the sub-pixels in the same row.

[0062] The disclosed embodiment first loads an effective level signal to the scanning signal lines electrically connected to at least some of the rows of sub-pixels in a plurality of rows of sub-pixels, and then loads an effective level signal to the luminescence signal lines electrically connected to the at least some of the rows of sub-pixels. That is, by reducing the time it takes to load the effective level signal on the luminescence signal lines, the image can be updated and displayed more quickly. At the same time, the actual display time of each frame can be shortened, and the overlap between the previous and next frames caused by the visual stasis of the human eye can be reduced. This improves motion blur in fast-moving scenes, avoids screen tearing or delay on the display panel, and enhances the smoothness and quality of the image, achieving ultra-high-performance image quality and improving the display effect.

[0063] Moreover, since the time for loading the effective level signal on the light-emitting signal line is shortened, the conduction time of the light-emitting transistor in the pixel circuit is shortened, thereby avoiding the ghosting problem caused by the threshold voltage offset of the light-emitting transistor in the pixel circuit due to long-term conduction, further improving the display effect.

[0064] For example, Figures 3 to 5 As shown, sc represents the effective level signal (for example, a low level signal) loaded on the scanning signal line, em represents the effective level signal (for example, a low level signal) loaded on the luminous signal line, and the end moment of the low level signal sc1 loaded on the scanning signal line electrically connected to the sub-pixels in the first row and the start moment of the low level signal em1 loaded on the luminous signal line electrically connected to the sub-pixels in the first row have a first time interval T1.

[0065] In some embodiments of the present disclosure, after loading valid level signals to the scanning signal lines electrically connected to each row of sub-pixels in multiple rows of sub-pixels in sequence, valid level signals are then loaded to the luminous signal lines electrically connected to each row of sub-pixels in multiple rows of sub-pixels in sequence.

[0066] For example, Figure 1 As shown, first, effective level signals are sequentially loaded onto the scanning signal lines electrically connected to the sub-pixels in each row of n rows of sub-pixels. For example, effective level signals are sequentially loaded onto the scanning signal line SC1 electrically connected to the sub-pixels in the first row, onto the scanning signal line SC2 electrically connected to the sub-pixels in the second row, onto the scanning signal line SC3 electrically connected to the sub-pixels in the third row, onto the scanning signal line SC4 electrically connected to the sub-pixels in the fourth row, onto the scanning signal line SC5 electrically connected to the sub-pixels in the fifth row, and finally onto the scanning signal line SCn electrically connected to the sub-pixels in the nth row. After the effective level signals are loaded onto the scanning signal line SCn electrically connected to the sub-pixels in the nth row;

[0067] Then, effective level signals are sequentially loaded to the light-emitting signal lines electrically connected to each row of sub-pixels in the n rows of sub-pixels. For example, effective level signals are sequentially loaded to the light-emitting signal line EM1 electrically connected to the sub-pixels in the first row, effective level signals are sequentially loaded to the light-emitting signal line EM2 electrically connected to the sub-pixels in the second row, effective level signals are sequentially loaded to the light-emitting signal line EM3 electrically connected to the sub-pixels in the third row, effective level signals are sequentially loaded to the light-emitting signal line EM4 electrically connected to the sub-pixels in the fourth row, effective level signals are sequentially loaded to the light-emitting signal line EM5 electrically connected to the sub-pixels in the fifth row... and effective level signals are sequentially loaded to the light-emitting signal line EMn electrically connected to the sub-pixels in the nth row.

[0068] In some embodiments of the present disclosure, the end time of loading the valid level signal on the scanning signal line electrically connected to the last row of sub-pixels is the same as the start time of loading the valid level signal on the luminous signal line electrically connected to the first row of sub-pixels.

[0069] For example, Figure 3 and Figure 6 As shown, 1H represents a display frame, L1 represents the duration of a display frame, L2 represents the total duration for loading valid level signals to the scanning signal lines electrically connected to all rows of sub-pixels; L3 represents the duration for loading valid level signals to the luminous signal lines electrically connected to a row of sub-pixels; F1 represents the first display frame, and F2 represents the second display frame.

[0070] For example, in the first display frame F1, the end time of loading the valid level signal scn on the scanning signal line electrically connected to the nth row of sub-pixels is t1, and the start time of loading the valid level signal em1 on the luminous signal line electrically connected to the 1st row of sub-pixels is t1.

[0071] The following will Figure 1 As an example, the structure shown in Figure 6 The signal timing diagram shown further details;

[0072] For example, Figure 6 As shown, sc1 represents the signal loaded on the scanning signal line SC1 electrically connected to the sub-pixels in the first row, sc2 represents the signal loaded on the scanning signal line SC2 electrically connected to the sub-pixels in the second row, sc3 represents the signal loaded on the scanning signal line SC3 electrically connected to the sub-pixels in the third row, sc4 represents the signal loaded on the scanning signal line SC4 electrically connected to the sub-pixels in the fourth row, sc5 represents the signal loaded on the scanning signal line SC5 electrically connected to the sub-pixels in the fifth row, scn represents the signal loaded on the scanning signal line SCn electrically connected to the sub-pixels in the nth row, em1 represents the signal loaded on the emission signal line EM1 electrically connected to the sub-pixels in the first row, em2 represents the signal loaded on the emission signal line EM2 electrically connected to the sub-pixels in the second row, em3 represents the signal loaded on the emission signal line EM3 electrically connected to the sub-pixels in the third row, em4 represents the signal loaded on the emission signal line EM4 electrically connected to the sub-pixels in the fourth row, em5 represents the signal loaded on the emission signal line EM5 electrically connected to the sub-pixels in the fifth row, and emn represents the signal loaded on the emission signal line EMn electrically connected to the sub-pixels in the nth row;

[0073] For example, the refresh rate of the display panel in the embodiment of the present disclosure is xHZ, and the corresponding refresh time of each frame is 1 / x second (s), that is, the duration L1 of a display frame 1H = 1 / x second (s);

[0074] First, a low-level signal is sequentially loaded onto the scanning signal line SC1 electrically connected to the sub-pixels in the first row, a low-level signal is loaded onto the scanning signal line SC2 electrically connected to the sub-pixels in the second row, a low-level signal is loaded onto the scanning signal line SC3 electrically connected to the sub-pixels in the third row, a low-level signal is loaded onto the scanning signal line SC4 electrically connected to the sub-pixels in the fourth row, a low-level signal is loaded onto the scanning signal line SC5 electrically connected to the sub-pixels in the fifth row... a low-level signal is loaded onto the scanning signal line SCn electrically connected to the sub-pixels in the nth row, wherein the total time it takes for all the scanning signal lines electrically connected to the sub-pixels in all rows to be loaded with the low-level signal is L2, and a low-level signal is set. The duration of loading a low-level signal on the scanning signal line electrically connected to a row of sub-pixels is (L2 / L1)*1h=0.8h, where 1h=1 second (S) / refresh rate of the display panel x / total number of rows of sub-pixels in the display panel n; the refresh rate of the low-level signal on the scanning signal line is

[0075] Then, after the low-level signal is loaded onto the scanning signal line SCn electrically connected to the sub-pixels in the nth row, a low-level signal is immediately loaded sequentially onto the luminous signal line EM1 electrically connected to the sub-pixels in the first row, a low-level signal is loaded onto the luminous signal line EM2 electrically connected to the sub-pixels in the second row, a low-level signal is loaded onto the luminous signal line EM3 electrically connected to the sub-pixels in the third row, a low-level signal is loaded onto the luminous signal line EM4 electrically connected to the sub-pixels in the fourth row, a low-level signal is loaded onto the luminous signal line EM5 electrically connected to the sub-pixels in the fifth row... and a low-level signal is loaded onto the luminous signal line EM6 electrically connected to the sub-pixels in the nth row, wherein the duration for which the low-level signal is loaded onto the luminous signal line electrically connected to each row of sub-pixels is L3 = (L3 / L1)*1H, and it is set Among them, L1+L2=L3, then the time for each display frame to complete the update display is shortened to 1 / 5L1; the refresh frequency of the low-level signal on the luminous signal line is The end time of loading the low level signal scn on the scanning signal line electrically connected to the sub-pixels in the nth row is t1, and the start time of loading the low level signal em1 on the luminous signal line electrically connected to the sub-pixels in the 1st row is t1;

[0076] In the above embodiment, L1 and L3 are made tangent, that is, low-level signals are loaded to the scanning signal lines electrically connected to all rows of sub-pixels within 0.8 times the frame time. After the data writing of all rows of sub-pixels is completed (that is, after 0.8 times the frame time), low-level signals are immediately loaded to the luminous signal lines electrically connected to each row of sub-pixels in sequence, thereby quickly completing the update of the display screen and shortening the actual display time of each frame of the display screen. This setting can reduce the overlap of the previous frame of the display screen and the next frame of the display screen caused by the visual stasis of the human eye, improve the motion blur problem in fast-moving scenes, avoid the problems of screen tearing and delay, and thus achieve ultra-high performance image quality.

[0077] Moreover, since the time duration of loading the low-level signal on the light-emitting signal line electrically connected to each row of sub-pixels is relatively short, the light-emitting transistor in the pixel circuit can be prevented from being turned on for a long time, thereby preventing the threshold voltage shift of the light-emitting transistor, and further avoiding the ghosting problem caused by the threshold voltage shift, thereby further improving the display quality.

[0078] In some embodiments of the present disclosure, there is at least one holding frame between two adjacent display frames. In the holding frame, an effective level signal is loaded to the light emitting signal line electrically connected to each row of sub-pixels.

[0079] In the embodiment of the present disclosure, by having at least one hold frame between two adjacent display frames, that is, one or even more hold frames can be inserted between two adjacent display frames as needed, thereby achieving a variable refresh rate, dynamically matching the real-time picture frame number, improving the smoothness of the video, and avoiding the problem of picture freeze.

[0080] For example, Figure 7 and Figure 8 As shown, sc represents the effective level signal (e.g., a low level signal) loaded onto the scan signal line, em represents the effective level signal (e.g., a low level signal) loaded onto the luminescence signal line, 1H represents a display frame, L1 represents the duration of a display frame, L2 represents the total duration during which effective level signals are loaded onto the scan signal lines electrically connected to all rows of sub-pixels, L3 represents the duration during which effective level signals are loaded onto the luminescence signal lines electrically connected to a row of sub-pixels, F1 represents the first display frame, F2 represents the second display frame, F3 represents the third display frame, and F4 represents the fourth display frame. A hold frame exists between the first display frame F1 and the third display frame F3, i.e., the second display frame F2 is a hold frame. In the second display frame F2, the effective level signal em is loaded onto the luminescence signal lines electrically connected to each row of sub-pixels.

[0081] For example, if the current refresh rate of the display panel is 120 Hz, the refresh rate of the display panel can be reduced to 60 Hz by providing one hold frame between two adjacent display frames. Alternatively, the refresh rate of the display panel can be reduced to 30 Hz by providing three hold frames between two adjacent display frames. The number of hold frames can be set as needed and is not specifically limited here.

[0082] For example, Figure 8 As shown, sc1 represents the signal loaded on the scanning signal line SC1 electrically connected to the sub-pixels in the first row, sc2 represents the signal loaded on the scanning signal line SC2 electrically connected to the sub-pixels in the second row, sc3 represents the signal loaded on the scanning signal line SC3 electrically connected to the sub-pixels in the third row, sc4 represents the signal loaded on the scanning signal line SC4 electrically connected to the sub-pixels in the fourth row, sc5 represents the signal loaded on the scanning signal line SC5 electrically connected to the sub-pixels in the fifth row, scn represents the signal loaded on the scanning signal line SCn electrically connected to the sub-pixels in the nth row, em1 represents the signal loaded on the emission signal line EM1 electrically connected to the sub-pixels in the first row, em2 represents the signal loaded on the emission signal line EM2 electrically connected to the sub-pixels in the second row, em3 represents the signal loaded on the emission signal line EM3 electrically connected to the sub-pixels in the third row, em4 represents the signal loaded on the emission signal line EM4 electrically connected to the sub-pixels in the fourth row, em5 represents the signal loaded on the emission signal line EM5 electrically connected to the sub-pixels in the fifth row, and emn represents the signal loaded on the emission signal line EMn electrically connected to the sub-pixels in the nth row;

[0083] For example, in the second display frame (i.e., the hold frame), a low-level signal is sequentially loaded onto the light-emitting signal line EM1 electrically connected to the sub-pixels in the first row, a low-level signal is loaded onto the light-emitting signal line EM2 electrically connected to the sub-pixels in the second row, a low-level signal is loaded onto the light-emitting signal line EM3 electrically connected to the sub-pixels in the third row, a low-level signal is loaded onto the light-emitting signal line EM4 electrically connected to the sub-pixels in the fourth row, a low-level signal is loaded onto the light-emitting signal line EM5 electrically connected to the sub-pixels in the fifth row…and a low-level signal is loaded onto the light-emitting signal line EMn electrically connected to the sub-pixels in the nth row, wherein the duration for which the low-level signal is loaded onto the light-emitting signal line electrically connected to each row of sub-pixels is L3.

[0084] In some embodiments of the present disclosure, there is a second time interval between the end time when the effective level signal is loaded on the scanning signal line electrically connected to the last row of sub-pixels and the start time when the effective level signal is loaded on the luminous signal line electrically connected to the first row of sub-pixels.

[0085] For example, Figure 4 and Figure 9As shown, 1H represents a display frame, L1 represents the duration of a display frame, L2 represents the total duration for loading valid level signals to the scanning signal lines electrically connected to all rows of sub-pixels; L3 represents the duration for loading valid level signals to the luminous signal lines electrically connected to a row of sub-pixels; F1 represents the first display frame, and F2 represents the second display frame.

[0086] For example, in the first display frame F1, the end moment of loading the valid level signal scn on the scanning signal line electrically connected to the nth row of sub-pixels and the start moment of loading the valid level signal em1 on the luminous signal line electrically connected to the 1st row of sub-pixels have a second time interval T2.

[0087] The following will Figure 1 As an example, the structure shown in Figure 9 The signal timing diagram shown further details;

[0088] For example, Figure 9 As shown, sc1 represents the signal loaded on the scanning signal line SC1 electrically connected to the sub-pixels in the first row, sc2 represents the signal loaded on the scanning signal line SC2 electrically connected to the sub-pixels in the second row, sc3 represents the signal loaded on the scanning signal line SC3 electrically connected to the sub-pixels in the third row, sc4 represents the signal loaded on the scanning signal line SC4 electrically connected to the sub-pixels in the fourth row, sc5 represents the signal loaded on the scanning signal line SC5 electrically connected to the sub-pixels in the fifth row, scn represents the signal loaded on the scanning signal line SCn electrically connected to the sub-pixels in the nth row, em1 represents the signal loaded on the emission signal line EM1 electrically connected to the sub-pixels in the first row, em2 represents the signal loaded on the emission signal line EM2 electrically connected to the sub-pixels in the second row, em3 represents the signal loaded on the emission signal line EM3 electrically connected to the sub-pixels in the third row, em4 represents the signal loaded on the emission signal line EM4 electrically connected to the sub-pixels in the fourth row, em5 represents the signal loaded on the emission signal line EM5 electrically connected to the sub-pixels in the fifth row, and emn represents the signal loaded on the emission signal line EMn electrically connected to the sub-pixels in the nth row;

[0089] For example, the refresh rate of the display panel in the embodiment of the present disclosure is xHZ, and the corresponding refresh time of each frame is 1 / x second (s), that is, the duration L1 of a display frame 1H = 1 / x second (s);

[0090] First, a low-level signal is sequentially loaded onto the scanning signal line SC1 electrically connected to the sub-pixels in the first row, a low-level signal is loaded onto the scanning signal line SC2 electrically connected to the sub-pixels in the second row, a low-level signal is loaded onto the scanning signal line SC3 electrically connected to the sub-pixels in the third row, a low-level signal is loaded onto the scanning signal line SC4 electrically connected to the sub-pixels in the fourth row, a low-level signal is loaded onto the scanning signal line SC5 electrically connected to the sub-pixels in the fifth row... a low-level signal is loaded onto the scanning signal line SCn electrically connected to the sub-pixels in the nth row, wherein the total time it takes for all the scanning signal lines electrically connected to the sub-pixels in all rows to be loaded with the low-level signal is L2, and a low-level signal is set. The duration of loading a low-level signal on the scanning signal line electrically connected to a row of sub-pixels is (L2 / L1)*1h=0.8h, where 1h=1 second (S) / refresh rate of the display panel x / total number of rows of sub-pixels in the display panel n; the refresh rate of the low-level signal on the scanning signal line is

[0091] Then, after the low-level signal is loaded onto the scanning signal line SCn electrically connected to the sub-pixels in the nth row, a low-level signal is sequentially loaded onto the luminous signal line EM1 electrically connected to the sub-pixels in the first row, a low-level signal is loaded onto the luminous signal line EM2 electrically connected to the sub-pixels in the second row, a low-level signal is loaded onto the luminous signal line EM3 electrically connected to the sub-pixels in the third row, a low-level signal is loaded onto the luminous signal line EM4 electrically connected to the sub-pixels in the fourth row, a low-level signal is loaded onto the luminous signal line EM5 electrically connected to the sub-pixels in the fifth row... and a low-level signal is loaded onto the luminous signal line EMn electrically connected to the sub-pixels in the nth row, wherein the duration for which the low-level signal is loaded onto the luminous signal line electrically connected to each row of sub-pixels is L3 = (L3 / L1)*1H, and it is set Among them, L1+L2<L3, then the time length of each display frame to complete the update display is shortened to 1 / 6L1; the refresh frequency of the low-level signal on the luminous signal line is There is a second time interval T2 between the end time of loading the low level signal scn on the scanning signal line electrically connected to the nth row of sub-pixels and the start time of loading the low level signal em1 on the luminous signal line electrically connected to the 1st row of sub-pixels;

[0092] In the above embodiment, L1 and L3 are spaced apart from each other, that is, low-level signals are loaded to the scanning signal lines electrically connected to all rows of sub-pixels within 0.8 times the frame time. After data writing to all rows of sub-pixels is completed (i.e., after 0.8 times the frame time), loading of low-level signals to the luminous signal lines electrically connected to the first row of sub-pixels is delayed, and loading of low-level signals to the luminous signal lines is stopped in advance. This can further shorten the time for loading low-level signals to the luminous signal lines, achieve faster picture update display, improve motion blur in fast-moving scenes, and achieve ultra-high performance image quality.

[0093] Moreover, since the time duration for which a low-level signal is loaded on the light-emitting signal line electrically connected to each row of sub-pixels is further shortened, the light-emitting transistor in the pixel circuit can be prevented from being turned on for a long time, thereby preventing the threshold voltage shift of the light-emitting transistor, and further avoiding the ghosting problem caused by the threshold voltage shift, thereby further improving the display quality.

[0094] In some embodiments of the present disclosure, there is at least one holding frame between two adjacent display frames. In the holding frame, an effective level signal is loaded to the light emitting signal line electrically connected to each row of sub-pixels.

[0095] In the embodiment of the present disclosure, by having at least one hold frame between two adjacent display frames, that is, one or even more hold frames can be inserted between two adjacent display frames as needed, thereby achieving a variable refresh rate, dynamically matching the real-time picture frame number, improving the smoothness of the video, and avoiding the problem of picture freeze.

[0096] For example, Figure 10 and Figure 11 As shown, sc represents the effective level signal (e.g., a low level signal) loaded onto the scan signal line, em represents the effective level signal (e.g., a low level signal) loaded onto the luminescence signal line, 1H represents a display frame, L1 represents the duration of a display frame, L2 represents the total duration during which effective level signals are loaded onto the scan signal lines electrically connected to all rows of sub-pixels, L3 represents the duration during which effective level signals are loaded onto the luminescence signal lines electrically connected to a row of sub-pixels, F1 represents the first display frame, F2 represents the second display frame, F3 represents the third display frame, and F4 represents the fourth display frame. A hold frame exists between the first display frame F1 and the third display frame F3, i.e., the second display frame F2 is a hold frame. In the second display frame F2, the effective level signal em is loaded onto the luminescence signal lines electrically connected to each row of sub-pixels.

[0097] For example, if the refresh rate of the current display panel is 120Hz, the refresh rate of the display panel can be set to 60Hz by having one hold frame between two adjacent display frames; of course, the refresh rate of the display panel can also be set to 30Hz by having three hold frames between two adjacent display frames.

[0098] For example, Figure 11As shown, sc1 represents the signal loaded on the scanning signal line SC1 electrically connected to the sub-pixels in the first row, sc2 represents the signal loaded on the scanning signal line SC2 electrically connected to the sub-pixels in the second row, sc3 represents the signal loaded on the scanning signal line SC3 electrically connected to the sub-pixels in the third row, sc4 represents the signal loaded on the scanning signal line SC4 electrically connected to the sub-pixels in the fourth row, sc5 represents the signal loaded on the scanning signal line SC5 electrically connected to the sub-pixels in the fifth row, scn represents the signal loaded on the scanning signal line SCn electrically connected to the sub-pixels in the nth row, em1 represents the signal loaded on the emission signal line EM1 electrically connected to the sub-pixels in the first row, em2 represents the signal loaded on the emission signal line EM2 electrically connected to the sub-pixels in the second row, em3 represents the signal loaded on the emission signal line EM3 electrically connected to the sub-pixels in the third row, em4 represents the signal loaded on the emission signal line EM4 electrically connected to the sub-pixels in the fourth row, em5 represents the signal loaded on the emission signal line EM5 electrically connected to the sub-pixels in the fifth row, and emn represents the signal loaded on the emission signal line EMn electrically connected to the sub-pixels in the nth row;

[0099] For example, in the second display frame (i.e., the hold frame), a low-level signal is sequentially loaded onto the light-emitting signal line EM1 electrically connected to the sub-pixels in the first row, a low-level signal is loaded onto the light-emitting signal line EM2 electrically connected to the sub-pixels in the second row, a low-level signal is loaded onto the light-emitting signal line EM3 electrically connected to the sub-pixels in the third row, a low-level signal is loaded onto the light-emitting signal line EM4 electrically connected to the sub-pixels in the fourth row, a low-level signal is loaded onto the light-emitting signal line EM5 electrically connected to the sub-pixels in the fifth row…and a low-level signal is loaded onto the light-emitting signal line EMn electrically connected to the sub-pixels in the nth row, wherein the duration for which the low-level signal is loaded onto the light-emitting signal line electrically connected to each row of sub-pixels is L3.

[0100] In some embodiments of the present disclosure, after loading valid level signals to the scanning signal lines electrically connected to some rows of sub-pixels in multiple rows of sub-pixels in sequence, valid level signals are loaded to the light emitting signal lines electrically connected to each row of sub-pixels in the multiple rows of sub-pixels in sequence.

[0101] For example, Figure 1As shown, first, effective level signals are sequentially loaded onto the scanning signal lines electrically connected to the sub-pixels in each row of rows of sub-pixels. For example, effective level signals are sequentially loaded onto the scanning signal line SC1 electrically connected to the sub-pixels in the first row, onto the scanning signal line SC2 electrically connected to the sub-pixels in the second row, onto the scanning signal line SC3 electrically connected to the sub-pixels in the third row, onto the scanning signal line SC4 electrically connected to the sub-pixels in the fourth row, onto the scanning signal line SC5 electrically connected to the sub-pixels in the fifth row, and so on. Effective level signals are then loaded onto the scanning signal lines electrically connected to the sub-pixels in the 2nd / 3nth row. After the effective level signals are loaded onto the scanning signal lines electrically connected to the sub-pixels in the 2nd / 3nth row;

[0102] Then, an effective level signal is sequentially applied to the light emitting signal line electrically connected to each row of sub-pixels in the n rows of sub-pixels. For example, an effective level signal is sequentially applied to the light emitting signal line EM1 electrically connected to the sub-pixels in the first row, an effective level signal is sequentially applied to the light emitting signal line EM2 electrically connected to the sub-pixels in the second row, an effective level signal is sequentially applied to the light emitting signal line EM3 electrically connected to the sub-pixels in the third row, an effective level signal is sequentially applied to the light emitting signal line EM4 electrically connected to the sub-pixels in the fourth row, an effective level signal is sequentially applied to the light emitting signal line EM5 electrically connected to the sub-pixels in the fifth row, and so on, an effective level signal is sequentially applied to the light emitting signal line EMn electrically connected to the sub-pixels in the nth row.

[0103] Among them, the scanning signal lines electrically connected to the remaining 1 / 3n rows of sub-pixels are still loaded with valid level signals in sequence; the time period in which the scanning signal lines electrically connected to some rows of sub-pixels in the remaining 1 / 3n rows are loaded with valid level signals overlaps with the time period in which the luminous signal lines electrically connected to the first row of sub-pixels are loaded with valid level signals.

[0104] In some embodiments of the present disclosure, the time when the effective level signal is loaded on the scanning signal line electrically connected to the last row of sub-pixels is later than the time when the effective level signal is loaded on the light emitting signal line electrically connected to the first row of sub-pixels.

[0105] For example, Figure 5 and Figure 12 As shown, 1H represents a display frame, L1 represents the duration of a display frame, L2 represents the total duration for loading valid level signals to the scanning signal lines electrically connected to all rows of sub-pixels; L3 represents the duration for loading valid level signals to the luminous signal lines electrically connected to a row of sub-pixels; F1 represents the first display frame, and F2 represents the second display frame.

[0106] For example, in the first display frame F1, the end time of loading the effective level signal scn on the scanning signal line electrically connected to the nth row of sub-pixels is later than the start time of loading the effective level signal em1 on the luminous signal line electrically connected to the 1st row of sub-pixels.

[0107] The following will Figure 1 As an example, combined with the structure shown Figure 12 The signal timing diagram shown further details;

[0108] For example, Figure 12 As shown, sc1 represents the signal loaded on the scanning signal line SC1 electrically connected to the sub-pixels in the first row, sc2 represents the signal loaded on the scanning signal line SC2 electrically connected to the sub-pixels in the second row, sc3 represents the signal loaded on the scanning signal line SC3 electrically connected to the sub-pixels in the third row, sc4 represents the signal loaded on the scanning signal line SC4 electrically connected to the sub-pixels in the fourth row, sc5 represents the signal loaded on the scanning signal line SC5 electrically connected to the sub-pixels in the fifth row, scn represents the signal loaded on the scanning signal line SCn electrically connected to the sub-pixels in the nth row, em1 represents the signal loaded on the emission signal line EM1 electrically connected to the sub-pixels in the first row, em2 represents the signal loaded on the emission signal line EM2 electrically connected to the sub-pixels in the second row, em3 represents the signal loaded on the emission signal line EM3 electrically connected to the sub-pixels in the third row, em4 represents the signal loaded on the emission signal line EM4 electrically connected to the sub-pixels in the fourth row, em5 represents the signal loaded on the emission signal line EM5 electrically connected to the sub-pixels in the fifth row, and emn represents the signal loaded on the emission signal line EMn electrically connected to the sub-pixels in the nth row;

[0109] For example, the refresh rate of the display panel in the embodiment of the present disclosure is xHZ, and the corresponding refresh time of each frame is 1 / x second (s), that is, the duration L1 of a display frame 1H = 1 / x second (s);

[0110] First, a low-level signal is sequentially loaded onto the scanning signal line SC1 electrically connected to the sub-pixels in the first row, a low-level signal is loaded onto the scanning signal line SC2 electrically connected to the sub-pixels in the second row, a low-level signal is loaded onto the scanning signal line SC3 electrically connected to the sub-pixels in the third row, a low-level signal is loaded onto the scanning signal line SC4 electrically connected to the sub-pixels in the fourth row, a low-level signal is loaded onto the scanning signal line SC5 electrically connected to the sub-pixels in the fifth row…a low-level signal is loaded onto the scanning signal lines electrically connected to the sub-pixels in the 2nd / 3nth row…a low-level signal is loaded onto the scanning signal line SCn electrically connected to the sub-pixels in the nth row, wherein the total time it takes for all the scanning signal lines electrically connected to the sub-pixels in all rows to be loaded with the low-level signal is L2, and a low-level signal is set. The duration of loading a low-level signal on the scanning signal line electrically connected to a row of sub-pixels is (L2 / L1)*1h=0.8h, where 1h=1 second (S) / refresh rate of the display panel x / total number of rows of sub-pixels in the display panel n; the refresh rate of the low-level signal on the scanning signal line is

[0111] Then, after the low-level signal is loaded on the scanning signal line electrically connected to the sub-pixels in the 2nd / 3nth row, the low-level signal is loaded in sequence to the luminous signal line EM1 electrically connected to the sub-pixels in the 1st row, the low-level signal is loaded to the luminous signal line EM2 electrically connected to the sub-pixels in the 2nd row, the low-level signal is loaded to the luminous signal line EM3 electrically connected to the sub-pixels in the 3rd row, the low-level signal is loaded to the luminous signal line EM4 electrically connected to the sub-pixels in the 4th row, the low-level signal is loaded to the luminous signal line EM5 electrically connected to the sub-pixels in the 5th row... and the low-level signal is loaded to the luminous signal line EMn electrically connected to the sub-pixels in the nth row, wherein the duration of loading the low-level signal on the luminous signal line electrically connected to each row of sub-pixels is L3=(L3 / L1)*1H, and it is set Among them, L1+L2>L3, then the time length of each display frame to complete the update display is shortened to 1 / 3L1; the refresh frequency of the low-level signal on the luminous signal line is There is a third time interval T3 between the end time of loading the low level signal scn onto the scanning signal line SCn electrically connected to the nth row of sub-pixels and the start time of loading the low level signal em1 onto the luminous signal line EM1 electrically connected to the 1st row of sub-pixels.

[0112] In the above embodiment, L1 and L3 are partially overlapped, and low-level signals are loaded to the scanning signal lines electrically connected to all rows of sub-pixels within 0.8 times the frame time; after the data writing of 2 / 3n rows of sub-pixels is completed, low-level signals are immediately loaded to the luminous signal lines electrically connected to the first row of sub-pixels. In this way, the time for loading the low-level signal to the luminous signal line can be appropriately extended, avoiding the problem of insufficient data writing caused by circuit RC loading. At the same time, if the time for loading the low-level signal to the luminous signal line is not too long, the update display of the picture can be accelerated, thereby improving the motion blur problem in fast-moving scenes and achieving ultra-high performance image quality.

[0113] In some embodiments of the present disclosure, there is at least one holding frame between two adjacent display frames. In the holding frame, an effective level signal is loaded to the light emitting signal line electrically connected to each row of sub-pixels.

[0114] In the embodiment of the present disclosure, by having at least one hold frame between two adjacent display frames, that is, one or even more hold frames can be inserted between two adjacent display frames as needed, thereby achieving a variable refresh rate, dynamically matching the real-time picture frame number, improving the smoothness of the video, and avoiding the problem of picture freeze.

[0115] For example, Figure 13 and Figure 14As shown, sc represents the effective level signal (e.g., a low level signal) loaded onto the scan signal line, em represents the effective level signal (e.g., a low level signal) loaded onto the luminescence signal line, 1H represents a display frame, L1 represents the duration of a display frame, L2 represents the total duration during which effective level signals are loaded onto the scan signal lines electrically connected to all rows of sub-pixels, L3 represents the duration during which effective level signals are loaded onto the luminescence signal lines electrically connected to a row of sub-pixels, F1 represents the first display frame, F2 represents the second display frame, F3 represents the third display frame, and F4 represents the fourth display frame. A hold frame exists between the first display frame F1 and the third display frame F3, i.e., the second display frame F2 is a hold frame. In the second display frame F2, the effective level signal em is loaded onto the luminescence signal lines electrically connected to each row of sub-pixels.

[0116] For example, if the refresh rate of the current display panel is 120Hz, the refresh rate of the display panel can be set to 60Hz by having one hold frame between two adjacent display frames; of course, the refresh rate of the display panel can also be set to 30Hz by having three hold frames between two adjacent display frames.

[0117] For example, Figure 14 As shown, sc1 represents the signal loaded on the scanning signal line SC1 electrically connected to the sub-pixels in the first row, sc2 represents the signal loaded on the scanning signal line SC2 electrically connected to the sub-pixels in the second row, sc3 represents the signal loaded on the scanning signal line SC3 electrically connected to the sub-pixels in the third row, sc4 represents the signal loaded on the scanning signal line SC4 electrically connected to the sub-pixels in the fourth row, sc5 represents the signal loaded on the scanning signal line SC5 electrically connected to the sub-pixels in the fifth row, scn represents the signal loaded on the scanning signal line SCn electrically connected to the sub-pixels in the nth row, em1 represents the signal loaded on the emission signal line EM1 electrically connected to the sub-pixels in the first row, em2 represents the signal loaded on the emission signal line EM2 electrically connected to the sub-pixels in the second row, em3 represents the signal loaded on the emission signal line EM3 electrically connected to the sub-pixels in the third row, em4 represents the signal loaded on the emission signal line EM4 electrically connected to the sub-pixels in the fourth row, em5 represents the signal loaded on the emission signal line EM5 electrically connected to the sub-pixels in the fifth row, and emn represents the signal loaded on the emission signal line EMn electrically connected to the sub-pixels in the nth row;

[0118] For example, in the second display frame (i.e., the hold frame), a low-level signal is sequentially loaded onto the light-emitting signal line EM1 electrically connected to the sub-pixels in the first row, a low-level signal is loaded onto the light-emitting signal line EM2 electrically connected to the sub-pixels in the second row, a low-level signal is loaded onto the light-emitting signal line EM3 electrically connected to the sub-pixels in the third row, a low-level signal is loaded onto the light-emitting signal line EM4 electrically connected to the sub-pixels in the fourth row, a low-level signal is loaded onto the light-emitting signal line EM5 electrically connected to the sub-pixels in the fifth row…and a low-level signal is loaded onto the light-emitting signal line EMn electrically connected to the sub-pixels in the nth row, wherein the duration for which the low-level signal is loaded onto the light-emitting signal line electrically connected to each row of sub-pixels is L3.

[0119] The display device provided by the embodiment of the present disclosure is as follows: Figure 15 and Figure 16 As shown, the gate drive circuit 10 includes a plurality of shift register units (eg Figure 15 SR1, SR2...SR(n / 3)); shift register unit (e.g. Figure 15 SR1, SR2...SR(n / 3)) in the image are set corresponding to at least two adjacent rows of sub-pixels spx.

[0120] The embodiment of the present disclosure reduces the pressure of signal writing on the gate drive circuit by arranging the shift register unit in correspondence with at least two adjacent rows of sub-pixels, that is, the shift register unit loads signals to at least two adjacent rows of sub-pixels at the same time, thereby avoiding the problems of inaccurate brightness and uneven picture caused by insufficient signal writing, and achieving faster picture update display.

[0121] Furthermore, by disposing the shift register unit corresponding to at least two adjacent rows of sub-pixels, the requirement for the circuit RC loading in the display panel can be reduced, and the process is easier to implement.

[0122] For example, each shift register unit can be set to correspond to two adjacent rows of sub-pixels; or, each shift register unit can be set to correspond to three adjacent rows of sub-pixels; or, each shift register unit can be set to correspond to four adjacent rows of sub-pixels; of course, each shift register unit can be set to correspond to more adjacent rows of sub-pixels; this is not limited here.

[0123] For example Figure 15 As shown, the shift register unit SR1 is set corresponding to three adjacent rows of sub-pixels, and the shift register unit SR1 is electrically connected to the corresponding rows of sub-pixels through the scanning signal lines SC1, SC2 and SC3; the shift register unit SR2 is set corresponding to three adjacent rows of sub-pixels, and the shift register unit SR2 is electrically connected to the corresponding rows of sub-pixels through the scanning signal lines SC4, SC5 and SC6; the connection methods of the remaining shift register units are similar, and will not be elaborated here.

[0124] For example Figure 16 As shown, the shift register unit SR1 is set corresponding to three adjacent rows of sub-pixels, and the shift register unit SR1 is electrically connected to the corresponding row of sub-pixels through the light-emitting signal lines EM1, EM2 and EM3; the shift register unit SR2 is set corresponding to three adjacent rows of sub-pixels, and the shift register unit SR2 is electrically connected to the corresponding row of sub-pixels through the light-emitting signal lines EM4, EM25 and EM6; the connection methods of the remaining shift register units are similar, and will not be elaborated here.

[0125] The display device provided by the embodiment of the present disclosure is as follows: Figure 17 and Figure 18 As shown, the gate driving circuit 10 includes a first gate driving circuit 101 and a second gate driving circuit 102; the first gate driving circuit 101 is corresponding to the odd-numbered rows of sub-pixels spx, and the second gate driving circuit 102 is corresponding to the even-numbered rows of sub-pixels spx.

[0126] In the embodiment of the present disclosure, by configuring the first gate drive circuit to correspond to the sub-pixels in odd-numbered rows and the second gate drive circuit to correspond to the sub-pixels in even-numbered rows, the pressure on the gate drive circuit to write signals can be reduced, thereby avoiding the problems of inaccurate brightness and uneven images caused by insufficient signal writing, and achieving faster image update and display.

[0127] Furthermore, by disposing the first gate driving circuit corresponding to the odd-numbered rows of sub-pixels and the second gate driving circuit corresponding to the even-numbered rows of sub-pixels, the requirement for the RC loading of the circuit in the display panel can be reduced, and the process is easier to implement.

[0128] For example, Figure 17 and Figure 18 As shown, the first gate driving circuit 101 is provided corresponding to the 1st, 3rd, 5th, ... rows of sub-pixels, and the second gate driving circuit 102 is provided corresponding to the 2nd, 4th, ... nth rows of sub-pixels.

[0129] For example Figure 17 As shown, the first gate driving circuit 101 includes a plurality of shift register units (eg Figure 17 SR1, SR3, SR5 ... in the first row), the shift register unit SR1 is electrically connected to the sub-pixels in the first row through the scanning signal line SC1, the shift register unit SR3 is electrically connected to the sub-pixels in the third row through the scanning signal line SC3, and the shift register unit SR5 is electrically connected to the sub-pixels in the fifth row through the scanning signal line SC5 ...; the second gate driving circuit 102 includes a plurality of shift register units (for example Figure 17SR2, SR4 ... SRn), the shift register unit SR2 is electrically connected to the sub-pixels in the second row through the scanning signal line SC2, the shift register unit SR4 is electrically connected to the sub-pixels in the fourth row through the scanning signal line SC4 ... the shift register unit SRn is electrically connected to the sub-pixels in the nth row through the scanning signal line SCn.

[0130] For example Figure 18 As shown, the first gate driving circuit 101 includes a plurality of shift register units (eg Figure 17 SR1, SR3, SR5, ...), the shift register unit SR1 is electrically connected to the sub-pixels in the first row via the light-emitting signal line EM1, the shift register unit SR3 is electrically connected to the sub-pixels in the third row via the light-emitting signal line EM3, and the shift register unit SR5 is electrically connected to the sub-pixels in the fifth row via the light-emitting signal line EM5 ...; the second gate driving circuit 102 includes a plurality of shift register units (for example Figure 17 SR2, SR4, ..., SRn), the shift register unit SR2 is electrically connected to the sub-pixels in the second row through the light-emitting signal line EM2, the shift register unit SR4 is electrically connected to the sub-pixels in the fourth row through the light-emitting signal line EM4... the shift register unit SRn is electrically connected to the sub-pixels in the nth row through the light-emitting signal line EMn.

[0131] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0132] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0133] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A method for driving a display panel, wherein: The display panel includes: a plurality of sub-pixels, a plurality of scanning signal lines, and a plurality of light-emitting signal lines; a row of sub-pixels is electrically connected to one of the scanning signal lines, and a row of sub-pixels is electrically connected to one of the light-emitting signal lines; The driving method includes: In a display frame, firstly, an effective level signal is applied to the scanning signal lines electrically connected to at least some rows of sub-pixels in a plurality of rows of sub-pixels, and then an effective level signal is applied to the light emitting signal lines electrically connected to the at least some rows of sub-pixels; There is a first time interval between the end time of loading the valid level signal on the scanning signal line electrically connected to the sub-pixels in the same row and the start time of loading the valid level signal on the luminescence signal line electrically connected to the sub-pixels in the same row.

2. The driving method according to claim 1, wherein: After loading the effective level signal to the scanning signal line electrically connected to each row of sub-pixels in the multiple rows of sub-pixels in sequence, the effective level signal is then loaded to the light emitting signal line electrically connected to each row of sub-pixels in the multiple rows of sub-pixels in sequence.

3. The driving method according to claim 2, wherein: The end time of loading the effective level signal on the scanning signal line electrically connected to the last row of sub-pixels is the same as the start time of loading the effective level signal on the light emitting signal line electrically connected to the first row of sub-pixels.

4. The driving method according to claim 2, wherein: There is a second time interval between the end time of loading the valid level signal on the scanning signal line electrically connected to the last row of sub-pixels and the start time of loading the valid level signal on the luminescence signal line electrically connected to the first row of sub-pixels.

5. The driving method according to claim 1, wherein: After loading effective level signals to the scanning signal lines electrically connected to some rows of sub-pixels in the multiple rows of sub-pixels in sequence, effective level signals are loaded to the light emitting signal lines electrically connected to each row of sub-pixels in the multiple rows of sub-pixels in sequence.

6. The driving method according to claim 5, wherein: The time when the effective level signal is loaded on the scanning signal line electrically connected to the sub-pixels in the last row is later than the time when the effective level signal is loaded on the light emitting signal line electrically connected to the sub-pixels in the first row.

7. The driving method according to any one of claims 1 to 6, wherein: There is at least one holding frame between two adjacent display frames, and in the holding frame, an effective level signal is loaded to the light emitting signal line electrically connected to each row of sub-pixels.

8. A display device, wherein: include: Display panel and gate drive circuit; The display panel includes: a plurality of rows of sub-pixels, a plurality of scanning signal lines and a plurality of light-emitting signal lines; A row of sub-pixels is electrically connected to one of the scanning signal lines, and a row of sub-pixels is electrically connected to one of the light-emitting signal lines; The gate driving circuit is electrically connected to the multiple rows of sub-pixels and is configured to, in a display frame, first apply an effective level signal to the scanning signal lines electrically connected to at least some of the multiple rows of sub-pixels, and then apply an effective level signal to the light emitting signal lines electrically connected to the at least some of the rows of sub-pixels; There is a first time interval between the end time of loading the valid level signal on the scanning signal line electrically connected to the sub-pixels in the same row and the start time of loading the valid level signal on the luminescence signal line electrically connected to the sub-pixels in the same row.

9. The display device according to claim 8, wherein: The gate driving circuit includes a plurality of shift register units; The shift register unit is arranged corresponding to at least two adjacent rows of sub-pixels.

10. The display device according to claim 8, wherein: The gate driving circuit includes a first gate driving circuit and a second gate driving circuit; The first gate driving circuit is disposed corresponding to the odd-numbered rows of sub-pixels, and the second gate driving circuit is disposed corresponding to the even-numbered rows of sub-pixels.

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